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2026-01-28 - 06:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #2, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack2slot7s.osadl.org (updated Tue Jan 27, 2026 19:55:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
682181998779,5cyclictest1504116-21grep18:10:272
682180996860,4cyclictest0-21swapper/117:50:181
682180996851,13cyclictest996519-21ntpq17:55:101
682179996851,11cyclictest12450irq/32-eth018:34:230
682181996453,5cyclictest0-21swapper/217:50:082
682180996355,5cyclictest1527107-21sh18:11:231
682179996041,12cyclictest0-21swapper/017:50:100
682179995332,17cyclictest1503178-21sort18:10:250
682181995241,6cyclictest987631-21sh17:43:192
68218099525,8cyclictest171rcu_preempt18:15:051
682181994938,6cyclictest1479864-21sh18:09:242
682180994942,4cyclictest1463426-21sh18:08:471
682181994837,7cyclictest1569027-21kernelversion18:20:012
682179994834,11cyclictest994242-21munin-run17:50:010
682180994738,4cyclictest0-21swapper/117:40:141
682180994730,10cyclictest271ktimers/118:00:061
68217999474,23cyclictest914359-21sh17:40:100
682181994640,3cyclictest0-21swapper/217:39:292
682181994638,5cyclictest686375-21whetstone-doubl17:20:012
682181994537,5cyclictest682469-21latency_hist17:05:032
68218099451,29cyclictest689653-21pipe17:30:051
682179994531,11cyclictest1424055-21sh18:07:120
682181994435,6cyclictest993948-21execl17:49:572
682180994436,5cyclictest685183-21latency17:15:011
682179994432,5cyclictest0-21swapper/017:35:070
682180994234,5cyclictest993946-21execl17:49:571
682179994226,14cyclictest682190-21sh17:05:010
682181994133,5cyclictest685182-21cat17:15:012
682181994025,10cyclictest997122-21fstime17:57:442
682179993930,6cyclictest997167-21pipe17:58:500
682181993831,3cyclictest0-21swapper/218:35:012
682181993830,5cyclictest690071-21systemd-run17:30:012
682180993830,5cyclictest912219-21sort17:40:011
682179993831,4cyclictest685098-21kernelversion17:15:010
682179993830,5cyclictest12450irq/32-eth017:20:120
682181993731,3cyclictest0-21swapper/217:35:012
682181993729,5cyclictest1285937-21spawn18:03:582
682180993627,6cyclictest1-21systemd18:25:021
682180993529,3cyclictest0-21swapper/118:40:011
682180993527,5cyclictest686937-21systemd17:20:021
682179993526,6cyclictest999061-21spawn18:02:560
682179993427,4cyclictest1569010-21systemd-run18:20:010
682179993426,6cyclictest686375-21whetstone-doubl17:20:010
682179993424,7cyclictest875043-21spawn17:35:000
682181993324,6cyclictest1570569-21cron18:25:012
682181993225,4cyclictest0-21swapper/218:40:012
682180993224,5cyclictest689922-21if_wlan017:30:001
68217999328,19cyclictest151ktimers/018:25:070
682181993024,3cyclictest0-21swapper/218:30:012
682181993022,4cyclictest0-21swapper/217:05:102
68218099305,4cyclictest171rcu_preempt17:25:011
682179993016,10cyclictest151ktimers/017:25:080
682181992915,3cyclictest171rcu_preempt17:20:502
682180992922,3cyclictest0-21swapper/117:10:001
682179992924,2cyclictest0-21swapper/017:10:010
68218099289,16cyclictest271ktimers/118:25:061
682180992821,3cyclictest0-21swapper/118:30:131
682179992618,3cyclictest171rcu_preempt18:20:120
682179992519,4cyclictest0-21swapper/018:40:010
682182992311,6cyclictest0-21swapper/317:20:073
682180992317,3cyclictest0-21swapper/117:05:031
68218299218,4cyclictest0-21swapper/317:10:093
68218299201,10cyclictest0-21swapper/318:06:233
68218299199,6cyclictest0-21swapper/318:00:063
68218299197,7cyclictest0-21swapper/318:10:173
68218299193,11cyclictest0-21swapper/317:57:013
68218299191,8cyclictest0-21swapper/317:45:113
68218299182,8cyclictest0-21swapper/317:40:063
68218299179,4cyclictest0-21swapper/318:25:053
68218299178,4cyclictest0-21swapper/317:15:063
68218299172,11cyclictest0-21swapper/317:50:103
68218299171,6cyclictest0-21swapper/317:05:053
68218299170,8cyclictest0-21swapper/317:35:103
68218299169,5cyclictest0-21swapper/318:15:043
68218299168,4cyclictest0-21swapper/317:25:063
682182991611,4cyclictest0-21swapper/318:34:233
68218299157,4cyclictest0-21swapper/317:30:043
682182991510,3cyclictest0-21swapper/318:20:093
68218299149,3cyclictest0-21swapper/318:35:103
68218299136,4cyclictest0-21swapper/317:05:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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