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2026-01-31 - 22:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #2, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack2slot7s.osadl.org (updated Sat Jan 31, 2026 07:55:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
638502996235,23cyclictest933499-21sh05:42:471
638502996143,14cyclictest1450783-21multi.sh06:10:031
638502995843,12cyclictest1486123-21rm06:11:351
638502995843,12cyclictest1486123-21rm06:11:351
638503995646,6cyclictest1457952-21sh06:10:262
638503995646,6cyclictest1457952-21sh06:10:262
638501995543,9cyclictest1458274-21sort06:10:270
638501995543,9cyclictest1458274-21sort06:10:270
638503995443,8cyclictest905036-21tee05:41:362
638503995431,17cyclictest351ktimers/205:55:152
638502995437,14cyclictest0-21swapper/105:49:511
638502995329,21cyclictest871315-21df_inode05:40:001
638502995324,6cyclictest999767-21spawn06:02:591
638503995242,6cyclictest1451867-21sh06:10:092
638501995243,3cyclictest0-21swapper/005:40:090
638502995040,4cyclictest0-21swapper/105:50:181
638503994735,5cyclictest0-21swapper/205:50:112
638501994734,4cyclictest1402523-21sh06:08:000
638503994537,5cyclictest1525912-21kworker/u8:3-xprtiod06:30:012
638503994436,5cyclictest645161-21latency_hist05:25:032
638503994334,5cyclictest953083-21execl05:50:042
638503994333,6cyclictest1528976-21sendmail06:40:012
638503994333,6cyclictest1528976-21sendmail06:40:012
638502994235,3cyclictest0-21swapper/105:20:011
638501994223,12cyclictest12450irq/32-eth006:30:010
638502994133,5cyclictest644831-21cron05:25:011
638501994135,3cyclictest0-21swapper/005:50:130
638501994132,6cyclictest871466-21multi.sh05:40:010
638503994033,4cyclictest646100-21pipe05:30:022
63850199408,23cyclictest1166-21mta-sts-daemon06:15:130
638501994032,4cyclictest641570-21Run05:15:010
638503993932,4cyclictest643227-21idleruntime-cro05:20:012
638503993930,6cyclictest1203050-21spawn06:03:472
638503993927,9cyclictest564-21dbus-daemon06:25:012
638502993830,5cyclictest564-21dbus-daemon06:35:011
638501993829,6cyclictest958143-21Run06:02:230
63850199381,4cyclictest952169-21dhry2reg05:45:070
638502993728,6cyclictest641564-21/usr/sbin/munin05:15:011
638501993730,4cyclictest638725-21cat05:05:020
638501993724,10cyclictest1527425-21latency_hist06:35:020
638501993720,12cyclictest12450irq/32-eth006:35:100
638501993720,12cyclictest12450irq/32-eth006:35:100
638502993626,5cyclictest647538-21unixbench_singl05:30:201
638502993626,5cyclictest647538-21unixbench_singl05:30:201
638503993528,4cyclictest636821-21kworker/u8:13-events_unbound05:15:002
638503993428,2cyclictest0-21swapper/205:40:002
638502993427,4cyclictest1522994-21latency_hist06:20:011
638502993426,5cyclictest639992-21cron05:10:001
638501993428,3cyclictest0-21swapper/006:25:010
638501993418,13cyclictest0-21swapper/005:25:010
638503993326,4cyclictest1522874-21sh06:20:002
638503993326,3cyclictest0-21swapper/205:35:022
638503993326,3cyclictest0-21swapper/205:35:022
638502993227,2cyclictest0-21swapper/106:30:001
638501993222,7cyclictest647732-21spawn05:33:320
638501993222,7cyclictest647732-21spawn05:33:320
638502993124,4cyclictest638652-21latency_hist05:05:021
63850299312,19cyclictest956205-21Run05:56:481
638501993112,10cyclictest171rcu_preempt05:55:150
638501993025,2cyclictest0-21swapper/005:30:020
638502992923,3cyclictest0-21swapper/106:25:021
638501992924,3cyclictest151ktimers/005:05:090
638503992822,3cyclictest0-21swapper/205:05:012
638502992720,4cyclictest1528978-21if_err_eth006:40:011
638502992720,4cyclictest1528978-21if_err_eth006:40:011
638502992715,6cyclictest646028-21fstime05:28:121
638503992620,3cyclictest0-21swapper/206:35:012
638501992610,12cyclictest642288-21proc_pri05:15:140
638503992517,5cyclictest639248-21proc_pri05:05:152
63850499171,7cyclictest0-21swapper/306:30:123
63850499162,9cyclictest0-21swapper/306:10:273
63850499162,9cyclictest0-21swapper/306:10:273
63850499162,9cyclictest0-21swapper/305:50:143
63850499162,7cyclictest0-21swapper/306:05:093
63850499161,7cyclictest0-21swapper/305:30:103
63850499161,7cyclictest0-21swapper/305:30:103
63850499161,6cyclictest0-21swapper/306:00:083
63850499153,7cyclictest0-21swapper/305:57:033
63850499143,7cyclictest0-21swapper/305:45:073
63850499142,8cyclictest0-21swapper/305:40:093
63850499141,7cyclictest0-21swapper/305:10:113
63850499140,6cyclictest0-21swapper/306:35:113
63850499140,6cyclictest0-21swapper/306:35:113
63850499132,6cyclictest0-21swapper/305:20:013
63850499131,7cyclictest0-21swapper/306:25:003
63850499131,7cyclictest0-21swapper/305:20:113
63850499123,5cyclictest0-21swapper/306:30:013
63850499123,5cyclictest0-21swapper/306:15:113
63850499120,6cyclictest0-21swapper/305:25:063
63850499114,5cyclictest0-21swapper/305:40:003
63850499112,6cyclictest0-21swapper/305:05:023
63850499112,4cyclictest0-21swapper/305:10:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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