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2026-02-11 - 06:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #2, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot7s.osadl.org (updated Tue Feb 10, 2026 19:55:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
491856996657,7cyclictest1310113-21multi.sh18:10:230
491856995750,3cyclictest0-21swapper/017:50:210
491858995547,5cyclictest1309130-21sh18:10:212
491856995541,11cyclictest1274669-21sh18:08:580
491856995446,5cyclictest745562-21tee17:41:110
491856995446,5cyclictest745562-21tee17:41:110
491857995244,5cyclictest755170-21sh17:41:371
491857995244,5cyclictest755170-21sh17:41:371
491856995142,6cyclictest497447-21execl17:20:150
491856995142,6cyclictest497447-21execl17:20:150
491858994941,5cyclictest1300904-21od18:10:012
491857994941,5cyclictest1303021-21sh18:10:061
491857994638,5cyclictest943672-21spawn18:03:451
491857994638,5cyclictest943672-21spawn18:03:451
491858994537,5cyclictest728332-21sh17:40:282
491858994537,5cyclictest728332-21sh17:40:282
491858994537,5cyclictest1-21systemd18:20:012
491857994538,4cyclictest1239950-21sh18:07:341
491858994433,5cyclictest0-21swapper/217:15:182
491858994433,5cyclictest0-21swapper/217:15:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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