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2026-02-28 - 17:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot1.osadl.org (updated Sat Feb 28, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
595499107102cyclictest0-21swapper/308:58:093
59549910392cyclictest0-21swapper/309:03:103
595499103102cyclictest0-21swapper/308:13:133
595499103102cyclictest0-21swapper/306:53:143
593599103102cyclictest21984-21tune2fs09:13:101
5954999492cyclictest0-21swapper/308:28:193
5954999371cyclictest0-21swapper/306:48:143
5954998982cyclictest32159-21aten2.4_r3power07:08:103
5954998882cyclictest0-21swapper/310:33:053
5954998872cyclictest0-21swapper/309:23:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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