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2026-02-25 - 15:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot1.osadl.org (updated Wed Feb 25, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1890199123122cyclictest20847-21sed09:56:003
188999910492cyclictest0-21swapper/111:30:491
1890199103102cyclictest0-21swapper/308:05:583
188999910392cyclictest0-21swapper/107:30:421
1889999103102cyclictest0-21swapper/109:56:001
18899999392cyclictest0-21swapper/109:21:001
18899998881cyclictest30405-21tune2fs06:35:581
18901998782cyclictest0-21swapper/311:35:333
18901998782cyclictest0-21swapper/310:05:593
18901998782cyclictest0-21swapper/309:35:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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