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2026-01-25 - 10:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot1.osadl.org (updated Sun Jan 25, 2026 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2125799123122cyclictest0-21swapper/319:49:273
2125599109102cyclictest24368-21tune2fs22:29:211
2125599108102cyclictest21507-21aten2.4-expect18:39:281
2125599107102cyclictest2783-21tune2fs20:24:261
2125599107102cyclictest2783-21tune2fs20:24:261
2125799103102cyclictest11232-21tune2fs20:44:263
2125799103102cyclictest0-21swapper/300:04:193
2125599103102cyclictest11567-21tune2fs21:59:221
21257999392cyclictest0-21swapper/321:49:233
21255998881cyclictest22528-21tune2fs23:39:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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