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2026-02-15 - 12:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot1.osadl.org (updated Sun Feb 15, 2026 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2769099124112cyclictest0-21swapper/121:50:081
276909911192cyclictest7102-21tune2fs21:15:241
2769099108102cyclictest0-21swapper/121:30:301
2769299107102cyclictest0-21swapper/321:30:303
276909910492cyclictest0-21swapper/121:30:091
2769099104102cyclictest2488-21tune2fs19:50:241
2769299103102cyclictest0-21swapper/319:50:243
2769099103102cyclictest0-21swapper/119:20:321
27692999892cyclictest0-21swapper/321:15:243
27690998684cyclictest0-21swapper/120:25:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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