You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-08 - 11:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot1.osadl.org (updated Sun Feb 08, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3018599113112cyclictest0-21swapper/118:36:351
301859910792cyclictest3200-21tune2fs23:36:381
3018799103102cyclictest0-21swapper/319:26:563
3018599103102cyclictest0-21swapper/123:47:121
3018599103102cyclictest0-21swapper/123:02:061
3018599103102cyclictest0-21swapper/120:26:411
3018599103102cyclictest0-21swapper/119:36:511
3018599103102cyclictest0-21swapper/119:16:321
3018599103102cyclictest0-21swapper/118:56:281
30187999997cyclictest0-21swapper/322:11:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional