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2026-02-18 - 13:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot1.osadl.org (updated Wed Feb 18, 2026 00:43:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
271969910892cyclictest0-21swapper/122:27:391
2719699108102cyclictest4430-21tune2fs22:22:361
2719699108102cyclictest25915-21tune2fs21:57:381
271969910792cyclictest0-21swapper/120:32:311
271969910792cyclictest0-21swapper/118:17:541
2719699106105cyclictest10745-21tune2fs18:52:461
2719699104102cyclictest32266-21tune2fs20:57:401
2719899103102cyclictest0-21swapper/320:37:433
2719899103102cyclictest0-21swapper/320:32:313
2719899103102cyclictest0-21swapper/320:27:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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