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2026-02-02 - 21:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot1.osadl.org (updated Mon Feb 02, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2079399115113cyclictest6660-21munin-node11:01:471
2081299114112cyclictest0-21swapper/308:11:483
2081299104103cyclictest0-21swapper/308:31:443
2079399104102cyclictest4272-21tune2fs08:21:461
2081299103102cyclictest0-21swapper/311:31:233
2081299103102cyclictest0-21swapper/311:01:473
2081299103102cyclictest0-21swapper/308:36:533
2081299103102cyclictest0-21swapper/308:21:463
2079399103102cyclictest0-21swapper/108:11:481
20812999594cyclictest16510-21runrttasks10:04:333
20812999392cyclictest0-21swapper/307:11:563
20793999392cyclictest0-21swapper/111:31:231
20793999392cyclictest0-21swapper/111:06:401
20793999392cyclictest0-21swapper/108:36:531
20793999392cyclictest0-21swapper/108:31:441
20793999392cyclictest0-21swapper/107:51:471
20793999392cyclictest0-21swapper/107:41:541
20793999392cyclictest0-21swapper/106:31:521
20793999189cyclictest19616-21tune2fs08:56:431
20793998785cyclictest2148-21tune2fs08:16:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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