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2026-06-04 - 22:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot1.osadl.org (updated Thu Jun 04, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2085699116102cyclictest15388-21tune2fs09:26:121
2085699104102cyclictest28552-21tune2fs09:56:091
2085699104102cyclictest26048-21tune2fs08:36:131
2085899103102cyclictest0-21swapper/309:56:093
2085899103102cyclictest0-21swapper/305:51:203
2085899103102cyclictest0-21swapper/305:51:203
20858999692cyclictest0-21swapper/306:33:503
20858999692cyclictest0-21swapper/305:33:403
20856999482cyclictest278-21usb-storage05:06:231
20858999392cyclictest0-21swapper/306:21:183
20856999392cyclictest0-21swapper/107:34:011
20856999392cyclictest0-21swapper/105:36:271
20856999371cyclictest32519-21tune2fs06:21:181
20858998972cyclictest0-21swapper/308:21:143
20858998872cyclictest0-21swapper/306:26:173
20858998782cyclictest0-21swapper/309:31:123
20858998782cyclictest0-21swapper/309:16:113
20858998782cyclictest0-21swapper/308:11:143
20858998782cyclictest0-21swapper/306:51:223
20858998782cyclictest0-21swapper/304:56:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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