You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-12 - 23:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot1.osadl.org (updated Mon Jan 12, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2835399125123cyclictest0-21swapper/307:05:593
2835399105102cyclictest0-21swapper/309:40:523
2835199104102cyclictest5175-21tune2fs09:40:441
2835199104102cyclictest13268-21aten2.4-expect07:30:431
2835399103102cyclictest0-21swapper/311:10:263
2835399103102cyclictest0-21swapper/308:20:573
2835399103102cyclictest0-21swapper/307:30:433
2835199103102cyclictest0-21swapper/107:05:591
28353999482cyclictest0-21swapper/310:20:463
28351999392cyclictest0-21swapper/111:15:401
28351999392cyclictest0-21swapper/108:45:481
28351998583cyclictest25027-21ps11:40:441
28353998482cyclictest27491-21sed10:30:503
28353998482cyclictest27491-21sed10:30:503
28351998483cyclictest0-21swapper/110:38:001
28351998482cyclictest492-21tune2fs10:45:401
28353998382cyclictest0-21swapper/312:05:453
28353998382cyclictest0-21swapper/311:40:393
28353998382cyclictest0-21swapper/311:35:373
28353998382cyclictest0-21swapper/311:15:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional