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2026-03-04 - 21:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot1.osadl.org (updated Wed Mar 04, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
743099104102cyclictest8422-21tune2fs11:04:261
743099104102cyclictest16968-21tune2fs10:09:291
743099104102cyclictest10568-21tune2fs08:39:331
744999103102cyclictest0-21swapper/311:04:263
744999103102cyclictest0-21swapper/310:09:293
744999103102cyclictest0-21swapper/308:39:333
744999103102cyclictest0-21swapper/307:54:213
743099103102cyclictest0-21swapper/107:54:211
7449999692cyclictest0-21swapper/306:09:253
7449999692cyclictest0-21swapper/306:09:253
7430999392cyclictest0-21swapper/110:34:341
7449998972cyclictest0-21swapper/306:14:373
7449998972cyclictest0-21swapper/306:09:393
7449998971cyclictest0-21swapper/306:54:353
7449998882cyclictest6600-21tr07:14:393
7449998882cyclictest31945-21fschecks_time08:14:343
7449998872cyclictest0-21swapper/308:59:383
7430998882cyclictest0-21swapper/106:09:391
7430998881cyclictest12403-21tune2fs06:14:371
7449998782cyclictest0-21swapper/308:44:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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