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2026-01-19 - 21:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot1.osadl.org (updated Mon Jan 19, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3189399143142cyclictest0-21swapper/311:04:263
3189199135134cyclictest15709-21sensors11:04:261
3189199123122cyclictest0-21swapper/111:44:261
3189199110109cyclictest32548-21head07:59:261
318939910992cyclictest0-21swapper/309:54:293
318939910892cyclictest0-21swapper/312:09:173
318939910692cyclictest0-21swapper/311:52:343
318939910692cyclictest0-21swapper/310:24:283
318939910692cyclictest0-21swapper/309:34:293
3189399106102cyclictest0-21swapper/307:24:263
3189399105102cyclictest0-21swapper/311:47:333
3189399105102cyclictest0-21swapper/311:22:293
3189399105102cyclictest0-21swapper/310:17:183
3189399105102cyclictest0-21swapper/309:17:083
3189399105102cyclictest0-21swapper/308:06:583
318939910392cyclictest0-21swapper/309:59:313
3189199103102cyclictest13005-21tune2fs07:14:271
3189199103102cyclictest0-21swapper/109:09:231
31893999792cyclictest0-21swapper/307:29:253
31893999692cyclictest0-21swapper/311:09:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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