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2026-02-08 - 02:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot1.osadl.org (updated Sun Feb 08, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3018599113112cyclictest0-21swapper/118:36:351
301859910792cyclictest3200-21tune2fs23:36:381
3018799103102cyclictest0-21swapper/319:26:563
3018599103102cyclictest0-21swapper/123:47:121
3018599103102cyclictest0-21swapper/123:02:061
3018599103102cyclictest0-21swapper/120:26:411
3018599103102cyclictest0-21swapper/119:36:511
3018599103102cyclictest0-21swapper/119:16:321
3018599103102cyclictest0-21swapper/118:56:281
30187999997cyclictest0-21swapper/322:11:423
30187999997cyclictest0-21swapper/322:11:423
30187999997cyclictest0-21swapper/318:36:593
30187999986cyclictest0-21swapper/320:56:443
30187999886cyclictest0-21swapper/322:42:033
30185999592cyclictest0-21swapper/120:06:381
30187999392cyclictest0-21swapper/323:36:443
30187999392cyclictest0-21swapper/323:06:463
30187999392cyclictest0-21swapper/322:20:373
30187999076cyclictest0-21swapper/319:01:483
30187999076cyclictest0-21swapper/319:01:483
30187998987cyclictest0-21swapper/322:51:403
30187998987cyclictest0-21swapper/320:41:443
30187998987cyclictest0-21swapper/319:16:323
30187998887cyclictest0-21swapper/322:22:003
30187998886cyclictest21436-21runrttasks19:19:243
30187998472cyclictest0-21swapper/323:01:383
30187998472cyclictest0-21swapper/321:51:443
30187998472cyclictest0-21swapper/320:36:453
30187998471cyclictest0-21swapper/321:26:503
30187998471cyclictest0-21swapper/321:11:463
30185998482cyclictest2722-21tune2fs19:51:461
30185998482cyclictest17979-21tune2fs21:41:421
30185998482cyclictest13798-21tune2fs21:31:441
30185998472cyclictest0-21swapper/119:31:481
30187998382cyclictest0-21swapper/323:36:243
30187998382cyclictest0-21swapper/323:16:463
30187998382cyclictest0-21swapper/323:11:453
30187998382cyclictest0-21swapper/321:06:293
30187998382cyclictest0-21swapper/320:06:383
30187998382cyclictest0-21swapper/319:36:513
30187998382cyclictest0-21swapper/319:01:353
30187998371cyclictest0-21swapper/322:36:273
30187998371cyclictest0-21swapper/320:11:453
30185998382cyclictest0-21swapper/123:42:111
30185998382cyclictest0-21swapper/123:27:101
30185998382cyclictest0-21swapper/123:21:251
30185998382cyclictest0-21swapper/123:17:251
30185998382cyclictest0-21swapper/123:06:361
30185998382cyclictest0-21swapper/122:56:391
30185998382cyclictest0-21swapper/122:51:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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