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Default latency plot of system in rack #3, slot #1

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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance

Characteristics of the 50 highest latencies:

System rack3slot1.osadl.org (updated Sat May 16, 2026 12:43:27)
Delayed (victim)					Switcher (culprit)			Timestamp	CPU
PID	Prio	Total latency (µs)	T^(,W^*) latency (µs)	Cmd	PID	Prio	Cmd	Timestamp	CPU
32278	99	123	122	cyclictest	0	-21	swapper/3	08:58:24	3
32276	99	115	113	cyclictest	7331	-21	tune2fs	08:58:24	1
32278	99	104	92	cyclictest	0	-21	swapper/3	07:53:39	3
32276	99	104	102	cyclictest	630	-21	tune2fs	07:28:30	1
32276	99	104	102	cyclictest	11952	-21	tune2fs	10:23:23	1
32278	99	103	102	cyclictest	0	-21	swapper/3	10:23:23	3
32278	99	103	102	cyclictest	0	-21	swapper/3	09:28:33	3
32278	99	103	102	cyclictest	0	-21	swapper/3	07:28:30	3
32276	99	103	102	cyclictest	0	-21	swapper/1	09:43:30	1
32276	99	103	102	cyclictest	0	-21	swapper/1	09:08:33	1
32276	99	103	102	cyclictest	0	-21	swapper/1	08:28:13	1
32276	99	97	92	cyclictest	0	-21	swapper/1	09:28:33	1
32276	99	91	90	cyclictest	0	-21	swapper/1	07:44:56	1
32276	99	85	83	cyclictest	18030	-21	tune2fs	06:53:33	1
32278	99	84	72	cyclictest	0	-21	swapper/3	08:18:31	3
32278	99	84	72	cyclictest	0	-21	swapper/3	08:08:14	3
32278	99	84	72	cyclictest	0	-21	swapper/3	07:48:33	3
32278	99	84	72	cyclictest	0	-21	swapper/3	06:48:34	3
32278	99	84	72	cyclictest	0	-21	swapper/3	06:23:18	3
32278	99	84	62	cyclictest	0	-21	swapper/3	06:58:29	3
32276	99	84	82	cyclictest	7286	-21	tune2fs	06:28:31	1
32276	99	84	82	cyclictest	21988	-21	tune2fs	05:48:33	1
32278	99	83	82	cyclictest	0	-21	swapper/3	10:18:30	3
32278	99	83	82	cyclictest	0	-21	swapper/3	10:03:21	3
32278	99	83	82	cyclictest	0	-21	swapper/3	08:51:31	3
32278	99	83	82	cyclictest	0	-21	swapper/3	08:33:34	3
32278	99	83	82	cyclictest	0	-21	swapper/3	07:38:30	3
32278	99	83	82	cyclictest	0	-21	swapper/3	05:53:41	3
32278	99	83	71	cyclictest	0	-21	swapper/3	05:48:37	3
32276	99	83	82	cyclictest	0	-21	swapper/1	10:18:28	1
32276	99	83	82	cyclictest	0	-21	swapper/1	10:03:22	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:58:21	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:53:23	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:48:22	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:38:25	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:33:24	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:23:25	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:18:51	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:13:26	1
32276	99	83	82	cyclictest	0	-21	swapper/1	09:03:25	1
32276	99	83	82	cyclictest	0	-21	swapper/1	08:53:15	1
32276	99	83	82	cyclictest	0	-21	swapper/1	08:43:28	1
32276	99	83	82	cyclictest	0	-21	swapper/1	08:28:26	1
32276	99	83	82	cyclictest	0	-21	swapper/1	08:23:08	1
32276	99	83	82	cyclictest	0	-21	swapper/1	08:13:27	1
32276	99	83	82	cyclictest	0	-21	swapper/1	08:08:31	1
32276	99	83	82	cyclictest	0	-21	swapper/1	08:03:31	1
32276	99	83	82	cyclictest	0	-21	swapper/1	07:58:27	1
32276	99	83	82	cyclictest	0	-21	swapper/1	07:53:29	1
32276	99	83	82	cyclictest	0	-21	swapper/1	07:48:29	1
^Timer ^*Wakeup (latency=timer+wakeup+contextswitch)


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This page was last modified on 2019-05-28 - 00:17