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2026-02-23 - 02:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Mon Feb 23, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
203359222810,3sleep02033593-21/usr/sbin/munin21:26:180
207218822720,3chrt2072189-21cat23:45:300
208395722490,3sleep02083956-21true00:30:020
202258122490,3chrt2022579-21users20:46:220
200553922480,3chrt2005537-21ntpq19:46:010
202890722440,3chrt2028905-21irqstats21:10:240
204447222320,4chrt2044469-21ntpq22:05:500
203049822240,3chrt2030493-21ntpq21:15:450
199517799221190,19cyclictest2082994-21kworker/u2:000:40:030
199517799216185,19cyclictest2082994-21kworker/u2:000:31:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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