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2026-01-24 - 00:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Fri Jan 23, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
377977222970,3sleep03779773-21mii-tool09:15:230
381774722660,3chrt3817735-21ntpq11:45:460
382865422520,4chrt11-21ksoftirqd/012:27:130
376196222520,3chrt3761959-21ntpq08:10:560
376581622410,3chrt3765817-21basename08:25:230
379288822200,2sleep03792890-21xargs10:01:180
378650022150,2sleep03786502-21grep09:40:070
374460399214179,23cyclictest3752729-21run-parts07:37:480
381188222060,4chrt3811880-21forks11:25:200
379405122060,2sleep03794052-21ntp_states10:06:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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