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2026-03-04 - 17:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Wed Mar 04, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
245962026200,4sleep02459621-21cat07:06:010
246022699305275,20cyclictest29-21kswapd007:45:190
246022699294264,19cyclictest29-21kswapd007:40:220
246022699285246,27cyclictest2468543-31find07:39:560
252162222630,4chrt2521618-21munin-run10:50:040
254008322550,4chrt2540081-21memory11:55:270
254595222540,3chrt2545948-21ps12:16:130
250957322460,2chrt2509570-21ntpq10:05:400
253296122450,3chrt2532959-21df_inode11:30:160
250087422140,2sleep02500877-21grep09:35:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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