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2026-03-05 - 19:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Thu Mar 05, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
302380622900,3sleep03023807-21ld11:20:400
295361099288255,21cyclictest3011381-21ntpq10:36:040
295361099276247,18cyclictest2961958-21kworker/u2:207:41:090
295794122450,3chrt2957939-21apt07:25:130
295361099239209,19cyclictest29-21kswapd007:45:200
295361099232202,19cyclictest2959776-21kworker/u2:007:31:180
295361099229191,25cyclictest2961988-31find07:40:130
295361099228199,17cyclictest2953618-21kworker/u2:207:21:170
295361099223193,19cyclictest2998249-21kworker/u2:209:56:170
295361099223192,19cyclictest2967610-21kworker/u2:008:36:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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