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2026-01-28 - 19:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Wed Jan 28, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
200600126090,4sleep02006002-21ld07:05:350
201737122710,3chrt358-21snmpd07:46:110
207526322430,2sleep02075266-21cut11:15:010
202802322370,2chrt2028024-21apt-get08:25:110
200691399230200,18cyclictest2059971-21kworker/u2:211:31:180
200691399226198,16cyclictest2012936-21kworker/u2:007:40:030
200691399216185,19cyclictest2020924-21kworker/u2:109:00:030
200691399214184,18cyclictest2059971-21kworker/u2:211:26:180
200691399213185,16cyclictest2090599-21kworker/u2:212:31:150
200691399211181,19cyclictest2020924-21kworker/u2:109:10:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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