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2026-03-03 - 04:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Tue Mar 03, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176428422490,3chrt1764285-21sh21:45:020
174346822450,3sleep01743469-21ls20:30:080
180600022380,3sleep01806003-21cut00:15:260
177613122330,2chrt1776134-21processes22:26:160
178540322190,2sleep01785404-21idleruntime23:00:200
172108999218190,17cyclictest1790329-21kworker/u2:000:26:170
172108999206179,18cyclictest1799086-21kworker/u2:100:05:080
172108999206179,17cyclictest1735038-21kworker/u2:120:05:040
172108999206177,18cyclictest1735038-21kworker/u2:120:10:040
172108999203176,17cyclictest1718799-21kworker/u2:219:10:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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