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2026-01-12 - 17:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Mon Jan 12, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
255026999310280,19cyclictest2556290-21kworker/u2:107:37:560
258003622560,3chrt2580033-21ntpq08:55:320
263648122480,3chrt2636480-21awk12:20:280
255502422480,3chrt2555021-21ntpq07:25:540
255362222480,3chrt2553618-21ntpq07:20:520
259809622470,4chrt2598094-21/usr/sbin/munin10:00:290
255026999244214,19cyclictest2574471-21kworker/u2:209:20:370
255026999241214,18cyclictest2574471-21kworker/u2:209:35:380
255026999235206,19cyclictest2592592-21kworker/u2:010:25:120
255026999234204,18cyclictest2564284-21kworker/u2:008:15:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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