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2026-01-24 - 18:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Sat Jan 24, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8654122610,3chrt86536-21ntpq10:26:040
3153999249220,18cyclictest34361-21kworker/u2:007:39:200
11818822480,3chrt118182-21df_inode12:20:190
8498822420,3sleep084989-21gcc10:20:330
5578722420,2chrt55780-21ntpq08:35:460
3153999241210,19cyclictest90555-21kworker/u2:211:15:030
3153999240210,18cyclictest36169-21kworker/u2:107:50:370
3153999236206,20cyclictest117973-21kworker/u2:212:30:090
3153999235204,19cyclictest77109-21kworker/u2:110:00:370
3153999232200,19cyclictest46931-21kworker/u2:208:20:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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