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2026-01-31 - 19:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Sat Jan 31, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
350605522610,2sleep03506057-21awk08:25:310
348464999249220,19cyclictest3546012-21kworker/u2:211:06:130
350182022440,3chrt3501818-21memory08:10:300
349617922420,3chrt3496180-21grep07:50:260
353788022410,2chrt3537878-21df_inode10:20:170
350744922270,4chrt3507448-21/usr/sbin/munin08:30:310
354790122240,3chrt3547898-21ntpq10:55:430
348464999219185,23cyclictest3492067-21kworker/u2:207:38:450
348464999205174,20cyclictest3553602-21ntpq11:16:120
348464999205173,20cyclictest3546012-21kworker/u2:211:20:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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