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2026-01-17 - 17:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Sat Jan 17, 2026 12:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88201822500,3chrt882019-21/usr/sbin/munin11:25:240
82096822500,3chrt820965-21ntpq07:45:570
85853922390,2chrt858536-21ntpq10:00:410
88779622380,3chrt887797-21gcc11:45:420
86524522170,2sleep0865247-21ls10:25:230
88587422080,2sleep0885875-21cron11:40:000
89240722040,3sleep0892408-21/usr/sbin/munin12:01:200
86713821980,3sleep0867140-21awk10:31:150
81548521960,2chrt815486-21sendmail_mailqu07:26:150
87669921900,2sleep0876700-21/usr/sbin/munin11:05:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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