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2026-01-14 - 17:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Wed Jan 14, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
353326599303274,19cyclictest3540249-21kworker/u2:307:38:010
353326599242212,19cyclictest3590249-21kworker/u2:011:00:110
353326599238208,19cyclictest3558413-21kworker/u2:208:40:360
353326599237206,19cyclictest3590249-21kworker/u2:010:50:380
358735222300,2sleep03587355-21sed10:25:260
361838022290,3chrt3618377-21ps12:16:150
353326599228199,17cyclictest3529514-21kworker/u2:107:20:090
353326599228197,20cyclictest3540232-21kworker/u2:008:05:310
353326599226201,16cyclictest3611149-21kworker/u2:211:55:320
353326599224194,19cyclictest3562618-21kworker/u2:009:00:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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