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2026-01-30 - 08:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Fri Jan 30, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
274380125110,2sleep02743799-21open_inodes19:05:560
278031123030,3sleep02780312-21/usr/sbin/munin21:16:220
275105022610,3sleep02751052-21sed19:31:210
278977722500,4chrt2789765-21ntpq21:50:570
277393922490,3chrt2773942-21sort20:55:090
274456999244214,19cyclictest2821224-21kworker/u2:100:00:050
274456999241212,18cyclictest2821224-21kworker/u2:100:00:370
282671822360,2chrt2826716-21/usr/sbin/munin00:05:140
280459822350,3chrt2804599-21latency_hist22:45:070
279613022180,3chrt2796131-21latency_hist22:15:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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