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2026-01-27 - 18:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Tue Jan 27, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156273822550,3chrt1562736-21apt10:10:110
156964822520,2sleep01569651-21latency_hist10:35:060
159251222470,2chrt1592510-21/usr/sbin/munin11:56:150
151938222410,3chrt1519380-21ls07:35:060
156426022280,3sleep01564261-21/usr/sbin/munin10:15:210
151237699221190,21cyclictest29-21kswapd012:11:010
158555222070,2sleep01585554-21proc_pri11:31:130
153897722010,2sleep01538978-21cat08:45:070
152187822000,2sleep01521880-21man-db07:42:210
151237699198161,25cyclictest1520469-31find07:37:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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