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2026-01-13 - 02:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Tue Jan 13, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287425222660,3chrt2874250-21memory23:50:270
279567322660,2sleep02795674-21uname19:05:460
282043422560,2sleep02820432-21if_err_eth020:35:220
279650199246216,18cyclictest2852030-21kworker/u2:022:45:370
279650199241212,17cyclictest2806283-21kworker/u2:220:00:390
284770722390,4chrt2847702-21irqstats22:15:250
279650199239209,18cyclictest2839531-21kworker/u2:122:10:370
279650199237207,18cyclictest2800694-21kworker/u2:019:45:390
279650199237206,19cyclictest2883769-21kworker/u2:000:35:330
279650199236207,18cyclictest2786932-21kworker/u2:219:20:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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