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2026-03-04 - 05:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Wed Mar 04, 2026 00:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
225440822490,3chrt2254409-21latency21:35:260
224242622440,3chrt2242427-21timerwakeupswit20:51:190
222436422420,3chrt2224362-21users19:46:230
221284722420,3chrt2212845-21ntpq19:05:470
226843922380,3chrt2268437-21ntp_kernel_err22:25:300
224345022370,3chrt2243440-21ntpq20:55:480
223639522300,3chrt2236397-21awk20:30:310
228069922280,3chrt2280702-21cpu23:10:100
221367399218188,18cyclictest2235565-21kworker/u2:221:06:180
221367399215187,17cyclictest2304293-21kworker/u2:000:36:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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