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2026-02-16 - 01:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Sun Feb 15, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
248739299324289,22cyclictest2496476-21collect207:41:130
248739299309279,20cyclictest29-21kswapd011:26:130
248752623010,3sleep02487527-21cat07:10:120
255656122940,3chrt2556562-21grep11:16:210
249774022580,3chrt2497741-21collect207:45:480
256898722560,2sleep02568988-21gzip12:01:170
248739299252224,18cyclictest29-21kswapd011:30:220
253363722510,3chrt2533635-21df_inode09:55:180
248739299248218,19cyclictest2500610-21kworker/u2:207:56:190
250982622420,3chrt2509828-21latency_hist08:30:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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