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2026-01-30 - 21:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Fri Jan 30, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299172099301241,48cyclictest2995167-21ntpq07:21:110
308368722590,3sleep03083691-21cut12:40:000
303246822530,4chrt3032466-21irqstats09:35:230
304780022420,2sleep03047802-21uname10:30:260
299172099237206,20cyclictest29-21kswapd007:41:020
299172099224195,19cyclictest29-21kswapd007:45:210
299172099216187,19cyclictest29-21kswapd007:37:500
299172099211180,19cyclictest3051676-21kworker/u2:111:20:380
306050422090,2sleep03060505-21collect211:15:400
305031722090,3sleep03050318-21latency_hist10:40:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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