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2026-02-01 - 19:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Sun Feb 01, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
399715923110,2sleep03997160-21date08:15:060
398665922500,2sleep03986657-21sendmail_mailtr07:36:180
404523222230,4chrt4045233-21/usr/sbin/munin11:06:170
406204822050,2sleep04062049-21cat12:06:190
397891299202172,18cyclictest4012456-21kworker/u2:209:20:090
397891299202171,19cyclictest4038920-21kworker/u2:110:50:320
397891299198172,16cyclictest3983103-21kworker/u2:207:40:350
405218321970,2sleep04052185-21grep11:31:160
397891299197167,18cyclictest4058893-21kworker/u2:012:30:040
397891299194164,19cyclictest4063021-21kworker/u2:212:10:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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