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2026-01-13 - 16:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Tue Jan 13, 2026 12:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
308625222610,3sleep03086256-21switchtime09:51:180
304208299246215,20cyclictest3036950-21kworker/u2:107:37:260
313054022440,3chrt3130537-21ntpq12:30:500
310495122430,3chrt3104952-21systemctl11:00:040
304208299241209,20cyclictest3036950-21kworker/u2:107:30:380
309176922340,3chrt3091770-21mailstats10:11:180
304208299232199,20cyclictest3096812-21kworker/u2:110:40:380
304208299231202,17cyclictest3060660-21kworker/u2:208:40:030
304208299231199,20cyclictest3051009-21kworker/u2:008:00:010
304208299228196,19cyclictest3108104-21kworker/u2:111:15:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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