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2026-02-27 - 03:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Fri Feb 27, 2026 00:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
400906922590,3chrt1-21systemd22:00:020
403303922550,3chrt4033037-21irqstats23:25:250
396164999247217,18cyclictest4041085-21kworker/u2:100:00:370
396818922440,3chrt3968185-21users19:31:370
400346122380,3chrt4003459-21cron21:40:000
404793422360,2chrt4047930-21diskstats00:20:190
396164999229198,19cyclictest3988659-21kworker/u2:020:56:160
396164999222193,17cyclictest3988659-21kworker/u2:021:46:180
396164999221192,18cyclictest4018725-21kworker/u2:123:16:170
396164999220191,18cyclictest3982955-21kworker/u2:220:31:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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