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2026-01-29 - 08:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot2.osadl.org (updated Thu Jan 29, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231148722700,5chrt2311475-21ntpq22:40:510
228085722630,3chrt2280845-21ntpq20:50:550
233734422610,2sleep02337345-21df00:15:130
225845522530,3chrt2258452-21ntpq19:30:320
232659222410,2sleep02326595-21latency23:35:260
226915022360,3chrt1-21systemd20:10:020
227941122320,3chrt2279405-21ntpq20:45:440
225242999209178,19cyclictest2266379-21kworker/u2:121:20:380
225242999205176,18cyclictest2329485-21kworker/u2:200:20:270
225242999205174,19cyclictest2329485-21kworker/u2:200:25:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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