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2026-02-19 - 19:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Thu Feb 19, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26610199282252,20cyclictest29-21kswapd007:45:210
26610199250208,19cyclictest271681-21kworker/u2:307:39:240
29465022490,4chrt294646-21ntpq08:51:090
31403222430,4chrt314022-21ntpq10:00:430
33224522420,3chrt332243-21ntp_states11:06:070
32501022310,2chrt325013-21grep10:40:250
35457722290,4chrt354579-21proc_pri12:26:140
33448822270,2sleep0334489-21cat11:15:070
26610199214185,19cyclictest337682-21kworker/u2:111:35:040
26610199205175,18cyclictest274474-21kworker/u2:208:00:090
35002522030,2sleep0350026-21uname12:10:240
26610199203173,18cyclictest348336-21kworker/u2:112:20:040
26610199203173,18cyclictest307960-21kworker/u2:109:45:110
26610199203168,23cyclictest326053-21kworker/u2:210:45:440
28902222020,2sleep0289023-21/usr/sbin/munin08:30:550
26610199202171,19cyclictest341386-21kworker/u2:212:05:040
26610199201174,18cyclictest317683-21kworker/u2:210:30:320
26610199201171,18cyclictest274474-21kworker/u2:207:40:240
26610199201170,19cyclictest307960-21kworker/u2:110:05:380
30375522000,3sleep0303756-21sh09:25:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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