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2026-03-01 - 23:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Sun Mar 01, 2026 12:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
98306699294264,19cyclictest29-21kswapd007:41:030
105182322600,4chrt1051824-21ld11:15:320
105021722530,4chrt1050216-21/usr/sbin/munin11:10:210
103978022430,3chrt1039778-21users10:31:220
102993622410,2chrt1029937-21switchtime09:56:180
98306699215176,26cyclictest990957-31find07:36:410
98671522080,2sleep0986717-21switchtime07:21:190
104615822020,3sleep01046159-21/usr/sbin/munin10:55:260
98306699197168,19cyclictest989089-21kworker/u2:107:45:210
106846321950,4chrt1068209-21/usr/sbin/munin12:15:270
107259321910,3chrt1072594-21if_eth012:30:210
98306699188157,19cyclictest1025380-21kworker/u2:109:50:060
102216221840,2sleep01022165-21latency_hist09:30:060
98306699182151,20cyclictest1012372-21kworker/u2:209:20:050
98306699176146,19cyclictest1004028-21kworker/u2:008:55:010
107085421760,4chrt1070852-21sshd12:24:290
98889921720,2sleep0988897-21if_err_eth007:30:220
103101221720,4chrt1031007-21ntpq10:00:450
104859121700,5chrt1048594-21cut11:05:010
100958221700,4chrt1009583-21latency_hist08:45:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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