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2026-02-07 - 05:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Sat Feb 07, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
257832822460,3chrt2578326-21sshd00:14:540
252525522440,2sleep02525253-21idleruntime21:00:210
249435899200173,17cyclictest2530254-21kworker/u2:021:25:100
255145221980,2sleep02551454-21latency_hist22:35:000
249435899196169,18cyclictest2550078-21kworker/u2:023:26:160
249435899193167,17cyclictest2495753-21kworker/u2:219:41:210
249435899190163,17cyclictest2550078-21kworker/u2:023:05:080
249435899190156,23cyclictest2574507-21b-backup00:00:000
249435899189161,19cyclictest2563785-21kworker/u2:123:25:040
249435899184157,17cyclictest2538938-21kworker/u2:022:10:080
249435899181155,17cyclictest2495753-21kworker/u2:219:46:190
249435899181155,17cyclictest2495753-21kworker/u2:219:16:170
249435899180153,18cyclictest2495753-21kworker/u2:219:55:090
249435899180152,18cyclictest2550078-21kworker/u2:023:11:160
249435899179154,16cyclictest2538938-21kworker/u2:022:06:180
252917821780,2sleep02529177-21true21:15:020
249435899178152,17cyclictest2571684-21kworker/u2:000:15:070
249435899177151,18cyclictest2556090-21kworker/u2:122:51:180
249435899177150,18cyclictest2579773-21kworker/u2:100:21:180
254213721750,3chrt2542138-21missed_timers22:00:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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