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2026-02-27 - 21:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Fri Feb 27, 2026 12:44:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1360799299264,22cyclictest23668-21awk07:45:220
1360799261223,26cyclictest21661-21systemd07:38:010
8485822580,3sleep084859-21ls11:25:070
4759822500,4chrt47595-21ntpq09:10:420
10154822500,4chrt101550-21wc12:25:070
6420222380,3chrt64199-21memory10:10:290
6832522290,4chrt68324-21/usr/sbin/munin10:25:270
1360799222190,20cyclictest47107-21kworker/u2:009:36:170
1360799213181,20cyclictest22645-21ntpq07:41:020
1360799210180,19cyclictest86601-21kworker/u2:012:01:160
7780922080,4chrt77786-21munin-run11:00:020
10458922020,3sleep0104592-21cut12:35:240
9882922010,2sleep098827-21cpu12:15:120
9386221960,2sleep093864-21mailstats11:56:190
1360799188158,19cyclictest76405-21kworker/u2:311:15:070
1360799187156,20cyclictest76402-21kworker/u2:210:55:030
1360799187155,20cyclictest86601-21kworker/u2:012:10:250
1360799185152,20cyclictest35065-21kworker/u2:108:35:120
1360799182147,24cyclictest55484-21kworker/u2:110:31:190
1360799180147,22cyclictest73392-21md.daily10:43:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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