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2026-02-18 - 18:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Wed Feb 18, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
396708999302244,47cyclictest29-21kswapd007:40:210
396708999260230,19cyclictest29-21kswapd011:40:200
396708999258197,48cyclictest29-21kswapd007:45:220
396708999257222,23cyclictest3975508-21time-dir07:40:020
403037022420,3chrt4030360-21ntpq10:55:470
400361222410,3chrt4003610-21diskstats09:20:180
396708999223193,20cyclictest29-21kswapd011:36:090
396720222060,2sleep03967201-21ls07:10:080
399857322050,4chrt3998574-21mailstats09:01:170
401037822020,2sleep04010379-21latency_hist09:45:060
396708999198166,20cyclictest3985698-21kworker/u2:208:20:030
396873121950,3chrt3968732-21basename07:15:240
396708999195162,22cyclictest3990485-21anacron08:32:090
396708999189159,18cyclictest4003396-21kworker/u2:209:30:320
396708999184154,19cyclictest3989890-21kworker/u2:208:40:070
396858121790,3chrt3968583-21grep07:15:070
396708999179154,16cyclictest4038708-21kworker/u2:111:30:080
396708999176146,19cyclictest3975378-21kworker/u2:108:11:180
396708999173145,19cyclictest3968965-21kworker/u2:107:26:180
403430321720,4chrt4034302-21/usr/sbin/munin11:10:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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