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2026-01-28 - 04:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Wed Jan 28, 2026 00:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
175901124860,2sleep01759012-21/usr/sbin/munin19:05:560
183566522690,3chrt1835654-21ntpq23:41:040
178941522560,3chrt1789413-21memory20:55:300
181573322510,3chrt1815734-21idleruntime22:30:220
179371122360,2chrt1793706-21ntpq21:10:420
181133422120,2sleep01811336-21latency_hist22:15:060
175978299205177,18cyclictest1836641-21kworker/u2:100:00:370
175978299202175,16cyclictest1818678-21kworker/u2:023:40:030
175978299200172,18cyclictest1842045-21kworker/u2:000:20:370
185005721980,2sleep01850058-21latency_hist00:35:070
175978299196167,18cyclictest1770951-21kworker/u2:320:00:140
175978299196166,19cyclictest1770951-21kworker/u2:320:05:360
175978299195166,18cyclictest1818678-21kworker/u2:023:20:020
175978299194166,17cyclictest1770515-21kworker/u2:219:55:120
175978299194163,19cyclictest1814107-21kworker/u2:222:40:020
175978299192163,18cyclictest1783247-21kworker/u2:221:35:020
175978299192162,18cyclictest1842045-21kworker/u2:000:20:070
175978299190159,19cyclictest1818678-21kworker/u2:023:06:250
175978299189160,18cyclictest1783247-21kworker/u2:221:55:370
175978299186158,17cyclictest1775509-21kworker/u2:120:10:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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