You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-14 - 04:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Wed Jan 14, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
332665022990,3sleep03326651-21ntpq21:30:420
328714899256227,18cyclictest3360984-21kworker/u2:100:00:030
328714899254223,19cyclictest3309878-21kworker/u2:220:40:380
328714899249218,19cyclictest3309878-21kworker/u2:220:35:380
329309822450,3chrt3293097-21sed19:30:270
328714899242213,17cyclictest3334553-21kworker/u2:323:25:380
328714899241210,19cyclictest3287655-21kworker/u2:120:10:380
328714899232201,19cyclictest3334553-21kworker/u2:323:11:180
328714899229200,17cyclictest3334553-21kworker/u2:323:21:180
328714899228197,19cyclictest3321962-21kworker/u2:121:30:020
329877922260,4chrt3298776-21ntpq19:50:400
328714899224195,18cyclictest3287655-21kworker/u2:119:35:380
328714899222191,19cyclictest3360984-21kworker/u2:100:40:020
328714899221193,17cyclictest3303879-21kworker/u2:020:25:380
328714899221190,19cyclictest3303879-21kworker/u2:020:30:140
328714899220190,18cyclictest3326150-21kworker/u2:021:50:360
328714899216186,19cyclictest3360984-21kworker/u2:100:26:190
328714899216186,18cyclictest3326150-21kworker/u2:021:35:320
328714899216185,19cyclictest3334553-21kworker/u2:322:40:070
328714899216185,19cyclictest3287655-21kworker/u2:119:50:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional