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2026-02-22 - 20:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Sun Feb 22, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174845399361332,19cyclictest1752644-21kworker/u2:207:45:250
174845399320286,22cyclictest1760277-21ntpq07:51:060
174845399314285,19cyclictest29-21kswapd007:41:020
178680722930,3sleep01786808-21/usr/sbin/munin09:26:150
180142722560,3sleep01801430-21sh10:20:000
174845399247214,21cyclictest1761174-21/usr/sbin/munin07:55:230
177797622440,3chrt1777974-21df_inode08:55:160
178393022430,2chrt1783920-21ntpq09:15:590
184051122390,3chrt1840512-21wc12:40:070
174845399237208,18cyclictest1752644-21kworker/u2:207:39:550
175173322300,3chrt1751723-21ntpq07:20:390
181594622270,2sleep01815947-21ld11:10:570
174845399213182,20cyclictest1804242-21kworker/u2:110:31:180
174845399210179,19cyclictest1801952-21kworker/u2:210:21:200
176803922000,2sleep01768040-21sh08:20:020
174845399200170,19cyclictest1832098-21kworker/u2:012:15:120
174845399199168,19cyclictest1801952-21kworker/u2:210:40:030
183708321980,4chrt1837081-21mailstats12:26:180
174845399195166,19cyclictest1801952-21kworker/u2:210:41:180
174845399195165,18cyclictest1832098-21kworker/u2:012:15:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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