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2026-03-09 - 06:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Mon Mar 09, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48222799315284,20cyclictest29-21kswapd000:11:030
53846322610,4chrt538451-21ntpq22:30:480
49485022470,3sleep0494852-21sort19:55:070
52043122460,3chrt520429-21ntp_states21:26:000
57100622430,3chrt1-21systemd00:30:030
56107522240,3sleep0561077-21timerandwakeup23:51:230
48222799222194,16cyclictest561982-21kworker/u2:000:25:040
48222799221190,19cyclictest538515-21kworker/u2:100:00:310
48222799214184,18cyclictest538515-21kworker/u2:123:05:050
53584722120,2sleep0535849-21grep22:21:160
48222799206176,19cyclictest538515-21kworker/u2:123:15:040
53516322030,3chrt1-21systemd22:20:040
48222799203175,19cyclictest561982-21kworker/u2:000:30:080
48222799203174,18cyclictest526794-21kworker/u2:222:10:030
56750222010,3sleep0567503-21ps00:16:170
48222799200172,17cyclictest538515-21kworker/u2:123:26:190
48222799200170,18cyclictest521229-21kworker/u2:021:40:010
52870921990,2sleep0528710-21ld21:55:480
48222799198167,19cyclictest538515-21kworker/u2:122:40:040
48222799196168,17cyclictest511908-21kworker/u2:221:15:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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