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2026-02-14 - 05:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Sat Feb 14, 2026 00:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174983199263232,19cyclictest1827819-21kworker/u2:000:00:120
179533222610,4chrt1795330-21users21:51:200
176457822550,3chrt1763897-21/usr/sbin/munin20:01:170
178268022540,3chrt1782679-21/usr/sbin/munin21:06:180
184075222520,4chrt1840753-21mailstats00:36:180
174983199236207,18cyclictest1827819-21kworker/u2:000:00:060
174983199236206,18cyclictest1831670-21kworker/u2:200:10:050
175456422350,4chrt1754561-21ntpq19:25:510
174983199218187,19cyclictest1754018-21kworker/u2:020:15:030
174990722170,4chrt1749908-21latency_hist19:10:080
174983199216185,19cyclictest1767529-21kworker/u2:120:25:040
174983199215185,18cyclictest1798584-21kworker/u2:222:30:050
174983199214186,17cyclictest1831670-21kworker/u2:200:20:050
174983199213184,18cyclictest1821833-21kworker/u2:123:35:050
174983199212182,18cyclictest1798584-21kworker/u2:222:35:050
174983199209180,18cyclictest1780916-21kworker/u2:121:05:030
174983199207179,17cyclictest1754018-21kworker/u2:019:55:040
174983199206178,18cyclictest1798584-21kworker/u2:222:15:050
174983199206177,17cyclictest1767529-21kworker/u2:120:40:040
174983199206175,20cyclictest1754018-21kworker/u2:019:40:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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