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2026-02-04 - 04:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot2.osadl.org (updated Wed Feb 04, 2026 00:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107182122940,2sleep01071824-21cut22:35:260
103056822700,3chrt1030567-21awk20:06:210
108180922610,4chrt1081797-21ntpq23:10:570
103899322550,3chrt1038991-21users20:36:220
102343322540,3chrt1023431-21/usr/sbin/munin19:41:120
102174922530,2sleep01021752-21wc19:35:300
106461422500,3chrt1064615-21ls22:10:070
107523222480,4chrt1075230-21vmstat22:46:270
110343922450,3chrt1103437-21df_inode00:30:170
108760522450,2sleep01087607-21mailstats23:31:260
104811422280,4chrt1048115-21awk21:10:240
101437899217188,18cyclictest29-21kswapd000:05:210
103537221950,2sleep01035373-21latency_hist20:25:060
101437899194163,19cyclictest1089611-21kworker/u2:000:00:080
101437899188157,18cyclictest1089611-21kworker/u2:000:00:160
101437899186155,19cyclictest1104996-21kworker/u2:100:40:040
101437899186155,19cyclictest1089611-21kworker/u2:000:20:120
101437899185152,20cyclictest1077495-21kworker/u2:023:00:030
101437899184153,19cyclictest1077495-21kworker/u2:023:05:110
101437899183148,23cyclictest1093559-21md.daily23:53:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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