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2026-09-15 - 07:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Tue Sep 15, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30550501160irq/54-eth0-tx-0-21swapper/719:06:149
6580210794sleep80-21swapper/819:07:2210
30549501030irq/53-eth0-rx-0-21swapper/219:08:224
3054950970irq/53-eth0-rx-0-21swapper/419:06:096
12250970irq/42-ahci0-21swapper/119:05:121
3054950940irq/53-eth0-rx-0-21swapper/319:05:235
3054950940irq/53-eth0-rx-0-21swapper/1019:07:152
3054950900irq/53-eth0-rx-0-21swapper/519:06:157
659427369sleep60-21swapper/619:07:328
646126753sleep00-21swapper/019:05:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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