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2026-05-04 - 06:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Mon May 04, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501340irq/42-ahci0-21swapper/219:08:554
128501170irq/42-ahci0-21swapper/119:09:371
4793210895sleep90-21swapper/919:05:5811
128501030irq/42-ahci0-21swapper/819:08:3910
991850950irq/53-eth0-rx-0-21swapper/1019:05:502
991850920irq/53-eth0-rx-0-21swapper/319:06:395
12850910irq/42-ahci0-21swapper/719:08:169
991950880irq/54-eth0-tx-0-21swapper/519:05:117
991850780irq/53-eth0-rx-0-21swapper/419:06:196
14050750irq/18-ehci_hcd0-21swapper/1119:09:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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