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2026-03-19 - 00:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Wed Mar 18, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501140irq/42-ahci0-21swapper/207:09:074
9918501130irq/53-eth0-rx-0-21swapper/107:09:151
9918501120irq/53-eth0-rx-0-21swapper/407:09:286
991850940irq/53-eth0-rx-0-21swapper/807:06:4510
1780329483sleep100-21swapper/1007:05:152
991850930irq/53-eth0-rx-0-21swapper/707:08:389
991850930irq/53-eth0-rx-0-21swapper/307:09:395
115050920irq/18-i801_smb0-21swapper/1107:06:413
991850900irq/53-eth0-rx-0-21swapper/507:07:577
1951427465sleep90-21swapper/907:07:5111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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