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2026-08-03 - 20:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Mon Aug 03, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9330210895sleep90-21swapper/907:05:5111
30549501070irq/53-eth0-rx-0-21swapper/707:09:019
9459210691sleep00-21swapper/007:07:300
30549501040irq/53-eth0-rx-0-21swapper/207:06:374
9401210291sleep50-21swapper/507:06:487
968029893sleep30-21swapper/307:09:465
3054950960irq/53-eth0-rx-0-21swapper/107:09:401
3055050930irq/54-eth0-tx-0-21swapper/807:05:1610
3054950910irq/53-eth0-rx-0-21swapper/407:05:036
3054950890irq/53-eth0-rx-0-21swapper/1107:06:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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