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2025-06-29 - 00:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Sat Jun 28, 2025 12:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501110irq/42-ahci0-21swapper/207:09:364
122501110irq/42-ahci0-21swapper/107:09:081
23777210895sleep30-21swapper/307:07:145
23737210896sleep80-21swapper/807:06:4310
23688210694sleep60-21swapper/607:06:058
2963450990irq/53-eth0-rx-0-21swapper/707:09:249
2963450960irq/53-eth0-rx-0-21swapper/507:07:557
2963450870irq/53-eth0-rx-0-21swapper/907:05:1511
2963450720irq/53-eth0-rx-0-21swapper/407:06:326
2963450720irq/53-eth0-rx-0-21swapper/1107:05:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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