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2025-08-27 - 21:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Wed Aug 27, 2025 12:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501280irq/42-ahci0-21swapper/307:08:555
29710211197sleep100-21swapper/1007:08:112
29539210793sleep80-21swapper/807:05:5710
29687210693sleep40-21swapper/407:07:536
29596210693sleep70-21swapper/707:06:449
122501030irq/42-ahci0-21swapper/107:08:481
122501010irq/42-ahci0-21swapper/207:09:094
3066350890irq/52-eth0-rx-0-21swapper/1107:05:233
2951728575sleep50-21swapper/507:05:427
2987428078sleep90-21swapper/907:09:4611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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