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2026-06-18 - 08:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Thu Jun 18, 2026 00:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501190irq/53-eth0-rx-0-21swapper/219:10:004
19085210691sleep00-21swapper/019:08:040
18935210693sleep70-21swapper/719:06:119
19032210591sleep60-21swapper/619:07:218
19057210290sleep50-21swapper/519:07:447
30549501000irq/53-eth0-rx-0-21swapper/119:08:151
3054950940irq/53-eth0-rx-0-21swapper/319:05:085
12250930irq/42-ahci0-21swapper/819:08:5010
3055050870irq/54-eth0-tx-0-21swapper/419:05:176
1898928074sleep100-21swapper/1019:06:492
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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