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2026-02-01 - 19:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Sun Feb 01, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6982211195sleep10-21swapper/107:07:191
991850950irq/53-eth0-rx-0-21swapper/207:07:364
991850930irq/53-eth0-rx-0-21swapper/507:07:187
991950920irq/54-eth0-tx-0-21swapper/307:07:035
991850920irq/53-eth0-rx-0-21swapper/707:05:029
991850920irq/53-eth0-rx-0-21swapper/407:05:496
991850850irq/53-eth0-rx-0-21swapper/1107:05:133
991850810irq/53-eth0-rx-0-21swapper/1007:06:532
991850700irq/53-eth0-rx-0-21swapper/807:07:1110
686726354sleep90-21swapper/907:05:5011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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