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2026-03-19 - 07:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Thu Mar 19, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501170irq/53-eth0-rx-0-21swapper/219:09:304
8911210997sleep10-21swapper/119:06:201
8919210693sleep70-21swapper/719:06:259
9918501020irq/53-eth0-rx-0-21swapper/419:06:376
991850950irq/53-eth0-rx-0-21swapper/519:06:597
12850940irq/42-ahci0-21swapper/319:09:285
991850910irq/53-eth0-rx-0-21swapper/1119:07:183
991850890irq/53-eth0-rx-0-21swapper/819:07:2410
172450700irq/56-eth1-rx-0-21swapper/919:09:3611
899726858sleep60-21swapper/619:07:258
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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