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2026-05-15 - 00:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Thu May 14, 2026 12:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9605210691sleep00-21swapper/007:05:030
128501060irq/42-ahci0-21swapper/107:05:201
12554210695sleep100-21swapper/1007:07:242
12454210692sleep70-21swapper/707:06:109
12850960irq/42-ahci0-21swapper/407:09:356
991850950irq/53-eth0-rx-0-21swapper/307:07:135
991850930irq/53-eth0-rx-0-21swapper/507:05:077
1248929380sleep110-21swapper/1107:06:373
991850900irq/53-eth0-rx-0-21swapper/207:05:194
991850880irq/53-eth0-rx-0-21swapper/807:05:2510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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