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2026-10-31 - 12:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot3.osadl.org (updated Sat Oct 31, 2026 00:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6800501120irq/52-eth0-rx-0-21swapper/219:05:094
124501120irq/42-ahci0-21swapper/119:08:291
6800501090irq/52-eth0-rx-0-21swapper/819:08:2410
12450950irq/42-ahci0-21swapper/719:08:239
680050920irq/52-eth0-rx-0-21swapper/419:05:456
680050910irq/52-eth0-rx-0-21swapper/519:05:537
680050910irq/52-eth0-rx-0-21swapper/319:05:195
680050880irq/52-eth0-rx-0-21swapper/1119:06:093
372027472sleep90-21swapper/919:09:4611
115450730irq/18-i801_smb0-21swapper/1019:05:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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