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2026-02-18 - 14:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Feb 18, 2026 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501110irq/42-ahci0-21swapper/107:08:261
9918501050irq/53-eth0-rx-0-21swapper/207:08:324
991950970irq/54-eth0-tx-0-21swapper/407:05:286
2990829782sleep100-21swapper/1007:05:202
991850960irq/53-eth0-rx-0-21swapper/507:06:157
3145729588sleep80-21swapper/807:09:4210
991850930irq/53-eth0-rx-0-21swapper/707:07:319
991850880irq/53-eth0-rx-0-21swapper/307:05:355
3124026656sleep90-21swapper/907:07:3111
991850650irq/53-eth0-rx-0-21swapper/1107:05:253
3125025955sleep60-21swapper/607:07:398
3108625955sleep00-21swapper/007:05:340
3158499340cyclictest0-21swapper/009:19:240
31584993215cyclictest0-21swapper/009:14:460
3158499310cyclictest0-21swapper/008:29:220
31626993014cyclictest12850irq/42-ahci07:24:453
12850300irq/42-ahci0-21swapper/009:20:010
31626992914cyclictest0-21swapper/1107:13:443
31626992914cyclictest0-21swapper/1107:13:443
3162699290cyclictest0-21swapper/1109:13:093
31622992726cyclictest991850irq/53-eth0-rx-08:29:319
3160899270cyclictest0-21swapper/309:40:285
3160899270cyclictest0-21swapper/309:40:285
31626992510cyclictest991850irq/53-eth0-rx-07:25:193
31584992510cyclictest11264-21taskset07:22:470
3158499246cyclictest991850irq/53-eth0-rx-07:26:110
31595992221cyclictest991850irq/53-eth0-rx-08:29:301
3158499193cyclictest0-21swapper/010:29:220
3158499190cyclictest0-21swapper/008:08:180
3162699186cyclictest0-21swapper/1107:43:513
3162699180cyclictest0-21swapper/1109:23:243
3162499181cyclictest991850irq/53-eth0-rx-10:15:1011
3162499181cyclictest11534-21ssh12:08:0011
3162499181cyclictest0-21swapper/912:32:2511
3162499181cyclictest0-21swapper/912:02:3311
3162499181cyclictest0-21swapper/911:58:1511
3162499181cyclictest0-21swapper/911:35:4911
3162499181cyclictest0-21swapper/911:25:1911
3162499181cyclictest0-21swapper/911:12:5111
3162499181cyclictest0-21swapper/910:57:1711
3162499181cyclictest0-21swapper/910:43:5211
3162499181cyclictest0-21swapper/910:11:1411
3162499181cyclictest0-21swapper/910:05:0711
3162499181cyclictest0-21swapper/909:52:5711
3162499181cyclictest0-21swapper/909:52:5711
3162499181cyclictest0-21swapper/909:30:1011
3162499181cyclictest0-21swapper/909:27:5711
3162499181cyclictest0-21swapper/909:27:5711
3162499181cyclictest0-21swapper/909:21:3411
3162499181cyclictest0-21swapper/909:16:4911
3162499181cyclictest0-21swapper/907:30:1811
31620991817cyclictest991850irq/53-eth0-rx-08:29:407
31624991716cyclictest10692-1kworker/9:1H08:46:2511
31624991716cyclictest0-21swapper/910:03:1111
31624991716cyclictest0-21swapper/908:34:3511
3162499171cyclictest0-21swapper/911:53:4611
3162499170cyclictest16409-21ssh09:55:5411
3162499170cyclictest10692-1kworker/9:1H08:29:4111
3162499170cyclictest10692-1kworker/9:1H08:20:0111
3162499170cyclictest0-21swapper/912:27:0311
3162499170cyclictest0-21swapper/912:20:4111
3162499170cyclictest0-21swapper/912:17:2611
3162499170cyclictest0-21swapper/912:12:4811
3162499170cyclictest0-21swapper/911:30:2511
3162499170cyclictest0-21swapper/911:20:3211
3162499170cyclictest0-21swapper/911:17:3511
3162499170cyclictest0-21swapper/911:08:4011
3162499170cyclictest0-21swapper/910:48:0111
3162499170cyclictest0-21swapper/910:35:2911
3162499170cyclictest0-21swapper/910:32:4711
3162499170cyclictest0-21swapper/909:39:3811
3162499170cyclictest0-21swapper/909:39:3711
3162499170cyclictest0-21swapper/909:11:0811
3162399175cyclictest0-21swapper/808:30:0110
31622991712cyclictest7885-21users08:00:279
31621991715cyclictest25302-21snmp_rack3slot911:51:468
31620991715cyclictest31646-21ssh11:57:257
31601991715cyclictest2308-21snmpd11:36:274
31584991715cyclictest2345-21lldpd08:12:270
3158499170cyclictest0-21swapper/007:19:510
3162699160cyclictest0-21swapper/1110:37:133
31624991615cyclictest991850irq/53-eth0-rx-11:45:0611
31624991615cyclictest0-21swapper/912:35:5711
31624991615cyclictest0-21swapper/911:02:0511
31624991615cyclictest0-21swapper/907:56:2211
31624991615cyclictest0-21swapper/907:54:2811
31624991615cyclictest0-21swapper/907:15:1011
3162499160cyclictest0-21swapper/909:05:2711
31621991614cyclictest12933-21snmp_rack3slot911:40:598
31601991614cyclictest2308-21snmpd11:54:284
31601991614cyclictest2308-21snmpd09:41:414
31601991614cyclictest2308-21snmpd09:41:414
3160199160cyclictest0-21swapper/207:20:394
3159599164cyclictest23472-21diskmemload09:28:241
3159599164cyclictest23472-21diskmemload09:28:231
31595991614cyclictest0-21swapper/112:13:361
31595991614cyclictest0-21swapper/112:02:021
31595991614cyclictest0-21swapper/109:58:471
31584991615cyclictest0-21swapper/007:10:260
31584991615cyclictest0-21swapper/007:10:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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