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2026-01-28 - 08:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Jan 28, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32698210491sleep60-21swapper/619:06:488
128501010irq/42-ahci0-21swapper/819:09:0310
991850990irq/53-eth0-rx-0-21swapper/119:08:401
12850990irq/42-ahci0-21swapper/219:08:534
3275329585sleep110-21swapper/1119:07:293
991950940irq/54-eth0-tx-0-21swapper/319:05:115
991850920irq/53-eth0-rx-0-21swapper/419:07:456
991850900irq/53-eth0-rx-0-21swapper/719:06:119
991850870irq/53-eth0-rx-0-21swapper/519:06:487
50027974sleep90-21swapper/919:09:3911
3263726654sleep00-21swapper/019:06:060
48726260sleep100-21swapper/1019:09:282
67799290cyclictest0-21swapper/1119:27:573
67799290cyclictest0-21swapper/1119:27:573
669992218cyclictest30742-21ssh22:07:105
677991911cyclictest3837-21diskstats19:55:133
67699192cyclictest268572sleep1022:58:192
67599192cyclictest0-21swapper/921:30:5511
677991817cyclictest20471-21chrt20:15:593
676991817cyclictest0-21swapper/1000:05:592
676991816cyclictest9494-21snmp_rack3slot920:01:132
676991816cyclictest3156-21ssh00:00:052
676991816cyclictest20776-21ssh21:31:472
67699181cyclictest991950irq/54-eth0-tx-23:23:332
67699181cyclictest991850irq/53-eth0-rx-23:41:262
67699181cyclictest991850irq/53-eth0-rx-23:11:292
67699181cyclictest991850irq/53-eth0-rx-23:01:002
67699181cyclictest991850irq/53-eth0-rx-22:51:352
67699181cyclictest991850irq/53-eth0-rx-22:40:122
67699181cyclictest991850irq/53-eth0-rx-22:40:122
67699181cyclictest991850irq/53-eth0-rx-21:53:012
67699181cyclictest991850irq/53-eth0-rx-21:40:582
67699181cyclictest991850irq/53-eth0-rx-21:10:142
67699181cyclictest12850irq/42-ahci23:58:552
67599182cyclictest0-21swapper/921:13:4611
67599181cyclictest0-21swapper/923:45:0511
67599181cyclictest0-21swapper/923:18:1311
67599181cyclictest0-21swapper/923:07:1711
67599181cyclictest0-21swapper/922:49:5511
67599181cyclictest0-21swapper/922:33:5411
67599181cyclictest0-21swapper/922:25:2111
67599181cyclictest0-21swapper/922:25:2011
67599181cyclictest0-21swapper/922:16:5211
67599181cyclictest0-21swapper/922:02:2111
67599181cyclictest0-21swapper/921:46:3911
67599181cyclictest0-21swapper/921:26:2711
67599181cyclictest0-21swapper/921:22:3311
67599181cyclictest0-21swapper/921:16:1911
67599181cyclictest0-21swapper/920:55:0011
67599181cyclictest0-21swapper/900:33:2711
67599181cyclictest0-21swapper/900:25:1211
67599181cyclictest0-21swapper/900:12:0911
67599181cyclictest0-21swapper/900:06:2911
67599181cyclictest0-21swapper/900:02:3211
671991816cyclictest13332-21qemu-kvm20:08:407
67799170cyclictest0-21swapper/1121:30:423
676991716cyclictest0-21swapper/1023:35:472
676991715cyclictest29700-21perl20:30:132
67699170cyclictest991950irq/54-eth0-tx-21:45:182
67699170cyclictest991850irq/53-eth0-rx-23:50:012
67699170cyclictest991850irq/53-eth0-rx-23:45:242
67699170cyclictest991850irq/53-eth0-rx-23:32:022
67699170cyclictest991850irq/53-eth0-rx-23:16:212
67699170cyclictest991850irq/53-eth0-rx-22:35:432
67699170cyclictest991850irq/53-eth0-rx-22:35:432
67699170cyclictest991850irq/53-eth0-rx-22:31:292
67699170cyclictest991850irq/53-eth0-rx-22:26:262
67699170cyclictest991850irq/53-eth0-rx-22:26:262
67699170cyclictest991850irq/53-eth0-rx-22:06:012
67699170cyclictest991850irq/53-eth0-rx-21:55:152
67699170cyclictest991850irq/53-eth0-rx-21:35:552
67699170cyclictest991850irq/53-eth0-rx-21:25:542
67699170cyclictest991850irq/53-eth0-rx-21:21:102
67699170cyclictest991850irq/53-eth0-rx-21:15:232
67699170cyclictest991850irq/53-eth0-rx-19:45:272
67699170cyclictest991850irq/53-eth0-rx-19:40:172
67699170cyclictest991850irq/53-eth0-rx-19:40:172
67699170cyclictest991850irq/53-eth0-rx-19:15:162
67699170cyclictest991850irq/53-eth0-rx-19:14:002
67699170cyclictest991850irq/53-eth0-rx-00:31:062
67699170cyclictest991850irq/53-eth0-rx-00:26:242
67699170cyclictest991850irq/53-eth0-rx-00:20:372
67699170cyclictest991850irq/53-eth0-rx-00:11:512
67699170cyclictest98992sleep1022:16:022
67699170cyclictest60932chrt19:59:452
67699170cyclictest48792sleep1020:40:142
67699170cyclictest37662sleep1022:10:492
67699170cyclictest289662sleep1023:25:342
67699170cyclictest278752sleep1020:27:252
67699170cyclictest26752sleep1020:35:492
67699170cyclictest246172sleep1022:01:592
67699170cyclictest241962sleep1020:22:002
67699170cyclictest23982sleep1019:54:452
67699170cyclictest235402sleep1019:35:302
67699170cyclictest235402sleep1019:35:302
67699170cyclictest211282sleep1000:15:032
67699170cyclictest209212sleep1021:00:532
67699170cyclictest205322sleep1020:16:472
67699170cyclictest19502sleep1023:05:072
67699170cyclictest172432chrt20:55:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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