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2026-02-22 - 07:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Feb 22, 2026 00:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9450210795sleep100-21swapper/1019:07:102
6026210693sleep20-21swapper/219:05:014
9425210392sleep10-21swapper/119:06:481
9476210090sleep50-21swapper/519:07:287
991850980irq/53-eth0-rx-0-21swapper/819:09:0810
991850930irq/53-eth0-rx-0-21swapper/1119:06:563
991850920irq/53-eth0-rx-0-21swapper/319:05:445
991850900irq/53-eth0-rx-0-21swapper/719:05:379
991850850irq/53-eth0-rx-0-21swapper/419:05:216
961326563sleep90-21swapper/919:08:3311
947725955sleep60-21swapper/619:07:298
937325753sleep00-21swapper/019:06:110
986599320cyclictest0-21swapper/1122:14:363
986599310cyclictest0-21swapper/1119:28:073
9865992914cyclictest0-21swapper/1122:27:203
9865992914cyclictest0-21swapper/1119:17:503
9865992612cyclictest0-21swapper/1120:09:193
9865992019cyclictest29646-21chrt20:17:063
9865992019cyclictest262122sleep1120:14:543
986499192cyclictest991950irq/54-eth0-tx-00:05:472
986499192cyclictest991850irq/53-eth0-rx-22:26:052
986499192cyclictest991850irq/53-eth0-rx-22:01:182
986499192cyclictest991850irq/53-eth0-rx-21:49:422
986399192cyclictest0-21swapper/923:31:2211
986399192cyclictest0-21swapper/922:57:5411
986399192cyclictest0-21swapper/922:51:2111
986399192cyclictest0-21swapper/922:02:4511
986399192cyclictest0-21swapper/921:30:5111
986199192cyclictest0-21swapper/700:31:499
9823991917cyclictest47652sleep020:29:320
9865991817cyclictest9382sleep1120:23:303
986599180cyclictest0-21swapper/1122:24:413
9864991817cyclictest0-21swapper/1023:57:022
9864991817cyclictest0-21swapper/1023:50:552
9864991817cyclictest0-21swapper/1021:10:182
9864991817cyclictest0-21swapper/1019:16:402
9864991816cyclictest26229-21ssh22:46:532
9864991816cyclictest1728-21df_inode23:20:122
986499181cyclictest991950irq/54-eth0-tx-21:40:112
986499181cyclictest991950irq/54-eth0-tx-00:26:412
986499181cyclictest991950irq/54-eth0-tx-00:26:402
986499181cyclictest991850irq/53-eth0-rx-23:48:052
986499181cyclictest991850irq/53-eth0-rx-23:44:422
986499181cyclictest991850irq/53-eth0-rx-23:35:182
986499181cyclictest991850irq/53-eth0-rx-23:19:032
986499181cyclictest991850irq/53-eth0-rx-23:07:362
986499181cyclictest991850irq/53-eth0-rx-22:35:362
986499181cyclictest991850irq/53-eth0-rx-22:21:072
986499181cyclictest991850irq/53-eth0-rx-22:15:272
986499181cyclictest991850irq/53-eth0-rx-21:50:342
986499181cyclictest991850irq/53-eth0-rx-21:31:592
986499181cyclictest991850irq/53-eth0-rx-21:22:512
986499181cyclictest991850irq/53-eth0-rx-00:15:182
986499181cyclictest115050irq/18-i801_smb20:45:212
986499181cyclictest115050irq/18-i801_smb20:45:212
986399181cyclictest991950irq/54-eth0-tx-21:49:4411
986399181cyclictest9210-21ssh22:34:2911
986399181cyclictest741rcuc/921:16:1011
986399181cyclictest2045-1kworker/9:0H19:18:0711
986399181cyclictest12850irq/42-ahci22:09:1411
986399181cyclictest0-21swapper/923:58:1511
986399181cyclictest0-21swapper/923:54:5911
986399181cyclictest0-21swapper/923:43:2311
986399181cyclictest0-21swapper/923:05:1111
986399181cyclictest0-21swapper/923:04:4511
986399181cyclictest0-21swapper/922:25:1711
986399181cyclictest0-21swapper/922:16:4611
986399181cyclictest0-21swapper/921:50:2411
986399181cyclictest0-21swapper/921:37:2511
986399181cyclictest0-21swapper/921:12:3711
986399181cyclictest0-21swapper/900:22:5111
986399181cyclictest0-21swapper/900:11:2311
986399181cyclictest0-21swapper/900:09:4211
986199183cyclictest0-21swapper/723:52:039
9859991816cyclictest9978-21qemu-kvm22:35:087
9859991816cyclictest21277-21ssh00:28:477
9859991816cyclictest21277-21ssh00:28:467
984799182cyclictest0-21swapper/319:29:275
982399180cyclictest0-21swapper/022:14:000
9865991716cyclictest13415-21chrt19:14:343
9864991716cyclictest17779-1kworker/10:0H19:35:112
9864991716cyclictest17779-1kworker/10:0H19:31:042
9864991716cyclictest13234-21ssh23:30:052
9864991716cyclictest0-21swapper/1020:56:452
9864991716cyclictest0-21swapper/1020:51:372
986499170cyclictest991950irq/54-eth0-tx-00:20:372
986499170cyclictest991850irq/53-eth0-rx-23:25:462
986499170cyclictest991850irq/53-eth0-rx-23:10:242
986499170cyclictest991850irq/53-eth0-rx-22:55:112
986499170cyclictest991850irq/53-eth0-rx-22:50:062
986499170cyclictest991850irq/53-eth0-rx-22:40:202
986499170cyclictest991850irq/53-eth0-rx-22:30:172
986499170cyclictest991850irq/53-eth0-rx-22:10:042
986499170cyclictest991850irq/53-eth0-rx-22:05:042
986499170cyclictest991850irq/53-eth0-rx-21:25:072
986499170cyclictest991850irq/53-eth0-rx-21:15:042
986499170cyclictest991850irq/53-eth0-rx-20:00:232
986499170cyclictest991850irq/53-eth0-rx-19:51:382
986499170cyclictest991850irq/53-eth0-rx-19:45:122
986499170cyclictest991850irq/53-eth0-rx-00:30:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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