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2026-01-21 - 05:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Jan 21, 2026 00:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501130irq/42-ahci0-21swapper/219:09:374
9918501030irq/53-eth0-rx-0-21swapper/119:08:271
991850980irq/53-eth0-rx-0-21swapper/719:09:309
991850950irq/53-eth0-rx-0-21swapper/819:09:1910
12850940irq/42-ahci0-21swapper/319:07:435
991850930irq/53-eth0-rx-0-21swapper/419:06:056
991950920irq/54-eth0-tx-0-21swapper/519:05:237
991850870irq/53-eth0-rx-0-21swapper/1119:06:583
991850710irq/53-eth0-rx-0-21swapper/1019:06:072
1817627164sleep60-21swapper/619:05:358
1832827061sleep00-21swapper/019:07:290
1824225955sleep90-21swapper/919:06:2611
1867599320cyclictest0-21swapper/022:19:120
12850300irq/42-ahci0-21swapper/019:10:380
18699992928cyclictest991850irq/53-eth0-rx-22:19:145
18684992928cyclictest991850irq/53-eth0-rx-22:19:131
1867599250cyclictest0-21swapper/019:30:040
1867599240cyclictest0-21swapper/022:25:590
1867599240cyclictest0-21swapper/022:11:050
1867599240cyclictest0-21swapper/019:25:160
18731992322cyclictest991850irq/53-eth0-rx-22:19:143
18721992322cyclictest991950irq/54-eth0-tx-22:19:119
1867599230cyclictest0-21swapper/019:24:090
1867599220cyclictest0-21swapper/019:19:090
991850200irq/53-eth0-rx-0-21swapper/000:35:220
1872999203cyclictest761ksoftirqd/923:58:1711
1872999203cyclictest761ksoftirqd/923:51:3511
1872999203cyclictest761ksoftirqd/923:44:5011
1872999203cyclictest761ksoftirqd/923:32:1211
1872999203cyclictest761ksoftirqd/923:24:4111
1872999203cyclictest761ksoftirqd/923:19:1711
1872999203cyclictest761ksoftirqd/923:14:4311
1872999203cyclictest761ksoftirqd/923:09:1311
1872999203cyclictest761ksoftirqd/923:04:3911
1872999203cyclictest761ksoftirqd/922:49:0311
1872999203cyclictest761ksoftirqd/922:40:5211
1872999203cyclictest761ksoftirqd/922:35:4411
1872999203cyclictest761ksoftirqd/922:26:2511
1872999203cyclictest761ksoftirqd/922:20:0811
1872999203cyclictest761ksoftirqd/922:19:4011
1872999203cyclictest761ksoftirqd/922:13:1611
1872999203cyclictest761ksoftirqd/922:08:0411
1872999203cyclictest761ksoftirqd/922:04:2911
1872999203cyclictest761ksoftirqd/921:45:3111
1872999203cyclictest761ksoftirqd/921:36:3611
1872999203cyclictest761ksoftirqd/921:33:1411
1872999203cyclictest761ksoftirqd/921:33:1411
1872999203cyclictest761ksoftirqd/921:26:2511
1872999203cyclictest761ksoftirqd/921:26:2411
1872999203cyclictest761ksoftirqd/921:20:3111
1872999203cyclictest761ksoftirqd/921:20:3011
1872999203cyclictest761ksoftirqd/921:16:1011
1872999203cyclictest761ksoftirqd/921:10:1311
1872999203cyclictest761ksoftirqd/920:40:4911
1872999203cyclictest761ksoftirqd/920:36:3411
1872999203cyclictest761ksoftirqd/920:28:3211
1872999203cyclictest761ksoftirqd/920:23:4111
1872999203cyclictest761ksoftirqd/920:18:3611
1872999203cyclictest761ksoftirqd/920:13:1811
1872999203cyclictest761ksoftirqd/920:06:0811
1872999203cyclictest761ksoftirqd/920:01:3211
1872999203cyclictest761ksoftirqd/919:55:3411
1872999203cyclictest761ksoftirqd/919:25:3511
1872999203cyclictest761ksoftirqd/919:20:1911
1872999203cyclictest761ksoftirqd/919:19:5111
1872999203cyclictest761ksoftirqd/919:10:3011
1872999203cyclictest761ksoftirqd/900:35:5011
1872999203cyclictest761ksoftirqd/900:30:3111
1872999203cyclictest761ksoftirqd/900:28:2611
1872999203cyclictest761ksoftirqd/900:24:0911
1872999203cyclictest761ksoftirqd/900:16:2211
1872999203cyclictest761ksoftirqd/900:11:3911
1872999203cyclictest761ksoftirqd/900:03:0911
1872999193cyclictest761ksoftirqd/921:57:4211
1872999192cyclictest761ksoftirqd/923:48:0211
1872999192cyclictest761ksoftirqd/923:36:3311
1872999192cyclictest761ksoftirqd/923:25:0111
1872999192cyclictest761ksoftirqd/922:55:0711
1872999192cyclictest761ksoftirqd/922:54:1911
1872999192cyclictest761ksoftirqd/922:30:4211
1872999192cyclictest761ksoftirqd/921:51:1511
1872999192cyclictest761ksoftirqd/921:41:1311
1872999192cyclictest761ksoftirqd/921:05:1111
1872999192cyclictest761ksoftirqd/920:57:2411
1872999192cyclictest761ksoftirqd/920:52:3411
1872999192cyclictest761ksoftirqd/920:31:3511
1872999192cyclictest761ksoftirqd/919:51:2111
1872999192cyclictest761ksoftirqd/919:46:0811
1872999192cyclictest761ksoftirqd/919:42:1311
1872999192cyclictest761ksoftirqd/919:35:2811
1872999192cyclictest761ksoftirqd/919:31:4111
1872999192cyclictest761ksoftirqd/900:08:5711
1871799194cyclictest0-21swapper/623:40:188
18711991918cyclictest991850irq/53-eth0-rx-22:19:147
18675991911cyclictest991850irq/53-eth0-rx-20:28:480
18675991911cyclictest89832sleep020:20:480
1873199180cyclictest0-21swapper/1119:22:103
18730991817cyclictest831ksoftirqd/1019:12:382
18730991817cyclictest0-21swapper/1023:21:012
18730991816cyclictest8842-21ssh22:58:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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