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2026-07-28 - 21:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Jul 28, 2026 12:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
944210894sleep100-21swapper/1007:07:262
941210893sleep70-21swapper/707:07:239
892210793sleep80-21swapper/807:06:4810
886210694sleep20-21swapper/207:06:424
12250990irq/42-ahci0-21swapper/107:09:491
3054950950irq/53-eth0-rx-0-21swapper/1107:05:323
12250950irq/42-ahci0-21swapper/307:05:205
3054950890irq/53-eth0-rx-0-21swapper/507:07:067
80028881sleep90-21swapper/907:05:3711
117328175sleep40-21swapper/407:09:446
96027055sleep00-21swapper/007:07:400
100026653sleep60-21swapper/607:08:108
1308992928cyclictest0-21swapper/009:12:390
130899250cyclictest0-21swapper/007:19:110
136099220cyclictest0-21swapper/1110:15:283
130899210cyclictest0-21swapper/008:13:160
1360992018cyclictest3057-21chrt09:15:293
1360992018cyclictest0-21swapper/1109:08:223
1352992013cyclictest0-21swapper/611:40:018
1308992018cyclictest0-21swapper/009:08:220
130899201cyclictest31ksoftirqd/009:23:200
3055050190irq/54-eth0-tx-0-21swapper/911:45:2811
135899192cyclictest3054950irq/53-eth0-rx-11:43:262
135799192cyclictest0-21swapper/910:11:4311
1326991915cyclictest5462-21python12:20:234
1308991918cyclictest0-21swapper/007:11:490
130899191cyclictest0-21swapper/011:06:590
130899190cyclictest0-21swapper/008:27:350
130899190cyclictest0-21swapper/008:27:350
135899181cyclictest3055050irq/54-eth0-tx-12:18:412
135899181cyclictest3055050irq/54-eth0-tx-11:34:292
135899181cyclictest3055050irq/54-eth0-tx-11:34:292
135899181cyclictest3054950irq/53-eth0-rx-10:23:292
135899181cyclictest267982chrt10:00:572
135899181cyclictest12250irq/42-ahci09:09:372
135799184cyclictest0-21swapper/908:20:1611
135799181cyclictest761ksoftirqd/911:02:5011
135799181cyclictest761ksoftirqd/908:40:1911
135799181cyclictest761ksoftirqd/908:40:1911
135799181cyclictest741rcuc/911:50:1311
135799181cyclictest741rcuc/910:25:5711
135799181cyclictest3054950irq/53-eth0-rx-12:27:5311
135799181cyclictest3054950irq/53-eth0-rx-09:10:0111
135799181cyclictest24746-1kworker/9:1H11:06:0311
135799181cyclictest24746-1kworker/9:1H08:46:4511
135799181cyclictest20372-21ssh10:22:4311
135799181cyclictest0-21swapper/912:14:3811
135799181cyclictest0-21swapper/912:02:3911
135799181cyclictest0-21swapper/911:41:2311
135799181cyclictest0-21swapper/911:35:2111
135799181cyclictest0-21swapper/911:27:2011
135799181cyclictest0-21swapper/911:14:3911
135799181cyclictest0-21swapper/910:55:1311
135799181cyclictest0-21swapper/910:50:1611
135799181cyclictest0-21swapper/910:16:3611
135799181cyclictest0-21swapper/910:01:0611
135799181cyclictest0-21swapper/909:59:5611
135799181cyclictest0-21swapper/909:49:1011
135799181cyclictest0-21swapper/909:42:5211
135799181cyclictest0-21swapper/909:25:5911
135799181cyclictest0-21swapper/909:22:5811
135799181cyclictest0-21swapper/908:10:1211
1352991816cyclictest25494-21qemu-kvm09:15:128
1352991816cyclictest25493-21qemu-kvm09:45:138
1326991816cyclictest24017-21snmp_rack3slot910:50:364
131899183cyclictest0-21swapper/107:33:441
3055050170irq/54-eth0-tx-0-21swapper/912:16:5211
136099173cyclictest0-21swapper/1110:59:553
136099173cyclictest0-21swapper/1107:57:013
136099172cyclictest0-21swapper/1108:45:593
136099172cyclictest0-21swapper/1108:04:433
1360991710cyclictest174862sleep1108:10:453
1358991716cyclictest0-21swapper/1012:21:142
1358991716cyclictest0-21swapper/1009:00:192
135899170cyclictest97132sleep1007:16:382
135899170cyclictest57942sleep1010:36:142
135899170cyclictest35832chrt08:38:352
135899170cyclictest323822sleep1009:15:042
135899170cyclictest315292chrt07:46:052
135899170cyclictest3055050irq/54-eth0-tx-12:08:412
135899170cyclictest3055050irq/54-eth0-tx-09:10:052
135899170cyclictest3054950irq/53-eth0-rx-12:14:312
135899170cyclictest3054950irq/53-eth0-rx-12:00:522
135899170cyclictest3054950irq/53-eth0-rx-11:55:282
135899170cyclictest3054950irq/53-eth0-rx-11:51:082
135899170cyclictest3054950irq/53-eth0-rx-11:45:082
135899170cyclictest3054950irq/53-eth0-rx-11:15:342
135899170cyclictest3054950irq/53-eth0-rx-11:00:312
135899170cyclictest3054950irq/53-eth0-rx-10:55:142
135899170cyclictest3054950irq/53-eth0-rx-10:52:412
135899170cyclictest3054950irq/53-eth0-rx-10:45:092
135899170cyclictest3054950irq/53-eth0-rx-10:40:362
135899170cyclictest3054950irq/53-eth0-rx-10:31:572
135899170cyclictest3054950irq/53-eth0-rx-10:16:152
135899170cyclictest3054950irq/53-eth0-rx-10:05:012
135899170cyclictest3054950irq/53-eth0-rx-09:45:262
135899170cyclictest3054950irq/53-eth0-rx-09:40:022
135899170cyclictest3054950irq/53-eth0-rx-09:37:592
135899170cyclictest3054950irq/53-eth0-rx-09:30:582
135899170cyclictest3054950irq/53-eth0-rx-09:25:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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