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2026-02-07 - 17:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Feb 07, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501140irq/42-ahci0-21swapper/307:08:505
9919501080irq/54-eth0-tx-0-21swapper/207:05:134
9918501080irq/53-eth0-rx-0-21swapper/107:08:591
30994210893sleep80-21swapper/807:06:1010
31057210390sleep50-21swapper/507:06:557
991850890irq/53-eth0-rx-0-21swapper/707:05:219
991850880irq/53-eth0-rx-0-21swapper/1107:08:063
991850680irq/53-eth0-rx-0-21swapper/1007:06:522
991850650irq/53-eth0-rx-0-21swapper/907:06:4411
3095026453sleep60-21swapper/607:05:318
3097226048sleep00-21swapper/007:05:500
3107025955sleep40-21swapper/407:07:066
31456993635cyclictest0-21swapper/009:22:550
31456993517cyclictest0-21swapper/009:13:170
31456993517cyclictest0-21swapper/009:08:150
31489993417cyclictest831ksoftirqd/1012:20:262
31483993029cyclictest991950irq/54-eth0-tx-09:22:506
31475993029cyclictest991850irq/53-eth0-rx-09:22:474
31490992914cyclictest0-21swapper/1110:09:043
31490992914cyclictest0-21swapper/1108:29:203
31487992928cyclictest991850irq/53-eth0-rx-09:22:4710
31490992827cyclictest991950irq/54-eth0-tx-09:22:463
31456992813cyclictest0-21swapper/007:50:020
31486992726cyclictest991950irq/54-eth0-tx-09:22:449
31468992625cyclictest991950irq/54-eth0-tx-09:22:451
3148999247cyclictest831ksoftirqd/1011:24:542
31482992423cyclictest991950irq/54-eth0-tx-09:22:365
31489992111cyclictest831ksoftirqd/1011:06:402
3145699213cyclictest0-21swapper/009:25:160
3148899203cyclictest761ksoftirqd/912:36:1411
3148899203cyclictest761ksoftirqd/912:23:5011
3148899203cyclictest761ksoftirqd/912:18:4511
3148899203cyclictest761ksoftirqd/912:14:2111
3148899203cyclictest761ksoftirqd/912:01:5311
3148899203cyclictest761ksoftirqd/911:58:3011
3148899203cyclictest761ksoftirqd/911:54:1911
3148899203cyclictest761ksoftirqd/911:40:3911
3148899203cyclictest761ksoftirqd/911:33:4711
3148899203cyclictest761ksoftirqd/911:25:0911
3148899203cyclictest761ksoftirqd/911:18:0611
3148899203cyclictest761ksoftirqd/911:14:0311
3148899203cyclictest761ksoftirqd/911:06:5811
3148899203cyclictest761ksoftirqd/911:01:0911
3148899203cyclictest761ksoftirqd/909:59:5711
3148899203cyclictest761ksoftirqd/909:59:5711
3148899203cyclictest761ksoftirqd/909:52:4811
3148899203cyclictest761ksoftirqd/909:46:2211
3148899203cyclictest761ksoftirqd/909:40:5311
3148899203cyclictest761ksoftirqd/909:36:1311
3148899203cyclictest761ksoftirqd/909:30:0711
3148899203cyclictest761ksoftirqd/909:26:5711
3148899203cyclictest761ksoftirqd/909:18:5811
3148899203cyclictest761ksoftirqd/909:14:2811
3148899203cyclictest761ksoftirqd/909:07:3611
3148899203cyclictest761ksoftirqd/909:04:0411
3148899203cyclictest761ksoftirqd/908:42:2611
3148899203cyclictest761ksoftirqd/908:37:3111
3148899203cyclictest761ksoftirqd/908:30:1511
3148899203cyclictest761ksoftirqd/908:20:4511
3148899203cyclictest761ksoftirqd/908:14:2911
3148899203cyclictest761ksoftirqd/908:08:0511
3148899203cyclictest761ksoftirqd/908:01:5611
3148899203cyclictest761ksoftirqd/907:52:4611
3148899203cyclictest761ksoftirqd/907:37:1211
3148899203cyclictest761ksoftirqd/907:34:3511
3148899203cyclictest761ksoftirqd/907:15:0511
3148899203cyclictest761ksoftirqd/907:11:4011
3148899203cyclictest761ksoftirqd/907:11:4011
31484992018cyclictest23337-21diskmemload09:22:437
3148999192cyclictest991850irq/53-eth0-rx-12:09:292
3148999192cyclictest991850irq/53-eth0-rx-11:14:032
3148999192cyclictest991850irq/53-eth0-rx-11:03:452
3148999192cyclictest991850irq/53-eth0-rx-10:45:342
3148999192cyclictest991850irq/53-eth0-rx-10:42:022
3148999192cyclictest991850irq/53-eth0-rx-10:26:262
3148999192cyclictest991850irq/53-eth0-rx-10:23:182
3148999192cyclictest991850irq/53-eth0-rx-10:23:182
3148999192cyclictest991850irq/53-eth0-rx-10:19:052
3148999192cyclictest991850irq/53-eth0-rx-10:19:052
3148999192cyclictest991850irq/53-eth0-rx-09:56:432
3148999192cyclictest991850irq/53-eth0-rx-09:56:432
3148999192cyclictest991850irq/53-eth0-rx-09:19:402
3148899192cyclictest761ksoftirqd/912:31:3111
3148899192cyclictest761ksoftirqd/912:26:3411
3148899192cyclictest761ksoftirqd/912:05:5611
3148899192cyclictest761ksoftirqd/911:45:5511
3148899192cyclictest761ksoftirqd/911:37:1711
3148899192cyclictest761ksoftirqd/911:20:0611
3148899192cyclictest761ksoftirqd/910:00:1711
3148899192cyclictest761ksoftirqd/909:20:2411
3148899192cyclictest761ksoftirqd/908:56:4311
3148899192cyclictest761ksoftirqd/908:50:0711
3148899192cyclictest761ksoftirqd/908:46:1811
3148899192cyclictest761ksoftirqd/908:25:1111
3148899192cyclictest761ksoftirqd/908:15:5711
3148899192cyclictest761ksoftirqd/907:57:1311
3148899192cyclictest761ksoftirqd/907:45:2811
3148899192cyclictest761ksoftirqd/907:41:1211
3148899192cyclictest761ksoftirqd/907:25:4311
3148899192cyclictest761ksoftirqd/907:20:2711
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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