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2026-03-02 - 13:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Mar 02, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501120irq/53-eth0-rx-0-21swapper/319:08:265
128501120irq/42-ahci0-21swapper/219:09:084
128501030irq/42-ahci0-21swapper/119:09:091
991850920irq/53-eth0-rx-0-21swapper/719:08:389
2144229287sleep100-21swapper/1019:09:382
991850900irq/53-eth0-rx-0-21swapper/419:08:496
991850840irq/53-eth0-rx-0-21swapper/819:08:4210
2126226961sleep90-21swapper/919:08:0111
991850670irq/53-eth0-rx-0-21swapper/519:07:487
2142026661sleep60-21swapper/619:09:218
2078426654sleep00-21swapper/019:05:280
2114026555sleep110-21swapper/1119:06:263
2161399330cyclictest0-21swapper/1121:26:583
2161399320cyclictest0-21swapper/1122:11:213
2157999268cyclictest991850irq/53-eth0-rx-21:13:580
21613992418cyclictest0-21swapper/1120:08:233
21579992117cyclictest991850irq/53-eth0-rx-21:19:330
21579992019cyclictest0-21swapper/022:25:580
21579992018cyclictest0-21swapper/020:08:220
2161199192cyclictest0-21swapper/921:35:5511
2161199192cyclictest0-21swapper/900:15:4011
21612991817cyclictest6801-21kworker/10:123:31:002
21612991817cyclictest6801-21kworker/10:122:25:492
21612991817cyclictest0-21swapper/1023:26:122
21612991817cyclictest0-21swapper/1022:58:412
21612991817cyclictest0-21swapper/1022:58:412
21612991817cyclictest0-21swapper/1022:07:522
2161299181cyclictest991950irq/54-eth0-tx-22:39:432
2161299181cyclictest991950irq/54-eth0-tx-21:35:352
2161299181cyclictest991950irq/54-eth0-tx-21:26:362
2161299181cyclictest991950irq/54-eth0-tx-21:14:102
2161299181cyclictest991950irq/54-eth0-tx-00:26:592
2161299181cyclictest991850irq/53-eth0-rx-23:02:092
2161299181cyclictest991850irq/53-eth0-rx-22:45:412
2161299181cyclictest991850irq/53-eth0-rx-21:49:452
2161299181cyclictest991850irq/53-eth0-rx-21:42:232
2161299181cyclictest991850irq/53-eth0-rx-21:23:482
2161299181cyclictest991850irq/53-eth0-rx-19:37:062
2161299181cyclictest991850irq/53-eth0-rx-19:37:052
2161299181cyclictest991850irq/53-eth0-rx-00:21:182
2161299181cyclictest991850irq/53-eth0-rx-00:10:192
2161199181cyclictest761ksoftirqd/923:10:1311
2161199181cyclictest741rcuc/919:25:1411
2161199181cyclictest0-21swapper/923:57:0011
2161199181cyclictest0-21swapper/923:51:2011
2161199181cyclictest0-21swapper/923:45:1011
2161199181cyclictest0-21swapper/923:40:1411
2161199181cyclictest0-21swapper/923:23:2311
2161199181cyclictest0-21swapper/923:23:2311
2161199181cyclictest0-21swapper/923:15:0211
2161199181cyclictest0-21swapper/923:15:0211
2161199181cyclictest0-21swapper/923:01:1711
2161199181cyclictest0-21swapper/922:56:4811
2161199181cyclictest0-21swapper/922:56:4811
2161199181cyclictest0-21swapper/922:52:4911
2161199181cyclictest0-21swapper/922:46:4711
2161199181cyclictest0-21swapper/922:43:3211
2161199181cyclictest0-21swapper/922:33:5511
2161199181cyclictest0-21swapper/922:26:0611
2161199181cyclictest0-21swapper/922:21:4511
2161199181cyclictest0-21swapper/922:14:4111
2161199181cyclictest0-21swapper/922:05:1811
2161199181cyclictest0-21swapper/922:03:0111
2161199181cyclictest0-21swapper/921:47:0211
2161199181cyclictest0-21swapper/921:40:1711
2161199181cyclictest0-21swapper/921:25:0511
2161199181cyclictest0-21swapper/921:21:4611
2161199181cyclictest0-21swapper/921:10:0311
2161199181cyclictest0-21swapper/921:00:1011
2161199181cyclictest0-21swapper/919:58:5011
2161199181cyclictest0-21swapper/919:16:4811
2161199181cyclictest0-21swapper/919:10:1911
2161199181cyclictest0-21swapper/900:35:0511
2161199181cyclictest0-21swapper/900:30:3111
2161199181cyclictest0-21swapper/900:20:3611
2161199181cyclictest0-21swapper/900:06:3111
2161199181cyclictest0-21swapper/900:04:1211
2160999185cyclictest0-21swapper/723:50:019
21608991816cyclictest20076-21snmp_rack3slot921:40:148
21607991816cyclictest1727-21qemu-kvm20:40:127
21607991816cyclictest1727-21qemu-kvm20:31:587
21607991816cyclictest1727-21qemu-kvm20:16:547
21612991716cyclictest0-21swapper/1022:50:152
2161299170cyclictest991950irq/54-eth0-tx-23:50:022
2161299170cyclictest991950irq/54-eth0-tx-19:40:242
2161299170cyclictest991850irq/53-eth0-rx-23:55:532
2161299170cyclictest991850irq/53-eth0-rx-23:40:082
2161299170cyclictest991850irq/53-eth0-rx-23:35:442
2161299170cyclictest991850irq/53-eth0-rx-23:15:532
2161299170cyclictest991850irq/53-eth0-rx-23:15:532
2161299170cyclictest991850irq/53-eth0-rx-22:30:072
2161299170cyclictest991850irq/53-eth0-rx-22:20:042
2161299170cyclictest991850irq/53-eth0-rx-22:01:512
2161299170cyclictest991850irq/53-eth0-rx-21:50:232
2161299170cyclictest991850irq/53-eth0-rx-19:11:182
2161299170cyclictest991850irq/53-eth0-rx-00:35:192
2161299170cyclictest991850irq/53-eth0-rx-00:15:162
2161299170cyclictest991850irq/53-eth0-rx-00:05:242
2161299170cyclictest991850irq/53-eth0-rx-00:00:522
2161299170cyclictest9622sleep1019:20:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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