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2026-01-30 - 21:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Jan 30, 2026 12:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31203210995sleep100-21swapper/1007:07:392
31064210894sleep90-21swapper/907:05:5011
31060210891sleep60-21swapper/607:05:478
9918501060irq/53-eth0-rx-0-21swapper/207:09:024
9918501020irq/53-eth0-rx-0-21swapper/107:09:581
9918501000irq/53-eth0-rx-0-21swapper/807:09:0710
991850960irq/53-eth0-rx-0-21swapper/407:05:476
3143329690sleep30-21swapper/307:09:585
991850920irq/53-eth0-rx-0-21swapper/707:09:599
991850820irq/53-eth0-rx-0-21swapper/1107:05:473
991850690irq/53-eth0-rx-0-21swapper/507:07:327
3116226855sleep00-21swapper/007:07:060
31581993714cyclictest0-21swapper/1109:24:403
3158199320cyclictest0-21swapper/1108:17:563
3153999320cyclictest0-21swapper/010:19:220
31539993029cyclictest991850irq/53-eth0-rx-09:29:250
31581992928cyclictest0-21swapper/1110:16:463
991950280irq/54-eth0-tx-0-21swapper/810:19:1510
991950280irq/54-eth0-tx-0-21swapper/710:19:209
991950280irq/54-eth0-tx-0-21swapper/110:19:211
991850280irq/53-eth0-rx-0-21swapper/310:19:305
991850280irq/53-eth0-rx-0-21swapper/210:19:134
991850280irq/53-eth0-rx-0-21swapper/1010:19:202
31581992827cyclictest10041-21kworker/11:210:20:423
31581992510cyclictest12850irq/42-ahci07:13:223
3158099192cyclictest991850irq/53-eth0-rx-12:09:172
3158099192cyclictest991850irq/53-eth0-rx-11:30:202
3158099192cyclictest991850irq/53-eth0-rx-11:30:192
3158099192cyclictest991850irq/53-eth0-rx-10:13:132
3158099192cyclictest991850irq/53-eth0-rx-09:59:592
3158099192cyclictest991850irq/53-eth0-rx-09:28:572
3158099192cyclictest12850irq/42-ahci12:21:492
3157999192cyclictest0-21swapper/909:55:5211
3157999192cyclictest0-21swapper/909:25:3511
31577991917cyclictest0-21swapper/709:44:569
3155999193cyclictest0-21swapper/310:10:105
3158199184cyclictest0-21swapper/1109:55:183
31580991817cyclictest28757-1kworker/10:2H09:51:282
31580991817cyclictest0-21swapper/1011:43:362
31580991817cyclictest0-21swapper/1011:25:532
31580991817cyclictest0-21swapper/1011:25:522
31580991817cyclictest0-21swapper/1011:11:242
31580991817cyclictest0-21swapper/1010:08:002
31580991817cyclictest0-21swapper/1010:00:012
31580991817cyclictest0-21swapper/1009:10:462
31580991817cyclictest0-21swapper/1008:52:032
3158099181cyclictest991950irq/54-eth0-tx-12:26:482
3158099181cyclictest991950irq/54-eth0-tx-11:55:152
3158099181cyclictest991950irq/54-eth0-tx-11:35:032
3158099181cyclictest991950irq/54-eth0-tx-10:45:102
3158099181cyclictest991950irq/54-eth0-tx-10:30:512
3158099181cyclictest991950irq/54-eth0-tx-10:26:152
3158099181cyclictest991950irq/54-eth0-tx-09:46:282
3158099181cyclictest991850irq/53-eth0-rx-12:35:452
3158099181cyclictest991850irq/53-eth0-rx-12:32:522
3158099181cyclictest991850irq/53-eth0-rx-12:16:182
3158099181cyclictest991850irq/53-eth0-rx-12:11:132
3158099181cyclictest991850irq/53-eth0-rx-12:03:462
3158099181cyclictest991850irq/53-eth0-rx-11:54:422
3158099181cyclictest991850irq/53-eth0-rx-11:46:562
3158099181cyclictest991850irq/53-eth0-rx-11:24:592
3158099181cyclictest991850irq/53-eth0-rx-11:24:582
3158099181cyclictest991850irq/53-eth0-rx-11:17:152
3158099181cyclictest991850irq/53-eth0-rx-11:17:142
3158099181cyclictest991850irq/53-eth0-rx-11:05:282
3158099181cyclictest991850irq/53-eth0-rx-11:05:272
3158099181cyclictest991850irq/53-eth0-rx-11:02:262
3158099181cyclictest991850irq/53-eth0-rx-10:56:422
3158099181cyclictest991850irq/53-eth0-rx-10:51:072
3158099181cyclictest991850irq/53-eth0-rx-10:37:322
3158099181cyclictest991850irq/53-eth0-rx-10:21:092
3158099181cyclictest991850irq/53-eth0-rx-09:35:122
3158099181cyclictest991850irq/53-eth0-rx-09:16:442
3158099181cyclictest991850irq/53-eth0-rx-07:36:142
3158099181cyclictest991850irq/53-eth0-rx-07:17:022
3158099181cyclictest12850irq/42-ahci08:02:042
3157999181cyclictest991950irq/54-eth0-tx-10:07:1111
3157999181cyclictest0-21swapper/912:37:0311
3157999181cyclictest0-21swapper/912:28:2411
3157999181cyclictest0-21swapper/912:20:3511
3157999181cyclictest0-21swapper/911:35:1211
3157999181cyclictest0-21swapper/911:01:5911
3157999181cyclictest0-21swapper/910:47:1611
3157999181cyclictest0-21swapper/910:35:2611
3157999181cyclictest0-21swapper/910:15:1311
3157999181cyclictest0-21swapper/909:44:4711
3157999181cyclictest0-21swapper/909:30:2111
3157999181cyclictest0-21swapper/908:03:4111
31573991816cyclictest27836-21snmp_rack3slot907:45:157
3155999183cyclictest14099-21ssh12:10:465
3155999182cyclictest23424-21diskmemload09:26:245
3155999182cyclictest0-21swapper/309:51:445
3155999182cyclictest0-21swapper/309:10:085
3155999181cyclictest0-21swapper/312:21:095
31580991716cyclictest0-21swapper/1008:45:162
31580991716cyclictest0-21swapper/1008:45:152
31580991716cyclictest0-21swapper/1007:25:472
3158099170cyclictest991850irq/53-eth0-rx-10:40:372
3158099170cyclictest991850irq/53-eth0-rx-09:20:012
3158099170cyclictest991850irq/53-eth0-rx-09:00:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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