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2026-01-24 - 17:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Jan 24, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
248822120107sleep50-21swapper/507:05:507
9918501170irq/53-eth0-rx-0-21swapper/207:09:124
9918501150irq/53-eth0-rx-0-21swapper/107:09:411
9918501100irq/53-eth0-rx-0-21swapper/407:06:016
25126210599sleep70-21swapper/707:08:159
24954210290sleep110-21swapper/1107:06:443
9919501000irq/54-eth0-tx-0-21swapper/907:09:2411
128501000irq/42-ahci0-21swapper/307:09:085
991850980irq/53-eth0-rx-0-21swapper/807:07:2710
2488427060sleep60-21swapper/607:05:518
2502126454sleep00-21swapper/007:07:320
2498226453sleep100-21swapper/1007:07:072
25359994314cyclictest0-21swapper/009:22:140
25359993013cyclictest0-21swapper/009:12:310
25359992913cyclictest2745-21runrttasks09:25:190
2535999290cyclictest290892sleep009:19:580
2540299280cyclictest991850irq/53-eth0-rx-09:09:213
2540299227cyclictest0-21swapper/1109:11:483
2540299220cyclictest0-21swapper/1109:18:453
2540299212cyclictest991850irq/53-eth0-rx-09:20:483
2540299210cyclictest0-21swapper/1109:28:353
25359992019cyclictest26748-1kworker/0:1H08:11:550
115050200irq/18-i801_smb0-21swapper/010:23:180
2540299190cyclictest0-21swapper/1109:30:023
2540199192cyclictest991850irq/53-eth0-rx-11:53:312
2540199192cyclictest991850irq/53-eth0-rx-11:06:422
2540199192cyclictest991850irq/53-eth0-rx-10:52:192
2540199192cyclictest991850irq/53-eth0-rx-10:24:342
991950180irq/54-eth0-tx-2536699cyclictest09:11:144
991950180irq/54-eth0-tx-20580-21timerwakeupswit09:10:259
991950180irq/54-eth0-tx-0-21swapper/709:20:099
991950180irq/54-eth0-tx-0-21swapper/209:29:244
991850180irq/53-eth0-rx-17093-21qemu-kvm09:17:118
991850180irq/53-eth0-rx-0-21swapper/909:26:5911
991850180irq/53-eth0-rx-0-21swapper/809:29:3110
991850180irq/53-eth0-rx-0-21swapper/109:26:441
991850180irq/53-eth0-rx-0-21swapper/109:15:101
25401991817cyclictest25387-21kworker/10:111:31:002
25401991817cyclictest1191-1kworker/10:2H12:37:112
25401991817cyclictest0-21swapper/1012:29:452
25401991817cyclictest0-21swapper/1011:12:072
25401991817cyclictest0-21swapper/1011:04:092
25401991817cyclictest0-21swapper/1010:35:502
25401991817cyclictest0-21swapper/1010:03:352
25401991817cyclictest0-21swapper/1009:25:492
25401991817cyclictest0-21swapper/1009:20:252
25401991817cyclictest0-21swapper/1009:00:102
25401991817cyclictest0-21swapper/1008:56:312
2540199181cyclictest991950irq/54-eth0-tx-10:10:302
2540199181cyclictest991950irq/54-eth0-tx-10:05:472
2540199181cyclictest991950irq/54-eth0-tx-09:17:172
2540199181cyclictest991850irq/53-eth0-rx-12:23:172
2540199181cyclictest991850irq/53-eth0-rx-12:12:212
2540199181cyclictest991850irq/53-eth0-rx-12:08:262
2540199181cyclictest991850irq/53-eth0-rx-11:56:272
2540199181cyclictest991850irq/53-eth0-rx-11:46:232
2540199181cyclictest991850irq/53-eth0-rx-11:36:072
2540199181cyclictest991850irq/53-eth0-rx-11:28:032
2540199181cyclictest991850irq/53-eth0-rx-11:28:022
2540199181cyclictest991850irq/53-eth0-rx-11:20:122
2540199181cyclictest991850irq/53-eth0-rx-11:20:112
2540199181cyclictest991850irq/53-eth0-rx-11:16:232
2540199181cyclictest991850irq/53-eth0-rx-11:16:232
2540199181cyclictest991850irq/53-eth0-rx-10:42:222
2540199181cyclictest991850irq/53-eth0-rx-10:33:472
2540199181cyclictest991850irq/53-eth0-rx-10:27:042
2540199181cyclictest991850irq/53-eth0-rx-10:15:412
2540199181cyclictest991850irq/53-eth0-rx-09:48:282
2540199181cyclictest991850irq/53-eth0-rx-09:37:162
2540199181cyclictest991850irq/53-eth0-rx-09:11:502
2540199181cyclictest991850irq/53-eth0-rx-08:33:162
2540199181cyclictest991850irq/53-eth0-rx-08:33:152
2540199181cyclictest991850irq/53-eth0-rx-08:27:222
2540199181cyclictest991850irq/53-eth0-rx-08:27:212
2540199181cyclictest991850irq/53-eth0-rx-08:12:562
2540199181cyclictest991850irq/53-eth0-rx-07:41:242
2540199181cyclictest991850irq/53-eth0-rx-07:40:002
2540199181cyclictest991850irq/53-eth0-rx-07:32:092
2540199181cyclictest12850irq/42-ahci07:25:022
2540199180cyclictest991850irq/53-eth0-rx-09:43:162
25389991816cyclictest17093-21qemu-kvm09:20:157
25389991816cyclictest17093-21qemu-kvm09:15:137
2538199180cyclictest0-21swapper/409:21:596
991950170irq/54-eth0-tx-0-21swapper/409:14:426
991850170irq/53-eth0-rx-0-21swapper/409:26:526
991850170irq/53-eth0-rx-0-21swapper/109:13:141
2540199170cyclictest991850irq/53-eth0-rx-12:30:052
2540199170cyclictest991850irq/53-eth0-rx-12:15:202
2540199170cyclictest991850irq/53-eth0-rx-12:00:292
2540199170cyclictest991850irq/53-eth0-rx-10:55:172
2540199170cyclictest991850irq/53-eth0-rx-09:55:082
2540199170cyclictest991850irq/53-eth0-rx-09:50:142
2540199170cyclictest991850irq/53-eth0-rx-09:30:372
2540199170cyclictest991850irq/53-eth0-rx-09:05:242
2540199170cyclictest991850irq/53-eth0-rx-08:35:112
2540199170cyclictest991850irq/53-eth0-rx-08:20:122
2540199170cyclictest991850irq/53-eth0-rx-08:20:112
2540199170cyclictest991850irq/53-eth0-rx-08:15:102
2540199170cyclictest991850irq/53-eth0-rx-08:15:092
2540199170cyclictest86742chrt07:27:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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