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2025-11-21 - 12:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Nov 21, 2025 00:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19515210894sleep20-21swapper/219:07:274
19505210893sleep80-21swapper/819:07:2210
19392210895sleep30-21swapper/319:05:535
16589210894sleep100-21swapper/1019:05:112
19539210390sleep110-21swapper/1119:07:483
1964729382sleep40-21swapper/419:08:306
12250920irq/42-ahci0-21swapper/119:08:161
3066350870irq/52-eth0-rx-0-21swapper/519:05:287
3066350850irq/52-eth0-rx-0-21swapper/719:08:419
1942628476sleep90-21swapper/919:06:2211
1955826556sleep00-21swapper/019:08:010
1946026454sleep60-21swapper/619:06:438
1990299340cyclictest0-21swapper/1120:09:163
1990299310cyclictest0-21swapper/1121:09:083
19855993129cyclictest30902sleep019:26:510
19902992423cyclictest0-21swapper/1120:15:153
1989299220cyclictest0-21swapper/623:00:018
1990299210cyclictest0-21swapper/1122:22:483
19896992013cyclictest31244-1kworker/10:2H21:44:532
19902991918cyclictest0-21swapper/1121:11:463
1989699192cyclictest3066350irq/52-eth0-rx-22:15:342
19896991913cyclictest19492-21cstates20:35:132
19896991912cyclictest0-21swapper/1022:57:262
1989699183cyclictest0-21swapper/1022:30:192
19896991812cyclictest25288-21smartctl21:25:302
19896991812cyclictest1042-21python23:05:302
1989699181cyclictest12250irq/42-ahci21:08:312
1989699181cyclictest12250irq/42-ahci20:10:342
1989599181cyclictest4412-1kworker/9:2H23:56:3511
1989599181cyclictest0-21swapper/920:17:3111
1989599181cyclictest0-21swapper/900:05:0111
1989399185cyclictest0-21swapper/720:00:019
19888991816cyclictest32386-21qemu-kvm20:08:237
19888991816cyclictest22893-21qemu-kvm22:46:047
19855991813cyclictest9722-21turbostat00:05:000
1989699173cyclictest0-21swapper/1019:45:312
1989699173cyclictest0-21swapper/1000:07:542
1989699173cyclictest0-21swapper/1000:07:542
1989699172cyclictest0-21swapper/1023:46:582
19896991716cyclictest9119-21cpuspeed_turbos21:50:142
19896991716cyclictest31244-1kworker/10:2H22:10:172
19896991716cyclictest31244-1kworker/10:2H22:10:172
1989699170cyclictest92172sleep1023:18:382
1989699170cyclictest77032chrt21:02:112
1989699170cyclictest74722sleep1021:45:282
1989699170cyclictest74722sleep1021:45:282
1989699170cyclictest72452sleep1020:17:082
1989699170cyclictest47762sleep1023:10:272
1989699170cyclictest39612sleep1020:56:232
1989699170cyclictest38332chrt19:30:012
1989699170cyclictest322742sleep1020:07:182
1989699170cyclictest316472sleep1023:50:062
1989699170cyclictest31582sleep1019:27:512
1989699170cyclictest312312sleep1000:31:002
1989699170cyclictest312312sleep1000:31:002
1989699170cyclictest312132sleep1021:35:152
1989699170cyclictest3066350irq/52-eth0-rx-23:55:302
1989699170cyclictest3066350irq/52-eth0-rx-23:35:232
1989699170cyclictest3066350irq/52-eth0-rx-23:21:032
1989699170cyclictest3066350irq/52-eth0-rx-22:25:142
1989699170cyclictest3066350irq/52-eth0-rx-20:47:092
1989699170cyclictest3066350irq/52-eth0-rx-20:00:202
1989699170cyclictest3066350irq/52-eth0-rx-00:20:222
1989699170cyclictest296922sleep1019:20:122
1989699170cyclictest296172sleep1021:32:142
1989699170cyclictest283982sleep1023:00:142
1989699170cyclictest281112chrt19:16:112
1989699170cyclictest258292chrt23:40:182
1989699170cyclictest255132sleep1020:42:572
1989699170cyclictest250902sleep1019:58:522
1989699170cyclictest24812chrt00:36:112
1989699170cyclictest233252sleep1022:53:112
1989699170cyclictest231602sleep1019:10:482
1989699170cyclictest213582sleep1019:52:422
1989699170cyclictest213582sleep1019:52:422
1989699170cyclictest199532chrt23:31:162
1989699170cyclictest190992sleep1000:15:212
1989699170cyclictest190992sleep1000:15:212
1989699170cyclictest182302sleep1020:32:562
1989699170cyclictest167792chrt00:12:092
1989699170cyclictest164262sleep1023:27:532
1989699170cyclictest159262chrt22:41:482
1989699170cyclictest157552sleep1021:15:012
1989699170cyclictest144512sleep1020:26:082
1989699170cyclictest141392sleep1021:10:252
1989699170cyclictest138922sleep1021:55:172
1989699170cyclictest125052sleep1019:40:152
1989699170cyclictest125052sleep1019:40:142
1989699170cyclictest12250irq/42-ahci22:45:482
1989699170cyclictest12250irq/42-ahci22:35:062
1989699170cyclictest12250irq/42-ahci22:08:572
1989699170cyclictest12250irq/42-ahci00:27:022
1989699170cyclictest12250irq/42-ahci00:27:012
1989699170cyclictest108102sleep1020:21:072
19895991716cyclictest0-21swapper/920:08:4111
19895991715cyclictest22521-21chrt21:24:4911
1989599170cyclictest31560-21fschecks_time21:35:1611
1989599170cyclictest0-21swapper/920:20:2111
1989399175cyclictest0-21swapper/723:00:029
19888991715cyclictest32387-21qemu-kvm20:47:237
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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