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2025-12-03 - 14:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Dec 03, 2025 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212772122108sleep100-21swapper/1007:05:382
21462210291sleep110-21swapper/1107:08:043
3066350950irq/52-eth0-rx-0-21swapper/507:05:327
3066350930irq/52-eth0-rx-0-21swapper/207:05:224
2161829388sleep30-21swapper/307:09:325
12250900irq/42-ahci0-21swapper/107:05:071
2162728481sleep90-21swapper/907:09:3811
3066450830irq/53-eth0-tx-0-21swapper/407:08:416
2133026653sleep60-21swapper/607:06:238
1848726554sleep00-21swapper/007:05:050
2158426462sleep80-21swapper/807:09:0010
2128926055sleep70-21swapper/707:05:489
21757992625cyclictest15294-21nscd07:15:140
2175799220cyclictest0-21swapper/007:45:250
2175799210cyclictest0-21swapper/011:25:230
2175799200cyclictest0-21swapper/011:20:270
2175799200cyclictest0-21swapper/010:50:250
2175799200cyclictest0-21swapper/010:50:250
2175799200cyclictest0-21swapper/007:25:260
2180499195cyclictest0-21swapper/907:25:0011
21757991917cyclictest0-21swapper/009:08:160
2175799190cyclictest0-21swapper/012:00:250
2175799190cyclictest0-21swapper/011:35:250
2175799190cyclictest0-21swapper/011:15:270
2175799190cyclictest0-21swapper/009:40:260
21805991817cyclictest0-21swapper/1012:22:252
21805991817cyclictest0-21swapper/1010:50:182
21805991817cyclictest0-21swapper/1010:50:182
21805991817cyclictest0-21swapper/1007:10:232
2180599181cyclictest831ksoftirqd/1012:15:292
2180599181cyclictest831ksoftirqd/1011:20:002
2180599181cyclictest831ksoftirqd/1010:35:142
2180599181cyclictest831ksoftirqd/1010:35:142
2180599181cyclictest12250irq/42-ahci09:08:542
2180499181cyclictest12250irq/42-ahci07:40:2011
2180499181cyclictest0-21swapper/909:15:0211
2180499181cyclictest0-21swapper/908:33:2411
21803991816cyclictest7113-21diskstats08:15:1310
21803991816cyclictest6990-21snmp_rack3slot907:30:1610
21803991816cyclictest4667-21perl09:40:1610
21803991816cyclictest31124-21iostat_ios11:00:2010
21803991816cyclictest29090-21snmp_rack3slot911:40:4910
21803991816cyclictest28990-21memory07:15:2610
21803991816cyclictest28750-21snmp_rack3slot910:56:3610
21803991816cyclictest26732-21snmp_rack3slot910:10:1610
21803991816cyclictest24627-21iostat12:20:2010
21803991816cyclictest2117-21snmp_rack3slot908:50:4910
21803991816cyclictest18391-21perl08:30:1510
21803991816cyclictest15312-21snmp_rack3slot910:40:1410
2176699183cyclictest0-21swapper/108:35:171
2176699182cyclictest0-21swapper/111:30:011
21757991816cyclictest20653-21chrt09:18:070
2175799180cyclictest0-21swapper/012:10:270
2175799180cyclictest0-21swapper/011:45:260
2175799180cyclictest0-21swapper/010:15:240
21806991716cyclictest280672sleep1109:29:443
21805991716cyclictest9812-21smartctl12:00:152
21805991716cyclictest8880-21python09:00:272
21805991716cyclictest831ksoftirqd/1011:50:132
21805991716cyclictest831ksoftirqd/1009:25:142
21805991716cyclictest831ksoftirqd/1008:05:152
21805991716cyclictest7789-21expr09:45:132
21805991716cyclictest5227-21cat08:10:282
21805991716cyclictest26602-21latency_hist12:25:012
21805991716cyclictest20235-21grep10:45:192
21805991716cyclictest18014-1kworker/10:1H09:10:022
21805991716cyclictest16647-21sensors09:55:262
2180599170cyclictest90452sleep1008:15:342
2180599170cyclictest831ksoftirqd/1011:05:122
2180599170cyclictest831ksoftirqd/1010:00:252
2180599170cyclictest831ksoftirqd/1009:20:202
2180599170cyclictest831ksoftirqd/1008:55:132
2180599170cyclictest831ksoftirqd/1008:35:122
2180599170cyclictest76902chrt11:56:352
2180599170cyclictest73902chrt11:12:182
2180599170cyclictest6482sleep1012:30:512
2180599170cyclictest63362sleep1009:40:442
2180599170cyclictest49372sleep1007:26:052
2180599170cyclictest3252sleep1011:46:452
2180599170cyclictest323402sleep1011:00:532
2180599170cyclictest319452sleep1010:16:132
2180599170cyclictest314912chrt09:31:422
2180599170cyclictest3066350irq/52-eth0-rx-10:25:132
2180599170cyclictest3066350irq/52-eth0-rx-08:45:142
2180599170cyclictest3066350irq/52-eth0-rx-08:40:192
2180599170cyclictest3066350irq/52-eth0-rx-08:40:192
2180599170cyclictest3066350irq/52-eth0-rx-08:26:132
2180599170cyclictest3066350irq/52-eth0-rx-08:26:122
2180599170cyclictest3066350irq/52-eth0-rx-07:35:152
2180599170cyclictest299802sleep1007:15:392
2180599170cyclictest290652sleep1011:40:332
2180599170cyclictest288122chrt10:57:272
2180599170cyclictest285372sleep1010:14:232
2180599170cyclictest268652sleep1007:57:072
2180599170cyclictest25572sleep1010:20:252
2180599170cyclictest254332sleep1011:35:322
2180599170cyclictest246032sleep1010:06:112
2180599170cyclictest23962sleep1012:35:152
2180599170cyclictest22152sleep1008:52:032
2180599170cyclictest218762sleep1011:31:322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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