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2026-02-26 - 03:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Feb 26, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501130irq/42-ahci0-21swapper/219:08:294
13263210995sleep50-21swapper/519:05:107
9918501020irq/53-eth0-rx-0-21swapper/919:09:5811
128501020irq/42-ahci0-21swapper/119:10:001
991850950irq/53-eth0-rx-0-21swapper/319:08:275
991850950irq/53-eth0-rx-0-21swapper/1119:07:473
991850930irq/53-eth0-rx-0-21swapper/1019:06:122
991850910irq/53-eth0-rx-0-21swapper/819:05:0710
991850910irq/53-eth0-rx-0-21swapper/419:05:256
991850900irq/53-eth0-rx-0-21swapper/719:07:569
1620726453sleep00-21swapper/019:07:400
1607325955sleep60-21swapper/619:05:588
16580993013cyclictest831ksoftirqd/1021:50:002
16580993013cyclictest811rcuc/1022:52:102
16580992912cyclictest831ksoftirqd/1023:37:522
16580992610cyclictest831ksoftirqd/1021:41:302
1658099258cyclictest831ksoftirqd/1022:19:142
1658099258cyclictest831ksoftirqd/1019:45:192
1658099214cyclictest831ksoftirqd/1021:20:402
1658599205cyclictest221532sleep1122:11:483
1658099192cyclictest991850irq/53-eth0-rx-22:25:112
1658099192cyclictest991850irq/53-eth0-rx-22:24:442
1658099192cyclictest991850irq/53-eth0-rx-22:00:192
1658099192cyclictest991850irq/53-eth0-rx-21:48:562
1657999192cyclictest0-21swapper/921:18:0411
1658599180cyclictest0-21swapper/1119:12:363
16580991817cyclictest0-21swapper/1023:45:332
16580991817cyclictest0-21swapper/1023:10:142
16580991817cyclictest0-21swapper/1020:36:212
16580991817cyclictest0-21swapper/1000:20:432
1658099181cyclictest991950irq/54-eth0-tx-21:25:282
1658099181cyclictest991950irq/54-eth0-tx-00:35:442
1658099181cyclictest991850irq/53-eth0-rx-23:55:102
1658099181cyclictest991850irq/53-eth0-rx-23:43:462
1658099181cyclictest991850irq/53-eth0-rx-23:33:582
1658099181cyclictest991850irq/53-eth0-rx-23:17:012
1658099181cyclictest991850irq/53-eth0-rx-22:59:582
1658099181cyclictest991850irq/53-eth0-rx-22:59:572
1658099181cyclictest991850irq/53-eth0-rx-22:36:192
1658099181cyclictest991850irq/53-eth0-rx-22:34:452
1658099181cyclictest991850irq/53-eth0-rx-22:14:142
1658099181cyclictest991850irq/53-eth0-rx-21:58:542
1658099181cyclictest991850irq/53-eth0-rx-21:36:442
1658099181cyclictest991850irq/53-eth0-rx-21:10:262
1658099181cyclictest991850irq/53-eth0-rx-00:28:442
1658099181cyclictest991850irq/53-eth0-rx-00:17:352
1658099181cyclictest991850irq/53-eth0-rx-00:06:192
1658099181cyclictest991850irq/53-eth0-rx-00:00:422
1658099181cyclictest831ksoftirqd/1023:20:112
1658099181cyclictest831ksoftirqd/1023:20:102
1658099181cyclictest831ksoftirqd/1023:02:152
1658099181cyclictest831ksoftirqd/1022:40:352
1658099181cyclictest12850irq/42-ahci22:05:152
1657999181cyclictest9008-21sh21:10:0811
1657999181cyclictest761ksoftirqd/923:45:2511
1657999181cyclictest761ksoftirqd/923:10:1111
1657999181cyclictest761ksoftirqd/922:40:1411
1657999181cyclictest761ksoftirqd/922:18:5311
1657999181cyclictest761ksoftirqd/920:15:2511
1657999181cyclictest761ksoftirqd/920:15:2411
1657999181cyclictest761ksoftirqd/919:45:1911
1657999181cyclictest761ksoftirqd/900:05:2211
1657999181cyclictest6231-21if_err_tap020:20:1611
1657999181cyclictest6231-21if_err_tap020:20:1611
1657999181cyclictest547-21ssh00:31:4811
1657999181cyclictest4571-21cat00:10:0111
1657999181cyclictest30282-21cat20:10:1211
1657999181cyclictest26425-21kernelversion00:00:1811
1657999181cyclictest24825-21ssh21:21:2111
1657999181cyclictest19641-21diskstats19:55:1311
1657999181cyclictest16233-21df23:00:1311
1657999181cyclictest1313-21diskstats19:30:1211
1657999181cyclictest12-21rcu_preempt23:50:2511
1657999181cyclictest12-21rcu_preempt23:05:1211
1657999181cyclictest12-21rcu_preempt23:05:1111
1657999181cyclictest12-21rcu_preempt21:55:1711
1657999181cyclictest12-21rcu_preempt20:36:1811
1657999181cyclictest0-21swapper/923:55:4911
1657999181cyclictest0-21swapper/923:40:0611
1657999181cyclictest0-21swapper/923:35:1411
1657999181cyclictest0-21swapper/923:30:2211
1657999181cyclictest0-21swapper/923:25:1911
1657999181cyclictest0-21swapper/923:20:2911
1657999181cyclictest0-21swapper/923:20:2811
1657999181cyclictest0-21swapper/923:16:5411
1657999181cyclictest0-21swapper/922:56:4011
1657999181cyclictest0-21swapper/922:56:3911
1657999181cyclictest0-21swapper/922:50:1111
1657999181cyclictest0-21swapper/922:46:2011
1657999181cyclictest0-21swapper/922:35:4911
1657999181cyclictest0-21swapper/922:30:0111
1657999181cyclictest0-21swapper/922:25:2411
1657999181cyclictest0-21swapper/922:23:1711
1657999181cyclictest0-21swapper/922:12:3911
1657999181cyclictest0-21swapper/922:05:0511
1657999181cyclictest0-21swapper/922:00:1211
1657999181cyclictest0-21swapper/921:50:0511
1657999181cyclictest0-21swapper/921:45:1511
1657999181cyclictest0-21swapper/921:40:0811
1657999181cyclictest0-21swapper/921:36:5311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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