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2026-04-14 - 14:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Apr 14, 2026 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501140irq/53-eth0-rx-0-21swapper/707:08:239
9918501130irq/53-eth0-rx-0-21swapper/207:09:254
2802210995sleep90-21swapper/907:05:5511
1161210189sleep50-21swapper/507:05:157
991850980irq/53-eth0-rx-0-21swapper/107:09:051
991850930irq/53-eth0-rx-0-21swapper/407:05:046
991850920irq/53-eth0-rx-0-21swapper/807:08:1210
991850850irq/53-eth0-rx-0-21swapper/1107:06:113
12850780irq/42-ahci0-21swapper/307:05:265
313026763sleep100-21swapper/1007:09:082
300526654sleep00-21swapper/007:08:110
279926353sleep60-21swapper/607:05:538
3309992914cyclictest0-21swapper/010:26:390
330999220cyclictest0-21swapper/009:30:010
330999210cyclictest0-21swapper/009:30:070
333399203cyclictest145102cat08:05:182
3309991917cyclictest0-21swapper/007:28:410
333399181cyclictest991850irq/53-eth0-rx-11:56:092
333399181cyclictest991850irq/53-eth0-rx-11:54:212
333399181cyclictest991850irq/53-eth0-rx-11:48:292
333399181cyclictest991850irq/53-eth0-rx-11:37:212
333399181cyclictest991850irq/53-eth0-rx-11:26:592
333399181cyclictest991850irq/53-eth0-rx-11:10:042
333399181cyclictest991850irq/53-eth0-rx-10:13:472
333399181cyclictest991850irq/53-eth0-rx-09:53:422
333399181cyclictest991850irq/53-eth0-rx-09:41:292
333399181cyclictest991850irq/53-eth0-rx-09:30:432
333399181cyclictest991850irq/53-eth0-rx-09:29:072
333399181cyclictest22202chrt12:18:442
333399180cyclictest0-21swapper/1012:10:142
333299181cyclictest761ksoftirqd/911:35:3911
333299181cyclictest0-21swapper/912:37:4211
333299181cyclictest0-21swapper/912:25:0311
333299181cyclictest0-21swapper/912:20:2611
333299181cyclictest0-21swapper/912:20:2511
333299181cyclictest0-21swapper/911:40:3611
333299181cyclictest0-21swapper/910:30:0911
333299181cyclictest0-21swapper/910:10:2011
3329991816cyclictest3469-21qemu-kvm10:08:288
3333991716cyclictest0-21swapper/1011:40:522
3333991716cyclictest0-21swapper/1011:20:152
3333991716cyclictest0-21swapper/1010:40:532
3333991715cyclictest811rcuc/1007:56:012
333399170cyclictest991950irq/54-eth0-tx-12:25:052
333399170cyclictest991850irq/53-eth0-rx-12:36:302
333399170cyclictest991850irq/53-eth0-rx-12:30:472
333399170cyclictest991850irq/53-eth0-rx-12:30:472
333399170cyclictest991850irq/53-eth0-rx-12:20:042
333399170cyclictest991850irq/53-eth0-rx-12:20:032
333399170cyclictest991850irq/53-eth0-rx-12:00:252
333399170cyclictest991850irq/53-eth0-rx-11:30:102
333399170cyclictest991850irq/53-eth0-rx-10:50:332
333399170cyclictest991850irq/53-eth0-rx-10:35:432
333399170cyclictest991850irq/53-eth0-rx-10:30:272
333399170cyclictest991850irq/53-eth0-rx-10:27:262
333399170cyclictest991850irq/53-eth0-rx-10:20:012
333399170cyclictest991850irq/53-eth0-rx-09:36:082
333399170cyclictest991850irq/53-eth0-rx-09:20:162
333399170cyclictest991850irq/53-eth0-rx-09:20:152
333399170cyclictest991850irq/53-eth0-rx-09:15:152
333399170cyclictest991850irq/53-eth0-rx-09:15:142
333399170cyclictest991850irq/53-eth0-rx-08:10:212
333399170cyclictest991850irq/53-eth0-rx-07:30:132
333399170cyclictest90002sleep1008:42:182
333399170cyclictest68222chrt07:13:572
333399170cyclictest53862sleep1011:01:012
333399170cyclictest47692chrt07:51:492
333399170cyclictest317922sleep1010:56:222
333399170cyclictest313292sleep1009:10:582
333399170cyclictest312022sleep1010:05:052
333399170cyclictest305152sleep1008:28:412
333399170cyclictest297802sleep1007:41:122
333399170cyclictest272792chrt09:07:332
333399170cyclictest272792chrt09:07:322
333399170cyclictest267512sleep1008:22:052
333399170cyclictest261922sleep1007:36:592
333399170cyclictest23762sleep1008:35:062
333399170cyclictest23762sleep1008:35:052
333399170cyclictest234522chrt09:00:332
333399170cyclictest231032chrt08:17:042
333399170cyclictest218202sleep1009:55:272
333399170cyclictest206142sleep1012:05:432
333399170cyclictest204162sleep1011:15:012
333399170cyclictest191932sleep1010:45:572
333399170cyclictest186932chrt08:55:192
333399170cyclictest15532sleep1008:31:292
333399170cyclictest152202sleep1007:21:202
333399170cyclictest142612sleep1010:15:312
333399170cyclictest133802chrt08:50:082
333399170cyclictest12850irq/42-ahci10:01:052
333399170cyclictest12850irq/42-ahci08:00:172
333399170cyclictest126152chrt08:46:562
333399170cyclictest116832sleep1007:17:572
333399170cyclictest106752sleep1011:05:242
333399170cyclictest10412sleep1007:47:232
333399170cyclictest103052sleep1009:46:492
3332991716cyclictest0-21swapper/907:40:1711
333299170cyclictest0-21swapper/912:30:2611
333299170cyclictest0-21swapper/912:30:2611
333299170cyclictest0-21swapper/912:10:0811
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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