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2026-09-05 - 21:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Sep 05, 2026 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9146210693sleep70-21swapper/707:06:569
30549501010irq/53-eth0-rx-0-21swapper/407:05:376
30549501000irq/53-eth0-rx-0-21swapper/107:08:211
3054950970irq/53-eth0-rx-0-21swapper/507:06:567
3054950950irq/53-eth0-rx-0-21swapper/807:06:3210
3054950950irq/53-eth0-rx-0-21swapper/207:08:574
3054950930irq/53-eth0-rx-0-21swapper/1107:05:563
3055050910irq/54-eth0-tx-0-21swapper/307:08:415
939826664sleep90-21swapper/907:09:3511
913026454sleep60-21swapper/607:06:428
915226353sleep00-21swapper/007:07:020
914926353sleep100-21swapper/1007:07:002
9536992914cyclictest0-21swapper/010:24:350
958399206cyclictest831ksoftirqd/1008:02:182
958399205cyclictest831ksoftirqd/1007:46:562
958399205cyclictest831ksoftirqd/1007:40:392
958399192cyclictest3054950irq/53-eth0-rx-11:56:572
958399192cyclictest3054950irq/53-eth0-rx-11:54:102
958399192cyclictest3054950irq/53-eth0-rx-11:30:262
958399192cyclictest3054950irq/53-eth0-rx-11:09:222
958399192cyclictest3054950irq/53-eth0-rx-10:06:362
958399192cyclictest12250irq/42-ahci11:11:372
9583991918cyclictest3055050irq/54-eth0-tx-11:40:242
9583991912cyclictest831ksoftirqd/1011:48:342
958299195cyclictest0-21swapper/912:24:1711
958299192cyclictest0-21swapper/912:31:1111
958299192cyclictest0-21swapper/912:25:0111
958299192cyclictest0-21swapper/912:25:0111
958299192cyclictest0-21swapper/912:07:5411
958299192cyclictest0-21swapper/910:25:1911
958299192cyclictest0-21swapper/910:03:2011
958299192cyclictest0-21swapper/910:03:2011
958299192cyclictest0-21swapper/909:54:4511
958299192cyclictest0-21swapper/909:18:5411
957899195cyclictest0-21swapper/612:10:198
957899195cyclictest0-21swapper/611:40:208
9583991817cyclictest831ksoftirqd/1012:14:482
9583991817cyclictest7663-21kworker/10:111:36:332
9583991817cyclictest0-21swapper/1012:07:282
9583991817cyclictest0-21swapper/1010:58:252
9583991817cyclictest0-21swapper/1009:56:292
9583991817cyclictest0-21swapper/1009:47:012
9583991817cyclictest0-21swapper/1009:30:422
9583991817cyclictest0-21swapper/1007:56:272
958399181cyclictest831ksoftirqd/1012:15:132
958399181cyclictest831ksoftirqd/1012:00:142
958399181cyclictest831ksoftirqd/1011:15:132
958399181cyclictest831ksoftirqd/1010:30:252
958399181cyclictest831ksoftirqd/1010:20:202
958399181cyclictest831ksoftirqd/1008:35:122
958399181cyclictest831ksoftirqd/1007:50:252
958399181cyclictest3055050irq/54-eth0-tx-10:36:552
958399181cyclictest3055050irq/54-eth0-tx-10:02:562
958399181cyclictest3055050irq/54-eth0-tx-10:02:562
958399181cyclictest3054950irq/53-eth0-rx-12:38:272
958399181cyclictest3054950irq/53-eth0-rx-12:26:052
958399181cyclictest3054950irq/53-eth0-rx-12:26:052
958399181cyclictest3054950irq/53-eth0-rx-10:10:432
958399181cyclictest3054950irq/53-eth0-rx-09:51:512
958399181cyclictest3054950irq/53-eth0-rx-09:29:442
958399181cyclictest3054950irq/53-eth0-rx-09:29:442
958399181cyclictest3054950irq/53-eth0-rx-08:17:032
958399181cyclictest222142sleep1008:08:532
958299181cyclictest0-21swapper/911:46:3111
958299181cyclictest0-21swapper/911:30:5511
958299181cyclictest0-21swapper/911:15:1111
958299181cyclictest0-21swapper/910:40:2111
958299181cyclictest0-21swapper/910:21:3911
958299181cyclictest0-21swapper/910:16:2211
957899184cyclictest0-21swapper/607:36:568
9555991816cyclictest16188-21snmp_rack3slot908:45:124
3054950180irq/53-eth0-rx-0-21swapper/1110:24:523
31180ksoftirqd/00-21swapper/010:40:230
9583991716cyclictest831ksoftirqd/1009:05:142
9583991716cyclictest831ksoftirqd/1009:05:142
9583991716cyclictest831ksoftirqd/1007:15:242
9583991716cyclictest31752-21sensors07:35:232
9583991716cyclictest0-21swapper/1011:25:112
9583991716cyclictest0-21swapper/1010:15:222
9583991716cyclictest0-21swapper/1007:10:202
958399170cyclictest831ksoftirqd/1011:20:052
958399170cyclictest831ksoftirqd/1011:00:132
958399170cyclictest831ksoftirqd/1010:50:052
958399170cyclictest831ksoftirqd/1010:45:152
958399170cyclictest831ksoftirqd/1010:40:122
958399170cyclictest831ksoftirqd/1009:35:192
958399170cyclictest831ksoftirqd/1009:00:132
958399170cyclictest831ksoftirqd/1008:50:012
958399170cyclictest831ksoftirqd/1007:30:132
958399170cyclictest831ksoftirqd/1007:30:122
958399170cyclictest80202chrt08:32:442
958399170cyclictest5882sleep1008:22:312
958399170cyclictest3054950irq/53-eth0-rx-12:20:182
958399170cyclictest3054950irq/53-eth0-rx-10:25:252
958399170cyclictest3054950irq/53-eth0-rx-09:40:222
958399170cyclictest3054950irq/53-eth0-rx-09:21:292
958399170cyclictest3054950irq/53-eth0-rx-09:15:142
958399170cyclictest3054950irq/53-eth0-rx-09:10:052
958399170cyclictest3054950irq/53-eth0-rx-08:40:172
958399170cyclictest3054950irq/53-eth0-rx-08:29:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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