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2026-08-20 - 02:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Aug 20, 2026 00:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501110irq/53-eth0-rx-0-21swapper/219:05:304
122501110irq/42-ahci0-21swapper/119:09:121
3054950990irq/53-eth0-rx-0-21swapper/719:08:139
4099970migration/40-21swapper/419:08:016
1883829691sleep30-21swapper/319:08:395
3054950870irq/53-eth0-rx-0-21swapper/519:08:077
1099870migration/00-21swapper/019:08:010
1863728475sleep100-21swapper/1019:06:462
3054950830irq/53-eth0-rx-0-21swapper/819:05:2710
119150640irq/18-parport00-21swapper/919:09:1311
3054950600irq/53-eth0-rx-0-21swapper/1119:08:093
1575225846sleep60-21swapper/619:05:058
1910199350cyclictest0-21swapper/022:09:470
1910199320cyclictest0-21swapper/019:21:000
1917699310cyclictest0-21swapper/1119:18:493
19101993011cyclictest0-21swapper/019:25:320
19101992410cyclictest0-21swapper/021:30:130
1910199240cyclictest0-21swapper/019:17:160
1917699238cyclictest3054950irq/53-eth0-rx-19:29:383
1910199230cyclictest0-21swapper/019:30:210
1917699210cyclictest0-21swapper/1119:30:013
1917699210cyclictest0-21swapper/1119:21:373
19144992116cyclictest0-21swapper/723:51:079
19139992114cyclictest0-21swapper/620:54:558
1910199200cyclictest0-21swapper/022:10:020
1916899192cyclictest3054950irq/53-eth0-rx-23:24:192
1916899192cyclictest3054950irq/53-eth0-rx-22:24:462
1916899192cyclictest3054950irq/53-eth0-rx-21:44:082
1916199195cyclictest0-21swapper/921:15:1711
1916199192cyclictest0-21swapper/923:47:0911
1916199192cyclictest0-21swapper/922:32:5111
1916199192cyclictest0-21swapper/921:53:1111
1916199192cyclictest0-21swapper/900:05:5811
1917699183cyclictest0-21swapper/1122:30:013
19168991817cyclictest0-21swapper/1023:45:442
19168991817cyclictest0-21swapper/1023:01:582
19168991817cyclictest0-21swapper/1022:38:352
19168991817cyclictest0-21swapper/1022:30:262
19168991817cyclictest0-21swapper/1022:13:432
19168991817cyclictest0-21swapper/1022:04:152
19168991817cyclictest0-21swapper/1000:34:342
1916899181cyclictest3055050irq/54-eth0-tx-23:16:012
1916899181cyclictest3055050irq/54-eth0-tx-23:13:432
1916899181cyclictest3054950irq/53-eth0-rx-23:56:232
1916899181cyclictest3054950irq/53-eth0-rx-23:56:232
1916899181cyclictest3054950irq/53-eth0-rx-23:28:452
1916899181cyclictest3054950irq/53-eth0-rx-23:06:062
1916899181cyclictest3054950irq/53-eth0-rx-22:52:462
1916899181cyclictest3054950irq/53-eth0-rx-22:42:382
1916899181cyclictest3054950irq/53-eth0-rx-21:58:462
1916899181cyclictest3054950irq/53-eth0-rx-21:52:042
1916899181cyclictest3054950irq/53-eth0-rx-21:49:082
1916899181cyclictest3054950irq/53-eth0-rx-21:23:262
1916899181cyclictest3054950irq/53-eth0-rx-21:17:362
1916899181cyclictest3054950irq/53-eth0-rx-21:11:092
1916899181cyclictest3054950irq/53-eth0-rx-20:17:252
1916899181cyclictest3054950irq/53-eth0-rx-19:39:352
1916899181cyclictest3054950irq/53-eth0-rx-19:22:162
1916899181cyclictest12250irq/42-ahci00:19:192
1916199181cyclictest23983-21snmp_rack3slot921:45:1211
1916199181cyclictest0-21swapper/923:55:2511
1916199181cyclictest0-21swapper/923:55:2511
1916199181cyclictest0-21swapper/923:53:0811
1916199181cyclictest0-21swapper/923:25:1311
1916199181cyclictest0-21swapper/923:11:4911
1916199181cyclictest0-21swapper/922:27:3511
1916199181cyclictest0-21swapper/922:19:0011
1916199181cyclictest0-21swapper/922:09:2311
1916199181cyclictest0-21swapper/921:55:3911
1916199181cyclictest0-21swapper/921:25:1111
1916199181cyclictest0-21swapper/920:16:0211
1916199181cyclictest0-21swapper/919:15:1511
1916199181cyclictest0-21swapper/900:21:3611
1916199181cyclictest0-21swapper/900:14:1111
1916199181cyclictest0-21swapper/900:14:1111
19101991817cyclictest10972-21diskmemload21:15:100
19176991716cyclictest31808-21turbostat20:10:003
19168991716cyclictest0-21swapper/1023:35:322
19168991716cyclictest0-21swapper/1022:25:012
19168991716cyclictest0-21swapper/1021:25:042
1916899170cyclictest831ksoftirqd/1021:05:222
1916899170cyclictest72672sleep1020:20:052
1916899170cyclictest60852sleep1019:33:362
1916899170cyclictest33212sleep1020:56:332
1916899170cyclictest323162sleep1020:10:032
1916899170cyclictest314892chrt00:00:552
1916899170cyclictest314102sleep1020:05:392
1916899170cyclictest3055050irq/54-eth0-tx-19:10:162
1916899170cyclictest3054950irq/53-eth0-rx-23:50:172
1916899170cyclictest3054950irq/53-eth0-rx-23:40:192
1916899170cyclictest3054950irq/53-eth0-rx-23:30:272
1916899170cyclictest3054950irq/53-eth0-rx-22:55:482
1916899170cyclictest3054950irq/53-eth0-rx-22:45:462
1916899170cyclictest3054950irq/53-eth0-rx-22:16:032
1916899170cyclictest3054950irq/53-eth0-rx-22:05:572
1916899170cyclictest3054950irq/53-eth0-rx-21:35:052
1916899170cyclictest3054950irq/53-eth0-rx-21:30:042
1916899170cyclictest3054950irq/53-eth0-rx-20:50:252
1916899170cyclictest3054950irq/53-eth0-rx-20:30:202
1916899170cyclictest3054950irq/53-eth0-rx-00:35:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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