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2026-09-04 - 19:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Sep 04, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501110irq/42-ahci0-21swapper/107:09:151
122501110irq/42-ahci0-21swapper/107:09:141
122501080irq/42-ahci0-21swapper/207:09:084
122501080irq/42-ahci0-21swapper/207:09:074
853210794sleep50-21swapper/507:07:207
853210794sleep50-21swapper/507:07:207
3054950980irq/53-eth0-rx-0-21swapper/307:05:565
3054950980irq/53-eth0-rx-0-21swapper/307:05:565
3054950940irq/53-eth0-rx-0-21swapper/807:07:0710
3054950940irq/53-eth0-rx-0-21swapper/807:07:0610
3054950920irq/53-eth0-rx-0-21swapper/907:09:0711
3054950920irq/53-eth0-rx-0-21swapper/907:09:0711
3054950910irq/53-eth0-rx-0-21swapper/707:06:529
3054950910irq/53-eth0-rx-0-21swapper/707:06:519
3054950910irq/53-eth0-rx-0-21swapper/407:06:326
3054950910irq/53-eth0-rx-0-21swapper/407:06:316
3054950910irq/53-eth0-rx-0-21swapper/1007:05:402
3054950910irq/53-eth0-rx-0-21swapper/1007:05:402
72625955sleep00-21swapper/007:05:390
72625955sleep00-21swapper/007:05:390
71325955sleep60-21swapper/607:05:338
71325955sleep60-21swapper/607:05:338
78125853sleep110-21swapper/1107:06:263
78125853sleep110-21swapper/1107:06:263
126999320cyclictest0-21swapper/1107:12:313
126999310cyclictest0-21swapper/1107:22:343
123199310cyclictest0-21swapper/008:14:300
1269992928cyclictest0-21swapper/1108:17:503
123199290cyclictest0-21swapper/008:20:430
126499221cyclictest0-21swapper/609:44:568
126999192cyclictest0-21swapper/1112:19:283
126899192cyclictest3054950irq/53-eth0-rx-10:56:282
126899192cyclictest3054950irq/53-eth0-rx-10:41:562
126899192cyclictest3054950irq/53-eth0-rx-10:41:562
126899192cyclictest3054950irq/53-eth0-rx-10:34:112
126899192cyclictest3054950irq/53-eth0-rx-10:05:342
126899192cyclictest3054950irq/53-eth0-rx-09:50:042
126899192cyclictest3054950irq/53-eth0-rx-09:39:302
126899192cyclictest3054950irq/53-eth0-rx-09:33:502
126799192cyclictest0-21swapper/912:23:2111
126999180cyclictest0-21swapper/1108:13:493
1268991817cyclictest0-21swapper/1012:00:212
1268991817cyclictest0-21swapper/1011:39:422
1268991816cyclictest15693-21kworker/10:012:40:002
126899181cyclictest831ksoftirqd/1008:25:162
126899181cyclictest3055050irq/54-eth0-tx-10:25:362
126899181cyclictest3054950irq/53-eth0-rx-12:32:372
126899181cyclictest3054950irq/53-eth0-rx-12:23:532
126899181cyclictest3054950irq/53-eth0-rx-12:15:392
126899181cyclictest3054950irq/53-eth0-rx-11:55:482
126899181cyclictest3054950irq/53-eth0-rx-11:50:032
126899181cyclictest3054950irq/53-eth0-rx-11:45:332
126899181cyclictest3054950irq/53-eth0-rx-11:42:212
126899181cyclictest3054950irq/53-eth0-rx-11:30:462
126899181cyclictest3054950irq/53-eth0-rx-11:20:212
126899181cyclictest3054950irq/53-eth0-rx-11:15:112
126899181cyclictest3054950irq/53-eth0-rx-11:06:482
126899181cyclictest3054950irq/53-eth0-rx-10:52:542
126899181cyclictest3054950irq/53-eth0-rx-10:47:232
126899181cyclictest3054950irq/53-eth0-rx-10:35:172
126899181cyclictest3054950irq/53-eth0-rx-10:20:062
126899181cyclictest3054950irq/53-eth0-rx-10:15:402
126899181cyclictest3054950irq/53-eth0-rx-10:10:092
126899181cyclictest3054950irq/53-eth0-rx-10:00:532
126899181cyclictest3054950irq/53-eth0-rx-09:48:562
126899181cyclictest3054950irq/53-eth0-rx-09:41:502
126899181cyclictest3054950irq/53-eth0-rx-09:25:052
126899181cyclictest3054950irq/53-eth0-rx-09:22:572
126899181cyclictest3054950irq/53-eth0-rx-09:16:582
126899181cyclictest3054950irq/53-eth0-rx-09:10:222
126899181cyclictest3054950irq/53-eth0-rx-07:17:452
126899181cyclictest277862sleep1012:10:252
126899181cyclictest12250irq/42-ahci07:45:372
126799181cyclictest761ksoftirqd/907:20:2511
126799181cyclictest6891-21cpuspeed07:15:1111
126799181cyclictest0-21swapper/911:50:2111
126799181cyclictest0-21swapper/911:37:4311
126799181cyclictest0-21swapper/911:14:4811
126799181cyclictest0-21swapper/911:06:4611
126799181cyclictest0-21swapper/910:46:5711
126799181cyclictest0-21swapper/910:23:5711
126799181cyclictest0-21swapper/909:40:1311
126799181cyclictest0-21swapper/909:33:0111
126799181cyclictest0-21swapper/909:25:1111
126799181cyclictest0-21swapper/909:23:2411
126799181cyclictest0-21swapper/909:11:5311
1254991816cyclictest2305-21snmpd10:42:484
1254991816cyclictest2305-21snmpd10:42:484
1268991716cyclictest0-21swapper/1012:25:132
126899170cyclictest63982sleep1007:55:542
126899170cyclictest47932sleep1007:13:002
126899170cyclictest3054950irq/53-eth0-rx-12:05:112
126899170cyclictest3054950irq/53-eth0-rx-11:25:182
126899170cyclictest3054950irq/53-eth0-rx-11:00:112
126899170cyclictest3054950irq/53-eth0-rx-09:02:102
126899170cyclictest3054950irq/53-eth0-rx-08:51:222
126899170cyclictest3054950irq/53-eth0-rx-08:40:122
126899170cyclictest3054950irq/53-eth0-rx-08:35:042
126899170cyclictest3054950irq/53-eth0-rx-08:30:162
126899170cyclictest3054950irq/53-eth0-rx-08:21:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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