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2025-11-26 - 17:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Nov 26, 2025 12:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30664501150irq/53-eth0-tx-0-21swapper/1007:06:372
23470210895sleep90-21swapper/907:06:2711
23529210692sleep60-21swapper/607:07:128
122501040irq/42-ahci0-21swapper/107:09:091
3066450950irq/53-eth0-tx-0-21swapper/207:08:264
2222029485sleep30-21swapper/307:05:215
3066350920irq/52-eth0-rx-0-21swapper/507:07:407
3066450820irq/53-eth0-tx-0-21swapper/407:05:306
2344526755sleep00-21swapper/007:06:060
2359826658sleep110-21swapper/1107:08:063
2354426354sleep70-21swapper/707:07:259
2350125853sleep80-21swapper/807:06:5010
2390599320cyclictest0-21swapper/007:25:160
23945992322cyclictest0-21swapper/1107:28:023
2393099192cyclictest0-21swapper/312:10:175
2393099192cyclictest0-21swapper/311:51:575
2393099192cyclictest0-21swapper/307:48:265
23945991817cyclictest7686-21taskset08:12:363
23944991817cyclictest0-21swapper/1011:29:502
23944991816cyclictest22438-21python10:00:262
2394499181cyclictest31372chrt12:34:042
2394499181cyclictest12250irq/42-ahci10:35:162
2394499181cyclictest12250irq/42-ahci08:46:362
2394499181cyclictest12250irq/42-ahci08:22:162
2394399181cyclictest0-21swapper/911:15:2211
2394399181cyclictest0-21swapper/908:26:3611
2394399181cyclictest0-21swapper/907:45:1511
23942991816cyclictest9498-21perl08:15:1310
23942991816cyclictest796-21iostat11:00:1910
23942991816cyclictest7950-21snmp_easybox.os07:30:1210
23942991816cyclictest5886-21snmp_rack3slot912:35:2410
23942991816cyclictest5197-21snmp_rack3slot908:10:1110
23942991816cyclictest31216-21snmp_rack3slot909:30:1210
23942991816cyclictest28407-21snmp_rack3slot909:25:1810
23942991816cyclictest24452-21snmp_easybox.os10:50:1110
23942991816cyclictest24257-21memory07:50:2110
23942991816cyclictest22314-21df12:15:1310
23942991816cyclictest15799-21snmp_rack3slot909:51:2510
23942991816cyclictest13453-21snmp_easybox.os10:35:1210
23942991816cyclictest13290-21snmp_rack3slot908:20:1810
23942991816cyclictest12627-21ntp_states12:00:2410
23942991816cyclictest12627-21ntp_states12:00:2410
2393399180cyclictest0-21swapper/607:28:028
2393099182cyclictest0-21swapper/312:36:225
2393099182cyclictest0-21swapper/312:30:085
2393099182cyclictest0-21swapper/312:26:145
2393099182cyclictest0-21swapper/312:20:535
2393099182cyclictest0-21swapper/312:15:455
2393099182cyclictest0-21swapper/312:07:005
2393099182cyclictest0-21swapper/312:01:315
2393099182cyclictest0-21swapper/312:01:305
2393099182cyclictest0-21swapper/311:55:535
2393099182cyclictest0-21swapper/311:55:525
2393099182cyclictest0-21swapper/311:46:475
2393099182cyclictest0-21swapper/311:40:465
2393099182cyclictest0-21swapper/311:38:025
2393099182cyclictest0-21swapper/311:32:125
2393099182cyclictest0-21swapper/311:21:035
2393099182cyclictest0-21swapper/311:15:455
2393099182cyclictest0-21swapper/311:10:075
2393099182cyclictest0-21swapper/311:05:525
2393099182cyclictest0-21swapper/311:01:205
2393099182cyclictest0-21swapper/310:57:515
2393099182cyclictest0-21swapper/310:50:455
2393099182cyclictest0-21swapper/310:45:055
2393099182cyclictest0-21swapper/310:42:175
2393099182cyclictest0-21swapper/310:36:585
2393099182cyclictest0-21swapper/310:33:025
2393099182cyclictest0-21swapper/310:29:385
2393099182cyclictest0-21swapper/310:20:015
2393099182cyclictest0-21swapper/310:18:025
2393099182cyclictest0-21swapper/310:06:345
2393099182cyclictest0-21swapper/310:00:315
2393099182cyclictest0-21swapper/309:55:085
2393099182cyclictest0-21swapper/309:54:255
2393099182cyclictest0-21swapper/309:46:265
2393099182cyclictest0-21swapper/309:35:345
2393099182cyclictest0-21swapper/309:30:535
2393099182cyclictest0-21swapper/309:28:135
2393099182cyclictest0-21swapper/309:20:435
2393099182cyclictest0-21swapper/309:20:425
2393099182cyclictest0-21swapper/309:16:565
2393099182cyclictest0-21swapper/309:16:565
2393099182cyclictest0-21swapper/309:11:395
2393099182cyclictest0-21swapper/309:05:095
2393099182cyclictest0-21swapper/309:02:015
2393099182cyclictest0-21swapper/308:55:585
2393099182cyclictest0-21swapper/308:50:095
2393099182cyclictest0-21swapper/308:46:565
2393099182cyclictest0-21swapper/308:40:575
2393099182cyclictest0-21swapper/308:37:225
2393099182cyclictest0-21swapper/308:31:255
2393099182cyclictest0-21swapper/308:27:105
2393099182cyclictest0-21swapper/308:20:445
2393099182cyclictest0-21swapper/308:19:185
2393099182cyclictest0-21swapper/308:12:115
2393099182cyclictest0-21swapper/307:57:065
2393099182cyclictest0-21swapper/307:52:105
2393099182cyclictest0-21swapper/307:44:435
2393099182cyclictest0-21swapper/307:36:245
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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