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2026-02-06 - 22:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Feb 06, 2026 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501190irq/42-ahci0-21swapper/207:09:254
128501190irq/42-ahci0-21swapper/207:09:254
4590210995sleep10-21swapper/107:07:421
4590210995sleep10-21swapper/107:07:421
4519210994sleep70-21swapper/707:06:479
4519210994sleep70-21swapper/707:06:479
4516210290sleep40-21swapper/407:06:446
4516210290sleep40-21swapper/407:06:446
450529181sleep80-21swapper/807:06:3610
450529181sleep80-21swapper/807:06:3610
991850900irq/53-eth0-rx-0-21swapper/1107:07:223
991850900irq/53-eth0-rx-0-21swapper/1107:07:223
991850840irq/53-eth0-rx-0-21swapper/507:08:087
991850840irq/53-eth0-rx-0-21swapper/507:08:087
12850800irq/42-ahci0-21swapper/307:08:175
12850800irq/42-ahci0-21swapper/307:08:175
991950680irq/54-eth0-tx-0-21swapper/1007:05:282
991950680irq/54-eth0-tx-0-21swapper/1007:05:282
449726856sleep00-21swapper/007:06:280
449726856sleep00-21swapper/007:06:280
453326354sleep60-21swapper/607:06:588
453326354sleep60-21swapper/607:06:588
445626253sleep90-21swapper/907:06:0211
445626253sleep90-21swapper/907:06:0111
4961993534cyclictest0-21swapper/1108:12:053
4919993314cyclictest0-21swapper/008:10:030
4919993314cyclictest0-21swapper/008:09:460
4919993115cyclictest0-21swapper/009:11:240
496199290cyclictest0-21swapper/1110:25:583
4961992610cyclictest30400-21tail10:30:133
496199200cyclictest0-21swapper/1108:08:223
496099192cyclictest991850irq/53-eth0-rx-09:36:072
496099192cyclictest991850irq/53-eth0-rx-09:36:072
496099192cyclictest991850irq/53-eth0-rx-09:29:192
496099192cyclictest991850irq/53-eth0-rx-09:21:352
496099192cyclictest12850irq/42-ahci10:03:272
496099192cyclictest12850irq/42-ahci10:03:272
495999192cyclictest26258-21ntp_kernel_pll_11:20:1911
495999192cyclictest0-21swapper/911:35:1211
495999192cyclictest0-21swapper/910:26:3511
495999192cyclictest0-21swapper/910:16:3011
495999192cyclictest0-21swapper/910:07:3111
495999192cyclictest0-21swapper/909:15:4411
494899192cyclictest0-21swapper/508:55:167
494499192cyclictest0-21swapper/312:01:075
4944991913cyclictest5234-21snmp_rack3slot911:57:145
4960991817cyclictest0-21swapper/1011:59:112
4960991817cyclictest0-21swapper/1011:26:452
4960991817cyclictest0-21swapper/1010:28:482
4960991817cyclictest0-21swapper/1010:20:082
4960991817cyclictest0-21swapper/1009:40:362
496099181cyclictest991850irq/53-eth0-rx-12:01:182
496099181cyclictest991850irq/53-eth0-rx-11:30:182
496099181cyclictest991850irq/53-eth0-rx-10:15:082
496099181cyclictest991850irq/53-eth0-rx-10:07:022
496099181cyclictest991850irq/53-eth0-rx-09:57:282
496099181cyclictest991850irq/53-eth0-rx-09:32:352
496099181cyclictest991850irq/53-eth0-rx-09:16:372
496099181cyclictest115050irq/18-i801_smb11:45:212
496099181cyclictest115050irq/18-i801_smb09:00:232
495999181cyclictest991950irq/54-eth0-tx-11:52:4911
495999181cyclictest30299-21ssh12:20:1711
495999181cyclictest23792-1kworker/9:0H07:32:0411
495999181cyclictest0-21swapper/912:11:3011
495999181cyclictest0-21swapper/912:05:2911
495999181cyclictest0-21swapper/909:46:1911
495999181cyclictest0-21swapper/909:46:1811
495999181cyclictest0-21swapper/909:26:4211
495999181cyclictest0-21swapper/909:10:1111
495899181cyclictest0-21swapper/811:05:1710
491999180cyclictest0-21swapper/010:30:090
4960991716cyclictest0-21swapper/1011:11:032
4960991715cyclictest25402-21perl11:20:132
4960991715cyclictest17344-21ssh09:52:132
4960991715cyclictest10818-21munin-node10:40:192
496099170cyclictest991850irq/53-eth0-rx-12:35:472
496099170cyclictest991850irq/53-eth0-rx-12:28:462
496099170cyclictest991850irq/53-eth0-rx-12:20:522
496099170cyclictest991850irq/53-eth0-rx-12:07:062
496099170cyclictest991850irq/53-eth0-rx-11:37:392
496099170cyclictest991850irq/53-eth0-rx-11:06:102
496099170cyclictest991850irq/53-eth0-rx-10:36:272
496099170cyclictest991850irq/53-eth0-rx-09:10:052
496099170cyclictest991850irq/53-eth0-rx-08:40:082
496099170cyclictest991850irq/53-eth0-rx-08:25:182
496099170cyclictest991850irq/53-eth0-rx-07:29:502
496099170cyclictest991850irq/53-eth0-rx-07:22:482
496099170cyclictest991850irq/53-eth0-rx-07:22:482
496099170cyclictest97712sleep1012:30:162
496099170cyclictest81272sleep1010:10:352
496099170cyclictest68822chrt08:35:472
496099170cyclictest63482chrt07:51:072
496099170cyclictest54082sleep1007:10:022
496099170cyclictest34592sleep1011:01:052
496099170cyclictest322662chrt10:31:012
496099170cyclictest32122sleep1008:30:352
496099170cyclictest314012sleep1007:41:052
496099170cyclictest307622sleep1011:50:342
496099170cyclictest288592sleep1009:06:512
496099170cyclictest283032sleep1008:20:582
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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