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2026-02-12 - 08:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Feb 12, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15996210795sleep30-21swapper/319:08:015
15993210791sleep00-21swapper/019:07:580
15849210795sleep100-21swapper/1019:06:072
9918501040irq/53-eth0-rx-0-21swapper/119:09:331
13017210290sleep50-21swapper/519:05:027
128501020irq/42-ahci0-21swapper/719:09:599
15930210090sleep110-21swapper/1119:07:083
991850990irq/53-eth0-rx-0-21swapper/219:05:364
991850910irq/53-eth0-rx-0-21swapper/819:06:3610
1614128179sleep40-21swapper/419:09:146
1614627573sleep90-21swapper/919:09:1911
1581426055sleep60-21swapper/619:05:398
1630799340cyclictest0-21swapper/022:26:410
16331993028cyclictest991950irq/54-eth0-tx-22:26:535
16348992912cyclictest831ksoftirqd/1023:42:232
16348992912cyclictest831ksoftirqd/1023:38:022
16324992928cyclictest991950irq/54-eth0-tx-22:26:514
1634899269cyclictest831ksoftirqd/1020:59:452
16339992625cyclictest991950irq/54-eth0-tx-22:26:446
16349992524cyclictest991850irq/53-eth0-rx-22:26:413
1634899258cyclictest811rcuc/1023:06:342
16318992423cyclictest4707-21ssh22:26:541
16349992221cyclictest0-21swapper/1121:16:303
1634899214cyclictest831ksoftirqd/1021:48:182
1634899192cyclictest831ksoftirqd/1023:01:242
1634899192cyclictest831ksoftirqd/1022:35:072
1634899192cyclictest831ksoftirqd/1022:35:072
1634899192cyclictest831ksoftirqd/1022:24:422
1634899192cyclictest831ksoftirqd/1022:17:062
1634899192cyclictest831ksoftirqd/1022:11:142
1634899192cyclictest831ksoftirqd/1021:55:532
1634899192cyclictest831ksoftirqd/1021:53:502
1634899192cyclictest831ksoftirqd/1020:15:222
1634899192cyclictest831ksoftirqd/1019:35:122
1634799192cyclictest991950irq/54-eth0-tx-21:28:3311
1634799192cyclictest0-21swapper/919:40:1311
1634799192cyclictest0-21swapper/900:05:2811
16347991918cyclictest17395-21missed_timers22:10:2011
16348991817cyclictest831ksoftirqd/1021:40:192
16348991817cyclictest831ksoftirqd/1021:25:152
16348991817cyclictest831ksoftirqd/1020:00:152
16348991817cyclictest831ksoftirqd/1019:15:192
16348991817cyclictest831ksoftirqd/1000:00:432
16348991817cyclictest26272-21snmp_rack3slot922:45:162
16348991817cyclictest0-21swapper/1022:06:462
16348991817cyclictest0-21swapper/1021:36:442
16348991817cyclictest0-21swapper/1021:30:072
1634899181cyclictest991850irq/53-eth0-rx-23:10:122
1634899181cyclictest991850irq/53-eth0-rx-22:00:122
1634899181cyclictest991850irq/53-eth0-rx-21:13:032
1634899181cyclictest991850irq/53-eth0-rx-19:29:232
1634899181cyclictest831ksoftirqd/1023:51:152
1634899181cyclictest831ksoftirqd/1023:45:562
1634899181cyclictest831ksoftirqd/1023:21:202
1634899181cyclictest831ksoftirqd/1023:17:182
1634899181cyclictest831ksoftirqd/1022:50:142
1634899181cyclictest831ksoftirqd/1022:25:052
1634899181cyclictest831ksoftirqd/1021:22:072
1634899181cyclictest831ksoftirqd/1021:00:182
1634899181cyclictest831ksoftirqd/1020:20:152
1634899181cyclictest831ksoftirqd/1020:15:012
1634899181cyclictest831ksoftirqd/1020:15:012
1634899181cyclictest831ksoftirqd/1000:37:512
1634899181cyclictest831ksoftirqd/1000:27:042
1634899181cyclictest831ksoftirqd/1000:21:482
1634899181cyclictest831ksoftirqd/1000:15:492
1634899181cyclictest831ksoftirqd/1000:10:192
1634899181cyclictest831ksoftirqd/1000:05:122
1634899181cyclictest112162chrt20:29:162
1634799181cyclictest8564-21latency_hist21:10:0011
1634799181cyclictest761ksoftirqd/919:30:1211
1634799181cyclictest761ksoftirqd/900:20:0111
1634799181cyclictest26949-21ssh21:50:2611
1634799181cyclictest20022-21ssh23:06:5711
1634799181cyclictest0-21swapper/923:22:2811
1634799181cyclictest0-21swapper/923:17:1111
1634799181cyclictest0-21swapper/922:26:5611
1634799181cyclictest0-21swapper/922:24:2011
1634799181cyclictest0-21swapper/921:46:3211
1634799181cyclictest0-21swapper/920:55:3111
1634799181cyclictest0-21swapper/920:50:2111
1634799181cyclictest0-21swapper/919:35:2511
1634799181cyclictest0-21swapper/900:25:1611
16343991816cyclictest28905-21qemu-kvm20:47:327
16339991810cyclictest991850irq/53-eth0-rx-19:17:286
1634999175cyclictest0-21swapper/1122:15:013
16348991716cyclictest831ksoftirqd/1020:35:142
16348991716cyclictest831ksoftirqd/1019:10:012
16348991716cyclictest15668-21df19:50:132
16348991716cyclictest0-21swapper/1022:30:132
16348991716cyclictest0-21swapper/1021:05:252
16348991716cyclictest0-21swapper/1020:45:222
16348991716cyclictest0-21swapper/1020:40:042
16348991716cyclictest0-21swapper/1019:55:152
16348991716cyclictest0-21swapper/1019:55:152
1634899170cyclictest991850irq/53-eth0-rx-23:55:072
1634899170cyclictest991850irq/53-eth0-rx-23:30:052
1634899170cyclictest991850irq/53-eth0-rx-22:40:032
1634899170cyclictest991850irq/53-eth0-rx-22:40:032
1634899170cyclictest831ksoftirqd/1023:25:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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