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2026-07-14 - 16:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Jul 14, 2026 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501150irq/53-eth0-rx-0-21swapper/907:08:4511
30549501120irq/53-eth0-rx-0-21swapper/107:05:221
21115210792sleep60-21swapper/607:06:208
21411210095sleep40-21swapper/407:09:306
3054950950irq/53-eth0-rx-0-21swapper/507:05:107
3054950920irq/53-eth0-rx-0-21swapper/207:05:474
2141429286sleep70-21swapper/707:09:339
3054950910irq/53-eth0-rx-0-21swapper/307:05:215
3054950900irq/53-eth0-rx-0-21swapper/1107:07:283
3054950830irq/53-eth0-rx-0-21swapper/807:08:1810
2138726967sleep100-21swapper/1007:09:132
2110526957sleep00-21swapper/007:06:140
21596993617cyclictest0-21swapper/1110:25:593
21546993517cyclictest0-21swapper/007:20:410
2159699310cyclictest0-21swapper/1107:17:553
2154699290cyclictest299382sleep007:17:510
2158399220cyclictest0-21swapper/510:53:317
2156899225cyclictest0-21swapper/311:05:185
2156899214cyclictest0-21swapper/310:54:435
2156899204cyclictest0-21swapper/307:16:595
2156899203cyclictest0-21swapper/311:48:375
2159599192cyclictest3054950irq/53-eth0-rx-09:45:002
2159599192cyclictest3054950irq/53-eth0-rx-07:25:152
2158499195cyclictest0-21swapper/608:02:468
2156899193cyclictest0-21swapper/312:36:245
2156899193cyclictest0-21swapper/312:26:145
2156899193cyclictest0-21swapper/312:22:515
2156899193cyclictest0-21swapper/312:16:255
2156899193cyclictest0-21swapper/312:14:015
2156899193cyclictest0-21swapper/312:05:325
2156899193cyclictest0-21swapper/312:02:025
2156899193cyclictest0-21swapper/311:55:145
2156899193cyclictest0-21swapper/311:53:345
2156899193cyclictest0-21swapper/311:40:335
2156899193cyclictest0-21swapper/311:27:165
2156899193cyclictest0-21swapper/311:15:325
2156899193cyclictest0-21swapper/311:15:325
2156899193cyclictest0-21swapper/311:13:565
2156899193cyclictest0-21swapper/311:13:565
2156899193cyclictest0-21swapper/311:00:585
2156899193cyclictest0-21swapper/310:47:365
2156899193cyclictest0-21swapper/310:40:245
2156899193cyclictest0-21swapper/310:30:235
2156899193cyclictest0-21swapper/310:25:415
2156899193cyclictest0-21swapper/310:15:385
2156899193cyclictest0-21swapper/310:12:005
2156899193cyclictest0-21swapper/310:09:005
2156899193cyclictest0-21swapper/310:01:175
2156899193cyclictest0-21swapper/309:57:185
2156899193cyclictest0-21swapper/309:50:105
2156899193cyclictest0-21swapper/309:46:025
2156899193cyclictest0-21swapper/309:37:235
2156899193cyclictest0-21swapper/309:31:075
2156899193cyclictest0-21swapper/309:25:425
2156899193cyclictest0-21swapper/309:22:225
2156899193cyclictest0-21swapper/309:10:015
2156899193cyclictest0-21swapper/309:09:395
2156899193cyclictest0-21swapper/308:57:025
2156899193cyclictest0-21swapper/308:50:305
2156899193cyclictest0-21swapper/308:35:105
2156899193cyclictest0-21swapper/307:39:445
2156899193cyclictest0-21swapper/307:23:485
2156899192cyclictest0-21swapper/311:35:585
2156899192cyclictest0-21swapper/309:42:385
2154699192cyclictest0-21swapper/009:11:540
21595991817cyclictest0-21swapper/1012:09:272
21595991817cyclictest0-21swapper/1010:03:582
2159599181cyclictest3055050irq/54-eth0-tx-12:00:552
2159599181cyclictest3055050irq/54-eth0-tx-10:09:572
2159599181cyclictest3055050irq/54-eth0-tx-09:32:332
2159599181cyclictest3054950irq/53-eth0-rx-11:06:452
2159599181cyclictest3054950irq/53-eth0-rx-10:37:202
2159599181cyclictest3054950irq/53-eth0-rx-10:15:272
2159599181cyclictest3054950irq/53-eth0-rx-10:10:502
2159599181cyclictest3054950irq/53-eth0-rx-09:55:432
2159599181cyclictest3054950irq/53-eth0-rx-09:51:072
2159599181cyclictest3054950irq/53-eth0-rx-09:26:012
2159599181cyclictest3054950irq/53-eth0-rx-08:46:142
2159599181cyclictest3054950irq/53-eth0-rx-07:16:152
2159599181cyclictest12250irq/42-ahci09:08:592
2159599181cyclictest12250irq/42-ahci09:04:472
2159599181cyclictest12250irq/42-ahci09:04:472
2158499180cyclictest0-21swapper/607:45:008
21583991816cyclictest8539-21snmp_rack3slot912:06:477
2156899183cyclictest13490-21diskmemload10:22:415
2156899183cyclictest0-21swapper/311:31:025
2156899182cyclictest0-21swapper/312:32:365
2156899182cyclictest0-21swapper/311:20:405
2156899182cyclictest0-21swapper/311:20:395
2156899182cyclictest0-21swapper/310:57:315
2156899182cyclictest0-21swapper/310:38:025
2156899182cyclictest0-21swapper/309:16:165
2156899182cyclictest0-21swapper/308:49:525
2156899182cyclictest0-21swapper/308:22:365
2156899182cyclictest0-21swapper/308:11:075
2156899182cyclictest0-21swapper/308:09:045
2156899182cyclictest0-21swapper/308:01:185
2156899182cyclictest0-21swapper/307:45:375
2156899182cyclictest0-21swapper/307:31:485
2156899182cyclictest0-21swapper/307:28:505
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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