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2026-01-21 - 18:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Jan 21, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501170irq/42-ahci0-21swapper/107:09:091
991850980irq/53-eth0-rx-0-21swapper/207:05:244
12850970irq/42-ahci0-21swapper/907:09:5511
991850960irq/53-eth0-rx-0-21swapper/807:06:4510
991850920irq/53-eth0-rx-0-21swapper/407:05:046
991850910irq/53-eth0-rx-0-21swapper/307:05:245
991850900irq/53-eth0-rx-0-21swapper/707:07:479
991850770irq/53-eth0-rx-0-21swapper/1107:05:173
991850690irq/53-eth0-rx-0-21swapper/1007:07:462
658126957sleep00-21swapper/007:05:410
663326653sleep50-21swapper/507:06:237
668425955sleep60-21swapper/607:06:598
7120993215cyclictest831ksoftirqd/1009:14:132
7103993231cyclictest991850irq/53-eth0-rx-09:28:485
991950300irq/54-eth0-tx-0-21swapper/009:28:420
7119993029cyclictest991950irq/54-eth0-tx-09:28:4811
7084993029cyclictest991950irq/54-eth0-tx-09:28:581
7070992928cyclictest0-21swapper/009:22:430
7070992927cyclictest0-21swapper/010:17:120
7070992927cyclictest0-21swapper/010:10:430
7121992827cyclictest31613-21turbostat10:09:563
7121992814cyclictest0-21swapper/1108:14:293
712199270cyclictest0-21swapper/1109:11:523
7120992710cyclictest831ksoftirqd/1012:30:092
7120992710cyclictest831ksoftirqd/1008:35:582
712199260cyclictest0-21swapper/1108:10:003
712099269cyclictest831ksoftirqd/1011:15:432
7070992610cyclictest0-21swapper/010:21:380
712099247cyclictest831ksoftirqd/1009:55:232
7121992322cyclictest991850irq/53-eth0-rx-10:10:273
7121992322cyclictest21905-21ssh09:28:463
7108992221cyclictest991850irq/53-eth0-rx-09:28:477
7070992218cyclictest0-21swapper/011:28:350
707099220cyclictest0-21swapper/008:09:480
712099215cyclictest831ksoftirqd/1011:38:592
712099214cyclictest831ksoftirqd/1012:24:142
7120992019cyclictest0-21swapper/1008:13:082
7110992019cyclictest991850irq/53-eth0-rx-09:28:409
7108992013cyclictest19659-21qemu-kvm08:08:447
707099200cyclictest0-21swapper/012:25:220
707099200cyclictest0-21swapper/012:25:210
707099200cyclictest0-21swapper/011:44:250
707099200cyclictest0-21swapper/011:19:200
712099192cyclictest991850irq/53-eth0-rx-10:40:092
712099192cyclictest991850irq/53-eth0-rx-10:32:332
712099192cyclictest991850irq/53-eth0-rx-10:29:542
712099192cyclictest991850irq/53-eth0-rx-09:30:562
712099192cyclictest991850irq/53-eth0-rx-09:30:552
712099192cyclictest991850irq/53-eth0-rx-09:25:342
712099192cyclictest831ksoftirqd/1009:50:122
711999192cyclictest0-21swapper/910:41:1011
7070991915cyclictest0-21swapper/011:45:230
7070991915cyclictest0-21swapper/010:34:110
707099190cyclictest0-21swapper/011:04:180
707099190cyclictest0-21swapper/009:39:030
707099190cyclictest0-21swapper/008:55:210
707099190cyclictest0-21swapper/008:30:220
707099190cyclictest0-21swapper/007:28:350
7120991817cyclictest831ksoftirqd/1012:35:152
7120991817cyclictest831ksoftirqd/1012:35:142
7120991817cyclictest831ksoftirqd/1012:02:302
7120991817cyclictest831ksoftirqd/1008:15:202
7120991817cyclictest0-21swapper/1012:26:192
7120991817cyclictest0-21swapper/1012:26:182
7120991817cyclictest0-21swapper/1011:48:412
7120991817cyclictest0-21swapper/1010:55:152
7120991817cyclictest0-21swapper/1010:50:062
7120991817cyclictest0-21swapper/1010:21:402
7120991817cyclictest0-21swapper/1009:45:082
7120991817cyclictest0-21swapper/1009:15:592
7120991817cyclictest0-21swapper/1007:30:262
712099181cyclictest991950irq/54-eth0-tx-11:50:252
712099181cyclictest991850irq/53-eth0-rx-11:20:122
712099181cyclictest991850irq/53-eth0-rx-11:04:452
712099181cyclictest991850irq/53-eth0-rx-09:37:142
712099181cyclictest831ksoftirqd/1012:10:222
712099181cyclictest831ksoftirqd/1011:56:082
712099181cyclictest831ksoftirqd/1011:41:272
712099181cyclictest831ksoftirqd/1011:06:232
712099181cyclictest831ksoftirqd/1010:06:092
712099181cyclictest831ksoftirqd/1009:40:402
712099181cyclictest831ksoftirqd/1009:20:062
712099181cyclictest831ksoftirqd/1009:05:252
712099181cyclictest831ksoftirqd/1009:00:132
712099181cyclictest831ksoftirqd/1007:55:222
712099181cyclictest831ksoftirqd/1007:25:132
712099181cyclictest12850irq/42-ahci10:46:502
712099181cyclictest12850irq/42-ahci10:16:032
712099181cyclictest12850irq/42-ahci08:30:582
711999181cyclictest32745-21ssh09:10:1111
711999181cyclictest30303-21ssh12:16:0811
711999181cyclictest30303-21ssh12:16:0711
711999181cyclictest18905-21ssh11:13:1511
711999181cyclictest0-21swapper/912:20:2111
711999181cyclictest0-21swapper/911:15:0411
711999181cyclictest0-21swapper/911:03:4811
711999181cyclictest0-21swapper/910:46:0811
711999181cyclictest0-21swapper/910:35:0211
711999181cyclictest0-21swapper/910:07:0211
711999181cyclictest0-21swapper/909:56:5911
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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