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2026-03-04 - 11:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Mar 04, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501110irq/53-eth0-rx-0-21swapper/819:08:5110
128501080irq/42-ahci0-21swapper/119:09:021
9918501030irq/53-eth0-rx-0-21swapper/319:05:155
31423210390sleep100-21swapper/1019:05:452
9918501020irq/53-eth0-rx-0-21swapper/219:06:304
31445210187sleep40-21swapper/419:06:036
991850990irq/53-eth0-rx-0-21swapper/719:09:179
991850920irq/53-eth0-rx-0-21swapper/919:06:1211
991850900irq/53-eth0-rx-0-21swapper/519:07:277
3144028272sleep00-21swapper/019:05:580
991850640irq/53-eth0-rx-0-21swapper/1119:05:213
3148125853sleep60-21swapper/619:06:288
31951994025cyclictest19278-21taskset20:15:523
31951994025cyclictest19278-21taskset20:15:513
31925993029cyclictest991850irq/53-eth0-rx-19:23:246
31951992726cyclictest15934-21kworker/11:222:29:293
31940992322cyclictest991950irq/54-eth0-tx-19:23:249
31911992120cyclictest12850irq/42-ahci19:23:194
3194899192cyclictest991850irq/53-eth0-rx-22:41:552
3194899192cyclictest991850irq/53-eth0-rx-20:45:142
3194899192cyclictest991850irq/53-eth0-rx-00:28:172
3194899192cyclictest991850irq/53-eth0-rx-00:15:152
31951991816cyclictest991850irq/53-eth0-rx-22:22:403
31951991816cyclictest26659-21chrt20:27:053
31951991816cyclictest229892sleep1120:21:413
31948991817cyclictest0-21swapper/1021:36:452
3194899181cyclictest991850irq/53-eth0-rx-23:53:462
3194899181cyclictest991850irq/53-eth0-rx-23:46:422
3194899181cyclictest991850irq/53-eth0-rx-23:28:312
3194899181cyclictest991850irq/53-eth0-rx-23:16:252
3194899181cyclictest991850irq/53-eth0-rx-23:02:392
3194899181cyclictest991850irq/53-eth0-rx-22:57:572
3194899181cyclictest991850irq/53-eth0-rx-22:32:032
3194899181cyclictest991850irq/53-eth0-rx-22:27:322
3194899181cyclictest991850irq/53-eth0-rx-22:20:492
3194899181cyclictest991850irq/53-eth0-rx-22:19:032
3194899181cyclictest991850irq/53-eth0-rx-22:13:142
3194899181cyclictest991850irq/53-eth0-rx-21:59:042
3194899181cyclictest991850irq/53-eth0-rx-21:53:302
3194899181cyclictest991850irq/53-eth0-rx-21:45:222
3194899181cyclictest991850irq/53-eth0-rx-21:17:052
3194899181cyclictest991850irq/53-eth0-rx-00:20:152
3194899181cyclictest991850irq/53-eth0-rx-00:02:112
3194899181cyclictest831ksoftirqd/1021:20:192
3194299181cyclictest0-21swapper/922:33:0811
3194299181cyclictest0-21swapper/921:46:0411
3194299181cyclictest0-21swapper/921:14:4111
3194299181cyclictest0-21swapper/919:31:3211
3194299181cyclictest0-21swapper/900:17:1611
3193999180cyclictest12149-21qemu-kvm20:20:108
3191999181cyclictest0-21swapper/300:17:055
15050180irq/18-uhci_hcd0-21swapper/020:40:210
3194899170cyclictest991950irq/54-eth0-tx-21:25:012
3194899170cyclictest991950irq/54-eth0-tx-19:50:312
3194899170cyclictest991850irq/53-eth0-rx-23:40:102
3194899170cyclictest991850irq/53-eth0-rx-23:36:362
3194899170cyclictest991850irq/53-eth0-rx-23:30:072
3194899170cyclictest991850irq/53-eth0-rx-23:20:152
3194899170cyclictest991850irq/53-eth0-rx-23:10:112
3194899170cyclictest991850irq/53-eth0-rx-23:10:102
3194899170cyclictest991850irq/53-eth0-rx-22:50:262
3194899170cyclictest991850irq/53-eth0-rx-22:45:412
3194899170cyclictest991850irq/53-eth0-rx-22:35:542
3194899170cyclictest991850irq/53-eth0-rx-22:02:152
3194899170cyclictest991850irq/53-eth0-rx-21:40:542
3194899170cyclictest991850irq/53-eth0-rx-21:30:052
3194899170cyclictest991850irq/53-eth0-rx-21:10:072
3194899170cyclictest991850irq/53-eth0-rx-21:00:582
3194899170cyclictest991850irq/53-eth0-rx-20:35:192
3194899170cyclictest991850irq/53-eth0-rx-20:20:092
3194899170cyclictest991850irq/53-eth0-rx-20:07:082
3194899170cyclictest991850irq/53-eth0-rx-20:07:072
3194899170cyclictest991850irq/53-eth0-rx-19:59:282
3194899170cyclictest991850irq/53-eth0-rx-19:20:112
3194899170cyclictest991850irq/53-eth0-rx-19:10:362
3194899170cyclictest991850irq/53-eth0-rx-00:35:322
3194899170cyclictest991850irq/53-eth0-rx-00:05:042
3194899170cyclictest96372sleep1020:50:072
3194899170cyclictest83492sleep1020:01:372
3194899170cyclictest54072sleep1023:05:122
3194899170cyclictest54072sleep1023:05:112
3194899170cyclictest48772chrt23:56:302
3194899170cyclictest40362sleep1020:40:172
3194899170cyclictest37832sleep1019:15:082
3194899170cyclictest303752sleep1020:33:072
3194899170cyclictest303752sleep1020:33:062
3194899170cyclictest288132sleep1022:05:162
3194899170cyclictest269562sleep1019:45:122
3194899170cyclictest262432chrt19:43:592
3194899170cyclictest253532sleep1020:25:172
3194899170cyclictest235702sleep1021:07:562
3194899170cyclictest216892chrt00:10:192
3194899170cyclictest195432sleep1020:19:302
3194899170cyclictest195432sleep1020:19:292
3194899170cyclictest160922sleep1020:55:562
3194899170cyclictest159172sleep1019:30:112
3194899170cyclictest156182chrt20:10:382
3194899170cyclictest151052sleep1019:26:102
3194899170cyclictest12850irq/42-ahci19:36:042
3194899170cyclictest120792sleep1000:30:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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