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2026-01-24 - 03:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Jan 24, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501170irq/53-eth0-rx-0-21swapper/119:09:521
9918501030irq/53-eth0-rx-0-21swapper/719:05:309
128501030irq/42-ahci0-21swapper/319:08:325
9918501020irq/53-eth0-rx-0-21swapper/219:05:114
128501010irq/42-ahci0-21swapper/419:05:226
991850950irq/53-eth0-rx-0-21swapper/519:06:167
991850930irq/53-eth0-rx-0-21swapper/1019:05:592
991850910irq/53-eth0-rx-0-21swapper/919:07:2711
991850900irq/53-eth0-rx-0-21swapper/819:05:0210
102528778sleep110-21swapper/1119:05:213
182926864sleep00-21swapper/019:05:330
193726553sleep60-21swapper/619:06:528
2359993228cyclictest0-21swapper/022:25:300
2359993228cyclictest0-21swapper/022:25:300
235999320cyclictest0-21swapper/021:19:140
238199290cyclictest0-21swapper/219:40:244
2359992827cyclictest0-21swapper/019:23:400
235999234cyclictest0-21swapper/020:21:300
240599192cyclictest991850irq/53-eth0-rx-23:58:542
240599192cyclictest991850irq/53-eth0-rx-23:23:012
240599192cyclictest991850irq/53-eth0-rx-00:01:332
240499192cyclictest0-21swapper/923:35:1011
240499192cyclictest0-21swapper/922:19:0311
240499192cyclictest0-21swapper/922:19:0311
240499192cyclictest0-21swapper/921:37:0511
240499192cyclictest0-21swapper/921:24:5611
240499192cyclictest0-21swapper/919:40:1411
240499192cyclictest0-21swapper/900:33:3311
2405991817cyclictest30218-21ssh21:10:572
2405991817cyclictest26340-1kworker/10:1H21:31:352
2405991817cyclictest25387-21kworker/10:121:47:342
2405991817cyclictest0-21swapper/1023:48:252
2405991817cyclictest0-21swapper/1023:05:482
2405991817cyclictest0-21swapper/1021:36:362
2405991817cyclictest0-21swapper/1020:08:242
240599181cyclictest991950irq/54-eth0-tx-22:33:342
240599181cyclictest991950irq/54-eth0-tx-22:33:342
240599181cyclictest991950irq/54-eth0-tx-22:22:432
240599181cyclictest991950irq/54-eth0-tx-22:22:422
240599181cyclictest991950irq/54-eth0-tx-21:54:052
240599181cyclictest991950irq/54-eth0-tx-00:28:172
240599181cyclictest991850irq/53-eth0-rx-23:51:592
240599181cyclictest991850irq/53-eth0-rx-23:41:382
240599181cyclictest991850irq/53-eth0-rx-23:28:592
240599181cyclictest991850irq/53-eth0-rx-22:51:582
240599181cyclictest991850irq/53-eth0-rx-22:35:252
240599181cyclictest991850irq/53-eth0-rx-22:00:032
240599181cyclictest991850irq/53-eth0-rx-21:56:052
240599181cyclictest991850irq/53-eth0-rx-21:24:332
240599181cyclictest991850irq/53-eth0-rx-21:16:302
240599181cyclictest991850irq/53-eth0-rx-20:00:142
240599181cyclictest991850irq/53-eth0-rx-00:35:182
240599181cyclictest991850irq/53-eth0-rx-00:11:012
240499181cyclictest761ksoftirqd/923:55:1711
240499181cyclictest761ksoftirqd/919:50:1411
240499181cyclictest0-21swapper/923:53:2411
240499181cyclictest0-21swapper/923:46:3111
240499181cyclictest0-21swapper/923:40:1611
240499181cyclictest0-21swapper/923:34:0711
240499181cyclictest0-21swapper/923:26:0711
240499181cyclictest0-21swapper/923:15:0311
240499181cyclictest0-21swapper/922:48:0711
240499181cyclictest0-21swapper/922:29:1711
240499181cyclictest0-21swapper/922:29:1611
240499181cyclictest0-21swapper/921:53:3011
240499181cyclictest0-21swapper/919:16:1711
2359991815cyclictest0-21swapper/022:06:310
2359991815cyclictest0-21swapper/022:06:310
2405991716cyclictest25387-21kworker/10:120:55:022
2405991716cyclictest0-21swapper/1023:35:232
2405991716cyclictest0-21swapper/1020:47:472
2405991716cyclictest0-21swapper/1019:17:502
240599170cyclictest991850irq/53-eth0-rx-23:15:172
240599170cyclictest991850irq/53-eth0-rx-23:10:392
240599170cyclictest991850irq/53-eth0-rx-23:00:152
240599170cyclictest991850irq/53-eth0-rx-22:55:152
240599170cyclictest991850irq/53-eth0-rx-22:25:072
240599170cyclictest991850irq/53-eth0-rx-22:25:062
240599170cyclictest991850irq/53-eth0-rx-22:15:372
240599170cyclictest991850irq/53-eth0-rx-22:15:362
240599170cyclictest991850irq/53-eth0-rx-22:10:172
240599170cyclictest991850irq/53-eth0-rx-22:10:172
240599170cyclictest991850irq/53-eth0-rx-22:05:312
240599170cyclictest991850irq/53-eth0-rx-22:05:302
240599170cyclictest991850irq/53-eth0-rx-21:40:362
240599170cyclictest991850irq/53-eth0-rx-20:50:202
240599170cyclictest991850irq/53-eth0-rx-19:47:152
240599170cyclictest991850irq/53-eth0-rx-19:25:202
240599170cyclictest991850irq/53-eth0-rx-19:11:222
240599170cyclictest991850irq/53-eth0-rx-00:30:322
240599170cyclictest991850irq/53-eth0-rx-00:20:102
240599170cyclictest991850irq/53-eth0-rx-00:06:152
240599170cyclictest92212sleep1022:40:562
240599170cyclictest78532sleep1020:40:542
240599170cyclictest74872sleep1019:57:132
240599170cyclictest294102sleep1020:27:292
240599170cyclictest260372sleep1021:05:322
240599170cyclictest25762sleep1023:30:142
240599170cyclictest251952chrt19:35:582
240599170cyclictest226852sleep1021:04:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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