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2026-07-16 - 09:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Jul 16, 2026 00:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501110irq/53-eth0-rx-0-21swapper/219:08:444
5819210693sleep10-21swapper/119:06:041
30549501050irq/53-eth0-rx-0-21swapper/019:08:490
5946210390sleep50-21swapper/519:07:447
3054950990irq/53-eth0-rx-0-21swapper/319:05:145
3054950960irq/53-eth0-rx-0-21swapper/1019:07:002
3054950920irq/53-eth0-rx-0-21swapper/919:05:4111
582529179sleep70-21swapper/719:06:109
3054950870irq/53-eth0-rx-0-21swapper/1119:07:443
612227977sleep40-21swapper/419:09:196
3054950660irq/53-eth0-rx-0-21swapper/819:07:3710
579426453sleep60-21swapper/619:05:448
6317993116cyclictest139642sleep1122:14:003
631199230cyclictest0-21swapper/519:55:017
6317992221cyclictest3054950irq/53-eth0-rx-22:24:393
631699192cyclictest3054950irq/53-eth0-rx-23:44:272
631699192cyclictest3054950irq/53-eth0-rx-00:20:472
631699192cyclictest3054950irq/53-eth0-rx-00:20:472
631699192cyclictest3054950irq/53-eth0-rx-00:03:142
631499193cyclictest0-21swapper/820:21:1810
631799180cyclictest0-21swapper/1122:08:163
6316991817cyclictest0-21swapper/1023:02:022
6316991817cyclictest0-21swapper/1022:56:112
6316991817cyclictest0-21swapper/1022:46:532
6316991817cyclictest0-21swapper/1021:48:282
6316991817cyclictest0-21swapper/1000:28:562
6316991817cyclictest0-21swapper/1000:14:132
6316991817cyclictest0-21swapper/1000:14:132
631699181cyclictest3055050irq/54-eth0-tx-22:02:302
631699181cyclictest3054950irq/53-eth0-rx-23:50:272
631699181cyclictest3054950irq/53-eth0-rx-23:36:342
631699181cyclictest3054950irq/53-eth0-rx-23:29:252
631699181cyclictest3054950irq/53-eth0-rx-23:24:252
631699181cyclictest3054950irq/53-eth0-rx-23:12:592
631699181cyclictest3054950irq/53-eth0-rx-23:06:182
631699181cyclictest3054950irq/53-eth0-rx-22:51:452
631699181cyclictest3054950irq/53-eth0-rx-22:32:512
631699181cyclictest3054950irq/53-eth0-rx-22:25:482
631699181cyclictest3054950irq/53-eth0-rx-22:17:322
631699181cyclictest3054950irq/53-eth0-rx-21:58:442
631699181cyclictest3054950irq/53-eth0-rx-21:34:282
631699181cyclictest3054950irq/53-eth0-rx-21:28:342
631699181cyclictest3054950irq/53-eth0-rx-21:17:012
631699181cyclictest3054950irq/53-eth0-rx-21:11:492
631699181cyclictest3054950irq/53-eth0-rx-19:12:362
631699181cyclictest3054950irq/53-eth0-rx-00:34:382
631699181cyclictest3054950irq/53-eth0-rx-00:17:292
631699181cyclictest12250irq/42-ahci21:44:342
631699180cyclictest17202sleep1020:30:082
631599181cyclictest26582-1kworker/9:1H22:41:1111
631599181cyclictest0-21swapper/922:10:1111
631599181cyclictest0-21swapper/921:24:0511
6312991816cyclictest7265-21qemu-kvm22:38:358
6312991816cyclictest7265-21qemu-kvm22:29:148
6312991816cyclictest7265-21qemu-kvm22:24:128
6312991816cyclictest7265-21qemu-kvm22:15:128
6312991816cyclictest7265-21qemu-kvm22:10:138
6312991816cyclictest7265-21qemu-kvm22:08:248
6312991816cyclictest18895-21qemu-kvm20:08:478
6312991816cyclictest18895-21qemu-kvm20:08:478
6311991816cyclictest6029-21qemu-kvm19:31:547
6306991816cyclictest0-21swapper/022:40:420
6316991716cyclictest13546-21smartctl20:00:152
6316991716cyclictest0-21swapper/1023:15:152
6316991716cyclictest0-21swapper/1019:35:372
631699170cyclictest831ksoftirqd/1020:15:142
631699170cyclictest76362sleep1020:35:222
631699170cyclictest315062sleep1019:40:162
631699170cyclictest306622sleep1000:35:502
631699170cyclictest3055050irq/54-eth0-tx-22:20:102
631699170cyclictest3054950irq/53-eth0-rx-23:55:032
631699170cyclictest3054950irq/53-eth0-rx-23:45:522
631699170cyclictest3054950irq/53-eth0-rx-23:30:462
631699170cyclictest3054950irq/53-eth0-rx-22:40:182
631699170cyclictest3054950irq/53-eth0-rx-22:35:132
631699170cyclictest3054950irq/53-eth0-rx-22:05:122
631699170cyclictest3054950irq/53-eth0-rx-21:50:232
631699170cyclictest3054950irq/53-eth0-rx-21:36:132
631699170cyclictest3054950irq/53-eth0-rx-21:21:432
631699170cyclictest3054950irq/53-eth0-rx-21:04:552
631699170cyclictest3054950irq/53-eth0-rx-20:52:252
631699170cyclictest3054950irq/53-eth0-rx-20:24:032
631699170cyclictest3054950irq/53-eth0-rx-20:14:192
631699170cyclictest3054950irq/53-eth0-rx-19:55:212
631699170cyclictest3054950irq/53-eth0-rx-19:50:232
631699170cyclictest3054950irq/53-eth0-rx-19:45:452
631699170cyclictest3054950irq/53-eth0-rx-19:32:022
631699170cyclictest3054950irq/53-eth0-rx-19:27:032
631699170cyclictest3054950irq/53-eth0-rx-19:15:142
631699170cyclictest3054950irq/53-eth0-rx-00:05:172
631699170cyclictest228652sleep1020:56:002
631699170cyclictest228652sleep1020:55:592
631699170cyclictest187042sleep1020:06:182
631699170cyclictest187042sleep1020:06:182
631699170cyclictest181642sleep1019:20:502
631699170cyclictest156042sleep1020:46:242
631699170cyclictest12250irq/42-ahci22:10:422
631699170cyclictest113132sleep1020:40:222
631599172cyclictest0-21swapper/923:05:2111
631599172cyclictest0-21swapper/922:03:4911
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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