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2026-08-21 - 07:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Aug 21, 2026 00:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1669211095sleep100-21swapper/1019:08:142
30549501090irq/53-eth0-rx-0-21swapper/119:09:281
1596210793sleep70-21swapper/719:08:009
30549501020irq/53-eth0-rx-0-21swapper/219:09:574
3054950950irq/53-eth0-rx-0-21swapper/819:07:0610
170829584sleep40-21swapper/419:08:456
3054950930irq/53-eth0-rx-0-21swapper/319:07:375
177528278sleep90-21swapper/919:09:3811
3054950780irq/53-eth0-rx-0-21swapper/519:05:207
156526353sleep60-21swapper/619:07:358
141226354sleep110-21swapper/1119:05:403
3106325753sleep00-21swapper/019:05:050
1925993718cyclictest0-21swapper/022:08:450
192599320cyclictest0-21swapper/019:21:270
1925992524cyclictest5573-21chrt21:18:430
195499195cyclictest0-21swapper/1023:55:192
195499195cyclictest0-21swapper/1022:35:012
195499192cyclictest3054950irq/53-eth0-rx-23:48:422
195499192cyclictest3054950irq/53-eth0-rx-23:41:452
195499192cyclictest3054950irq/53-eth0-rx-22:55:452
195499192cyclictest3054950irq/53-eth0-rx-22:48:472
195499192cyclictest3054950irq/53-eth0-rx-22:30:282
195499192cyclictest3054950irq/53-eth0-rx-21:24:112
195499192cyclictest3054950irq/53-eth0-rx-21:24:112
195499192cyclictest3054950irq/53-eth0-rx-00:18:182
195499192cyclictest3054950irq/53-eth0-rx-00:18:182
195499190cyclictest16615-21snmp_rack3slot920:10:132
195399192cyclictest0-21swapper/923:15:1611
195399192cyclictest0-21swapper/921:46:2911
195399192cyclictest0-21swapper/900:36:5911
1952991910cyclictest12250irq/42-ahci21:40:0210
195099195cyclictest0-21swapper/623:05:508
6199180migration/731503-21latency_hist21:40:029
1954991817cyclictest811rcuc/1021:25:302
1954991817cyclictest26455-1kworker/10:1H19:10:252
1954991817cyclictest0-21swapper/1021:45:422
1954991817cyclictest0-21swapper/1021:12:142
1954991817cyclictest0-21swapper/1020:24:202
1954991817cyclictest0-21swapper/1000:05:072
195499181cyclictest3055050irq/54-eth0-tx-23:51:172
195499181cyclictest3055050irq/54-eth0-tx-23:35:142
195499181cyclictest3054950irq/53-eth0-rx-23:31:162
195499181cyclictest3054950irq/53-eth0-rx-23:28:142
195499181cyclictest3054950irq/53-eth0-rx-23:15:102
195499181cyclictest3054950irq/53-eth0-rx-23:06:472
195499181cyclictest3054950irq/53-eth0-rx-23:04:122
195499181cyclictest3054950irq/53-eth0-rx-22:50:352
195499181cyclictest3054950irq/53-eth0-rx-22:42:322
195499181cyclictest3054950irq/53-eth0-rx-22:26:112
195499181cyclictest3054950irq/53-eth0-rx-22:13:092
195499181cyclictest3054950irq/53-eth0-rx-22:01:092
195499181cyclictest3054950irq/53-eth0-rx-21:56:142
195499181cyclictest3054950irq/53-eth0-rx-21:36:592
195499181cyclictest3054950irq/53-eth0-rx-21:33:362
195499181cyclictest3054950irq/53-eth0-rx-21:15:292
195499181cyclictest3054950irq/53-eth0-rx-21:05:132
195499181cyclictest3054950irq/53-eth0-rx-20:40:452
195499181cyclictest3054950irq/53-eth0-rx-20:18:412
195499181cyclictest3054950irq/53-eth0-rx-19:38:522
195499181cyclictest3054950irq/53-eth0-rx-19:24:032
195499181cyclictest3054950irq/53-eth0-rx-00:37:512
195499181cyclictest3054950irq/53-eth0-rx-00:25:022
195499181cyclictest3054950irq/53-eth0-rx-00:25:022
195499181cyclictest3054950irq/53-eth0-rx-00:20:222
195499181cyclictest3054950irq/53-eth0-rx-00:01:422
195499181cyclictest12250irq/42-ahci20:08:582
1953991816cyclictest28440-21ssh00:13:2611
1953991816cyclictest26067-21ssh22:52:5811
195399181cyclictest0-21swapper/923:23:3511
195399181cyclictest0-21swapper/922:57:4911
195399181cyclictest0-21swapper/922:44:1411
195399181cyclictest0-21swapper/922:37:1411
195399181cyclictest0-21swapper/921:37:2911
195399181cyclictest0-21swapper/921:12:1511
195399181cyclictest0-21swapper/900:28:4411
195399181cyclictest0-21swapper/900:28:4411
195399181cyclictest0-21swapper/900:00:2711
195099184cyclictest0-21swapper/619:53:048
195099180cyclictest0-21swapper/621:59:568
1939991816cyclictest17831-21snmp_rack3slot922:20:154
1954991716cyclictest0-21swapper/1022:20:042
1954991716cyclictest0-21swapper/1019:50:112
195499170cyclictest70532sleep1019:55:442
195499170cyclictest3055050irq/54-eth0-tx-19:45:132
195499170cyclictest3054950irq/53-eth0-rx-23:10:092
195499170cyclictest3054950irq/53-eth0-rx-22:15:062
195499170cyclictest3054950irq/53-eth0-rx-22:05:062
195499170cyclictest3054950irq/53-eth0-rx-21:50:232
195499170cyclictest3054950irq/53-eth0-rx-21:00:022
195499170cyclictest3054950irq/53-eth0-rx-20:55:272
195499170cyclictest3054950irq/53-eth0-rx-20:50:042
195499170cyclictest3054950irq/53-eth0-rx-20:45:162
195499170cyclictest3054950irq/53-eth0-rx-20:35:352
195499170cyclictest3054950irq/53-eth0-rx-20:30:162
195499170cyclictest3054950irq/53-eth0-rx-20:25:332
195499170cyclictest3054950irq/53-eth0-rx-19:16:242
195499170cyclictest3054950irq/53-eth0-rx-00:30:552
195499170cyclictest3054950irq/53-eth0-rx-00:30:552
195499170cyclictest3054950irq/53-eth0-rx-00:10:172
195499170cyclictest265052sleep1023:20:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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