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2025-12-08 - 01:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Dec 08, 2025 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25085211197sleep40-21swapper/419:05:386
30663501030irq/52-eth0-rx-0-21swapper/819:07:5610
3066350970irq/52-eth0-rx-0-21swapper/219:05:344
12250960irq/42-ahci0-21swapper/119:09:021
3066350920irq/52-eth0-rx-0-21swapper/319:05:035
2539929085sleep70-21swapper/719:09:059
2522828981sleep90-21swapper/919:07:3211
2546026664sleep100-21swapper/1019:09:572
2512526653sleep00-21swapper/019:06:090
2518926354sleep110-21swapper/1119:06:583
2511726055sleep50-21swapper/519:06:037
2510125955sleep60-21swapper/619:05:528
25610992914cyclictest0-21swapper/1120:10:243
12250290irq/42-ahci0-21swapper/221:17:594
25573992725cyclictest243122sleep021:16:010
25573992514cyclictest0-21swapper/020:10:330
2561099240cyclictest0-21swapper/1121:18:463
2557399230cyclictest0-21swapper/023:15:330
2557399210cyclictest0-21swapper/023:20:260
25610992018cyclictest0-21swapper/1119:25:223
2557399200cyclictest0-21swapper/022:45:290
2557399200cyclictest0-21swapper/021:55:320
2557399200cyclictest0-21swapper/021:55:320
2557399200cyclictest0-21swapper/019:10:320
2561099195cyclictest0-21swapper/1120:25:293
2561099190cyclictest0-21swapper/1121:08:293
2557399190cyclictest0-21swapper/020:50:330
25609991817cyclictest47192sleep1020:05:272
2560999181cyclictest12250irq/42-ahci19:58:282
2560999181cyclictest12250irq/42-ahci19:16:022
2560899181cyclictest0-21swapper/921:40:1111
2560899181cyclictest0-21swapper/921:05:1911
2560899181cyclictest0-21swapper/919:10:3711
25607991816cyclictest9659-21memory22:25:2310
25607991816cyclictest9517-21diskstats23:55:1610
25607991816cyclictest8433-21snmp_easybox.os20:55:2610
25607991816cyclictest830-21df_inode21:30:1710
25607991816cyclictest5978-21snmp_easybox.os19:25:1310
25607991816cyclictest467-21snmp_rack3slot923:41:1410
25607991816cyclictest30525-21snmp_easybox.os00:25:1510
25607991816cyclictest29908-21snmp_rack3slot919:15:1310
25607991816cyclictest26954-21snmp_rack3slot919:10:1710
25607991816cyclictest24833-21irqstats00:15:2110
25607991816cyclictest24642-21snmp_easybox.os20:35:1410
25607991816cyclictest20781-21iostat_ios23:25:2110
25607991816cyclictest19657-21snmp_easybox.os00:10:1110
25607991816cyclictest18826-21snmp_easybox.os22:40:1310
25607991816cyclictest18063-21snmp_rack3slot920:25:1510
25607991816cyclictest14148-21snmp_rack3slot920:20:1510
25607991816cyclictest1243-21df22:15:1410
25607991816cyclictest12218-21snmp_rack3slot922:30:1410
25607991816cyclictest11405-21munin-run23:14:5910
25598991816cyclictest28618-21qemu-kvm22:13:217
25598991816cyclictest25327-21qemu-kvm19:47:237
25598991816cyclictest25327-21qemu-kvm19:14:257
25573991816cyclictest0-21swapper/021:08:230
2557399180cyclictest0-21swapper/021:50:280
2557399180cyclictest0-21swapper/021:30:310
25609991716cyclictest377-1kworker/10:1H23:47:552
25609991716cyclictest377-1kworker/10:1H00:31:572
25609991716cyclictest377-1kworker/10:1H00:31:572
25609991716cyclictest28275-21python22:50:312
2560999170cyclictest92432sleep1020:11:012
2560999170cyclictest87802chrt19:26:342
2560999170cyclictest86502chrt23:55:042
2560999170cyclictest78752sleep1020:55:202
2560999170cyclictest71682sleep1022:22:532
2560999170cyclictest69982sleep1000:35:202
2560999170cyclictest68612sleep1023:05:362
2560999170cyclictest58682sleep1023:50:162
2560999170cyclictest51542chrt19:21:452
2560999170cyclictest5132chrt23:41:502
2560999170cyclictest34272sleep1022:16:292
2560999170cyclictest316952sleep1021:27:112
2560999170cyclictest3066450irq/53-eth0-tx-20:00:262
2560999170cyclictest3066450irq/53-eth0-tx-20:00:252
2560999170cyclictest3066350irq/52-eth0-rx-22:55:192
2560999170cyclictest3066350irq/52-eth0-rx-22:40:282
2560999170cyclictest3066350irq/52-eth0-rx-21:50:232
2560999170cyclictest3066350irq/52-eth0-rx-20:50:292
2560999170cyclictest3066350irq/52-eth0-rx-20:40:402
2560999170cyclictest3066350irq/52-eth0-rx-20:16:072
2560999170cyclictest3066350irq/52-eth0-rx-19:45:182
2560999170cyclictest3066350irq/52-eth0-rx-19:30:152
2560999170cyclictest296672sleep1000:20:422
2560999170cyclictest29542sleep1021:31:482
2560999170cyclictest293292sleep1023:36:392
2560999170cyclictest289552sleep1019:11:572
2560999170cyclictest284242sleep1022:06:152
2560999170cyclictest276712sleep1020:39:062
2560999170cyclictest266512sleep1021:20:232
2560999170cyclictest260782chrt00:16:182
2560999170cyclictest243092sleep1021:15:572
2560999170cyclictest239782chrt22:45:202
2560999170cyclictest239232chrt22:00:272
2560999170cyclictest239232chrt22:00:272
2560999170cyclictest225902chrt00:13:302
2560999170cyclictest220032sleep1023:26:022
2560999170cyclictest209692sleep1020:30:052
2560999170cyclictest194782chrt19:40:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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