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2026-02-02 - 07:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Feb 02, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501060irq/42-ahci0-21swapper/319:08:535
9918501030irq/53-eth0-rx-0-21swapper/219:06:164
991850980irq/53-eth0-rx-0-21swapper/719:09:459
1418629888sleep10-21swapper/119:08:331
991850900irq/53-eth0-rx-0-21swapper/819:05:2010
991850890irq/53-eth0-rx-0-21swapper/519:06:347
991850890irq/53-eth0-rx-0-21swapper/1119:06:213
172450750irq/56-eth1-rx-0-21swapper/1019:09:222
991850720irq/53-eth0-rx-0-21swapper/419:08:086
1428326664sleep90-21swapper/919:09:5311
1395026553sleep60-21swapper/619:06:148
1392926553sleep00-21swapper/019:05:560
14388994214cyclictest0-21swapper/022:21:320
1444499290cyclictest0-21swapper/1119:15:583
1443199280cyclictest0-21swapper/521:24:597
14388992221cyclictest15871-21kworker/0:220:26:440
1442899210cyclictest0-21swapper/400:37:356
1444399192cyclictest991850irq/53-eth0-rx-23:03:062
1444399192cyclictest991850irq/53-eth0-rx-22:46:022
1444399192cyclictest991850irq/53-eth0-rx-21:34:262
1444399192cyclictest991850irq/53-eth0-rx-21:23:462
1444399192cyclictest991850irq/53-eth0-rx-21:14:242
1444399192cyclictest991850irq/53-eth0-rx-00:17:432
1444299192cyclictest0-21swapper/923:37:3311
1444299192cyclictest0-21swapper/921:26:3111
1444299192cyclictest0-21swapper/900:31:2211
14443991817cyclictest5793-21ssh21:37:582
14443991817cyclictest19123-21ssh22:19:052
14443991817cyclictest0-21swapper/1023:41:002
14443991817cyclictest0-21swapper/1023:20:312
14443991817cyclictest0-21swapper/1022:58:042
14443991817cyclictest0-21swapper/1022:44:582
14443991817cyclictest0-21swapper/1022:12:392
14443991817cyclictest0-21swapper/1020:13:032
14443991817cyclictest0-21swapper/1000:06:592
14443991817cyclictest0-21swapper/1000:06:592
1444399181cyclictest991950irq/54-eth0-tx-23:57:572
1444399181cyclictest991950irq/54-eth0-tx-23:57:572
1444399181cyclictest991850irq/53-eth0-rx-23:53:462
1444399181cyclictest991850irq/53-eth0-rx-23:16:252
1444399181cyclictest991850irq/53-eth0-rx-23:10:102
1444399181cyclictest991850irq/53-eth0-rx-23:07:502
1444399181cyclictest991850irq/53-eth0-rx-22:26:232
1444399181cyclictest991850irq/53-eth0-rx-22:20:472
1444399181cyclictest991850irq/53-eth0-rx-22:09:002
1444399181cyclictest991850irq/53-eth0-rx-22:02:352
1444399181cyclictest991850irq/53-eth0-rx-21:50:392
1444399181cyclictest991850irq/53-eth0-rx-21:46:192
1444399181cyclictest991850irq/53-eth0-rx-19:12:012
1444399181cyclictest991850irq/53-eth0-rx-00:20:462
1444399181cyclictest991850irq/53-eth0-rx-00:02:272
1444399181cyclictest12850irq/42-ahci21:08:512
1444399181cyclictest115050irq/18-i801_smb22:35:242
1444399180cyclictest228662sleep1019:18:542
1444299181cyclictest24418-21kworker/9:022:30:1711
1444299181cyclictest0-21swapper/923:56:2511
1444299181cyclictest0-21swapper/923:56:2511
1444299181cyclictest0-21swapper/923:49:1011
1444299181cyclictest0-21swapper/923:49:1011
1444299181cyclictest0-21swapper/923:32:1111
1444299181cyclictest0-21swapper/922:50:1411
1444299181cyclictest0-21swapper/922:47:0411
1444299181cyclictest0-21swapper/922:26:0711
1444299181cyclictest0-21swapper/922:20:2011
1444299181cyclictest0-21swapper/921:37:4211
1444299181cyclictest0-21swapper/921:30:1311
1444299181cyclictest0-21swapper/920:20:2111
1444299181cyclictest0-21swapper/919:26:4311
1444299181cyclictest0-21swapper/900:37:4711
14436991816cyclictest6680-21qemu-kvm22:13:098
1444499170cyclictest0-21swapper/1121:13:213
14443991716cyclictest0-21swapper/1023:45:272
14443991716cyclictest0-21swapper/1023:45:272
14443991716cyclictest0-21swapper/1019:25:172
14443991716cyclictest0-21swapper/1000:35:192
1444399170cyclictest991950irq/54-eth0-tx-21:41:312
1444399170cyclictest991950irq/54-eth0-tx-20:44:552
1444399170cyclictest991950irq/54-eth0-tx-20:44:552
1444399170cyclictest991850irq/53-eth0-rx-23:30:212
1444399170cyclictest991850irq/53-eth0-rx-23:25:572
1444399170cyclictest991850irq/53-eth0-rx-22:30:432
1444399170cyclictest991850irq/53-eth0-rx-21:55:012
1444399170cyclictest991850irq/53-eth0-rx-21:25:072
1444399170cyclictest991850irq/53-eth0-rx-21:15:052
1444399170cyclictest991850irq/53-eth0-rx-20:45:552
1444399170cyclictest991850irq/53-eth0-rx-20:35:212
1444399170cyclictest991850irq/53-eth0-rx-20:24:542
1444399170cyclictest991850irq/53-eth0-rx-19:40:142
1444399170cyclictest991850irq/53-eth0-rx-00:25:352
1444399170cyclictest991850irq/53-eth0-rx-00:10:252
1444399170cyclictest991850irq/53-eth0-rx-00:10:252
1444399170cyclictest90352sleep1020:25:382
1444399170cyclictest48942sleep1019:36:202
1444399170cyclictest309482sleep1020:56:052
1444399170cyclictest273032sleep1020:50:532
1444399170cyclictest268602sleep1020:07:002
1444399170cyclictest268602sleep1020:07:002
1444399170cyclictest254462sleep1022:50:192
1444399170cyclictest234692sleep1019:20:072
1444399170cyclictest21242sleep1021:00:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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