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2026-02-28 - 04:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Feb 28, 2026 00:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501130irq/53-eth0-rx-0-21swapper/119:09:351
9918501090irq/53-eth0-rx-0-21swapper/319:09:415
13921210991sleep60-21swapper/619:08:018
13845210794sleep40-21swapper/419:06:586
991850950irq/53-eth0-rx-0-21swapper/1119:06:513
1411129387sleep70-21swapper/719:09:509
991850920irq/53-eth0-rx-0-21swapper/219:08:104
991850900irq/53-eth0-rx-0-21swapper/819:06:2110
1407427872sleep00-21swapper/019:09:190
991850700irq/53-eth0-rx-0-21swapper/519:07:027
1399726866sleep100-21swapper/1019:08:172
1389826556sleep90-21swapper/919:07:4011
14228994328cyclictest0-21swapper/021:24:160
1427099290cyclictest0-21swapper/1121:27:593
991850280irq/53-eth0-rx-0-21swapper/921:23:5611
991850280irq/53-eth0-rx-0-21swapper/421:24:006
991850280irq/53-eth0-rx-0-21swapper/121:24:151
14228992221cyclictest2305-21nscd19:30:000
14248992117cyclictest9751-21munin-node22:05:125
1426899202cyclictest0-21swapper/900:31:2011
14228992018cyclictest0-21swapper/020:08:290
1427099195cyclictest0-21swapper/1120:26:563
14270991917cyclictest0-21swapper/1119:30:113
1426999192cyclictest991850irq/53-eth0-rx-23:38:202
1426999192cyclictest991850irq/53-eth0-rx-23:38:192
1426999192cyclictest991850irq/53-eth0-rx-22:50:232
1426999192cyclictest991850irq/53-eth0-rx-22:40:232
1426999192cyclictest991850irq/53-eth0-rx-22:11:542
1426999192cyclictest991850irq/53-eth0-rx-22:06:422
1426999192cyclictest991850irq/53-eth0-rx-21:20:402
1426999192cyclictest991850irq/53-eth0-rx-00:16:392
14269991917cyclictest0-21swapper/1021:46:562
1426899192cyclictest0-21swapper/923:59:4211
1426899192cyclictest0-21swapper/922:56:2011
1426899192cyclictest0-21swapper/922:43:3811
1426899192cyclictest0-21swapper/922:25:1311
1426899192cyclictest0-21swapper/922:15:5411
1426899192cyclictest0-21swapper/900:21:3611
14228991917cyclictest0-21swapper/019:30:160
1427099180cyclictest0-21swapper/1122:23:583
14269991817cyclictest0-21swapper/1023:55:112
14269991817cyclictest0-21swapper/1023:50:522
14269991817cyclictest0-21swapper/1023:50:522
14269991817cyclictest0-21swapper/1022:37:152
14269991817cyclictest0-21swapper/1021:59:572
14269991817cyclictest0-21swapper/1021:50:012
14269991817cyclictest0-21swapper/1021:41:562
14269991817cyclictest0-21swapper/1020:15:232
14269991817cyclictest0-21swapper/1019:38:102
14269991817cyclictest0-21swapper/1019:20:512
14269991817cyclictest0-21swapper/1000:38:052
1426999181cyclictest991850irq/53-eth0-rx-23:41:372
1426999181cyclictest991850irq/53-eth0-rx-23:22:552
1426999181cyclictest991850irq/53-eth0-rx-23:15:522
1426999181cyclictest991850irq/53-eth0-rx-23:15:522
1426999181cyclictest991850irq/53-eth0-rx-23:07:212
1426999181cyclictest991850irq/53-eth0-rx-23:03:462
1426999181cyclictest991850irq/53-eth0-rx-22:45:462
1426999181cyclictest991850irq/53-eth0-rx-22:25:082
1426999181cyclictest991850irq/53-eth0-rx-22:20:312
1426999181cyclictest991850irq/53-eth0-rx-22:00:462
1426999181cyclictest991850irq/53-eth0-rx-21:35:182
1426999181cyclictest991850irq/53-eth0-rx-21:10:342
1426999181cyclictest991850irq/53-eth0-rx-21:10:342
1426999181cyclictest991850irq/53-eth0-rx-00:32:462
1426999181cyclictest991850irq/53-eth0-rx-00:26:592
1426999181cyclictest991850irq/53-eth0-rx-00:05:102
1426999181cyclictest991850irq/53-eth0-rx-00:02:262
1426899181cyclictest991950irq/54-eth0-tx-23:00:1111
1426899181cyclictest0-21swapper/923:52:1411
1426899181cyclictest0-21swapper/923:52:1411
1426899181cyclictest0-21swapper/923:46:0511
1426899181cyclictest0-21swapper/923:40:3711
1426899181cyclictest0-21swapper/923:35:5411
1426899181cyclictest0-21swapper/923:35:5311
1426899181cyclictest0-21swapper/923:30:4211
1426899181cyclictest0-21swapper/923:12:2611
1426899181cyclictest0-21swapper/923:05:5111
1426899181cyclictest0-21swapper/922:51:3211
1426899181cyclictest0-21swapper/922:46:1511
1426899181cyclictest0-21swapper/922:21:5811
1426899181cyclictest0-21swapper/922:12:5611
1426899181cyclictest0-21swapper/921:55:4811
1426899181cyclictest0-21swapper/921:51:5511
1426899181cyclictest0-21swapper/921:47:2311
1426899181cyclictest0-21swapper/921:31:1911
1426899181cyclictest0-21swapper/921:28:0411
1426899181cyclictest0-21swapper/921:11:2911
1426899181cyclictest0-21swapper/921:11:2911
1426899181cyclictest0-21swapper/920:06:3211
1426899181cyclictest0-21swapper/900:39:5211
1426899181cyclictest0-21swapper/900:28:2411
1426899181cyclictest0-21swapper/900:00:3911
14262991816cyclictest14923-21ssh21:41:347
14228991816cyclictest0-21swapper/020:25:170
991850170irq/53-eth0-rx-0-21swapper/821:24:1110
991850170irq/53-eth0-rx-0-21swapper/221:24:034
14269991716cyclictest0-21swapper/1023:46:122
14269991716cyclictest0-21swapper/1000:20:262
14269991716cyclictest0-21swapper/1000:10:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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