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2026-05-10 - 04:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun May 10, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501120irq/42-ahci0-21swapper/319:09:045
128501120irq/42-ahci0-21swapper/119:09:261
12850990irq/42-ahci0-21swapper/219:09:494
991850980irq/53-eth0-rx-0-21swapper/519:07:237
991850910irq/53-eth0-rx-0-21swapper/719:05:409
1903828075sleep40-21swapper/419:07:106
991850730irq/53-eth0-rx-0-21swapper/919:08:5411
1926627371sleep80-21swapper/819:09:2710
1902126853sleep00-21swapper/019:06:530
991850660irq/53-eth0-rx-0-21swapper/1119:06:033
1922226157sleep100-21swapper/1019:08:512
1895325955sleep60-21swapper/619:05:598
19412993718cyclictest0-21swapper/022:08:430
19412993317cyclictest0-21swapper/020:22:440
1944299280cyclictest0-21swapper/421:42:406
19439992723cyclictest13312-21ssh22:33:315
1945499241cyclictest0-21swapper/923:05:2611
1945499232cyclictest0-21swapper/922:22:2311
19454992316cyclictest0-21swapper/922:01:1211
19454992315cyclictest0-21swapper/921:47:1911
1945499220cyclictest0-21swapper/923:37:5911
19443992221cyclictest16132-21qemu-kvm22:45:147
19456992120cyclictest0-21swapper/1120:13:103
19456992120cyclictest0-21swapper/1120:13:093
1945499210cyclictest0-21swapper/922:44:3011
19456991917cyclictest0-21swapper/1120:08:223
1945599192cyclictest991850irq/53-eth0-rx-22:45:242
1945599192cyclictest991850irq/53-eth0-rx-22:30:322
1945599192cyclictest991850irq/53-eth0-rx-00:10:042
1945499192cyclictest0-21swapper/922:10:0911
19455991817cyclictest25193-1kworker/10:0H23:29:512
19455991817cyclictest0-21swapper/1022:59:592
19455991817cyclictest0-21swapper/1022:59:582
19455991817cyclictest0-21swapper/1020:30:372
19455991817cyclictest0-21swapper/1000:35:232
19455991817cyclictest0-21swapper/1000:01:132
19455991816cyclictest19850-21munin-node22:10:222
1945599181cyclictest991950irq/54-eth0-tx-23:10:402
1945599181cyclictest991950irq/54-eth0-tx-23:10:402
1945599181cyclictest991950irq/54-eth0-tx-23:05:072
1945599181cyclictest991950irq/54-eth0-tx-22:20:102
1945599181cyclictest991850irq/53-eth0-rx-23:55:522
1945599181cyclictest991850irq/53-eth0-rx-23:49:372
1945599181cyclictest991850irq/53-eth0-rx-23:43:252
1945599181cyclictest991850irq/53-eth0-rx-23:36:272
1945599181cyclictest991850irq/53-eth0-rx-23:31:112
1945599181cyclictest991850irq/53-eth0-rx-22:51:352
1945599181cyclictest991850irq/53-eth0-rx-22:35:432
1945599181cyclictest991850irq/53-eth0-rx-22:27:522
1945599181cyclictest991850irq/53-eth0-rx-22:15:392
1945599181cyclictest991850irq/53-eth0-rx-21:58:392
1945599181cyclictest991850irq/53-eth0-rx-21:51:362
1945599181cyclictest991850irq/53-eth0-rx-21:16:292
1945599181cyclictest991850irq/53-eth0-rx-20:22:372
1945599181cyclictest991850irq/53-eth0-rx-19:31:252
1945599181cyclictest991850irq/53-eth0-rx-00:33:532
1945599181cyclictest991850irq/53-eth0-rx-00:22:332
1945599181cyclictest991850irq/53-eth0-rx-00:20:022
1945599181cyclictest991850irq/53-eth0-rx-00:09:052
1945599180cyclictest12850irq/42-ahci20:08:242
1945499181cyclictest11736-21cpu22:05:1211
1945499181cyclictest0-21swapper/923:45:5511
1945499181cyclictest0-21swapper/923:41:5711
1945499181cyclictest0-21swapper/923:18:2511
1945499181cyclictest0-21swapper/923:12:1611
1945499181cyclictest0-21swapper/923:12:1611
1945499181cyclictest0-21swapper/922:33:5711
1945499181cyclictest0-21swapper/921:55:4011
1945499181cyclictest0-21swapper/921:22:4611
1945499181cyclictest0-21swapper/921:03:4611
1945499181cyclictest0-21swapper/920:27:5811
1945499181cyclictest0-21swapper/920:22:1411
1945499181cyclictest0-21swapper/920:16:1011
1945499181cyclictest0-21swapper/920:09:1611
1945499181cyclictest0-21swapper/920:03:4811
1945499181cyclictest0-21swapper/919:58:2311
1945499181cyclictest0-21swapper/919:53:3111
1945499181cyclictest0-21swapper/919:38:1211
1945499181cyclictest0-21swapper/919:28:5811
1945499181cyclictest0-21swapper/919:12:3311
1945499181cyclictest0-21swapper/900:35:2211
1945499181cyclictest0-21swapper/900:15:1211
19443991816cyclictest32032-21qemu-kvm20:45:157
19443991816cyclictest32032-21qemu-kvm20:30:147
19443991816cyclictest32031-21qemu-kvm20:15:137
19443991816cyclictest16133-21qemu-kvm22:40:137
19443991816cyclictest16133-21qemu-kvm22:35:127
19443991816cyclictest16133-21qemu-kvm22:20:127
19443991815cyclictest32031-21qemu-kvm20:10:127
19443991815cyclictest32031-21qemu-kvm20:10:117
19434991816cyclictest2308-21snmpd23:58:114
1941299180cyclictest0-21swapper/020:10:420
1941299180cyclictest0-21swapper/020:10:420
1945699179cyclictest0-21swapper/1120:04:093
19455991716cyclictest0-21swapper/1022:00:012
19455991716cyclictest0-21swapper/1019:40:162
1945599170cyclictest991850irq/53-eth0-rx-23:20:052
1945599170cyclictest991850irq/53-eth0-rx-23:20:042
1945599170cyclictest991850irq/53-eth0-rx-23:16:092
1945599170cyclictest991850irq/53-eth0-rx-23:00:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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