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2026-01-26 - 20:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Jan 26, 2026 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501150irq/53-eth0-rx-0-21swapper/207:06:064
23192210490sleep50-21swapper/507:07:237
128501040irq/42-ahci0-21swapper/107:09:061
2341829489sleep90-21swapper/907:09:4011
991850930irq/53-eth0-rx-0-21swapper/1007:06:112
12850910irq/42-ahci0-21swapper/307:08:365
991850890irq/53-eth0-rx-0-21swapper/707:05:139
991850870irq/53-eth0-rx-0-21swapper/407:05:416
2306728775sleep60-21swapper/607:05:488
119350740irq/18-parport00-21swapper/807:07:2710
2322826757sleep110-21swapper/1107:07:533
2324725955sleep00-21swapper/007:08:070
2359399320cyclictest0-21swapper/1107:18:463
2359299300cyclictest0-21swapper/1010:13:152
2359299300cyclictest0-21swapper/1010:13:142
23593992928cyclictest0-21swapper/1110:16:473
991950280irq/54-eth0-tx-0-21swapper/810:13:2210
991950280irq/54-eth0-tx-0-21swapper/810:13:2210
991950280irq/54-eth0-tx-0-21swapper/410:13:176
991950280irq/54-eth0-tx-0-21swapper/410:13:166
23593992827cyclictest0-21swapper/1110:13:573
23593992827cyclictest0-21swapper/1110:13:563
2355499240cyclictest0-21swapper/010:24:550
2358999220cyclictest0-21swapper/707:59:569
2359399210cyclictest0-21swapper/1110:30:043
2359399210cyclictest0-21swapper/1110:30:033
2359399210cyclictest0-21swapper/1110:25:443
2359399210cyclictest0-21swapper/1110:25:433
2359399210cyclictest0-21swapper/1110:09:293
2359399210cyclictest0-21swapper/1108:11:533
23554992118cyclictest0-21swapper/011:08:560
23593992019cyclictest0-21swapper/1108:27:393
2359299192cyclictest991850irq/53-eth0-rx-12:19:122
2359299192cyclictest991850irq/53-eth0-rx-12:09:062
2359299192cyclictest991850irq/53-eth0-rx-11:52:502
2359299192cyclictest991850irq/53-eth0-rx-11:24:022
2359299192cyclictest991850irq/53-eth0-rx-11:13:212
2359299192cyclictest991850irq/53-eth0-rx-10:35:112
2359299192cyclictest991850irq/53-eth0-rx-10:30:232
2359299192cyclictest991850irq/53-eth0-rx-10:30:222
2359299192cyclictest991850irq/53-eth0-rx-10:17:192
2359299192cyclictest991850irq/53-eth0-rx-10:03:462
2359299192cyclictest991850irq/53-eth0-rx-09:52:412
2359299192cyclictest991850irq/53-eth0-rx-09:46:462
2359299192cyclictest991850irq/53-eth0-rx-09:31:252
2359299192cyclictest991850irq/53-eth0-rx-09:28:172
2359299192cyclictest991850irq/53-eth0-rx-09:15:022
2359299192cyclictest991850irq/53-eth0-rx-09:14:302
2359299192cyclictest991850irq/53-eth0-rx-08:35:122
23592991917cyclictest32085-1kworker/10:2H11:55:262
2359199192cyclictest0-21swapper/911:56:4211
2359199192cyclictest0-21swapper/910:56:2811
2359199192cyclictest0-21swapper/910:49:3611
2359199192cyclictest0-21swapper/910:29:0711
2359199192cyclictest0-21swapper/910:29:0711
2359199192cyclictest0-21swapper/910:19:5311
2359199192cyclictest0-21swapper/909:56:2611
2359199192cyclictest0-21swapper/909:24:0511
23554991916cyclictest0-21swapper/010:35:120
2355499191cyclictest0-21swapper/010:13:120
2355499191cyclictest0-21swapper/010:13:120
23592991817cyclictest32085-1kworker/10:2H09:06:212
23592991817cyclictest32085-1kworker/10:2H07:14:302
23592991817cyclictest1969-21ssh11:42:052
23592991817cyclictest0-21swapper/1012:23:152
23592991817cyclictest0-21swapper/1010:57:412
23592991817cyclictest0-21swapper/1009:40:172
23592991817cyclictest0-21swapper/1009:24:092
23592991817cyclictest0-21swapper/1007:23:352
23592991817cyclictest0-21swapper/1007:23:342
23592991816cyclictest19609-21kworker/10:109:59:192
2359299181cyclictest991950irq/54-eth0-tx-12:35:312
2359299181cyclictest991950irq/54-eth0-tx-12:02:362
2359299181cyclictest991850irq/53-eth0-rx-12:30:242
2359299181cyclictest991850irq/53-eth0-rx-12:25:082
2359299181cyclictest991850irq/53-eth0-rx-11:45:022
2359299181cyclictest991850irq/53-eth0-rx-11:35:382
2359299181cyclictest991850irq/53-eth0-rx-11:30:512
2359299181cyclictest991850irq/53-eth0-rx-11:26:292
2359299181cyclictest991850irq/53-eth0-rx-11:15:302
2359299181cyclictest991850irq/53-eth0-rx-11:07:432
2359299181cyclictest991850irq/53-eth0-rx-11:02:172
2359299181cyclictest991850irq/53-eth0-rx-10:53:432
2359299181cyclictest991850irq/53-eth0-rx-10:46:122
2359299181cyclictest991850irq/53-eth0-rx-10:41:072
2359299181cyclictest991850irq/53-eth0-rx-10:25:122
2359299181cyclictest991850irq/53-eth0-rx-10:25:112
2359299181cyclictest991850irq/53-eth0-rx-10:20:062
2359299181cyclictest991850irq/53-eth0-rx-10:05:222
2359299181cyclictest991850irq/53-eth0-rx-09:37:142
2359299181cyclictest991850irq/53-eth0-rx-08:40:542
2359299181cyclictest991850irq/53-eth0-rx-08:25:582
2359299181cyclictest991850irq/53-eth0-rx-08:16:112
2359299181cyclictest991850irq/53-eth0-rx-08:02:022
2359299181cyclictest12850irq/42-ahci07:50:032
2359199181cyclictest761ksoftirqd/910:10:1211
2359199181cyclictest761ksoftirqd/910:10:1111
2359199181cyclictest741rcuc/911:18:1911
2359199181cyclictest4556-21cpuspeed08:10:1211
2359199181cyclictest0-21swapper/912:07:1711
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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