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2026-01-28 - 21:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Jan 28, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25480210692sleep70-21swapper/707:06:599
9918501020irq/53-eth0-rx-0-21swapper/107:07:011
991850970irq/53-eth0-rx-0-21swapper/807:05:2110
14050960irq/18-ehci_hcd0-21swapper/207:06:174
119350940irq/18-parport00-21swapper/407:06:176
991850920irq/53-eth0-rx-0-21swapper/307:09:315
991850910irq/53-eth0-rx-0-21swapper/507:08:127
991850910irq/53-eth0-rx-0-21swapper/1107:05:033
12850900irq/42-ahci0-21swapper/907:05:4111
2554427768sleep100-21swapper/1007:07:512
2551827363sleep00-21swapper/007:07:280
2544926151sleep60-21swapper/607:06:358
2591499300cyclictest0-21swapper/1110:17:193
991850280irq/53-eth0-rx-6099-21qemu-kvm08:09:217
991850280irq/53-eth0-rx-12220-21kworker/9:208:09:1311
991850280irq/53-eth0-rx-0-21swapper/708:09:149
25914992812cyclictest816-21chrt09:20:423
25914992812cyclictest816-21chrt09:20:413
2591499280cyclictest236102sleep1109:14:433
2591499280cyclictest236102sleep1109:14:433
12850280irq/42-ahci0-21swapper/808:09:1910
25914992610cyclictest991850irq/53-eth0-rx-09:15:133
25914992322cyclictest0-21swapper/1110:26:163
2591499230cyclictest0-21swapper/1109:26:523
991850200irq/53-eth0-rx-0-21swapper/009:20:110
991850200irq/53-eth0-rx-0-21swapper/009:20:110
2591499206cyclictest0-21swapper/1110:14:053
2591499190cyclictest0-21swapper/1109:09:033
2591399192cyclictest991850irq/53-eth0-rx-12:12:512
2591399192cyclictest991850irq/53-eth0-rx-09:40:102
2591399192cyclictest991850irq/53-eth0-rx-09:26:502
2591399192cyclictest991850irq/53-eth0-rx-09:16:142
2591299192cyclictest0-21swapper/910:48:5911
2590399195cyclictest0-21swapper/711:05:019
2589999193cyclictest0-21swapper/310:17:005
2589999193cyclictest0-21swapper/309:12:045
2589999193cyclictest0-21swapper/309:12:035
2589999193cyclictest0-21swapper/308:05:485
991950180irq/54-eth0-tx-0-21swapper/909:17:5511
991950180irq/54-eth0-tx-0-21swapper/809:20:0210
991950180irq/54-eth0-tx-0-21swapper/809:20:0110
991950180irq/54-eth0-tx-0-21swapper/709:30:169
991950180irq/54-eth0-tx-0-21swapper/409:16:366
991950180irq/54-eth0-tx-0-21swapper/309:20:085
991950180irq/54-eth0-tx-0-21swapper/309:20:085
991950180irq/54-eth0-tx-0-21swapper/209:13:264
991950180irq/54-eth0-tx-0-21swapper/209:13:264
991950180irq/54-eth0-tx-0-21swapper/009:28:130
991850180irq/53-eth0-rx-0-21swapper/909:21:1911
991850180irq/53-eth0-rx-0-21swapper/909:21:1911
991850180irq/53-eth0-rx-0-21swapper/809:19:5910
991850180irq/53-eth0-rx-0-21swapper/709:19:559
991850180irq/53-eth0-rx-0-21swapper/409:26:086
991850180irq/53-eth0-rx-0-21swapper/409:20:106
991850180irq/53-eth0-rx-0-21swapper/409:20:096
991850180irq/53-eth0-rx-0-21swapper/309:30:105
991850180irq/53-eth0-rx-0-21swapper/309:28:105
991850180irq/53-eth0-rx-0-21swapper/309:16:315
991850180irq/53-eth0-rx-0-21swapper/209:26:044
991850180irq/53-eth0-rx-0-21swapper/209:20:074
991850180irq/53-eth0-rx-0-21swapper/209:20:074
991850180irq/53-eth0-rx-0-21swapper/209:15:514
991850180irq/53-eth0-rx-0-21swapper/1009:30:162
991850180irq/53-eth0-rx-0-21swapper/109:20:121
991850180irq/53-eth0-rx-0-21swapper/109:20:111
991850180irq/53-eth0-rx-0-21swapper/109:19:541
991850180irq/53-eth0-rx-0-21swapper/009:15:590
2591499180cyclictest0-21swapper/1108:08:153
25913991817cyclictest21647-21snmp_rack3slot907:45:132
25913991817cyclictest0-21swapper/1011:37:102
25913991817cyclictest0-21swapper/1011:07:472
2591399181cyclictest991950irq/54-eth0-tx-12:04:132
2591399181cyclictest991950irq/54-eth0-tx-11:30:272
2591399181cyclictest991950irq/54-eth0-tx-11:12:582
2591399181cyclictest991950irq/54-eth0-tx-09:20:192
2591399181cyclictest991950irq/54-eth0-tx-09:20:192
2591399181cyclictest991850irq/53-eth0-rx-12:36:362
2591399181cyclictest991850irq/53-eth0-rx-12:20:412
2591399181cyclictest991850irq/53-eth0-rx-12:20:412
2591399181cyclictest991850irq/53-eth0-rx-12:15:202
2591399181cyclictest991850irq/53-eth0-rx-12:15:202
2591399181cyclictest991850irq/53-eth0-rx-11:52:272
2591399181cyclictest991850irq/53-eth0-rx-11:29:232
2591399181cyclictest991850irq/53-eth0-rx-11:02:192
2591399181cyclictest991850irq/53-eth0-rx-10:57:412
2591399181cyclictest991850irq/53-eth0-rx-10:50:592
2591399181cyclictest991850irq/53-eth0-rx-10:46:492
2591399181cyclictest991850irq/53-eth0-rx-10:43:542
2591399181cyclictest991850irq/53-eth0-rx-10:37:142
2591399181cyclictest991850irq/53-eth0-rx-10:33:562
2591399181cyclictest991850irq/53-eth0-rx-10:29:042
2591399181cyclictest991850irq/53-eth0-rx-10:22:032
2591399181cyclictest991850irq/53-eth0-rx-10:16:162
2591399181cyclictest991850irq/53-eth0-rx-10:12:002
2591399181cyclictest991850irq/53-eth0-rx-09:55:432
2591399181cyclictest991850irq/53-eth0-rx-09:50:042
2591399181cyclictest991850irq/53-eth0-rx-09:39:172
2591399181cyclictest991850irq/53-eth0-rx-09:12:022
2591399181cyclictest991850irq/53-eth0-rx-09:12:012
2591399181cyclictest811rcuc/1011:17:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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