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2026-03-22 - 23:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Mar 22, 2026 12:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26907211195sleep40-21swapper/407:06:466
26923210895sleep30-21swapper/307:06:575
27016210694sleep20-21swapper/207:08:084
26978210693sleep10-21swapper/107:07:431
26988210492sleep70-21swapper/707:07:499
26920210191sleep00-21swapper/007:06:540
2717929893sleep90-21swapper/907:09:3911
991850950irq/53-eth0-rx-0-21swapper/507:07:297
991850940irq/53-eth0-rx-0-21swapper/1107:05:283
991850930irq/53-eth0-rx-0-21swapper/807:05:3710
2715427977sleep100-21swapper/1007:09:162
2687726454sleep60-21swapper/607:06:248
2731999420cyclictest0-21swapper/008:15:260
2731999350cyclictest0-21swapper/008:13:130
2735899320cyclictest0-21swapper/1108:17:263
2735899320cyclictest0-21swapper/1108:12:453
27350992625cyclictest883-21rm10:12:4210
27319992625cyclictest830-21ssh10:12:370
27358992524cyclictest991850irq/53-eth0-rx-10:12:353
2731999250cyclictest0-21swapper/007:17:190
2735299214cyclictest811rcuc/1012:36:152
2735299203cyclictest991850irq/53-eth0-rx-10:48:132
2734399200cyclictest0-21swapper/311:47:475
2735299192cyclictest991850irq/53-eth0-rx-12:14:432
2735299192cyclictest991850irq/53-eth0-rx-10:54:592
2735299192cyclictest991850irq/53-eth0-rx-10:35:242
2735299192cyclictest991850irq/53-eth0-rx-09:40:112
2735299192cyclictest831ksoftirqd/1008:20:232
2735199192cyclictest991850irq/53-eth0-rx-10:12:1511
2735199192cyclictest0-21swapper/912:35:1711
2735199192cyclictest0-21swapper/911:56:2111
2735199192cyclictest0-21swapper/911:20:1311
2735199192cyclictest0-21swapper/909:18:4711
2733899190cyclictest0-21swapper/210:59:004
2731999190cyclictest0-21swapper/009:23:220
27352991817cyclictest30463-21kworker/10:109:32:192
27352991817cyclictest0-21swapper/1011:41:202
27352991817cyclictest0-21swapper/1011:20:262
27352991817cyclictest0-21swapper/1010:57:582
27352991817cyclictest0-21swapper/1009:39:422
2735299181cyclictest991950irq/54-eth0-tx-10:32:362
2735299181cyclictest991850irq/53-eth0-rx-12:27:542
2735299181cyclictest991850irq/53-eth0-rx-12:27:542
2735299181cyclictest991850irq/53-eth0-rx-12:23:052
2735299181cyclictest991850irq/53-eth0-rx-12:05:342
2735299181cyclictest991850irq/53-eth0-rx-12:02:072
2735299181cyclictest991850irq/53-eth0-rx-11:56:342
2735299181cyclictest991850irq/53-eth0-rx-11:53:382
2735299181cyclictest991850irq/53-eth0-rx-11:45:292
2735299181cyclictest991850irq/53-eth0-rx-11:28:412
2735299181cyclictest991850irq/53-eth0-rx-11:28:412
2735299181cyclictest991850irq/53-eth0-rx-11:19:152
2735299181cyclictest991850irq/53-eth0-rx-11:14:132
2735299181cyclictest991850irq/53-eth0-rx-11:07:352
2735299181cyclictest991850irq/53-eth0-rx-10:43:012
2735299181cyclictest991850irq/53-eth0-rx-10:25:022
2735299181cyclictest991850irq/53-eth0-rx-10:06:252
2735299181cyclictest991850irq/53-eth0-rx-10:02:262
2735299181cyclictest991850irq/53-eth0-rx-09:52:052
2735299181cyclictest991850irq/53-eth0-rx-09:25:242
2735299181cyclictest991850irq/53-eth0-rx-09:23:492
2735299181cyclictest991850irq/53-eth0-rx-09:14:162
2735299181cyclictest831ksoftirqd/1009:55:192
2735299181cyclictest831ksoftirqd/1008:30:202
2735299181cyclictest305932sleep1009:45:102
2735299181cyclictest12850irq/42-ahci11:34:002
2735299181cyclictest12850irq/42-ahci10:23:302
2735199181cyclictest991850irq/53-eth0-rx-11:13:5811
2735199181cyclictest991850irq/53-eth0-rx-10:15:1111
2735199181cyclictest28024-21kworker/9:009:37:3811
2735199181cyclictest2557-1kworker/9:0H09:00:1611
2735199181cyclictest0-21swapper/912:25:4511
2735199181cyclictest0-21swapper/912:25:4511
2735199181cyclictest0-21swapper/912:20:1411
2735199181cyclictest0-21swapper/912:11:1411
2735199181cyclictest0-21swapper/912:08:1711
2735199181cyclictest0-21swapper/911:30:1411
2735199181cyclictest0-21swapper/911:26:2611
2735199181cyclictest0-21swapper/911:26:2611
2735199181cyclictest0-21swapper/910:54:5211
2735199181cyclictest0-21swapper/910:40:1411
2735199181cyclictest0-21swapper/910:05:2311
2735199181cyclictest0-21swapper/909:51:3911
2735199181cyclictest0-21swapper/909:20:3911
2735199181cyclictest0-21swapper/908:54:0711
2735199181cyclictest0-21swapper/907:45:2111
27348991816cyclictest27066-21qemu-kvm07:30:008
27348991816cyclictest27066-21qemu-kvm07:20:118
27348991816cyclictest27059-21qemu-kvm07:15:168
27347991816cyclictest13809-21ssh11:40:517
2733899180cyclictest0-21swapper/210:15:454
2731999183cyclictest0-21swapper/010:25:190
2735899170cyclictest0-21swapper/1110:08:153
27352991716cyclictest5165-21perl07:20:122
27352991715cyclictest17614-21irqstats09:05:202
27352991715cyclictest17614-21irqstats09:05:202
2735299170cyclictest991850irq/53-eth0-rx-12:30:202
2735299170cyclictest991850irq/53-eth0-rx-11:35:342
2735299170cyclictest991850irq/53-eth0-rx-11:00:152
2735299170cyclictest991850irq/53-eth0-rx-10:16:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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