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2026-02-25 - 11:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Feb 25, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27332211098sleep90-21swapper/919:05:4011
27356210996sleep30-21swapper/319:05:575
9918501070irq/53-eth0-rx-0-21swapper/119:09:191
991850980irq/53-eth0-rx-0-21swapper/719:09:339
991850980irq/53-eth0-rx-0-21swapper/519:05:197
12850980irq/42-ahci0-21swapper/219:09:234
991850940irq/53-eth0-rx-0-21swapper/419:05:366
991850930irq/53-eth0-rx-0-21swapper/819:08:2410
991850880irq/53-eth0-rx-0-21swapper/1119:07:523
991850840irq/53-eth0-rx-0-21swapper/1019:08:032
119350670irq/18-parport00-21swapper/019:09:330
2737325853sleep60-21swapper/619:06:138
27865993617cyclictest0-21swapper/1122:27:283
27865993617cyclictest0-21swapper/1122:27:283
2786599300cyclictest0-21swapper/1119:17:263
2783399290cyclictest0-21swapper/022:16:090
27833992827cyclictest31ksoftirqd/019:23:330
2786499225cyclictest831ksoftirqd/1023:56:272
2786499225cyclictest831ksoftirqd/1000:10:132
2786499225cyclictest831ksoftirqd/1000:05:172
2783399220cyclictest0-21swapper/020:30:070
2785799210cyclictest0-21swapper/319:22:445
2783399216cyclictest15002-21chrt20:15:240
2786599200cyclictest0-21swapper/1121:08:423
2786499203cyclictest831ksoftirqd/1021:20:132
27833992018cyclictest0-21swapper/022:08:300
2783399200cyclictest0-21swapper/021:08:410
27865991918cyclictest0-21swapper/1121:18:393
2786499192cyclictest991850irq/53-eth0-rx-00:32:032
2785799190cyclictest0-21swapper/320:23:535
2783399192cyclictest151rcuc/022:29:240
2783399192cyclictest151rcuc/022:29:240
27833991917cyclictest81792sleep019:25:080
27864991817cyclictest5520-21expr21:50:112
27864991817cyclictest11001-21kworker/10:223:20:012
27864991817cyclictest0-21swapper/1021:19:512
27864991816cyclictest369-21ssh22:38:242
2786499181cyclictest991950irq/54-eth0-tx-00:29:072
2786499181cyclictest991850irq/53-eth0-rx-22:08:072
2786499181cyclictest991850irq/53-eth0-rx-20:13:142
2786499181cyclictest991850irq/53-eth0-rx-00:00:182
2786499181cyclictest831ksoftirqd/1022:23:042
2786499181cyclictest831ksoftirqd/1022:23:042
2786499181cyclictest831ksoftirqd/1000:36:252
2786499181cyclictest12850irq/42-ahci20:08:482
2785799180cyclictest0-21swapper/320:53:155
2785799180cyclictest0-21swapper/319:39:235
2785799180cyclictest0-21swapper/319:39:225
2785799180cyclictest0-21swapper/319:31:185
27833991817cyclictest31ksoftirqd/021:21:260
2783399180cyclictest0-21swapper/021:35:010
27864991716cyclictest29349-21fschecks_count00:20:152
27864991716cyclictest0-21swapper/1021:30:102
27864991716cyclictest0-21swapper/1021:25:242
2786499171cyclictest831ksoftirqd/1021:00:152
2786499170cyclictest991850irq/53-eth0-rx-23:51:042
2786499170cyclictest991850irq/53-eth0-rx-23:45:192
2786499170cyclictest991850irq/53-eth0-rx-23:40:082
2786499170cyclictest991850irq/53-eth0-rx-23:35:212
2786499170cyclictest991850irq/53-eth0-rx-23:15:112
2786499170cyclictest991850irq/53-eth0-rx-23:10:222
2786499170cyclictest991850irq/53-eth0-rx-23:05:472
2786499170cyclictest991850irq/53-eth0-rx-22:55:242
2786499170cyclictest991850irq/53-eth0-rx-22:45:302
2786499170cyclictest991850irq/53-eth0-rx-22:25:262
2786499170cyclictest991850irq/53-eth0-rx-22:25:262
2786499170cyclictest991850irq/53-eth0-rx-22:00:412
2786499170cyclictest991850irq/53-eth0-rx-21:55:572
2786499170cyclictest991850irq/53-eth0-rx-21:46:132
2786499170cyclictest991850irq/53-eth0-rx-20:35:292
2786499170cyclictest991850irq/53-eth0-rx-19:32:402
2786499170cyclictest84202sleep1020:51:402
2786499170cyclictest831ksoftirqd/1023:30:062
2786499170cyclictest831ksoftirqd/1022:30:202
2786499170cyclictest831ksoftirqd/1022:30:202
2786499170cyclictest831ksoftirqd/1022:10:152
2786499170cyclictest831ksoftirqd/1020:40:202
2786499170cyclictest831ksoftirqd/1019:35:142
2786499170cyclictest831ksoftirqd/1019:35:132
2786499170cyclictest65682chrt22:15:372
2786499170cyclictest6102sleep1019:58:222
2786499170cyclictest47872sleep1020:46:502
2786499170cyclictest43292sleep1020:02:342
2786499170cyclictest43292sleep1020:02:332
2786499170cyclictest37112sleep1019:15:532
2786499170cyclictest311142chrt19:10:392
2786499170cyclictest298042sleep1023:00:432
2786499170cyclictest294112chrt19:53:092
2786499170cyclictest294112chrt19:53:082
2786499170cyclictest285762sleep1023:26:102
2786499170cyclictest257212sleep1019:47:452
2786499170cyclictest257212sleep1019:47:442
2786499170cyclictest249392sleep1021:40:102
2786499170cyclictest238352sleep1021:11:292
2786499170cyclictest226852sleep1020:28:372
2786499170cyclictest193482sleep1021:06:172
2786499170cyclictest18812chrt22:40:052
2786499170cyclictest174072sleep1022:50:422
2786499170cyclictest160252chrt20:20:112
2786499170cyclictest152352sleep1020:16:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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