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2026-02-10 - 20:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Feb 10, 2026 12:46:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501090irq/42-ahci0-21swapper/207:08:244
9918501080irq/53-eth0-rx-0-21swapper/107:08:281
2861210791sleep00-21swapper/007:07:120
12850980irq/42-ahci0-21swapper/407:08:156
991850940irq/53-eth0-rx-0-21swapper/707:07:009
991850910irq/53-eth0-rx-0-21swapper/807:05:0310
991850900irq/53-eth0-rx-0-21swapper/507:06:437
991850900irq/53-eth0-rx-0-21swapper/307:06:425
991850880irq/53-eth0-rx-0-21swapper/1107:05:233
280626959sleep60-21swapper/607:06:318
272626861sleep90-21swapper/907:05:3211
285826353sleep100-21swapper/1007:07:112
325699310cyclictest0-21swapper/007:19:130
12850300irq/42-ahci0-21swapper/1107:19:253
3294992423cyclictest172450irq/56-eth1-rx-07:19:259
325699243cyclictest0-21swapper/008:55:020
329899200cyclictest0-21swapper/1109:08:423
325699200cyclictest0-21swapper/008:08:290
325699200cyclictest0-21swapper/008:08:290
329799192cyclictest991850irq/53-eth0-rx-11:51:412
329799192cyclictest991850irq/53-eth0-rx-11:14:512
329799192cyclictest991850irq/53-eth0-rx-10:20:282
329799192cyclictest991850irq/53-eth0-rx-10:08:252
329799192cyclictest991850irq/53-eth0-rx-10:08:242
329799192cyclictest991850irq/53-eth0-rx-09:30:112
3297991918cyclictest0-21swapper/1008:48:452
3297991917cyclictest3670-21kworker/10:212:14:092
329699192cyclictest0-21swapper/908:20:1411
325699190cyclictest0-21swapper/009:08:430
3297991817cyclictest10845-1kworker/10:1H07:24:492
3297991817cyclictest0-21swapper/1012:04:012
3297991817cyclictest0-21swapper/1011:46:092
3297991817cyclictest0-21swapper/1011:26:112
3297991817cyclictest0-21swapper/1011:01:292
3297991817cyclictest0-21swapper/1010:38:222
3297991817cyclictest0-21swapper/1010:13:102
3297991817cyclictest0-21swapper/1010:01:132
3297991816cyclictest30387-21ssh12:21:182
329799181cyclictest991950irq/54-eth0-tx-10:15:042
329799181cyclictest991850irq/53-eth0-rx-12:31:212
329799181cyclictest991850irq/53-eth0-rx-12:06:402
329799181cyclictest991850irq/53-eth0-rx-11:39:512
329799181cyclictest991850irq/53-eth0-rx-11:31:262
329799181cyclictest991850irq/53-eth0-rx-11:23:082
329799181cyclictest991850irq/53-eth0-rx-11:15:112
329799181cyclictest991850irq/53-eth0-rx-11:15:112
329799181cyclictest991850irq/53-eth0-rx-11:06:282
329799181cyclictest991850irq/53-eth0-rx-10:56:452
329799181cyclictest991850irq/53-eth0-rx-10:54:182
329799181cyclictest991850irq/53-eth0-rx-10:40:132
329799181cyclictest991850irq/53-eth0-rx-09:56:452
329799181cyclictest991850irq/53-eth0-rx-09:41:272
329799181cyclictest991850irq/53-eth0-rx-09:24:112
329799181cyclictest991850irq/53-eth0-rx-09:15:042
329799181cyclictest991850irq/53-eth0-rx-07:15:252
329799181cyclictest991850irq/53-eth0-rx-07:12:422
329699181cyclictest0-21swapper/912:28:1111
329699181cyclictest0-21swapper/912:18:1111
329699181cyclictest0-21swapper/911:31:5511
329699181cyclictest0-21swapper/911:10:4911
329699181cyclictest0-21swapper/911:07:0511
329699181cyclictest0-21swapper/911:00:5311
329699181cyclictest0-21swapper/909:44:1111
329699181cyclictest0-21swapper/909:17:1311
329699181cyclictest0-21swapper/909:13:4411
3297991716cyclictest26419-21cstates_1109:35:132
3297991716cyclictest0-21swapper/1012:35:302
3297991716cyclictest0-21swapper/1008:40:102
3297991716cyclictest0-21swapper/1007:59:302
3297991716cyclictest0-21swapper/1007:43:202
329799170cyclictest991950irq/54-eth0-tx-10:30:232
329799170cyclictest991850irq/53-eth0-rx-12:25:112
329799170cyclictest991850irq/53-eth0-rx-12:15:042
329799170cyclictest991850irq/53-eth0-rx-11:55:022
329799170cyclictest991850irq/53-eth0-rx-11:40:072
329799170cyclictest991850irq/53-eth0-rx-10:45:242
329799170cyclictest991850irq/53-eth0-rx-10:25:142
329799170cyclictest991850irq/53-eth0-rx-09:50:112
329799170cyclictest991850irq/53-eth0-rx-09:25:172
329799170cyclictest991850irq/53-eth0-rx-09:10:182
329799170cyclictest991850irq/53-eth0-rx-09:05:242
329799170cyclictest991850irq/53-eth0-rx-09:00:352
329799170cyclictest991850irq/53-eth0-rx-08:30:212
329799170cyclictest991850irq/53-eth0-rx-08:30:212
329799170cyclictest991850irq/53-eth0-rx-08:25:032
329799170cyclictest991850irq/53-eth0-rx-07:54:332
329799170cyclictest991850irq/53-eth0-rx-07:26:462
329799170cyclictest9352chrt07:46:252
329799170cyclictest53522sleep1008:37:422
329799170cyclictest52232sleep1009:45:042
329799170cyclictest266112sleep1008:20:412
329799170cyclictest261852sleep1007:37:242
329799170cyclictest225122sleep1007:32:012
329799170cyclictest201532sleep1008:15:042
329799170cyclictest197872chrt08:55:582
329799170cyclictest192952chrt08:10:272
329799170cyclictest161342sleep1008:50:452
329799170cyclictest12850irq/42-ahci08:05:252
329799170cyclictest12850irq/42-ahci08:05:242
3296991716cyclictest25482-21ssh11:23:3411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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