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2025-12-04 - 11:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Dec 04, 2025 00:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13596210994sleep40-21swapper/419:06:426
13581210896sleep90-21swapper/919:06:3511
13602210794sleep100-21swapper/1019:06:482
122501040irq/42-ahci0-21swapper/319:09:295
122501000irq/42-ahci0-21swapper/119:09:231
12250900irq/42-ahci0-21swapper/219:08:404
12250880irq/42-ahci0-21swapper/719:08:519
1357826757sleep60-21swapper/619:06:318
1357026653sleep00-21swapper/019:06:250
1365626556sleep80-21swapper/819:07:3410
1351725853sleep50-21swapper/519:05:437
1072625753sleep110-21swapper/1119:05:133
14000993318cyclictest0-21swapper/020:17:200
1400099330cyclictest0-21swapper/021:22:410
14037992914cyclictest9016-21turbostat20:30:003
14000992928cyclictest0-21swapper/022:30:080
14000992928cyclictest0-21swapper/019:10:330
14037992813cyclictest51562sleep1120:22:093
14037992726cyclictest0-21swapper/1119:10:293
14000992625cyclictest0-21swapper/020:27:350
14037992510cyclictest16272sleep1120:19:573
14000992524cyclictest0-21swapper/020:23:260
1400099224cyclictest0-21swapper/020:14:450
1400099220cyclictest0-21swapper/022:20:050
1400099220cyclictest0-21swapper/022:20:050
14000992120cyclictest0-21swapper/021:25:260
1403799200cyclictest0-21swapper/1120:30:283
1403799200cyclictest0-21swapper/1120:09:253
1403699192cyclictest3066350irq/52-eth0-rx-20:30:312
14036991817cyclictest0-21swapper/1022:58:112
1403699181cyclictest12250irq/42-ahci21:07:502
1403599181cyclictest21438-1kworker/9:2H20:46:3411
1403599181cyclictest0-21swapper/922:10:1511
14034991816cyclictest983-21snmp_rack3slot922:30:1510
14034991816cyclictest9345-21snmp_easybox.os22:40:2210
14034991816cyclictest5369-21sensors_fan21:50:2610
14034991816cyclictest4278-21ntp_states20:20:2610
14034991816cyclictest3788-21snmp_rack3slot900:02:1410
14034991816cyclictest25045-21users23:45:3010
14034991816cyclictest23039-21perl23:00:1610
14034991816cyclictest22263-21df22:15:1610
14034991816cyclictest18699-21df_inode22:10:1710
14034991816cyclictest18152-21snmp_rack3slot921:25:1310
14034991816cyclictest10388-21df_inode20:30:1410
14000991817cyclictest2391-21nscd22:10:250
14000991814cyclictest0-21swapper/022:30:000
12250180irq/42-ahci0-21swapper/820:16:0110
3066350170irq/52-eth0-rx-0-21swapper/720:15:269
14036991716cyclictest18014-1kworker/10:1H22:47:312
1403699170cyclictest96512chrt21:56:182
1403699170cyclictest8692sleep1020:15:312
1403699170cyclictest75992sleep1019:40:272
1403699170cyclictest65262sleep1022:36:232
1403699170cyclictest44712sleep1020:20:312
1403699170cyclictest3472sleep1023:15:022
1403699170cyclictest321042sleep1023:12:152
1403699170cyclictest3066350irq/52-eth0-rx-23:50:222
1403699170cyclictest3066350irq/52-eth0-rx-23:30:282
1403699170cyclictest3066350irq/52-eth0-rx-23:28:272
1403699170cyclictest3066350irq/52-eth0-rx-22:25:132
1403699170cyclictest3066350irq/52-eth0-rx-21:50:292
1403699170cyclictest3066350irq/52-eth0-rx-21:45:262
1403699170cyclictest3066350irq/52-eth0-rx-21:41:402
1403699170cyclictest3066350irq/52-eth0-rx-21:30:132
1403699170cyclictest3066350irq/52-eth0-rx-19:45:212
1403699170cyclictest3066350irq/52-eth0-rx-19:25:222
1403699170cyclictest3066350irq/52-eth0-rx-19:20:222
1403699170cyclictest3066350irq/52-eth0-rx-19:15:282
1403699170cyclictest3066350irq/52-eth0-rx-00:35:152
1403699170cyclictest3066350irq/52-eth0-rx-00:25:212
1403699170cyclictest3066350irq/52-eth0-rx-00:15:202
1403699170cyclictest3066350irq/52-eth0-rx-00:10:062
1403699170cyclictest3066350irq/52-eth0-rx-00:05:222
1403699170cyclictest279052sleep1022:20:332
1403699170cyclictest279052sleep1022:20:322
1403699170cyclictest274562chrt21:36:162
1403699170cyclictest273182sleep1020:10:062
1403699170cyclictest241122sleep1020:50:112
1403699170cyclictest228362sleep1020:01:172
1403699170cyclictest196092sleep1020:40:322
1403699170cyclictest194222chrt19:59:412
1403699170cyclictest182702sleep1000:21:222
1403699170cyclictest182142sleep1021:25:152
1403699170cyclictest179672chrt23:37:422
1403699170cyclictest17592sleep1021:01:002
1403699170cyclictest169532sleep1022:05:552
1403699170cyclictest165262sleep1021:21:032
1403699170cyclictest154802sleep1019:50:412
1403699170cyclictest154802sleep1019:50:402
1403699170cyclictest147982sleep1022:50:132
1403699170cyclictest132702sleep1022:00:542
1403699170cyclictest12250irq/42-ahci23:45:342
1403699170cyclictest12250irq/42-ahci23:06:312
1403699170cyclictest12250irq/42-ahci23:01:092
1403699170cyclictest12250irq/42-ahci22:41:132
1403699170cyclictest12250irq/42-ahci22:10:102
1403699170cyclictest12250irq/42-ahci21:20:002
1403699170cyclictest12250irq/42-ahci21:10:122
1403699170cyclictest12250irq/42-ahci20:59:402
1403699170cyclictest12250irq/42-ahci20:47:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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