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2026-02-03 - 06:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Feb 03, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501140irq/42-ahci0-21swapper/219:09:144
9918501090irq/53-eth0-rx-0-21swapper/419:05:336
128501060irq/42-ahci0-21swapper/119:09:291
10674210391sleep60-21swapper/619:08:018
10538210190sleep110-21swapper/1119:06:183
991850930irq/53-eth0-rx-0-21swapper/519:05:437
991850920irq/53-eth0-rx-0-21swapper/319:05:315
991850910irq/53-eth0-rx-0-21swapper/719:07:139
991850880irq/53-eth0-rx-0-21swapper/919:08:5811
1066228577sleep100-21swapper/1019:07:532
1060726757sleep00-21swapper/019:07:070
991850640irq/53-eth0-rx-0-21swapper/819:05:2510
1102499370cyclictest0-21swapper/1122:14:303
1098299370cyclictest0-21swapper/022:15:230
11024993433cyclictest0-21swapper/1121:26:563
1102499310cyclictest19864-21chrt22:16:033
1102499310cyclictest0-21swapper/1119:20:323
10982993014cyclictest0-21swapper/020:26:100
1098299270cyclictest13584-21chrt22:10:260
11024992611cyclictest10073-21turbostat22:10:003
1098299238cyclictest2345-21lldpd20:12:450
1098299237cyclictest22268-21nscd21:10:240
11024992018cyclictest0-21swapper/1121:08:223
10982992018cyclictest0-21swapper/021:08:220
1098299200cyclictest23726-21turbostat20:10:010
1102499190cyclictest0-21swapper/1120:08:443
1102399192cyclictest991850irq/53-eth0-rx-23:01:072
1102399192cyclictest991850irq/53-eth0-rx-22:30:032
1102399192cyclictest991850irq/53-eth0-rx-22:19:342
1102399192cyclictest991850irq/53-eth0-rx-22:09:232
1102399192cyclictest991850irq/53-eth0-rx-21:50:442
1102399192cyclictest991850irq/53-eth0-rx-21:49:542
1102399192cyclictest991850irq/53-eth0-rx-00:28:492
1102399192cyclictest131342sleep1020:38:272
1102299192cyclictest0-21swapper/900:27:0011
1102299191cyclictest761ksoftirqd/920:25:1411
1098299190cyclictest0-21swapper/019:26:070
11023991817cyclictest25001-21sh23:42:362
11023991817cyclictest0-21swapper/1022:37:252
11023991817cyclictest0-21swapper/1022:37:252
11023991817cyclictest0-21swapper/1022:01:412
11023991817cyclictest0-21swapper/1020:50:382
11023991817cyclictest0-21swapper/1000:36:362
11023991816cyclictest6238-1kworker/10:2H00:03:112
1102399181cyclictest991950irq/54-eth0-tx-23:17:262
1102399181cyclictest991950irq/54-eth0-tx-22:45:242
1102399181cyclictest991950irq/54-eth0-tx-21:20:452
1102399181cyclictest991950irq/54-eth0-tx-21:12:412
1102399181cyclictest991850irq/53-eth0-rx-23:45:222
1102399181cyclictest991850irq/53-eth0-rx-23:38:052
1102399181cyclictest991850irq/53-eth0-rx-23:30:042
1102399181cyclictest991850irq/53-eth0-rx-23:25:392
1102399181cyclictest991850irq/53-eth0-rx-23:12:412
1102399181cyclictest991850irq/53-eth0-rx-23:06:022
1102399181cyclictest991850irq/53-eth0-rx-22:56:422
1102399181cyclictest991850irq/53-eth0-rx-22:50:282
1102399181cyclictest991850irq/53-eth0-rx-22:50:282
1102399181cyclictest991850irq/53-eth0-rx-22:43:422
1102399181cyclictest991850irq/53-eth0-rx-22:26:542
1102399181cyclictest991850irq/53-eth0-rx-22:26:542
1102399181cyclictest991850irq/53-eth0-rx-22:22:072
1102399181cyclictest991850irq/53-eth0-rx-22:11:312
1102399181cyclictest991850irq/53-eth0-rx-21:43:212
1102399181cyclictest991850irq/53-eth0-rx-21:35:132
1102399181cyclictest991850irq/53-eth0-rx-21:34:072
1102399181cyclictest991850irq/53-eth0-rx-21:26:132
1102399181cyclictest991850irq/53-eth0-rx-21:18:432
1102399181cyclictest991850irq/53-eth0-rx-19:39:572
1102399181cyclictest991850irq/53-eth0-rx-00:31:472
1102399181cyclictest991850irq/53-eth0-rx-00:22:512
1102399181cyclictest991850irq/53-eth0-rx-00:16:412
1102399181cyclictest12850irq/42-ahci23:50:482
1102299181cyclictest8315-21ssh21:13:5911
1102299181cyclictest761ksoftirqd/923:55:1711
1102299181cyclictest761ksoftirqd/921:51:4011
1102299181cyclictest761ksoftirqd/921:31:2711
1102299181cyclictest761ksoftirqd/921:00:1611
1102299181cyclictest761ksoftirqd/900:23:2111
1102299181cyclictest7528-21munin-node19:45:1911
1102299181cyclictest5035-21munin-node19:40:2711
1102299181cyclictest3444-21ssh22:56:5811
1102299181cyclictest30231-21ssh22:52:4611
1102299181cyclictest30231-21ssh22:52:4611
1102299181cyclictest28194-21ssh21:55:5411
1102299181cyclictest24883-21sh23:42:2411
1102299181cyclictest23084-21snmp_rack3slot922:20:1311
1102299181cyclictest19074-21python20:00:2311
1102299181cyclictest18529-21ssh21:49:5311
1102299181cyclictest17120-21expr19:15:1711
1102299181cyclictest13568-21load23:05:1711
1102299181cyclictest12628-21ssh22:38:1211
1102299181cyclictest12628-21ssh22:38:1111
1102299181cyclictest0-21swapper/923:50:0711
1102299181cyclictest0-21swapper/923:45:1411
1102299181cyclictest0-21swapper/923:35:1011
1102299181cyclictest0-21swapper/923:32:0611
1102299181cyclictest0-21swapper/923:29:2811
1102299181cyclictest0-21swapper/923:22:2611
1102299181cyclictest0-21swapper/923:18:3611
1102299181cyclictest0-21swapper/923:14:4011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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