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2026-02-23 - 02:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Feb 23, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501140irq/53-eth0-rx-0-21swapper/219:09:574
128501140irq/42-ahci0-21swapper/119:09:531
9918501070irq/53-eth0-rx-0-21swapper/419:05:466
24079210693sleep60-21swapper/619:07:288
12850950irq/42-ahci0-21swapper/319:08:225
991850930irq/53-eth0-rx-0-21swapper/719:07:109
991850910irq/53-eth0-rx-0-21swapper/819:07:0410
2411728575sleep00-21swapper/019:07:580
991850770irq/53-eth0-rx-0-21swapper/519:06:027
2425927674sleep100-21swapper/1019:09:072
2114527565sleep90-21swapper/919:05:0711
2397527062sleep110-21swapper/1119:06:093
2447699192cyclictest991850irq/53-eth0-rx-23:55:042
2447699192cyclictest991850irq/53-eth0-rx-23:55:042
2447699192cyclictest991850irq/53-eth0-rx-21:42:592
2447699192cyclictest991850irq/53-eth0-rx-21:30:532
2447299192cyclictest0-21swapper/923:27:5611
2447299192cyclictest0-21swapper/922:48:1511
2447299192cyclictest0-21swapper/921:40:1511
24441991917cyclictest17918-21turbostat22:30:004
2442799190cyclictest0-21swapper/021:13:070
24476991817cyclictest17779-1kworker/10:0H19:17:272
24476991817cyclictest0-21swapper/1023:10:572
24476991817cyclictest0-21swapper/1023:00:522
24476991817cyclictest0-21swapper/1022:38:362
24476991817cyclictest0-21swapper/1022:18:222
24476991817cyclictest0-21swapper/1021:58:542
24476991817cyclictest0-21swapper/1021:15:292
24476991817cyclictest0-21swapper/1021:09:442
24476991817cyclictest0-21swapper/1021:09:442
24476991817cyclictest0-21swapper/1000:23:522
24476991816cyclictest8862-21perl23:40:142
24476991816cyclictest7879-21ssh00:31:002
24476991816cyclictest32162-21ssh23:33:012
24476991816cyclictest22358-21ssh00:17:012
2447699181cyclictest991950irq/54-eth0-tx-23:53:102
2447699181cyclictest991950irq/54-eth0-tx-23:45:232
2447699181cyclictest991950irq/54-eth0-tx-23:45:232
2447699181cyclictest991950irq/54-eth0-tx-23:16:102
2447699181cyclictest991950irq/54-eth0-tx-22:50:352
2447699181cyclictest991950irq/54-eth0-tx-21:50:122
2447699181cyclictest991950irq/54-eth0-tx-21:38:412
2447699181cyclictest991950irq/54-eth0-tx-00:06:542
2447699181cyclictest991850irq/53-eth0-rx-23:06:252
2447699181cyclictest991850irq/53-eth0-rx-22:57:192
2447699181cyclictest991850irq/53-eth0-rx-22:40:242
2447699181cyclictest991850irq/53-eth0-rx-22:28:212
2447699181cyclictest991850irq/53-eth0-rx-21:45:432
2447699181cyclictest991850irq/53-eth0-rx-21:28:172
2447699181cyclictest991850irq/53-eth0-rx-21:10:052
2447699181cyclictest991850irq/53-eth0-rx-21:00:262
2447699181cyclictest991850irq/53-eth0-rx-19:13:482
2447699181cyclictest991850irq/53-eth0-rx-00:35:392
2447699181cyclictest991850irq/53-eth0-rx-00:26:452
2447699181cyclictest991850irq/53-eth0-rx-00:12:012
2447699181cyclictest991850irq/53-eth0-rx-00:12:012
2447699181cyclictest991850irq/53-eth0-rx-00:01:482
2447699181cyclictest991850irq/53-eth0-rx-00:01:482
2447699181cyclictest12850irq/42-ahci23:38:382
2447699181cyclictest12850irq/42-ahci19:36:462
2447699180cyclictest991850irq/53-eth0-rx-22:01:332
2447299181cyclictest991850irq/53-eth0-rx-22:33:3611
2447299181cyclictest741rcuc/919:31:2011
2447299181cyclictest0-21swapper/923:41:3711
2447299181cyclictest0-21swapper/923:10:1711
2447299181cyclictest0-21swapper/923:03:0011
2447299181cyclictest0-21swapper/922:58:3611
2447299181cyclictest0-21swapper/922:35:1611
2447299181cyclictest0-21swapper/922:20:4911
2447299181cyclictest0-21swapper/922:09:2011
2447299181cyclictest0-21swapper/919:19:4311
2447299181cyclictest0-21swapper/900:27:4611
2447299181cyclictest0-21swapper/900:12:0711
2447299181cyclictest0-21swapper/900:12:0711
2447299181cyclictest0-21swapper/900:07:0811
2447299181cyclictest0-21swapper/900:01:5711
2447299181cyclictest0-21swapper/900:01:5711
24477991716cyclictest0-21swapper/1122:25:203
2447699170cyclictest991950irq/54-eth0-tx-23:20:232
2447699170cyclictest991850irq/53-eth0-rx-23:25:222
2447699170cyclictest991850irq/53-eth0-rx-22:45:022
2447699170cyclictest991850irq/53-eth0-rx-22:30:062
2447699170cyclictest991850irq/53-eth0-rx-22:20:282
2447699170cyclictest991850irq/53-eth0-rx-22:10:032
2447699170cyclictest991850irq/53-eth0-rx-21:20:172
2447699170cyclictest991850irq/53-eth0-rx-20:45:292
2447699170cyclictest991850irq/53-eth0-rx-19:51:462
2447699170cyclictest991850irq/53-eth0-rx-19:30:142
2447699170cyclictest991850irq/53-eth0-rx-19:25:342
2447699170cyclictest87252sleep1020:57:202
2447699170cyclictest831ksoftirqd/1019:22:462
2447699170cyclictest82702sleep1020:12:262
2447699170cyclictest50582chrt20:51:552
2447699170cyclictest44232sleep1020:05:382
2447699170cyclictest311022sleep1020:00:142
2447699170cyclictest288342sleep1020:40:182
2447699170cyclictest268562sleep1019:55:132
2447699170cyclictest264012sleep1020:35:532
2447699170cyclictest221812sleep1019:45:592
2447699170cyclictest199472sleep1022:05:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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