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2026-03-03 - 15:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Mar 03, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501320irq/42-ahci0-21swapper/107:09:211
128501320irq/42-ahci0-21swapper/107:09:201
6978210693sleep80-21swapper/807:06:0810
6978210693sleep80-21swapper/807:06:0710
12850970irq/42-ahci0-21swapper/307:08:275
12850970irq/42-ahci0-21swapper/307:08:265
991850960irq/53-eth0-rx-0-21swapper/407:08:006
991850960irq/53-eth0-rx-0-21swapper/407:07:596
732329489sleep70-21swapper/707:09:549
732329489sleep70-21swapper/707:09:549
991850920irq/53-eth0-rx-0-21swapper/207:06:564
991850920irq/53-eth0-rx-0-21swapper/207:06:564
991850890irq/53-eth0-rx-0-21swapper/1007:06:072
991850890irq/53-eth0-rx-0-21swapper/1007:06:062
991850850irq/53-eth0-rx-0-21swapper/507:06:007
991850850irq/53-eth0-rx-0-21swapper/507:05:597
991850660irq/53-eth0-rx-0-21swapper/907:07:0311
991850660irq/53-eth0-rx-0-21swapper/907:07:0211
712126662sleep110-21swapper/1107:07:593
712126662sleep110-21swapper/1107:07:583
711026654sleep00-21swapper/007:07:480
711026654sleep00-21swapper/007:07:470
694826253sleep60-21swapper/607:05:428
694826253sleep60-21swapper/607:05:418
7475993831cyclictest0-21swapper/1110:09:573
7475993831cyclictest0-21swapper/1110:09:563
7473993029cyclictest991950irq/54-eth0-tx-10:19:5711
747599290cyclictest0-21swapper/1110:10:023
747599290cyclictest0-21swapper/1108:19:233
7452992928cyclictest991950irq/54-eth0-tx-10:19:541
747599280cyclictest26962-21ssh10:24:363
7460992827cyclictest991850irq/53-eth0-rx-10:20:004
744099270cyclictest0-21swapper/010:14:030
747599260cyclictest0-21swapper/1110:29:273
747599260cyclictest0-21swapper/1110:29:263
7474992518cyclictest991850irq/53-eth0-rx-10:19:582
7468992524cyclictest991850irq/53-eth0-rx-10:19:576
744099249cyclictest0-21swapper/010:15:250
14050230irq/18-ehci_hcd0-21swapper/010:30:200
747599220cyclictest0-21swapper/1110:15:523
991950190irq/54-eth0-tx-0-21swapper/010:28:070
991950190irq/54-eth0-tx-0-21swapper/010:28:060
747599190cyclictest0-21swapper/1108:08:293
747499192cyclictest991850irq/53-eth0-rx-12:37:292
747499192cyclictest991850irq/53-eth0-rx-11:51:392
747499192cyclictest991850irq/53-eth0-rx-10:12:162
747499192cyclictest991850irq/53-eth0-rx-09:30:262
747499192cyclictest991850irq/53-eth0-rx-09:10:482
747399192cyclictest0-21swapper/911:16:4311
7472991918cyclictest991850irq/53-eth0-rx-10:19:5410
991850180irq/53-eth0-rx-0-21swapper/010:24:100
7474991817cyclictest0-21swapper/1011:40:072
7474991817cyclictest0-21swapper/1010:37:112
7474991817cyclictest0-21swapper/1010:31:222
7474991817cyclictest0-21swapper/1010:28:172
7474991817cyclictest0-21swapper/1010:28:162
7474991817cyclictest0-21swapper/1010:02:392
7474991817cyclictest0-21swapper/1009:42:392
7474991817cyclictest0-21swapper/1008:19:272
747499181cyclictest991950irq/54-eth0-tx-11:12:332
747499181cyclictest991950irq/54-eth0-tx-09:20:222
747499181cyclictest991950irq/54-eth0-tx-09:19:002
747499181cyclictest991850irq/53-eth0-rx-12:28:382
747499181cyclictest991850irq/53-eth0-rx-12:20:432
747499181cyclictest991850irq/53-eth0-rx-12:12:402
747499181cyclictest991850irq/53-eth0-rx-12:08:292
747499181cyclictest991850irq/53-eth0-rx-12:00:362
747499181cyclictest991850irq/53-eth0-rx-11:55:362
747499181cyclictest991850irq/53-eth0-rx-11:30:272
747499181cyclictest991850irq/53-eth0-rx-11:22:362
747499181cyclictest991850irq/53-eth0-rx-11:05:362
747499181cyclictest991850irq/53-eth0-rx-11:00:372
747499181cyclictest991850irq/53-eth0-rx-10:56:152
747499181cyclictest991850irq/53-eth0-rx-10:50:072
747499181cyclictest991850irq/53-eth0-rx-10:45:012
747499181cyclictest991850irq/53-eth0-rx-10:42:262
747499181cyclictest991850irq/53-eth0-rx-10:42:262
747499181cyclictest991850irq/53-eth0-rx-10:24:572
747499181cyclictest991850irq/53-eth0-rx-09:58:532
747499181cyclictest991850irq/53-eth0-rx-09:47:042
747499181cyclictest991850irq/53-eth0-rx-09:35:592
747499181cyclictest991850irq/53-eth0-rx-09:26:212
747499181cyclictest991850irq/53-eth0-rx-08:35:002
747499181cyclictest811rcuc/1008:27:182
747499181cyclictest12850irq/42-ahci12:15:152
747499181cyclictest12850irq/42-ahci08:50:592
747499181cyclictest12850irq/42-ahci07:30:142
747499181cyclictest12850irq/42-ahci07:25:322
747499181cyclictest115050irq/18-i801_smb11:45:202
747399181cyclictest9637-21rm10:35:1811
747399181cyclictest17985-21ls08:50:1311
747399181cyclictest0-21swapper/912:11:4411
747399181cyclictest0-21swapper/912:07:5511
747399181cyclictest0-21swapper/911:58:3911
747399181cyclictest0-21swapper/911:30:0211
747399181cyclictest0-21swapper/910:30:3911
7469991816cyclictest1812-21ssh09:36:257
7460991816cyclictest2308-21snmpd10:13:004
7474991716cyclictest0-21swapper/1010:05:592
7474991716cyclictest0-21swapper/1010:05:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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