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2026-02-13 - 18:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Feb 13, 2026 12:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501160irq/42-ahci0-21swapper/307:09:085
128501150irq/42-ahci0-21swapper/107:09:131
28644210991sleep00-21swapper/007:05:010
9918501010irq/53-eth0-rx-0-21swapper/407:09:016
128501010irq/42-ahci0-21swapper/207:09:134
991850950irq/53-eth0-rx-0-21swapper/707:08:599
991850920irq/53-eth0-rx-0-21swapper/1007:08:062
3183729286sleep80-21swapper/807:09:1010
991850860irq/53-eth0-rx-0-21swapper/1107:05:023
991850690irq/53-eth0-rx-0-21swapper/507:05:587
3156226553sleep60-21swapper/607:06:208
3155125955sleep90-21swapper/907:06:1111
3203199320cyclictest0-21swapper/008:13:240
32049993028cyclictest0-21swapper/1107:14:383
991850280irq/53-eth0-rx-0-21swapper/508:13:107
991850280irq/53-eth0-rx-0-21swapper/108:13:191
3204099280cyclictest0-21swapper/210:43:514
3203199220cyclictest0-21swapper/007:15:150
3203699210cyclictest0-21swapper/110:52:021
3203199203cyclictest0-21swapper/007:10:260
3204899192cyclictest991850irq/53-eth0-rx-12:35:592
3204899192cyclictest991850irq/53-eth0-rx-12:33:522
3204899192cyclictest991850irq/53-eth0-rx-12:10:182
3204899192cyclictest991850irq/53-eth0-rx-12:00:002
3204899192cyclictest991850irq/53-eth0-rx-11:08:552
3204899192cyclictest991850irq/53-eth0-rx-10:53:502
3204899192cyclictest991850irq/53-eth0-rx-10:35:092
3204899192cyclictest991850irq/53-eth0-rx-10:19:112
3204899192cyclictest991850irq/53-eth0-rx-10:06:552
3204899192cyclictest991850irq/53-eth0-rx-09:56:532
3204799192cyclictest0-21swapper/911:44:3411
3204799192cyclictest0-21swapper/911:44:3411
3204799192cyclictest0-21swapper/910:50:0211
3204799192cyclictest0-21swapper/909:35:1911
32048991817cyclictest0-21swapper/1011:10:592
32048991817cyclictest0-21swapper/1009:16:012
3204899181cyclictest991950irq/54-eth0-tx-11:34:362
3204899181cyclictest991950irq/54-eth0-tx-11:34:362
3204899181cyclictest991950irq/54-eth0-tx-09:25:402
3204899181cyclictest991850irq/53-eth0-rx-12:29:222
3204899181cyclictest991850irq/53-eth0-rx-12:06:292
3204899181cyclictest991850irq/53-eth0-rx-12:04:202
3204899181cyclictest991850irq/53-eth0-rx-11:36:292
3204899181cyclictest991850irq/53-eth0-rx-11:20:132
3204899181cyclictest991850irq/53-eth0-rx-11:17:052
3204899181cyclictest991850irq/53-eth0-rx-10:56:442
3204899181cyclictest991850irq/53-eth0-rx-10:40:302
3204899181cyclictest991850irq/53-eth0-rx-10:27:262
3204899181cyclictest991850irq/53-eth0-rx-10:11:512
3204899181cyclictest991850irq/53-eth0-rx-09:52:392
3204899181cyclictest991850irq/53-eth0-rx-09:35:262
3204899181cyclictest991850irq/53-eth0-rx-09:30:252
3204899181cyclictest991850irq/53-eth0-rx-09:24:062
3204899181cyclictest991850irq/53-eth0-rx-09:13:312
3204899181cyclictest12850irq/42-ahci10:47:312
3204899181cyclictest12850irq/42-ahci10:33:022
3204899181cyclictest12850irq/42-ahci10:23:012
3204899181cyclictest12850irq/42-ahci09:46:552
3204899181cyclictest12850irq/42-ahci09:08:232
3204799181cyclictest761ksoftirqd/908:15:1411
3204799181cyclictest761ksoftirqd/908:15:1411
3204799181cyclictest27151-1kworker/9:1H07:29:4211
3204799181cyclictest12903-21kworker/9:112:30:2311
3204799181cyclictest0-21swapper/912:25:2211
3204799181cyclictest0-21swapper/912:15:1811
3204799181cyclictest0-21swapper/911:57:2611
3204799181cyclictest0-21swapper/911:30:5111
3204799181cyclictest0-21swapper/911:30:5111
3204799181cyclictest0-21swapper/911:01:5211
3204799181cyclictest0-21swapper/910:41:3511
3204799181cyclictest0-21swapper/910:15:5711
3204799181cyclictest0-21swapper/910:05:2211
3204799181cyclictest0-21swapper/909:55:3811
3204799181cyclictest0-21swapper/909:46:2611
3204799181cyclictest0-21swapper/909:42:2711
3204799181cyclictest0-21swapper/909:33:0211
3204799181cyclictest0-21swapper/909:20:2111
3204799181cyclictest0-21swapper/908:34:0811
3204799181cyclictest0-21swapper/908:34:0811
3204799181cyclictest0-21swapper/907:35:0011
32031991816cyclictest0-21swapper/009:08:290
31180ksoftirqd/00-21swapper/011:13:200
32048991716cyclictest20785-1kworker/10:0H10:00:012
32048991716cyclictest0-21swapper/1012:15:132
32048991716cyclictest0-21swapper/1007:35:142
3204899170cyclictest991950irq/54-eth0-tx-11:40:162
3204899170cyclictest991950irq/54-eth0-tx-11:40:162
3204899170cyclictest991850irq/53-eth0-rx-11:50:432
3204899170cyclictest991850irq/53-eth0-rx-11:25:072
3204899170cyclictest991850irq/53-eth0-rx-11:00:032
3204899170cyclictest991850irq/53-eth0-rx-09:40:042
3204899170cyclictest991850irq/53-eth0-rx-08:55:222
3204899170cyclictest991850irq/53-eth0-rx-08:50:132
3204899170cyclictest991850irq/53-eth0-rx-08:25:072
3204899170cyclictest991850irq/53-eth0-rx-08:25:062
3204899170cyclictest991850irq/53-eth0-rx-07:45:112
3204899170cyclictest991850irq/53-eth0-rx-07:40:462
3204899170cyclictest991850irq/53-eth0-rx-07:20:412
3204899170cyclictest89152sleep1008:46:112
3204899170cyclictest83292sleep1008:00:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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