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2026-02-20 - 17:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Feb 20, 2026 12:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501250irq/53-eth0-rx-0-21swapper/807:09:5310
128501070irq/42-ahci0-21swapper/107:08:501
128501050irq/42-ahci0-21swapper/707:08:419
991850990irq/53-eth0-rx-0-21swapper/207:05:134
991850940irq/53-eth0-rx-0-21swapper/307:06:145
991850930irq/53-eth0-rx-0-21swapper/407:05:056
183028984sleep100-21swapper/1007:09:092
991850870irq/53-eth0-rx-0-21swapper/507:07:077
119350740irq/18-parport00-21swapper/907:07:1511
991850670irq/53-eth0-rx-0-21swapper/1107:07:563
150226653sleep00-21swapper/007:05:350
165126556sleep60-21swapper/607:07:308
200399490cyclictest0-21swapper/007:17:180
200399460cyclictest0-21swapper/007:10:020
2048993316cyclictest831ksoftirqd/1012:05:232
2048993215cyclictest831ksoftirqd/1007:16:202
2048992912cyclictest831ksoftirqd/1010:05:362
2048992811cyclictest831ksoftirqd/1009:22:392
2048992710cyclictest831ksoftirqd/1009:13:082
204899258cyclictest831ksoftirqd/1010:12:312
2049992220cyclictest0-21swapper/1108:24:143
204899192cyclictest991850irq/53-eth0-rx-10:55:432
204899192cyclictest831ksoftirqd/1012:25:112
204899192cyclictest831ksoftirqd/1011:49:322
204799192cyclictest0-21swapper/912:21:3311
204799192cyclictest0-21swapper/910:25:2811
204799192cyclictest0-21swapper/910:16:0811
204799192cyclictest0-21swapper/909:35:1111
204499191cyclictest0-21swapper/709:00:029
2048991817cyclictest21856-21smartctl11:15:222
2048991817cyclictest13830-21ssh12:01:212
2048991817cyclictest12-21rcu_preempt11:30:252
2048991817cyclictest0-21swapper/1011:23:312
2048991817cyclictest0-21swapper/1010:49:072
2048991817cyclictest0-21swapper/1009:42:172
2048991817cyclictest0-21swapper/1009:15:022
2048991817cyclictest0-21swapper/1009:15:012
2048991817cyclictest0-21swapper/1007:40:042
2048991817cyclictest0-21swapper/1007:10:202
2048991816cyclictest991850irq/53-eth0-rx-08:15:202
204899181cyclictest991950irq/54-eth0-tx-12:37:562
204899181cyclictest991950irq/54-eth0-tx-10:35:582
204899181cyclictest991950irq/54-eth0-tx-08:30:172
204899181cyclictest991850irq/53-eth0-rx-12:32:422
204899181cyclictest991850irq/53-eth0-rx-12:22:532
204899181cyclictest991850irq/53-eth0-rx-11:57:242
204899181cyclictest991850irq/53-eth0-rx-11:40:082
204899181cyclictest991850irq/53-eth0-rx-11:12:532
204899181cyclictest991850irq/53-eth0-rx-10:32:462
204899181cyclictest831ksoftirqd/1012:15:102
204899181cyclictest831ksoftirqd/1012:14:402
204899181cyclictest831ksoftirqd/1011:50:002
204899181cyclictest831ksoftirqd/1011:27:092
204899181cyclictest831ksoftirqd/1011:09:102
204899181cyclictest831ksoftirqd/1010:53:282
204899181cyclictest831ksoftirqd/1010:25:232
204899181cyclictest831ksoftirqd/1009:50:072
204899181cyclictest831ksoftirqd/1009:46:582
204899181cyclictest831ksoftirqd/1009:30:122
204899181cyclictest831ksoftirqd/1009:30:112
204899181cyclictest831ksoftirqd/1009:25:212
204899181cyclictest831ksoftirqd/1008:25:122
204899181cyclictest12850irq/42-ahci11:35:012
204899181cyclictest12850irq/42-ahci09:08:332
204799181cyclictest991950irq/54-eth0-tx-10:46:4511
204799181cyclictest991950irq/54-eth0-tx-10:05:3511
204799181cyclictest9566-21sed09:20:2511
204799181cyclictest761ksoftirqd/909:40:2411
204799181cyclictest761ksoftirqd/908:40:2011
204799181cyclictest761ksoftirqd/908:39:1711
204799181cyclictest25002-21kworker/9:107:40:1311
204799181cyclictest12850irq/42-ahci07:55:0111
204799181cyclictest12850irq/42-ahci07:30:0711
204799181cyclictest0-21swapper/912:19:4711
204799181cyclictest0-21swapper/912:06:2711
204799181cyclictest0-21swapper/912:00:1911
204799181cyclictest0-21swapper/911:45:2911
204799181cyclictest0-21swapper/911:41:4911
204799181cyclictest0-21swapper/911:14:4811
204799181cyclictest0-21swapper/910:41:3911
204799181cyclictest0-21swapper/910:35:4811
204799181cyclictest0-21swapper/910:30:0011
204799181cyclictest0-21swapper/910:11:4911
204799181cyclictest0-21swapper/909:57:2711
204799181cyclictest0-21swapper/909:51:5611
204199180cyclictest0-21swapper/512:25:257
204999170cyclictest0-21swapper/1107:16:283
204999170cyclictest0-21swapper/1107:10:323
2048991716cyclictest9370-21snmp_rack3slot908:45:122
2048991716cyclictest831ksoftirqd/1009:55:072
2048991716cyclictest831ksoftirqd/1008:10:132
2048991716cyclictest831ksoftirqd/1007:56:142
2048991716cyclictest30620-21snmp_rack3slot907:45:132
2048991716cyclictest0-21swapper/1008:58:582
2048991716cyclictest0-21swapper/1007:35:122
2048991716cyclictest0-21swapper/1007:25:152
2048991715cyclictest2213-21munin-node07:50:182
204899170cyclictest991850irq/53-eth0-rx-10:15:052
204899170cyclictest991850irq/53-eth0-rx-09:35:162
204899170cyclictest991850irq/53-eth0-rx-08:50:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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