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2026-02-03 - 19:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Feb 03, 2026 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501150irq/53-eth0-rx-0-21swapper/207:09:314
30375210996sleep100-21swapper/1007:05:382
30388210894sleep90-21swapper/907:05:4911
9918501020irq/53-eth0-rx-0-21swapper/407:09:086
128501000irq/42-ahci0-21swapper/107:09:381
991850990irq/53-eth0-rx-0-21swapper/807:08:5710
991850940irq/53-eth0-rx-0-21swapper/707:07:279
12850940irq/42-ahci0-21swapper/307:08:255
991850860irq/53-eth0-rx-0-21swapper/507:06:107
991850830irq/53-eth0-rx-0-21swapper/1107:07:013
3040927253sleep00-21swapper/007:06:050
3049526354sleep60-21swapper/607:07:128
30908994314cyclictest0-21swapper/1108:10:463
30853993617cyclictest0-21swapper/008:10:310
3090899310cyclictest0-21swapper/1107:28:433
30853993028cyclictest75082chrt10:20:020
30853992519cyclictest0-21swapper/010:19:540
3090799240cyclictest991850irq/53-eth0-rx-09:39:532
30908992322cyclictest0-21swapper/1110:30:123
30908992322cyclictest0-21swapper/1109:19:243
30890992117cyclictest17563-21ssh09:34:325
30853992120cyclictest0-21swapper/009:13:100
30853992120cyclictest0-21swapper/009:13:090
30890992016cyclictest11838-21ssh11:16:235
30890992014cyclictest7099-21ssh11:13:335
3090799192cyclictest991850irq/53-eth0-rx-12:11:442
3090799192cyclictest991850irq/53-eth0-rx-11:54:202
3090799192cyclictest991850irq/53-eth0-rx-10:53:332
3090799192cyclictest991850irq/53-eth0-rx-10:40:232
3090799192cyclictest991850irq/53-eth0-rx-09:25:162
3090799192cyclictest991850irq/53-eth0-rx-09:17:262
3090699192cyclictest0-21swapper/912:03:5011
3090699192cyclictest0-21swapper/910:01:4111
3090699192cyclictest0-21swapper/909:28:1611
3089999193cyclictest0-21swapper/408:30:156
30890991915cyclictest30858-21ssh12:26:555
30890991915cyclictest30858-21ssh12:26:545
30853991912cyclictest22267-21nscd10:26:520
30853991912cyclictest143032chrt07:29:180
30907991817cyclictest23654-1kworker/10:1H10:33:482
30907991817cyclictest0-21swapper/1012:02:472
30907991817cyclictest0-21swapper/1011:33:212
30907991817cyclictest0-21swapper/1011:19:572
30907991817cyclictest0-21swapper/1010:47:002
30907991817cyclictest0-21swapper/1010:36:112
30907991817cyclictest0-21swapper/1010:25:112
30907991817cyclictest0-21swapper/1007:22:012
3090799181cyclictest991950irq/54-eth0-tx-11:59:382
3090799181cyclictest991950irq/54-eth0-tx-09:43:312
3090799181cyclictest991950irq/54-eth0-tx-09:43:302
3090799181cyclictest991850irq/53-eth0-rx-12:20:392
3090799181cyclictest991850irq/53-eth0-rx-12:16:222
3090799181cyclictest991850irq/53-eth0-rx-12:05:582
3090799181cyclictest991850irq/53-eth0-rx-11:29:472
3090799181cyclictest991850irq/53-eth0-rx-11:13:482
3090799181cyclictest991850irq/53-eth0-rx-11:08:292
3090799181cyclictest991850irq/53-eth0-rx-10:58:412
3090799181cyclictest991850irq/53-eth0-rx-10:21:102
3090799181cyclictest991850irq/53-eth0-rx-10:15:252
3090799181cyclictest991850irq/53-eth0-rx-10:08:412
3090799181cyclictest991850irq/53-eth0-rx-10:02:042
3090799181cyclictest991850irq/53-eth0-rx-09:57:572
3090799181cyclictest991850irq/53-eth0-rx-09:50:342
3090799181cyclictest991850irq/53-eth0-rx-09:20:482
3090799181cyclictest991850irq/53-eth0-rx-09:05:572
3090799181cyclictest12850irq/42-ahci11:43:402
3090799181cyclictest12850irq/42-ahci11:00:402
3090699181cyclictest0-21swapper/911:50:0011
3090699181cyclictest0-21swapper/911:36:1411
3090699181cyclictest0-21swapper/911:32:4211
3090699181cyclictest0-21swapper/911:07:4411
3090699181cyclictest0-21swapper/911:00:2011
3090699181cyclictest0-21swapper/910:44:4711
3090699181cyclictest0-21swapper/910:39:0311
3090699181cyclictest0-21swapper/910:10:2211
3090699181cyclictest0-21swapper/910:06:0511
3090699181cyclictest0-21swapper/909:51:2311
3090699181cyclictest0-21swapper/909:45:3711
3090699181cyclictest0-21swapper/908:45:2011
30902991816cyclictest6540-21ssh10:19:137
30902991816cyclictest26340-21qemu-kvm10:08:417
30890991814cyclictest4134-21ssh11:37:365
30890991814cyclictest25678-21ssh10:07:015
30853991812cyclictest15736-21chrt08:19:250
30907991716cyclictest6238-1kworker/10:2H07:40:262
30907991716cyclictest0-21swapper/1011:20:272
30907991716cyclictest0-21swapper/1008:36:512
3090799170cyclictest991950irq/54-eth0-tx-11:35:242
3090799170cyclictest991950irq/54-eth0-tx-07:36:042
3090799170cyclictest991850irq/53-eth0-rx-12:35:012
3090799170cyclictest991850irq/53-eth0-rx-12:35:012
3090799170cyclictest991850irq/53-eth0-rx-12:31:132
3090799170cyclictest991850irq/53-eth0-rx-12:26:002
3090799170cyclictest991850irq/53-eth0-rx-12:25:592
3090799170cyclictest991850irq/53-eth0-rx-11:45:232
3090799170cyclictest991850irq/53-eth0-rx-10:10:502
3090799170cyclictest991850irq/53-eth0-rx-09:45:102
3090799170cyclictest991850irq/53-eth0-rx-09:30:212
3090799170cyclictest991850irq/53-eth0-rx-08:50:272
3090799170cyclictest991850irq/53-eth0-rx-08:45:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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