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2026-04-27 - 16:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Apr 27, 2026 12:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501050irq/42-ahci0-21swapper/207:09:004
9918501040irq/53-eth0-rx-0-21swapper/107:09:351
9918501010irq/53-eth0-rx-0-21swapper/907:05:1811
17896210191sleep100-21swapper/1007:06:442
991850910irq/53-eth0-rx-0-21swapper/707:07:229
991850900irq/53-eth0-rx-0-21swapper/307:05:175
991850890irq/53-eth0-rx-0-21swapper/507:06:177
172450870irq/56-eth1-rx-0-21swapper/807:05:2810
991850690irq/53-eth0-rx-0-21swapper/407:06:276
991850690irq/53-eth0-rx-0-21swapper/1107:06:123
1789225955sleep60-21swapper/607:06:398
1502525753sleep00-21swapper/007:05:090
18305993127cyclictest0-21swapper/008:30:080
18355993029cyclictest0-21swapper/1108:26:063
1830599300cyclictest0-21swapper/008:19:280
1833499291cyclictest0-21swapper/412:02:296
1835599268cyclictest991850irq/53-eth0-rx-10:18:003
18354992617cyclictest0-21swapper/1012:09:472
18354992416cyclictest14144-21munin-node10:05:232
1834599225cyclictest0-21swapper/808:41:3110
1834499200cyclictest0-21swapper/709:08:429
18343992013cyclictest0-21swapper/609:40:008
18305992017cyclictest0-21swapper/012:31:390
1835499192cyclictest991850irq/53-eth0-rx-12:28:172
1835499192cyclictest991850irq/53-eth0-rx-12:23:192
1835499192cyclictest991850irq/53-eth0-rx-12:03:072
1835499192cyclictest991850irq/53-eth0-rx-11:58:282
1835499192cyclictest991850irq/53-eth0-rx-11:23:062
1835499192cyclictest991850irq/53-eth0-rx-11:04:542
1835499192cyclictest991850irq/53-eth0-rx-10:45:232
1835499192cyclictest991850irq/53-eth0-rx-10:11:292
1835499192cyclictest991850irq/53-eth0-rx-10:11:282
1835499192cyclictest991850irq/53-eth0-rx-09:43:332
1835499192cyclictest991850irq/53-eth0-rx-09:31:102
1835499192cyclictest119982chrt09:36:232
18305991917cyclictest991850irq/53-eth0-rx-09:22:520
1835499182cyclictest991850irq/53-eth0-rx-11:43:392
18354991817cyclictest0-21swapper/1011:17:022
18354991817cyclictest0-21swapper/1010:19:012
18354991817cyclictest0-21swapper/1010:00:132
18354991817cyclictest0-21swapper/1010:00:122
18354991817cyclictest0-21swapper/1008:34:092
1835499181cyclictest991950irq/54-eth0-tx-10:23:372
1835499181cyclictest991950irq/54-eth0-tx-09:16:062
1835499181cyclictest991850irq/53-eth0-rx-12:36:542
1835499181cyclictest991850irq/53-eth0-rx-12:31:152
1835499181cyclictest991850irq/53-eth0-rx-12:13:082
1835499181cyclictest991850irq/53-eth0-rx-11:50:212
1835499181cyclictest991850irq/53-eth0-rx-11:36:402
1835499181cyclictest991850irq/53-eth0-rx-11:32:112
1835499181cyclictest991850irq/53-eth0-rx-11:25:512
1835499181cyclictest991850irq/53-eth0-rx-11:13:492
1835499181cyclictest991850irq/53-eth0-rx-11:08:582
1835499181cyclictest991850irq/53-eth0-rx-10:55:492
1835499181cyclictest991850irq/53-eth0-rx-10:54:102
1835499181cyclictest991850irq/53-eth0-rx-10:39:022
1835499181cyclictest991850irq/53-eth0-rx-10:26:152
1835499181cyclictest991850irq/53-eth0-rx-09:56:422
1835499181cyclictest991850irq/53-eth0-rx-09:50:552
1835499181cyclictest991850irq/53-eth0-rx-09:10:282
1835499181cyclictest234832chrt07:57:132
1835499181cyclictest12850irq/42-ahci07:53:492
1835499180cyclictest12850irq/42-ahci09:46:222
18351991816cyclictest12601-21chrt07:43:2111
1835199181cyclictest31809-1kworker/9:2H09:29:5911
1835199181cyclictest0-21swapper/912:03:1311
1835199181cyclictest0-21swapper/911:46:2111
1835199181cyclictest0-21swapper/911:16:2711
1835199181cyclictest0-21swapper/910:50:4611
1835199181cyclictest0-21swapper/910:42:2011
1835199181cyclictest0-21swapper/910:25:0911
1835199181cyclictest0-21swapper/910:20:1211
1835199181cyclictest0-21swapper/908:06:3511
1834399186cyclictest0-21swapper/611:40:008
18343991816cyclictest5331-21snmp_rack3slot911:46:258
1833499180cyclictest0-21swapper/410:59:026
1832699180cyclictest0-21swapper/310:59:025
18305991816cyclictest991850irq/53-eth0-rx-09:26:000
18305991816cyclictest23909-21ssh10:15:080
18305991816cyclictest223742sleep010:13:180
18305991816cyclictest223742sleep010:13:170
18305991814cyclictest991850irq/53-eth0-rx-09:11:170
18354991716cyclictest57552sleep1008:16:392
18354991716cyclictest0-21swapper/1008:45:182
18354991716cyclictest0-21swapper/1008:01:152
1835499170cyclictest991850irq/53-eth0-rx-12:15:082
1835499170cyclictest991850irq/53-eth0-rx-10:40:032
1835499170cyclictest991850irq/53-eth0-rx-10:30:042
1835499170cyclictest991850irq/53-eth0-rx-09:25:082
1835499170cyclictest991850irq/53-eth0-rx-09:20:452
1835499170cyclictest991850irq/53-eth0-rx-08:42:212
1835499170cyclictest991850irq/53-eth0-rx-08:21:072
1835499170cyclictest991850irq/53-eth0-rx-08:10:302
1835499170cyclictest991850irq/53-eth0-rx-07:35:172
1835499170cyclictest991850irq/53-eth0-rx-07:28:402
1835499170cyclictest53172sleep1007:33:222
1835499170cyclictest33792sleep1009:00:072
1835499170cyclictest320822sleep1008:55:072
1835499170cyclictest298112sleep1008:50:182
1835499170cyclictest273812chrt07:20:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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