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2026-01-26 - 07:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Jan 26, 2026 00:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501150irq/42-ahci0-21swapper/419:05:026
9918501130irq/53-eth0-rx-0-21swapper/319:09:465
9918501090irq/53-eth0-rx-0-21swapper/119:09:361
7649210394sleep100-21swapper/1019:07:432
7479210290sleep110-21swapper/1119:05:303
991850990irq/53-eth0-rx-0-21swapper/219:07:474
783429491sleep70-21swapper/719:09:279
750927967sleep00-21swapper/019:05:550
991850770irq/53-eth0-rx-0-21swapper/519:05:137
785127371sleep90-21swapper/919:09:4211
765826858sleep60-21swapper/619:07:508
594426658sleep80-21swapper/819:05:1610
991950320irq/54-eth0-tx-0-21swapper/022:13:550
12850310irq/42-ahci0-21swapper/022:28:160
8020992827cyclictest0-21swapper/1121:14:363
798599280cyclictest0-21swapper/022:24:470
8020992711cyclictest164392sleep1122:16:403
802099260cyclictest0-21swapper/1122:26:013
7985992613cyclictest0-21swapper/022:15:540
802099250cyclictest0-21swapper/1122:23:193
798599230cyclictest0-21swapper/022:30:040
798599230cyclictest0-21swapper/022:09:050
802099220cyclictest0-21swapper/1122:09:093
802099210cyclictest0-21swapper/1122:30:203
802099210cyclictest0-21swapper/1122:13:273
8019991917cyclictest0-21swapper/1023:03:272
8019991917cyclictest0-21swapper/1021:41:512
7985991918cyclictest0-21swapper/019:25:320
8019991817cyclictest0-21swapper/1022:50:552
8019991817cyclictest0-21swapper/1022:28:232
8019991817cyclictest0-21swapper/1000:34:012
8019991816cyclictest5789-21ssh23:55:572
8019991816cyclictest28262-21df_inode22:00:142
8019991816cyclictest2503-21snmp_rack3slot923:26:372
8019991816cyclictest19609-21kworker/10:122:15:062
8019991816cyclictest19609-21kworker/10:121:52:202
8019991816cyclictest19609-21kworker/10:121:47:322
8019991816cyclictest17357-21snmp_rack3slot922:45:152
8019991816cyclictest1532-21memory20:25:232
8019991816cyclictest1532-21memory20:25:222
8019991816cyclictest0-21swapper/1023:51:112
8019991816cyclictest0-21swapper/1023:51:112
8019991816cyclictest0-21swapper/1022:35:152
8019991816cyclictest0-21swapper/1022:33:402
8019991816cyclictest0-21swapper/1021:30:042
8019991816cyclictest0-21swapper/1021:10:202
8019991816cyclictest0-21swapper/1020:36:182
8019991816cyclictest0-21swapper/1019:30:172
8019991816cyclictest0-21swapper/1019:16:182
8019991816cyclictest0-21swapper/1000:38:482
801899182cyclictest0-21swapper/923:40:2211
801899182cyclictest0-21swapper/923:40:2111
801899182cyclictest0-21swapper/921:15:0411
801899181cyclictest0-21swapper/923:55:5211
801899181cyclictest0-21swapper/923:49:3811
801899181cyclictest0-21swapper/923:49:3711
801899181cyclictest0-21swapper/923:38:2311
801899181cyclictest0-21swapper/923:38:2211
801899181cyclictest0-21swapper/923:34:3211
801899181cyclictest0-21swapper/923:25:2111
801899181cyclictest0-21swapper/923:16:1211
801899181cyclictest0-21swapper/922:22:0411
801899181cyclictest0-21swapper/922:07:4811
801899181cyclictest0-21swapper/921:57:5111
801899181cyclictest0-21swapper/921:50:3811
801899181cyclictest0-21swapper/921:20:4511
801899181cyclictest0-21swapper/921:05:1511
798599183cyclictest0-21swapper/020:25:190
798599183cyclictest0-21swapper/020:25:190
7985991813cyclictest991850irq/53-eth0-rx-21:28:130
7985991811cyclictest0-21swapper/022:35:460
798599180cyclictest0-21swapper/021:18:340
8019991716cyclictest9114-21ssh22:10:202
8019991716cyclictest29210-1kworker/10:1H20:53:442
8019991716cyclictest0-21swapper/1023:44:412
8019991716cyclictest0-21swapper/1023:44:402
8019991716cyclictest0-21swapper/1023:30:242
8019991716cyclictest0-21swapper/1023:20:492
8019991716cyclictest0-21swapper/1023:08:142
8019991716cyclictest0-21swapper/1022:56:222
8019991716cyclictest0-21swapper/1022:43:452
8019991716cyclictest0-21swapper/1022:07:542
8019991716cyclictest0-21swapper/1021:35:552
8019991716cyclictest0-21swapper/1021:25:312
8019991716cyclictest0-21swapper/1021:20:152
8019991716cyclictest0-21swapper/1021:15:312
8019991716cyclictest0-21swapper/1020:45:032
8019991716cyclictest0-21swapper/1020:40:232
8019991716cyclictest0-21swapper/1020:33:072
8019991716cyclictest0-21swapper/1020:33:072
8019991716cyclictest0-21swapper/1020:06:132
8019991716cyclictest0-21swapper/1019:55:042
8019991716cyclictest0-21swapper/1019:44:402
8019991716cyclictest0-21swapper/1000:28:252
8019991716cyclictest0-21swapper/1000:15:052
8019991716cyclictest0-21swapper/1000:08:442
8019991716cyclictest0-21swapper/1000:04:132
8019991715cyclictest4726-21ssh00:23:272
8019991715cyclictest22979-21ssh23:16:202
801899172cyclictest0-21swapper/923:52:0311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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