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2026-04-18 - 05:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Apr 18, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15306210894sleep50-21swapper/519:06:447
9918501050irq/53-eth0-rx-0-21swapper/119:09:381
991850960irq/53-eth0-rx-0-21swapper/319:05:295
991850950irq/53-eth0-rx-0-21swapper/719:05:229
12850940irq/42-ahci0-21swapper/219:08:174
991850920irq/53-eth0-rx-0-21swapper/919:06:0511
12850900irq/42-ahci0-21swapper/819:08:4910
991850880irq/53-eth0-rx-0-21swapper/1019:08:042
12850810irq/42-ahci0-21swapper/419:09:186
1538827566sleep110-21swapper/1119:07:503
1242126553sleep00-21swapper/019:05:030
1532225955sleep60-21swapper/619:06:578
15749992018cyclictest6470-21kworker/11:121:18:473
15749991917cyclictest0-21swapper/1122:19:243
1574899192cyclictest991850irq/53-eth0-rx-23:58:162
1574899192cyclictest991850irq/53-eth0-rx-23:50:142
1574899192cyclictest991850irq/53-eth0-rx-21:49:182
1574899192cyclictest991850irq/53-eth0-rx-00:04:362
1574799192cyclictest0-21swapper/923:20:1011
1574799192cyclictest0-21swapper/923:16:5311
1574799192cyclictest0-21swapper/921:49:2911
1574799192cyclictest0-21swapper/900:00:0111
15724991915cyclictest920-21ssh00:06:335
15724991913cyclictest28168-21ssh21:50:295
15707991914cyclictest0-21swapper/022:19:130
1574899182cyclictest991850irq/53-eth0-rx-00:31:262
15748991817cyclictest0-21swapper/1021:13:072
15748991817cyclictest0-21swapper/1000:15:092
1574899181cyclictest991950irq/54-eth0-tx-22:22:092
1574899181cyclictest991950irq/54-eth0-tx-21:40:452
1574899181cyclictest991850irq/53-eth0-rx-23:19:382
1574899181cyclictest991850irq/53-eth0-rx-23:05:132
1574899181cyclictest991850irq/53-eth0-rx-23:02:242
1574899181cyclictest991850irq/53-eth0-rx-22:58:512
1574899181cyclictest991850irq/53-eth0-rx-22:37:152
1574899181cyclictest991850irq/53-eth0-rx-22:12:512
1574899181cyclictest991850irq/53-eth0-rx-22:00:072
1574899181cyclictest991850irq/53-eth0-rx-21:50:292
1574899181cyclictest991850irq/53-eth0-rx-21:37:062
1574899181cyclictest991850irq/53-eth0-rx-21:28:162
1574899181cyclictest991850irq/53-eth0-rx-21:22:192
1574899181cyclictest991850irq/53-eth0-rx-21:15:162
1574899181cyclictest991850irq/53-eth0-rx-20:36:392
1574899181cyclictest991850irq/53-eth0-rx-00:36:522
1574899181cyclictest991850irq/53-eth0-rx-00:28:282
1574899181cyclictest991850irq/53-eth0-rx-00:14:222
1574799181cyclictest761ksoftirqd/922:00:0911
1574799181cyclictest761ksoftirqd/900:10:2411
1574799181cyclictest5383-21diskmemload00:36:2911
1574799181cyclictest31254-21ssh23:13:0511
1574799181cyclictest31254-21ssh23:13:0411
1574799181cyclictest19597-21ssh23:04:0911
1574799181cyclictest0-21swapper/923:55:1311
1574799181cyclictest0-21swapper/923:44:0411
1574799181cyclictest0-21swapper/923:35:4511
1574799181cyclictest0-21swapper/923:33:1311
1574799181cyclictest0-21swapper/923:06:1711
1574799181cyclictest0-21swapper/922:59:0611
1574799181cyclictest0-21swapper/922:50:0711
1574799181cyclictest0-21swapper/922:45:3811
1574799181cyclictest0-21swapper/922:44:0611
1574799181cyclictest0-21swapper/922:35:2011
1574799181cyclictest0-21swapper/922:30:0711
1574799181cyclictest0-21swapper/922:27:3111
1574799181cyclictest0-21swapper/922:20:1911
1574799181cyclictest0-21swapper/922:15:1211
1574799181cyclictest0-21swapper/922:07:1511
1574799181cyclictest0-21swapper/921:51:0211
1574799181cyclictest0-21swapper/921:40:5611
1574799181cyclictest0-21swapper/921:35:1011
1574799181cyclictest0-21swapper/921:31:5111
1574799181cyclictest0-21swapper/921:22:1811
1574799181cyclictest0-21swapper/921:12:0011
1574799181cyclictest0-21swapper/920:20:2811
1574799181cyclictest0-21swapper/920:16:2611
1574799181cyclictest0-21swapper/920:10:1111
1574799181cyclictest0-21swapper/919:39:2911
1574799181cyclictest0-21swapper/919:39:2911
1574799181cyclictest0-21swapper/919:25:2911
1574799181cyclictest0-21swapper/919:10:1911
1574799181cyclictest0-21swapper/900:33:5411
1574799181cyclictest0-21swapper/900:28:1011
1574799181cyclictest0-21swapper/900:06:0611
1574699180cyclictest0-21swapper/800:10:0110
15744991816cyclictest28329-21qemu-kvm20:21:558
15744991816cyclictest15937-21qemu-kvm22:30:268
15736991816cyclictest15461-21qemu-kvm19:15:127
1570799180cyclictest0-21swapper/023:00:090
15748991716cyclictest0-21swapper/1023:45:552
15748991716cyclictest0-21swapper/1021:05:172
1574899170cyclictest991950irq/54-eth0-tx-00:22:002
1574899170cyclictest991850irq/53-eth0-rx-23:35:272
1574899170cyclictest991850irq/53-eth0-rx-23:30:332
1574899170cyclictest991850irq/53-eth0-rx-23:25:082
1574899170cyclictest991850irq/53-eth0-rx-23:20:122
1574899170cyclictest991850irq/53-eth0-rx-23:10:322
1574899170cyclictest991850irq/53-eth0-rx-23:10:312
1574899170cyclictest991850irq/53-eth0-rx-22:50:202
1574899170cyclictest991850irq/53-eth0-rx-22:40:532
1574899170cyclictest991850irq/53-eth0-rx-22:30:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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