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2026-02-23 - 22:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Feb 23, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501120irq/53-eth0-rx-0-21swapper/207:09:334
20364211098sleep30-21swapper/307:08:005
20302210692sleep10-21swapper/107:07:101
20292210691sleep50-21swapper/507:07:027
9918501040irq/53-eth0-rx-0-21swapper/707:08:599
991850920irq/53-eth0-rx-0-21swapper/1007:06:482
1739429182sleep80-21swapper/807:05:0410
2030528374sleep40-21swapper/407:07:136
2043926563sleep90-21swapper/907:08:1811
2029926357sleep110-21swapper/1107:07:073
2036126253sleep00-21swapper/007:07:570
1960125853sleep60-21swapper/607:05:268
20716993620cyclictest0-21swapper/1110:13:503
20673993213cyclictest991850irq/53-eth0-rx-09:20:010
2067399300cyclictest0-21swapper/007:10:400
2067399290cyclictest0-21swapper/007:18:290
991850280irq/53-eth0-rx-0-21swapper/1007:18:312
20678992827cyclictest12850irq/42-ahci07:10:384
2067399280cyclictest0-21swapper/010:20:250
20713992726cyclictest12850irq/42-ahci07:10:3810
20689992519cyclictest8764-21ssh10:50:575
20689992512cyclictest16773-21ssh10:59:185
20674992524cyclictest991850irq/53-eth0-rx-07:10:411
2071699240cyclictest0-21swapper/1110:22:083
2067399240cyclictest0-21swapper/010:18:080
2071699237cyclictest0-21swapper/1110:16:413
2071699230cyclictest0-21swapper/1110:09:223
2067399230cyclictest0-21swapper/010:30:350
2067399230cyclictest0-21swapper/010:26:450
2067399230cyclictest0-21swapper/010:10:230
2071699220cyclictest0-21swapper/1110:25:183
20673992221cyclictest0-21swapper/009:17:540
2067399220cyclictest0-21swapper/010:09:450
20689992016cyclictest27371-21ssh10:40:205
2071699194cyclictest18576-21taskset09:14:453
2071599192cyclictest991850irq/53-eth0-rx-10:55:562
2071599192cyclictest991850irq/53-eth0-rx-09:34:422
2071499192cyclictest0-21swapper/912:13:2811
2071499192cyclictest0-21swapper/912:13:2811
2071499192cyclictest0-21swapper/910:04:3011
2071499192cyclictest0-21swapper/909:42:4211
20716991817cyclictest991850irq/53-eth0-rx-07:10:333
20715991817cyclictest29608-21ssh09:22:392
20715991817cyclictest0-21swapper/1012:29:092
20715991817cyclictest0-21swapper/1012:03:012
20715991817cyclictest0-21swapper/1010:40:112
20715991817cyclictest0-21swapper/1010:26:122
20715991817cyclictest0-21swapper/1009:27:102
2071599181cyclictest991950irq/54-eth0-tx-12:38:292
2071599181cyclictest991950irq/54-eth0-tx-10:48:272
2071599181cyclictest991950irq/54-eth0-tx-10:13:132
2071599181cyclictest991850irq/53-eth0-rx-12:33:402
2071599181cyclictest991850irq/53-eth0-rx-12:10:072
2071599181cyclictest991850irq/53-eth0-rx-12:10:072
2071599181cyclictest991850irq/53-eth0-rx-11:51:022
2071599181cyclictest991850irq/53-eth0-rx-11:36:342
2071599181cyclictest991850irq/53-eth0-rx-11:24:312
2071599181cyclictest991850irq/53-eth0-rx-11:11:492
2071599181cyclictest991850irq/53-eth0-rx-11:05:312
2071599181cyclictest991850irq/53-eth0-rx-10:31:022
2071599181cyclictest991850irq/53-eth0-rx-10:21:552
2071599181cyclictest991850irq/53-eth0-rx-10:00:492
2071599181cyclictest991850irq/53-eth0-rx-09:40:342
2071599181cyclictest991850irq/53-eth0-rx-07:10:182
2071599181cyclictest811rcuc/1008:01:002
2071599181cyclictest12850irq/42-ahci10:09:422
2071599181cyclictest12850irq/42-ahci09:03:532
2071599181cyclictest12850irq/42-ahci09:03:532
2071499181cyclictest20903-21if_eth009:15:1711
2071499181cyclictest2045-1kworker/9:0H12:40:0111
2071499181cyclictest17540-21ssh12:19:1811
2071499181cyclictest0-21swapper/912:30:5411
2071499181cyclictest0-21swapper/912:28:4211
2071499181cyclictest0-21swapper/911:35:4911
2071499181cyclictest0-21swapper/911:24:1411
2071499181cyclictest0-21swapper/911:06:0911
2071499181cyclictest0-21swapper/910:56:3511
2071499181cyclictest0-21swapper/910:51:0611
2071499181cyclictest0-21swapper/910:42:1911
2071499181cyclictest0-21swapper/910:35:2311
2071499181cyclictest0-21swapper/910:27:5611
2071499181cyclictest0-21swapper/910:10:5711
2071499181cyclictest0-21swapper/909:55:5911
2071499181cyclictest0-21swapper/909:45:1411
2071499181cyclictest0-21swapper/908:57:4911
2071499181cyclictest0-21swapper/908:17:3811
20689991812cyclictest7695-21ssh12:35:555
2067399180cyclictest21432chrt09:25:350
2067399180cyclictest0-21swapper/007:20:040
991950170irq/54-eth0-tx-0-21swapper/309:54:155
20716991715cyclictest0-21swapper/1109:30:403
2071699170cyclictest0-21swapper/1107:30:403
20715991716cyclictest6486-21perl08:15:132
2071599170cyclictest991950irq/54-eth0-tx-11:00:202
2071599170cyclictest991950irq/54-eth0-tx-09:45:102
2071599170cyclictest991950irq/54-eth0-tx-09:10:012
2071599170cyclictest991850irq/53-eth0-rx-12:15:152
2071599170cyclictest991850irq/53-eth0-rx-11:55:272
2071599170cyclictest991850irq/53-eth0-rx-11:45:032
2071599170cyclictest991850irq/53-eth0-rx-11:30:572
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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