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2026-06-20 - 14:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Jun 20, 2026 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15740211196sleep20-21swapper/207:06:194
13670210997sleep90-21swapper/907:05:1411
15839210894sleep80-21swapper/807:07:3710
30549501070irq/53-eth0-rx-0-21swapper/107:05:181
30549501040irq/53-eth0-rx-0-21swapper/307:09:415
15682210495sleep70-21swapper/707:05:369
3054950930irq/53-eth0-rx-0-21swapper/407:08:066
3054950870irq/53-eth0-rx-0-21swapper/1007:07:502
3054950850irq/53-eth0-rx-0-21swapper/507:05:297
3054950680irq/53-eth0-rx-0-21swapper/1107:07:373
1580026754sleep00-21swapper/007:07:050
1575926453sleep60-21swapper/607:06:358
1617599310cyclictest2276-21nscd09:15:110
1617599220cyclictest0-21swapper/007:26:450
1617599220cyclictest0-21swapper/007:26:450
16175992016cyclictest0-21swapper/009:41:550
1621699192cyclictest3054950irq/53-eth0-rx-10:30:232
1621699192cyclictest3054950irq/53-eth0-rx-10:16:352
1621699192cyclictest3054950irq/53-eth0-rx-09:30:412
1621599192cyclictest0-21swapper/912:35:1711
1621599192cyclictest0-21swapper/909:56:4511
1621399195cyclictest0-21swapper/708:31:289
16216991817cyclictest19913-21ssh09:19:352
16216991817cyclictest0-21swapper/1012:25:332
16216991817cyclictest0-21swapper/1011:29:542
16216991817cyclictest0-21swapper/1010:47:022
16216991817cyclictest0-21swapper/1010:36:032
16216991816cyclictest4156-21kworker/10:110:07:102
16216991816cyclictest4156-21kworker/10:110:07:092
16216991816cyclictest0-21swapper/1012:10:152
16216991816cyclictest0-21swapper/1009:25:192
1621699181cyclictest3055050irq/54-eth0-tx-10:21:542
1621699181cyclictest3055050irq/54-eth0-tx-10:21:542
1621699181cyclictest3055050irq/54-eth0-tx-09:55:112
1621699181cyclictest3055050irq/54-eth0-tx-07:15:182
1621699181cyclictest3054950irq/53-eth0-rx-12:36:022
1621699181cyclictest3054950irq/53-eth0-rx-12:00:472
1621699181cyclictest3054950irq/53-eth0-rx-11:59:222
1621699181cyclictest3054950irq/53-eth0-rx-11:52:112
1621699181cyclictest3054950irq/53-eth0-rx-11:40:072
1621699181cyclictest3054950irq/53-eth0-rx-11:23:142
1621699181cyclictest3054950irq/53-eth0-rx-11:19:502
1621699181cyclictest3054950irq/53-eth0-rx-11:12:462
1621699181cyclictest3054950irq/53-eth0-rx-11:06:532
1621699181cyclictest3054950irq/53-eth0-rx-10:12:562
1621699181cyclictest3054950irq/53-eth0-rx-10:01:052
1621699181cyclictest3054950irq/53-eth0-rx-09:52:492
1621699181cyclictest3054950irq/53-eth0-rx-09:46:122
1621699181cyclictest3054950irq/53-eth0-rx-09:40:422
1621699181cyclictest3054950irq/53-eth0-rx-09:39:072
1621699181cyclictest3054950irq/53-eth0-rx-09:24:172
1621699181cyclictest3054950irq/53-eth0-rx-09:10:112
1621699181cyclictest3054950irq/53-eth0-rx-08:30:152
1621699181cyclictest3054950irq/53-eth0-rx-08:17:312
1621699181cyclictest12250irq/42-ahci11:30:252
1621699181cyclictest114150irq/18-i801_smb08:40:222
1621699180cyclictest12250irq/42-ahci11:35:332
1621599181cyclictest545-21ssh12:11:2011
1621599181cyclictest3055050irq/54-eth0-tx-11:59:5011
1621599181cyclictest3055050irq/54-eth0-tx-10:55:1911
1621599181cyclictest3055050irq/54-eth0-tx-10:40:5111
1621599181cyclictest3055050irq/54-eth0-tx-09:39:5211
1621599181cyclictest3054950irq/53-eth0-rx-10:08:1911
1621599181cyclictest3054950irq/53-eth0-rx-10:08:1911
1621599181cyclictest0-21swapper/912:26:1711
1621599181cyclictest0-21swapper/911:43:1311
1621599181cyclictest0-21swapper/911:26:5211
1621599181cyclictest0-21swapper/911:05:0511
1621599181cyclictest0-21swapper/910:31:4811
1621599181cyclictest0-21swapper/910:02:5611
1621599181cyclictest0-21swapper/909:51:0311
1621599181cyclictest0-21swapper/909:32:5611
1621699170cyclictest80612sleep1008:25:112
1621699170cyclictest77572sleep1009:06:152
1621699170cyclictest77572sleep1009:06:152
1621699170cyclictest68362sleep1007:38:182
1621699170cyclictest68362sleep1007:38:182
1621699170cyclictest66222chrt08:20:232
1621699170cyclictest42732sleep1009:03:152
1621699170cyclictest327652sleep1008:56:032
1621699170cyclictest31492sleep1007:32:412
1621699170cyclictest31492sleep1007:32:412
1621699170cyclictest3055050irq/54-eth0-tx-10:25:082
1621699170cyclictest3054950irq/53-eth0-rx-12:30:022
1621699170cyclictest3054950irq/53-eth0-rx-12:21:332
1621699170cyclictest3054950irq/53-eth0-rx-12:15:012
1621699170cyclictest3054950irq/53-eth0-rx-12:05:072
1621699170cyclictest3054950irq/53-eth0-rx-11:45:392
1621699170cyclictest3054950irq/53-eth0-rx-11:00:132
1621699170cyclictest3054950irq/53-eth0-rx-10:55:312
1621699170cyclictest3054950irq/53-eth0-rx-10:50:272
1621699170cyclictest3054950irq/53-eth0-rx-10:40:272
1621699170cyclictest3054950irq/53-eth0-rx-08:35:012
1621699170cyclictest3054950irq/53-eth0-rx-08:05:292
1621699170cyclictest3054950irq/53-eth0-rx-07:51:372
1621699170cyclictest3054950irq/53-eth0-rx-07:25:132
1621699170cyclictest3054950irq/53-eth0-rx-07:25:132
1621699170cyclictest3054950irq/53-eth0-rx-07:20:412
1621699170cyclictest248742sleep1008:00:342
1621699170cyclictest195552sleep1007:11:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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