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2026-06-26 - 23:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Jun 26, 2026 12:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29324211294sleep00-21swapper/007:05:190
30622210793sleep80-21swapper/807:06:5210
122501040irq/42-ahci0-21swapper/107:08:511
3054950990irq/53-eth0-rx-0-21swapper/207:05:254
3090329590sleep90-21swapper/907:09:5311
3054950940irq/53-eth0-rx-0-21swapper/407:05:476
12250930irq/42-ahci0-21swapper/307:07:385
3054950920irq/53-eth0-rx-0-21swapper/707:06:339
3069829079sleep100-21swapper/1007:07:552
3054950900irq/53-eth0-rx-0-21swapper/1107:07:563
3054950870irq/53-eth0-rx-0-21swapper/507:05:087
3053626553sleep60-21swapper/607:05:508
3054950320irq/53-eth0-rx-0-21swapper/309:17:565
3054950320irq/53-eth0-rx-0-21swapper/309:17:555
31080993029cyclictest3055050irq/54-eth0-tx-09:17:549
31080993029cyclictest3055050irq/54-eth0-tx-09:17:539
3055050300irq/54-eth0-tx-0-21swapper/109:17:561
3055050300irq/54-eth0-tx-0-21swapper/109:17:551
31087992928cyclictest3054950irq/53-eth0-rx-09:17:5710
31087992928cyclictest3054950irq/53-eth0-rx-09:17:5610
31059992827cyclictest3054950irq/53-eth0-rx-09:17:566
31059992827cyclictest3054950irq/53-eth0-rx-09:17:566
3054950280irq/53-eth0-rx-0-21swapper/808:11:1110
3054950280irq/53-eth0-rx-0-21swapper/208:11:244
31100992726cyclictest3055050irq/54-eth0-tx-09:18:032
31100992726cyclictest3055050irq/54-eth0-tx-09:18:032
31095992221cyclictest3054950irq/53-eth0-rx-09:17:5411
31095992221cyclictest3054950irq/53-eth0-rx-09:17:5411
31049992221cyclictest3054950irq/53-eth0-rx-09:17:564
31049992221cyclictest3054950irq/53-eth0-rx-09:17:554
3104799200cyclictest24176-21latency_hist10:05:020
3109599192cyclictest0-21swapper/912:07:5511
3109599192cyclictest0-21swapper/910:59:3511
3109599192cyclictest0-21swapper/910:30:2311
3109599192cyclictest0-21swapper/909:20:3611
3109599181cyclictest3054950irq/53-eth0-rx-12:24:5311
3109599181cyclictest0-21swapper/912:39:1311
3109599181cyclictest0-21swapper/912:39:1311
3109599181cyclictest0-21swapper/912:16:1711
3109599181cyclictest0-21swapper/911:40:1911
3109599181cyclictest0-21swapper/911:37:1211
3109599181cyclictest0-21swapper/911:17:3711
3109599181cyclictest0-21swapper/911:12:2511
3109599181cyclictest0-21swapper/910:50:0711
3109599181cyclictest0-21swapper/910:25:5511
3109599181cyclictest0-21swapper/910:19:5211
3109599181cyclictest0-21swapper/910:08:4311
3109599181cyclictest0-21swapper/910:02:3011
3109599181cyclictest0-21swapper/909:30:1611
3109599181cyclictest0-21swapper/909:30:1511
3109599181cyclictest0-21swapper/909:25:4911
3109599181cyclictest0-21swapper/909:25:4811
3109599181cyclictest0-21swapper/908:50:1311
3109599181cyclictest0-21swapper/908:20:2011
3109599181cyclictest0-21swapper/908:10:0111
31049991816cyclictest9770-21ntp_states07:20:214
31049991816cyclictest4287-21snmp_easybox.os10:40:254
31049991816cyclictest24191-21snmp_rack3slot909:10:114
31049991816cyclictest2305-21snmpd08:38:564
3104899181cyclictest0-21swapper/108:20:271
3055050180irq/54-eth0-tx-0-21swapper/911:34:0011
3109599170cyclictest0-21swapper/912:25:3611
3109599170cyclictest0-21swapper/912:10:1411
3109599170cyclictest0-21swapper/911:45:2611
3109599170cyclictest0-21swapper/911:28:3111
3109599170cyclictest0-21swapper/911:09:5611
3109599170cyclictest0-21swapper/911:01:4311
3109599170cyclictest0-21swapper/910:49:3811
3109599170cyclictest0-21swapper/909:54:3311
3109599170cyclictest0-21swapper/908:17:2011
3109599170cyclictest0-21swapper/907:40:1611
3105499171cyclictest0-21swapper/312:25:255
31049991715cyclictest8622-21snmp_rack3slot912:05:484
31049991715cyclictest7234-21munin-run07:20:004
31049991715cyclictest3300-21snmp_rack3slot911:07:124
31049991715cyclictest30128-21df_inode12:25:124
31049991715cyclictest29534-21snmp_rack3slot911:56:344
31049991715cyclictest27579-21irqstats07:45:194
31049991715cyclictest20383-21snmp_rack3slot908:20:134
31048991716cyclictest22938-21diskmemload11:15:331
31048991710cyclictest22938-21diskmemload09:13:431
3104899171cyclictest0-21swapper/112:20:151
3104899171cyclictest0-21swapper/107:35:251
3104799177cyclictest0-21swapper/008:17:230
31095991615cyclictest24447-21ssh11:53:1211
31095991615cyclictest0-21swapper/912:03:3611
31095991615cyclictest0-21swapper/911:20:0911
31095991615cyclictest0-21swapper/909:56:3711
31095991615cyclictest0-21swapper/909:48:3211
31095991615cyclictest0-21swapper/909:41:3111
31095991615cyclictest0-21swapper/909:41:3011
31095991615cyclictest0-21swapper/909:10:5711
31095991615cyclictest0-21swapper/908:57:1011
31095991615cyclictest0-21swapper/907:46:0811
31087991615cyclictest17252-21smartctl07:30:2410
3105999160cyclictest0-21swapper/410:42:126
3105499160cyclictest0-21swapper/310:41:525
3105499160cyclictest0-21swapper/310:15:295
31049991615cyclictest28894-21ssh09:40:184
31049991615cyclictest28894-21ssh09:40:174
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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