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2026-01-31 - 09:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Jan 31, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13156210793sleep80-21swapper/819:07:5010
13100210793sleep10-21swapper/119:07:071
9918501060irq/53-eth0-rx-0-21swapper/419:05:396
128501060irq/42-ahci0-21swapper/219:08:594
12850990irq/42-ahci0-21swapper/319:05:065
991950940irq/54-eth0-tx-0-21swapper/719:07:129
991850930irq/53-eth0-rx-0-21swapper/1019:07:542
991850790irq/53-eth0-rx-0-21swapper/519:06:247
1336127472sleep90-21swapper/919:09:5111
1334327066sleep110-21swapper/1119:09:423
115050630irq/18-i801_smb0-21swapper/019:09:180
1300825955sleep60-21swapper/619:06:018
13524993617cyclictest0-21swapper/1122:27:203
1347599290cyclictest0-21swapper/020:11:080
13475992827cyclictest0-21swapper/021:11:140
1352499220cyclictest0-21swapper/1120:21:273
13523992214cyclictest0-21swapper/1000:06:242
13523992114cyclictest0-21swapper/1023:16:312
13523992114cyclictest0-21swapper/1022:48:482
13523992113cyclictest28757-1kworker/10:2H22:08:242
13523992113cyclictest28374-21ssh21:27:452
13523992113cyclictest11976-21ssh00:23:442
1352399203cyclictest991850irq/53-eth0-rx-22:26:182
13523992014cyclictest28757-1kworker/10:2H22:03:342
13523992014cyclictest0-21swapper/1022:31:322
13523992014cyclictest0-21swapper/1022:18:482
13523992014cyclictest0-21swapper/1000:02:322
13523992013cyclictest30103-21ssh22:23:192
13523992013cyclictest28190-21ssh00:35:372
13523992013cyclictest13481-21ssh23:03:352
13523992013cyclictest13306-21ssh21:41:152
13523992013cyclictest0-21swapper/1023:50:032
13523992013cyclictest0-21swapper/1021:11:142
13523992012cyclictest0-21swapper/1021:59:292
1352499190cyclictest0-21swapper/1121:25:373
13523991914cyclictest0-21swapper/1020:34:242
13523991914cyclictest0-21swapper/1000:29:242
13523991913cyclictest15035-21snmp_rack3slot919:10:132
13523991912cyclictest0-21swapper/1022:53:212
13523991912cyclictest0-21swapper/1022:36:192
13523991911cyclictest0-21swapper/1021:23:192
1347599190cyclictest0-21swapper/019:28:140
13523991817cyclictest0-21swapper/1023:21:062
13523991817cyclictest0-21swapper/1020:35:592
13523991817cyclictest0-21swapper/1000:16:562
13523991816cyclictest15656-21ssh23:31:162
13523991816cyclictest15656-21ssh23:31:152
1352399181cyclictest991950irq/54-eth0-tx-23:40:022
1352399181cyclictest991950irq/54-eth0-tx-23:40:012
1352399181cyclictest991850irq/53-eth0-rx-21:47:132
1352399181cyclictest991850irq/53-eth0-rx-21:34:262
1352299181cyclictest0-21swapper/921:23:5211
1352299181cyclictest0-21swapper/921:05:1011
1352299181cyclictest0-21swapper/919:25:1611
13475991814cyclictest991850irq/53-eth0-rx-21:16:390
1352499173cyclictest0-21swapper/1120:55:173
1352499171cyclictest0-21swapper/1120:18:023
13523991716cyclictest0-21swapper/1000:12:122
1352399170cyclictest991950irq/54-eth0-tx-23:12:422
1352399170cyclictest991850irq/53-eth0-rx-23:45:312
1352399170cyclictest991850irq/53-eth0-rx-23:35:492
1352399170cyclictest991850irq/53-eth0-rx-23:26:392
1352399170cyclictest991850irq/53-eth0-rx-23:26:382
1352399170cyclictest991850irq/53-eth0-rx-23:07:182
1352399170cyclictest991850irq/53-eth0-rx-22:55:002
1352399170cyclictest991850irq/53-eth0-rx-22:11:092
1352399170cyclictest991850irq/53-eth0-rx-20:11:412
1352399170cyclictest991850irq/53-eth0-rx-19:56:302
1352399170cyclictest991850irq/53-eth0-rx-19:44:512
1352399170cyclictest991850irq/53-eth0-rx-00:30:592
1352399170cyclictest7682sleep1020:16:232
1352399170cyclictest75292sleep1020:25:242
1352399170cyclictest52272chrt21:08:402
1352399170cyclictest46292chrt20:22:482
1352399170cyclictest38752sleep1021:35:082
1352399170cyclictest3172sleep1019:32:422
1352399170cyclictest30572sleep1019:35:182
1352399170cyclictest290342sleep1019:26:182
1352399170cyclictest263972chrt20:51:162
1352399170cyclictest258792sleep1020:06:222
1352399170cyclictest253762chrt19:21:042
1352399170cyclictest221812sleep1020:00:572
1352399170cyclictest217902sleep1019:16:532
1352399170cyclictest190842sleep1020:40:502
1352399170cyclictest189602sleep1022:40:162
1352399170cyclictest149582chrt19:51:452
1352399170cyclictest136882sleep1021:15:182
1352399170cyclictest130602sleep1023:56:132
1352399170cyclictest12850irq/42-ahci21:50:262
1352399170cyclictest12850irq/42-ahci19:45:122
1352399170cyclictest11752sleep1021:00:402
1352399170cyclictest11752sleep1021:00:392
1352299170cyclictest0-21swapper/923:54:0611
1352299170cyclictest0-21swapper/922:43:4011
1352299170cyclictest0-21swapper/921:37:3611
1352299170cyclictest0-21swapper/920:08:1211
1352299170cyclictest0-21swapper/900:16:4611
1351399174cyclictest0-21swapper/722:40:019
1351399173cyclictest0-21swapper/722:15:009
13508991715cyclictest5185-21qemu-kvm21:08:397
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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