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2025-12-02 - 03:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Dec 02, 2025 00:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201142121108sleep100-21swapper/1019:07:062
18825210995sleep30-21swapper/319:05:225
20126210594sleep70-21swapper/719:07:159
30663501040irq/52-eth0-rx-0-21swapper/219:05:144
2015829182sleep90-21swapper/919:07:4111
12250910irq/42-ahci0-21swapper/119:08:351
2032428280sleep40-21swapper/419:09:126
2000227363sleep50-21swapper/519:05:367
2031526763sleep80-21swapper/819:09:0410
124050670irq/18-i801_smb0-21swapper/1119:05:273
2002525955sleep00-21swapper/019:05:550
2000325955sleep60-21swapper/619:05:378
2048599330cyclictest0-21swapper/021:30:130
2048799301cyclictest0-21swapper/221:35:304
2052799210cyclictest0-21swapper/1119:26:033
2052799210cyclictest0-21swapper/1119:26:033
2048599210cyclictest0-21swapper/019:30:080
2052799184cyclictest0-21swapper/1119:30:163
2052799180cyclictest0-21swapper/1121:27:193
20526991817cyclictest27318-1kworker/10:1H22:47:292
20526991817cyclictest0-21swapper/1022:15:362
2052699181cyclictest831ksoftirqd/1022:50:152
2052699181cyclictest831ksoftirqd/1022:25:142
2052699181cyclictest831ksoftirqd/1021:45:152
2052699181cyclictest831ksoftirqd/1020:25:322
2052699181cyclictest831ksoftirqd/1000:25:262
2052699181cyclictest811rcuc/1023:15:132
2052699181cyclictest36712chrt19:26:072
2052699181cyclictest36712chrt19:26:072
2052699181cyclictest3066350irq/52-eth0-rx-22:20:282
2052699181cyclictest124050irq/18-i801_smb19:30:312
2052699181cyclictest12250irq/42-ahci23:01:222
2052699181cyclictest120422chrt21:08:062
2052599181cyclictest3066450irq/53-eth0-tx-22:15:1511
2052599181cyclictest0-21swapper/921:40:2311
2052599181cyclictest0-21swapper/920:00:1811
20524991816cyclictest9971-21snmp_rack3slot920:20:1910
20524991816cyclictest9643-21snmp_rack3slot923:15:4910
20524991816cyclictest4371-21perl23:10:1410
20524991816cyclictest32573-21iostat21:35:1910
20524991816cyclictest31932-21snmp_easybox.os20:05:2910
20524991816cyclictest27923-21iostat_ios20:00:2210
20524991816cyclictest25545-21snmp_easybox.os21:25:2610
20524991816cyclictest25080-21snmp_easybox.os23:40:1410
20524991816cyclictest21006-21snmp_easybox.os19:50:2510
20524991816cyclictest20982-21snmp_easybox.os22:50:1110
20524991816cyclictest1702-21snmp_rack3slot920:10:1310
20524991816cyclictest14117-21snmp_rack3slot921:10:1510
20524991816cyclictest1373-21perl00:35:1510
20524991816cyclictest11281-21perl22:35:1710
20524991816cyclictest11065-21snmp_rack3slot921:05:2510
20524991816cyclictest1059-21iostat_ios23:05:2210
20524991816cyclictest10156-21ntp_states19:35:2610
20526991716cyclictest831ksoftirqd/1000:05:132
20526991716cyclictest3066350irq/52-eth0-rx-21:30:162
20526991716cyclictest0-21swapper/1021:55:302
2052699170cyclictest831ksoftirqd/1023:59:002
2052699170cyclictest831ksoftirqd/1022:40:142
2052699170cyclictest831ksoftirqd/1022:10:132
2052699170cyclictest831ksoftirqd/1021:50:312
2052699170cyclictest831ksoftirqd/1021:40:252
2052699170cyclictest831ksoftirqd/1020:55:182
2052699170cyclictest831ksoftirqd/1020:45:152
2052699170cyclictest831ksoftirqd/1020:20:172
2052699170cyclictest831ksoftirqd/1019:35:132
2052699170cyclictest831ksoftirqd/1019:15:162
2052699170cyclictest831ksoftirqd/1000:15:182
2052699170cyclictest831ksoftirqd/1000:00:252
2052699170cyclictest8262sleep1023:05:212
2052699170cyclictest77742sleep1020:15:362
2052699170cyclictest60202sleep1023:10:562
2052699170cyclictest4432sleep1023:50:122
2052699170cyclictest326142sleep1019:24:192
2052699170cyclictest318732sleep1000:31:062
2052699170cyclictest309752sleep1021:35:092
2052699170cyclictest3066350irq/52-eth0-rx-23:40:332
2052699170cyclictest3066350irq/52-eth0-rx-23:35:292
2052699170cyclictest3066350irq/52-eth0-rx-21:10:172
2052699170cyclictest3066350irq/52-eth0-rx-20:50:152
2052699170cyclictest3066350irq/52-eth0-rx-20:10:272
2052699170cyclictest3066350irq/52-eth0-rx-19:10:272
2052699170cyclictest3066350irq/52-eth0-rx-00:12:172
2052699170cyclictest29642sleep1000:35:292
2052699170cyclictest271152chrt22:55:302
2052699170cyclictest265932sleep1021:26:562
2052699170cyclictest252462sleep1019:55:342
2052699170cyclictest246402sleep1000:21:282
2052699170cyclictest233222sleep1022:06:012
2052699170cyclictest205652sleep1023:30:582
2052699170cyclictest195272sleep1020:35:032
2052699170cyclictest188682sleep1022:00:242
2052699170cyclictest178982chrt19:45:332
2052699170cyclictest170102sleep1023:27:102
2052699170cyclictest163992sleep1021:15:072
2052699170cyclictest133912sleep1023:22:222
2052699170cyclictest130282sleep1022:38:182
2052699170cyclictest12250irq/42-ahci22:31:442
2052699170cyclictest12250irq/42-ahci22:31:442
2052699170cyclictest12250irq/42-ahci20:31:192
2052699170cyclictest12250irq/42-ahci20:08:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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