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2026-02-05 - 01:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Feb 05, 2026 00:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22255210795sleep30-21swapper/319:07:295
22166210692sleep70-21swapper/719:06:229
128501010irq/42-ahci0-21swapper/219:08:264
22249210088sleep100-21swapper/1019:07:242
991850990irq/53-eth0-rx-0-21swapper/119:06:011
991850980irq/53-eth0-rx-0-21swapper/519:05:207
991850980irq/53-eth0-rx-0-21swapper/419:05:386
2231429593sleep80-21swapper/819:08:1010
2225828978sleep60-21swapper/619:07:338
2215627765sleep110-21swapper/1119:06:133
2210926354sleep90-21swapper/919:05:3511
2220825955sleep00-21swapper/019:06:510
2264399192cyclictest991850irq/53-eth0-rx-22:36:162
2264399192cyclictest991850irq/53-eth0-rx-22:20:242
2264399192cyclictest991850irq/53-eth0-rx-21:19:422
2264399192cyclictest991850irq/53-eth0-rx-00:22:202
2264399192cyclictest991850irq/53-eth0-rx-00:18:272
22640991917cyclictest0-21swapper/720:44:559
2260299190cyclictest0-21swapper/020:47:290
2260299190cyclictest0-21swapper/000:26:160
115050190irq/18-i801_smb0-21swapper/020:35:210
22643991817cyclictest22683-21kworker/10:123:39:072
22643991817cyclictest0-21swapper/1023:07:202
22643991817cyclictest0-21swapper/1022:55:112
22643991817cyclictest0-21swapper/1022:50:432
22643991817cyclictest0-21swapper/1022:15:592
22643991817cyclictest0-21swapper/1021:35:212
22643991817cyclictest0-21swapper/1021:21:592
22643991817cyclictest0-21swapper/1020:35:342
22643991817cyclictest0-21swapper/1019:40:192
22643991817cyclictest0-21swapper/1019:33:412
22643991817cyclictest0-21swapper/1000:05:122
22643991816cyclictest9224-21iostat_ios21:00:202
22643991816cyclictest30670-21munin-node23:10:212
2264399181cyclictest991950irq/54-eth0-tx-22:04:142
2264399181cyclictest991950irq/54-eth0-tx-21:41:482
2264399181cyclictest991950irq/54-eth0-tx-00:03:412
2264399181cyclictest991850irq/53-eth0-rx-23:59:382
2264399181cyclictest991850irq/53-eth0-rx-23:50:132
2264399181cyclictest991850irq/53-eth0-rx-23:48:182
2264399181cyclictest991850irq/53-eth0-rx-23:41:432
2264399181cyclictest991850irq/53-eth0-rx-22:45:352
2264399181cyclictest991850irq/53-eth0-rx-22:40:422
2264399181cyclictest991850irq/53-eth0-rx-22:40:412
2264399181cyclictest991850irq/53-eth0-rx-22:30:272
2264399181cyclictest991850irq/53-eth0-rx-22:25:492
2264399181cyclictest991850irq/53-eth0-rx-22:25:482
2264399181cyclictest991850irq/53-eth0-rx-22:12:552
2264399181cyclictest991850irq/53-eth0-rx-22:12:542
2264399181cyclictest991850irq/53-eth0-rx-21:55:242
2264399181cyclictest991850irq/53-eth0-rx-21:51:052
2264399181cyclictest991850irq/53-eth0-rx-21:47:292
2264399181cyclictest991850irq/53-eth0-rx-21:29:042
2264399181cyclictest991850irq/53-eth0-rx-21:11:462
2264399181cyclictest991850irq/53-eth0-rx-21:09:302
2264399181cyclictest991850irq/53-eth0-rx-00:35:372
2264399181cyclictest991850irq/53-eth0-rx-00:30:062
2264399181cyclictest991850irq/53-eth0-rx-00:27:082
2264399181cyclictest991850irq/53-eth0-rx-00:12:482
2264399181cyclictest12850irq/42-ahci22:08:342
2264399181cyclictest12850irq/42-ahci21:30:182
2264399181cyclictest12850irq/42-ahci20:47:292
2264299181cyclictest8657-21ssh23:46:5211
2264299181cyclictest0-21swapper/923:40:2211
2264299181cyclictest0-21swapper/923:00:4411
2264299181cyclictest0-21swapper/922:33:4111
2264299181cyclictest0-21swapper/921:58:3811
2264299181cyclictest0-21swapper/921:27:4511
2264299181cyclictest0-21swapper/919:35:2611
2264299181cyclictest0-21swapper/900:35:1011
22639991816cyclictest20502-21qemu-kvm22:40:518
22639991816cyclictest20502-21qemu-kvm22:40:518
22639991816cyclictest20502-21qemu-kvm22:30:128
22639991816cyclictest20502-21qemu-kvm22:29:118
22639991816cyclictest20502-21qemu-kvm22:29:108
22639991816cyclictest20502-21qemu-kvm22:22:288
22639991816cyclictest20502-21qemu-kvm22:14:098
22639991816cyclictest20502-21qemu-kvm22:14:088
2263999181cyclictest20500-21qemu-kvm22:37:148
2263999180cyclictest11616-21snmp_rack3slot919:35:168
22602991817cyclictest991850irq/53-eth0-rx-21:15:090
22643991716cyclictest29381-1kworker/10:0H23:20:302
22643991716cyclictest0-21swapper/1020:55:142
2264399170cyclictest991950irq/54-eth0-tx-23:15:082
2264399170cyclictest991850irq/53-eth0-rx-23:30:212
2264399170cyclictest991850irq/53-eth0-rx-23:25:102
2264399170cyclictest991850irq/53-eth0-rx-23:00:362
2264399170cyclictest991850irq/53-eth0-rx-20:50:022
2264399170cyclictest991850irq/53-eth0-rx-20:40:222
2264399170cyclictest991850irq/53-eth0-rx-20:30:012
2264399170cyclictest991850irq/53-eth0-rx-20:20:162
2264399170cyclictest991850irq/53-eth0-rx-20:15:282
2264399170cyclictest991850irq/53-eth0-rx-20:00:092
2264399170cyclictest991850irq/53-eth0-rx-19:50:202
2264399170cyclictest991850irq/53-eth0-rx-19:50:192
2264399170cyclictest991850irq/53-eth0-rx-19:45:552
2264399170cyclictest991850irq/53-eth0-rx-19:21:172
2264399170cyclictest991850irq/53-eth0-rx-19:21:162
2264399170cyclictest991850irq/53-eth0-rx-19:13:262
2264399170cyclictest65092chrt20:13:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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