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2025-11-29 - 02:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Nov 29, 2025 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30663501130irq/52-eth0-rx-0-21swapper/219:09:264
9086210793sleep80-21swapper/819:06:3710
30664501050irq/53-eth0-tx-0-21swapper/419:05:176
901429990sleep110-21swapper/1119:05:393
3066350930irq/52-eth0-rx-0-21swapper/119:05:191
932829286sleep30-21swapper/319:09:085
3066350730irq/52-eth0-rx-0-21swapper/719:08:189
907227264sleep90-21swapper/919:06:2511
935126765sleep100-21swapper/1019:09:272
915926253sleep50-21swapper/519:07:337
825225955sleep00-21swapper/019:05:290
623225955sleep60-21swapper/619:05:118
9536993617cyclictest0-21swapper/1122:12:323
9536993314cyclictest0-21swapper/1121:13:203
953699320cyclictest0-21swapper/1121:18:403
953699320cyclictest0-21swapper/1121:18:393
949499320cyclictest0-21swapper/020:15:530
9533992516cyclictest21806-21diskstats23:05:1510
949499210cyclictest0-21swapper/021:20:100
9494992019cyclictest0-21swapper/019:28:050
949499190cyclictest0-21swapper/021:20:010
949499190cyclictest0-21swapper/021:20:000
6199190migration/724495-21munin-node21:40:159
9535991817cyclictest0-21swapper/1021:40:152
953599181cyclictest3066450irq/53-eth0-tx-20:05:262
953599181cyclictest247152chrt00:38:392
953599181cyclictest128352chrt22:51:142
953599181cyclictest12250irq/42-ahci22:27:372
953499181cyclictest19994-21switchtime23:45:2911
953499181cyclictest0-21swapper/923:30:2211
953499181cyclictest0-21swapper/923:00:0111
953499181cyclictest0-21swapper/921:15:1311
953499181cyclictest0-21swapper/921:15:1311
953499181cyclictest0-21swapper/920:45:2511
9533991816cyclictest5062-21snmp_rack3slot921:56:3610
9533991816cyclictest31867-21snmp_easybox.os23:20:1210
9533991816cyclictest30167-21iostat_ios00:00:2110
9533991816cyclictest29797-21iostat_ios23:15:1810
9533991816cyclictest27822-21snmp_rack3slot923:56:5010
9533991816cyclictest27822-21snmp_rack3slot923:56:4910
9533991816cyclictest27381-21snmp_rack3slot923:10:5110
9533991816cyclictest25251-21perl22:25:1410
9533991816cyclictest24938-21snmp_rack3slot921:40:1710
9533991816cyclictest23567-21snmp_rack3slot920:10:1410
9533991816cyclictest22206-21snmp_easybox.os19:25:1110
9533991816cyclictest20199-21perl20:05:1510
9533991816cyclictest17719-21snmp_rack3slot922:15:1410
9533991816cyclictest15627-21iostat_ios23:40:2010
9533991816cyclictest14505-21snmp_rack3slot919:15:1510
9533991816cyclictest13207-21munin-node19:15:0110
9533991816cyclictest13207-21munin-node19:15:0110
9533991816cyclictest12894-21snmp_rack3slot922:52:0210
9533991816cyclictest1173-21snmp_rack3slot920:25:1310
953699170cyclictest0-21swapper/1121:20:123
9535991716cyclictest9365-21python00:15:282
9535991716cyclictest0-21swapper/1022:47:202
953599170cyclictest95472sleep1023:30:322
953599170cyclictest831ksoftirqd/1022:30:302
953599170cyclictest811rcuc/1023:20:132
953599170cyclictest77692sleep1020:31:242
953599170cyclictest64912sleep1000:12:592
953599170cyclictest57382sleep1022:44:032
953599170cyclictest316012sleep1020:20:222
953599170cyclictest31502sleep1021:10:142
953599170cyclictest313752sleep1000:00:482
953599170cyclictest310962sleep1023:16:552
953599170cyclictest3066450irq/53-eth0-tx-20:50:392
953599170cyclictest3066350irq/52-eth0-rx-23:13:252
953599170cyclictest3066350irq/52-eth0-rx-22:10:162
953599170cyclictest3066350irq/52-eth0-rx-21:45:282
953599170cyclictest3066350irq/52-eth0-rx-21:35:252
953599170cyclictest3066350irq/52-eth0-rx-19:57:182
953599170cyclictest296352sleep1021:01:152
953599170cyclictest292642sleep1020:17:232
953599170cyclictest287002sleep1019:31:302
953599170cyclictest277402sleep1023:55:472
953599170cyclictest277402sleep1023:55:472
953599170cyclictest260182sleep1020:57:022
953599170cyclictest250142sleep1019:25:532
953599170cyclictest243752sleep1023:54:232
953599170cyclictest239332sleep1023:08:162
953599170cyclictest235712chrt22:24:242
953599170cyclictest214632chrt19:22:032
953599170cyclictest204452chrt23:45:332
953599170cyclictest197102sleep1022:16:242
953599170cyclictest184332sleep1021:30:302
953599170cyclictest184332sleep1021:30:302
953599170cyclictest176442sleep1020:45:262
953599170cyclictest156192sleep1021:27:062
953599170cyclictest151642sleep1020:43:002
953599170cyclictest14212sleep1021:52:442
953599170cyclictest137142chrt19:15:022
953599170cyclictest136802sleep1000:21:502
953599170cyclictest132992sleep1023:37:092
953599170cyclictest128472sleep1019:11:272
953599170cyclictest128472sleep1019:11:272
953599170cyclictest12250irq/42-ahci23:25:002
953599170cyclictest12250irq/42-ahci22:55:152
953599170cyclictest12250irq/42-ahci22:00:012
953599170cyclictest12250irq/42-ahci20:25:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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