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2026-03-14 - 04:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Mar 14, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9919501130irq/54-eth0-tx-0-21swapper/219:05:224
27765210996sleep80-21swapper/819:05:0910
30577210895sleep100-21swapper/1019:05:592
9918501050irq/53-eth0-rx-0-21swapper/319:09:485
30587210491sleep60-21swapper/619:06:068
9918501010irq/53-eth0-rx-0-21swapper/719:08:289
9918501000irq/53-eth0-rx-0-21swapper/119:09:441
991850920irq/53-eth0-rx-0-21swapper/419:06:006
991850860irq/53-eth0-rx-0-21swapper/519:06:207
991850740irq/53-eth0-rx-0-21swapper/1119:05:083
172450720irq/56-eth1-rx-0-21swapper/919:08:1811
991850620irq/53-eth0-rx-0-21swapper/019:05:460
31086993617cyclictest0-21swapper/1119:22:463
31085993619cyclictest991850irq/53-eth0-rx-19:16:382
3104499330cyclictest0-21swapper/022:28:410
3108699320cyclictest0-21swapper/1121:26:393
3104499320cyclictest0-21swapper/019:16:310
31086993129cyclictest7663-21ssh21:22:373
31077993029cyclictest991850irq/53-eth0-rx-19:16:416
31086992827cyclictest0-21swapper/1120:10:323
3108599192cyclictest991850irq/53-eth0-rx-23:51:572
3108599192cyclictest991850irq/53-eth0-rx-23:12:562
3108599192cyclictest991850irq/53-eth0-rx-22:31:272
3108599192cyclictest991850irq/53-eth0-rx-22:23:022
3108599192cyclictest991850irq/53-eth0-rx-21:19:272
3108599192cyclictest991850irq/53-eth0-rx-00:25:522
3108599192cyclictest991850irq/53-eth0-rx-00:21:562
3108599192cyclictest991850irq/53-eth0-rx-00:15:092
3108499192cyclictest0-21swapper/923:38:5611
3108499192cyclictest0-21swapper/922:52:0811
3108699180cyclictest0-21swapper/1119:28:173
31085991817cyclictest0-21swapper/1023:58:482
31085991817cyclictest0-21swapper/1023:58:472
31085991817cyclictest0-21swapper/1022:00:192
31085991817cyclictest0-21swapper/1021:57:472
31085991817cyclictest0-21swapper/1021:30:082
31085991817cyclictest0-21swapper/1020:50:172
31085991817cyclictest0-21swapper/1000:30:492
31085991816cyclictest21687-21ssh22:53:012
3108599181cyclictest991950irq/54-eth0-tx-23:02:382
3108599181cyclictest991950irq/54-eth0-tx-21:40:362
3108599181cyclictest991850irq/53-eth0-rx-23:45:332
3108599181cyclictest991850irq/53-eth0-rx-23:42:032
3108599181cyclictest991850irq/53-eth0-rx-23:39:072
3108599181cyclictest991850irq/53-eth0-rx-23:30:252
3108599181cyclictest991850irq/53-eth0-rx-23:25:412
3108599181cyclictest991850irq/53-eth0-rx-23:22:032
3108599181cyclictest991850irq/53-eth0-rx-23:19:122
3108599181cyclictest991850irq/53-eth0-rx-23:05:352
3108599181cyclictest991850irq/53-eth0-rx-22:55:492
3108599181cyclictest991850irq/53-eth0-rx-22:35:312
3108599181cyclictest991850irq/53-eth0-rx-22:25:112
3108599181cyclictest991850irq/53-eth0-rx-22:06:312
3108599181cyclictest991850irq/53-eth0-rx-21:50:172
3108599181cyclictest991850irq/53-eth0-rx-21:45:462
3108599181cyclictest991850irq/53-eth0-rx-21:36:262
3108599181cyclictest991850irq/53-eth0-rx-21:27:332
3108599181cyclictest991850irq/53-eth0-rx-21:20:032
3108599181cyclictest991850irq/53-eth0-rx-21:11:242
3108599181cyclictest991850irq/53-eth0-rx-21:00:412
3108599181cyclictest991850irq/53-eth0-rx-00:36:092
3108599181cyclictest991850irq/53-eth0-rx-00:10:442
3108599181cyclictest991850irq/53-eth0-rx-00:10:432
3108599181cyclictest991850irq/53-eth0-rx-00:05:352
3108599181cyclictest991850irq/53-eth0-rx-00:05:352
3108599181cyclictest991850irq/53-eth0-rx-00:00:022
3108599181cyclictest12850irq/42-ahci22:47:332
3108599181cyclictest12850irq/42-ahci22:10:082
3108599181cyclictest12850irq/42-ahci20:47:242
3108599181cyclictest12850irq/42-ahci20:08:552
3108599180cyclictest12850irq/42-ahci19:20:392
3108499181cyclictest761ksoftirqd/923:05:1511
3108499181cyclictest22920-21ssh22:27:2411
3108499181cyclictest0-21swapper/923:01:3811
3108499181cyclictest0-21swapper/922:20:4611
3108499181cyclictest0-21swapper/921:20:0211
3108499181cyclictest0-21swapper/900:29:2111
31044991815cyclictest0-21swapper/022:12:320
3108699170cyclictest0-21swapper/1120:23:163
31085991716cyclictest0-21swapper/1020:35:182
3108599170cyclictest991850irq/53-eth0-rx-22:40:022
3108599170cyclictest991850irq/53-eth0-rx-20:25:552
3108599170cyclictest991850irq/53-eth0-rx-20:25:542
3108599170cyclictest991850irq/53-eth0-rx-20:15:172
3108599170cyclictest991850irq/53-eth0-rx-20:10:202
3108599170cyclictest991850irq/53-eth0-rx-20:01:592
3108599170cyclictest991850irq/53-eth0-rx-19:55:412
3108599170cyclictest991850irq/53-eth0-rx-19:46:572
3108599170cyclictest991850irq/53-eth0-rx-19:40:102
3108599170cyclictest991850irq/53-eth0-rx-19:27:112
3108599170cyclictest991850irq/53-eth0-rx-19:13:082
3108599170cyclictest84322sleep1022:15:202
3108599170cyclictest34972chrt20:40:202
3108599170cyclictest34972chrt20:40:202
3108599170cyclictest296312sleep1019:50:022
3108599170cyclictest293752sleep1020:31:072
3108599170cyclictest212022sleep1019:35:252
3108599170cyclictest159152sleep1019:30:132
3108599170cyclictest152222chrt20:55:452
3108599170cyclictest12850irq/42-ahci21:05:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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