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2026-02-16 - 19:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Feb 16, 2026 12:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26993211094sleep100-21swapper/1007:07:552
26873210995sleep90-21swapper/907:06:1811
26916210795sleep70-21swapper/707:06:529
991850970irq/53-eth0-rx-0-21swapper/207:05:104
2719029792sleep10-21swapper/107:09:471
991850960irq/53-eth0-rx-0-21swapper/407:05:176
12850920irq/42-ahci0-21swapper/307:08:555
12850910irq/42-ahci0-21swapper/807:09:3710
2682829081sleep00-21swapper/007:05:450
991850890irq/53-eth0-rx-0-21swapper/507:06:067
991850880irq/53-eth0-rx-0-21swapper/1107:07:433
2701027868sleep60-21swapper/607:08:038
27363995627cyclictest259482sleep1110:09:543
27363993617cyclictest0-21swapper/1110:10:043
2736399310cyclictest0-21swapper/1107:12:283
27326992827cyclictest0-21swapper/008:19:150
27326992712cyclictest0-21swapper/010:19:150
27326992712cyclictest0-21swapper/010:19:140
2736199251cyclictest0-21swapper/911:21:2411
2736199251cyclictest0-21swapper/910:54:4111
27361992415cyclictest991950irq/54-eth0-tx-11:57:5311
2736199241cyclictest15564-21diskmemload10:26:1411
2736199241cyclictest0-21swapper/910:14:0211
2736199241cyclictest0-21swapper/909:32:3811
2736199240cyclictest0-21swapper/910:56:1211
2736199240cyclictest0-21swapper/909:11:4311
2735799240cyclictest0-21swapper/512:18:577
27361992315cyclictest31584-21ssh11:07:1611
27361992315cyclictest0-21swapper/909:42:4311
2736199231cyclictest0-21swapper/910:01:2511
2736199230cyclictest0-21swapper/911:49:3411
27361992215cyclictest0-21swapper/912:21:3711
2736199221cyclictest0-21swapper/912:07:4611
2736199220cyclictest0-21swapper/911:34:2511
27361992115cyclictest0-21swapper/912:31:1411
2736199210cyclictest19238-1kworker/9:0H10:08:5711
2736199210cyclictest0-21swapper/909:37:4811
2736399205cyclictest991850irq/53-eth0-rx-10:28:583
2736199200cyclictest0-21swapper/911:54:3811
2736299192cyclictest991950irq/54-eth0-tx-12:28:592
2736299192cyclictest991850irq/53-eth0-rx-12:08:372
2736299192cyclictest991850irq/53-eth0-rx-11:58:172
2736299192cyclictest991850irq/53-eth0-rx-10:57:522
2736299192cyclictest991850irq/53-eth0-rx-10:53:502
2736299192cyclictest991850irq/53-eth0-rx-10:11:072
2736299192cyclictest991850irq/53-eth0-rx-09:37:332
2736199192cyclictest0-21swapper/911:11:4211
2732699193cyclictest29571-21chrt10:10:290
2732699191cyclictest0-21swapper/011:26:170
27362991817cyclictest25371-21kworker/10:212:39:542
27362991817cyclictest0-21swapper/1011:00:572
27362991817cyclictest0-21swapper/1009:01:012
27362991817cyclictest0-21swapper/1008:29:162
2736299181cyclictest991950irq/54-eth0-tx-10:06:422
2736299181cyclictest991950irq/54-eth0-tx-09:40:202
2736299181cyclictest991950irq/54-eth0-tx-09:12:082
2736299181cyclictest991850irq/53-eth0-rx-12:30:212
2736299181cyclictest991850irq/53-eth0-rx-12:19:262
2736299181cyclictest991850irq/53-eth0-rx-12:13:562
2736299181cyclictest991850irq/53-eth0-rx-12:01:112
2736299181cyclictest991850irq/53-eth0-rx-11:47:222
2736299181cyclictest991850irq/53-eth0-rx-11:42:152
2736299181cyclictest991850irq/53-eth0-rx-11:37:122
2736299181cyclictest991850irq/53-eth0-rx-11:26:202
2736299181cyclictest991850irq/53-eth0-rx-11:10:322
2736299181cyclictest991850irq/53-eth0-rx-11:05:132
2736299181cyclictest991850irq/53-eth0-rx-10:45:222
2736299181cyclictest991850irq/53-eth0-rx-10:41:012
2736299181cyclictest991850irq/53-eth0-rx-10:37:222
2736299181cyclictest991850irq/53-eth0-rx-10:30:072
2736299181cyclictest991850irq/53-eth0-rx-10:28:202
2736299181cyclictest991850irq/53-eth0-rx-10:20:082
2736299181cyclictest991850irq/53-eth0-rx-10:20:072
2736299181cyclictest991850irq/53-eth0-rx-10:18:532
2736299181cyclictest991850irq/53-eth0-rx-10:18:522
2736299181cyclictest991850irq/53-eth0-rx-10:00:232
2736299181cyclictest991850irq/53-eth0-rx-09:56:352
2736299181cyclictest991850irq/53-eth0-rx-09:31:202
2736299181cyclictest991850irq/53-eth0-rx-09:28:242
2736299181cyclictest991850irq/53-eth0-rx-07:40:242
2736299181cyclictest991850irq/53-eth0-rx-07:40:242
2736299181cyclictest12850irq/42-ahci09:50:372
2736199181cyclictest23922-1kworker/9:1H08:19:2711
2736199181cyclictest13856-21latency_hist12:15:0111
2736199181cyclictest0-21swapper/912:26:5911
2736199181cyclictest0-21swapper/912:11:3811
2736199181cyclictest0-21swapper/911:38:3111
2736199181cyclictest0-21swapper/911:25:5811
2736199181cyclictest0-21swapper/910:47:5211
2736199181cyclictest0-21swapper/910:42:3511
2736199181cyclictest0-21swapper/910:34:0611
2736199181cyclictest0-21swapper/909:53:4511
2736199181cyclictest0-21swapper/909:46:2311
2736199181cyclictest0-21swapper/909:26:0111
2736199181cyclictest0-21swapper/908:31:4111
2736199181cyclictest0-21swapper/908:25:2711
2736199181cyclictest0-21swapper/908:11:0011
2736199181cyclictest0-21swapper/908:01:5111
2734899182cyclictest0-21swapper/309:58:585
27362991716cyclictest4689-1kworker/10:1H07:25:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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