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2026-02-08 - 16:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Feb 08, 2026 12:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501090irq/42-ahci0-21swapper/107:09:321
24000210894sleep50-21swapper/507:06:437
23916210891sleep00-21swapper/007:05:380
23939210794sleep90-21swapper/907:05:5811
991850990irq/53-eth0-rx-0-21swapper/307:05:145
2247829887sleep20-21swapper/207:05:164
991850970irq/53-eth0-rx-0-21swapper/1007:06:342
991850950irq/53-eth0-rx-0-21swapper/407:08:006
991850930irq/53-eth0-rx-0-21swapper/807:07:3310
991850930irq/53-eth0-rx-0-21swapper/707:08:589
2410728172sleep60-21swapper/607:08:088
2397426859sleep110-21swapper/1107:06:253
2445599350cyclictest0-21swapper/1110:09:493
2443799310cyclictest0-21swapper/007:20:030
24446993029cyclictest12850irq/42-ahci07:20:054
2445599290cyclictest0-21swapper/1110:10:023
24455992423cyclictest991850irq/53-eth0-rx-09:24:443
24437992423cyclictest0-21swapper/007:19:490
24437992314cyclictest0-21swapper/007:10:240
2445599212cyclictest991850irq/53-eth0-rx-08:17:293
24452992019cyclictest12850irq/42-ahci07:20:0510
24455991917cyclictest0-21swapper/1107:10:313
2445399192cyclictest741rcuc/909:57:0511
2445399192cyclictest0-21swapper/909:20:3811
24447991918cyclictest991850irq/53-eth0-rx-07:20:075
24442991918cyclictest1808-21ssh09:24:421
24437991915cyclictest991850irq/53-eth0-rx-10:22:450
24454991817cyclictest0-21swapper/1011:07:412
24454991816cyclictest23119-21ssh11:57:502
2445499181cyclictest991950irq/54-eth0-tx-10:37:392
2445499181cyclictest991850irq/53-eth0-rx-12:36:302
2445499181cyclictest991850irq/53-eth0-rx-12:36:302
2445499181cyclictest991850irq/53-eth0-rx-11:04:022
2445499181cyclictest991850irq/53-eth0-rx-10:50:242
2445499181cyclictest991850irq/53-eth0-rx-10:01:372
2445499181cyclictest991850irq/53-eth0-rx-09:54:242
2445499181cyclictest991850irq/53-eth0-rx-09:23:282
2445499181cyclictest991850irq/53-eth0-rx-09:11:222
2445399185cyclictest0-21swapper/912:20:0211
2445399182cyclictest0-21swapper/912:38:3611
2445399182cyclictest0-21swapper/912:38:3611
2445399181cyclictest0-21swapper/912:30:2111
2445399181cyclictest0-21swapper/912:10:1811
2445399181cyclictest0-21swapper/912:05:2311
2445399181cyclictest0-21swapper/911:54:5711
2445399181cyclictest0-21swapper/911:14:4511
2445399181cyclictest0-21swapper/910:52:4111
2445399181cyclictest0-21swapper/910:38:4611
2445399181cyclictest0-21swapper/910:24:1811
2445399181cyclictest0-21swapper/909:52:4811
2445399181cyclictest0-21swapper/909:32:2711
2445399181cyclictest0-21swapper/909:32:2611
24446991816cyclictest2308-21snmpd11:00:474
24446991816cyclictest2308-21snmpd08:52:014
24454991716cyclictest0-21swapper/1008:16:182
24454991715cyclictest20737-21ssh11:28:492
2445499170cyclictest991950irq/54-eth0-tx-12:10:222
2445499170cyclictest991950irq/54-eth0-tx-10:30:552
2445499170cyclictest991850irq/53-eth0-rx-12:33:532
2445499170cyclictest991850irq/53-eth0-rx-12:28:112
2445499170cyclictest991850irq/53-eth0-rx-12:06:002
2445499170cyclictest991850irq/53-eth0-rx-12:00:592
2445499170cyclictest991850irq/53-eth0-rx-11:50:552
2445499170cyclictest991850irq/53-eth0-rx-11:35:052
2445499170cyclictest991850irq/53-eth0-rx-11:30:242
2445499170cyclictest991850irq/53-eth0-rx-10:45:512
2445499170cyclictest991850irq/53-eth0-rx-10:25:302
2445499170cyclictest991850irq/53-eth0-rx-10:16:102
2445499170cyclictest991850irq/53-eth0-rx-10:10:072
2445499170cyclictest991850irq/53-eth0-rx-09:45:362
2445499170cyclictest991850irq/53-eth0-rx-09:40:122
2445499170cyclictest991850irq/53-eth0-rx-09:35:172
2445499170cyclictest991850irq/53-eth0-rx-09:30:072
2445499170cyclictest991850irq/53-eth0-rx-09:30:072
2445499170cyclictest991850irq/53-eth0-rx-09:25:252
2445499170cyclictest991850irq/53-eth0-rx-08:45:262
2445499170cyclictest991850irq/53-eth0-rx-07:40:102
2445499170cyclictest991850irq/53-eth0-rx-07:16:542
2445499170cyclictest89982sleep1011:45:192
2445499170cyclictest87852sleep1008:58:242
2445499170cyclictest81412sleep1008:11:052
2445499170cyclictest74512sleep1011:16:172
2445499170cyclictest70672sleep1010:21:452
2445499170cyclictest60972chrt09:55:062
2445499170cyclictest51072sleep1008:53:002
2445499170cyclictest47962sleep1011:41:312
2445499170cyclictest44722sleep1008:06:302
2445499170cyclictest42462sleep1007:25:032
2445499170cyclictest39222chrt07:20:352
2445499170cyclictest305052chrt10:41:122
2445499170cyclictest294302chrt07:55:282
2445499170cyclictest292192sleep1008:40:222
2445499170cyclictest277022sleep1007:10:362
2445499170cyclictest264992chrt08:37:322
2445499170cyclictest261782chrt09:16:022
2445499170cyclictest261222sleep1007:54:532
2445499170cyclictest227242chrt08:30:572
2445499170cyclictest222772chrt07:47:262
2445499170cyclictest194632sleep1012:21:122
2445499170cyclictest191042sleep1008:26:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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