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2026-04-24 - 06:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Apr 24, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501140irq/53-eth0-rx-0-21swapper/119:06:241
18637210591sleep110-21swapper/1119:05:353
991850990irq/53-eth0-rx-0-21swapper/1019:05:322
991850930irq/53-eth0-rx-0-21swapper/219:05:504
991850920irq/53-eth0-rx-0-21swapper/719:07:089
991850920irq/53-eth0-rx-0-21swapper/419:05:376
991850870irq/53-eth0-rx-0-21swapper/519:07:307
1897328277sleep30-21swapper/319:09:165
991850780irq/53-eth0-rx-0-21swapper/819:06:0710
1670926754sleep00-21swapper/019:05:120
1902726462sleep90-21swapper/919:09:5811
1585026454sleep60-21swapper/619:05:068
991850280irq/53-eth0-rx-0-21swapper/719:30:049
991850280irq/53-eth0-rx-0-21swapper/119:30:021
12850280irq/42-ahci0-21swapper/219:30:064
19176992726cyclictest991850irq/53-eth0-rx-20:21:5511
19126992221cyclictest2745-21runrttasks20:09:540
19126992221cyclictest2745-21runrttasks20:09:540
991850200irq/53-eth0-rx-0-21swapper/019:30:160
1918299200cyclictest0-21swapper/1120:10:013
1918299200cyclictest0-21swapper/1120:09:473
1918299200cyclictest0-21swapper/1120:09:463
1918299200cyclictest0-21swapper/1119:23:153
19168992019cyclictest12-21rcu_preempt20:22:086
19182991917cyclictest1305-21chrt21:26:383
1918299190cyclictest0-21swapper/1120:29:213
1918199192cyclictest991850irq/53-eth0-rx-21:51:342
19181991917cyclictest2158-21kworker/10:223:30:282
1917699192cyclictest0-21swapper/923:52:1311
1917699192cyclictest0-21swapper/923:52:1311
19126991918cyclictest991850irq/53-eth0-rx-21:19:280
115050190irq/18-i801_smb0-21swapper/419:20:196
19181991817cyclictest0-21swapper/1021:58:052
19181991817cyclictest0-21swapper/1020:00:232
19181991816cyclictest31913-21ssh22:18:362
19181991816cyclictest25827-21ssh21:46:122
1918199181cyclictest991950irq/54-eth0-tx-21:33:352
1918199181cyclictest991850irq/53-eth0-rx-22:31:132
1918199181cyclictest991850irq/53-eth0-rx-21:21:182
1918199181cyclictest991850irq/53-eth0-rx-21:18:372
1918199180cyclictest991850irq/53-eth0-rx-21:37:192
1917699181cyclictest31809-1kworker/9:2H20:41:3111
1917699181cyclictest31104-1kworker/9:1H20:01:3511
1917699181cyclictest26722-21kworker/9:123:56:0411
1917699181cyclictest0-21swapper/923:37:0911
1917699181cyclictest0-21swapper/923:37:0911
1917699181cyclictest0-21swapper/923:32:1111
1917699181cyclictest0-21swapper/922:58:1211
1917699181cyclictest0-21swapper/922:49:0911
1917699181cyclictest0-21swapper/922:24:2911
1917699181cyclictest0-21swapper/922:10:0511
1917699181cyclictest0-21swapper/922:02:5711
1917699181cyclictest0-21swapper/921:50:0711
1917699181cyclictest0-21swapper/921:49:2811
1917699181cyclictest0-21swapper/921:29:4011
1917699181cyclictest0-21swapper/900:29:3011
19181991716cyclictest7116-1kworker/10:0H21:08:272
19181991716cyclictest0-21swapper/1019:57:032
19181991716cyclictest0-21swapper/1000:25:062
19181991715cyclictest5368-21perl21:00:132
19181991715cyclictest15983-21ssh22:57:382
1918199170cyclictest991950irq/54-eth0-tx-23:06:002
1918199170cyclictest991950irq/54-eth0-tx-00:06:362
1918199170cyclictest991850irq/53-eth0-rx-23:55:522
1918199170cyclictest991850irq/53-eth0-rx-23:45:112
1918199170cyclictest991850irq/53-eth0-rx-23:45:112
1918199170cyclictest991850irq/53-eth0-rx-23:41:142
1918199170cyclictest991850irq/53-eth0-rx-23:35:062
1918199170cyclictest991850irq/53-eth0-rx-23:35:062
1918199170cyclictest991850irq/53-eth0-rx-22:51:112
1918199170cyclictest991850irq/53-eth0-rx-22:40:202
1918199170cyclictest991850irq/53-eth0-rx-22:21:152
1918199170cyclictest991850irq/53-eth0-rx-22:08:532
1918199170cyclictest991850irq/53-eth0-rx-22:00:232
1918199170cyclictest991850irq/53-eth0-rx-21:40:122
1918199170cyclictest991850irq/53-eth0-rx-21:28:022
1918199170cyclictest991850irq/53-eth0-rx-21:10:152
1918199170cyclictest991850irq/53-eth0-rx-00:35:352
1918199170cyclictest991850irq/53-eth0-rx-00:00:222
1918199170cyclictest97652chrt19:38:012
1918199170cyclictest8692sleep1023:10:392
1918199170cyclictest67792sleep1020:19:182
1918199170cyclictest61792chrt19:33:492
1918199170cyclictest40282sleep1023:15:022
1918199170cyclictest321122chrt20:51:222
1918199170cyclictest321122chrt20:51:212
1918199170cyclictest317522sleep1000:30:122
1918199170cyclictest313302sleep1019:25:012
1918199170cyclictest311352sleep1019:22:232
1918199170cyclictest29112sleep1022:46:232
1918199170cyclictest274102sleep1019:16:232
1918199170cyclictest272222chrt20:45:212
1918199170cyclictest248142sleep1020:41:202
1918199170cyclictest239842sleep1022:10:322
1918199170cyclictest228332sleep1022:36:102
1918199170cyclictest217442chrt00:20:232
1918199170cyclictest204122sleep1023:00:252
1918199170cyclictest196292sleep1019:10:112
1918199170cyclictest194672sleep1023:25:412
1918199170cyclictest194672sleep1023:25:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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