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2026-04-06 - 11:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Apr 06, 2026 00:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501170irq/53-eth0-rx-0-21swapper/119:09:551
9918501020irq/53-eth0-rx-0-21swapper/319:07:255
128501020irq/42-ahci0-21swapper/219:09:594
991850930irq/53-eth0-rx-0-21swapper/819:08:0910
991850920irq/53-eth0-rx-0-21swapper/1019:06:422
991850890irq/53-eth0-rx-0-21swapper/719:06:119
991850890irq/53-eth0-rx-0-21swapper/519:06:597
2456628475sleep40-21swapper/419:05:566
15050710irq/18-uhci_hcd0-21swapper/1119:05:223
2454426253sleep00-21swapper/019:05:400
2472625955sleep90-21swapper/919:08:0211
2456825955sleep60-21swapper/619:05:588
2503499370cyclictest0-21swapper/020:25:220
25076993617cyclictest0-21swapper/1122:13:523
25063992928cyclictest19075-21sensors20:25:226
2507099280cyclictest0-21swapper/500:11:517
25075992726cyclictest991850irq/53-eth0-rx-20:25:212
25072992625cyclictest991850irq/53-eth0-rx-20:25:379
25043992423cyclictest991850irq/53-eth0-rx-20:25:261
25034992314cyclictest0-21swapper/019:29:260
25070992120cyclictest5259-21qemu-kvm20:25:347
2507699190cyclictest0-21swapper/1122:08:263
2507599192cyclictest991850irq/53-eth0-rx-21:23:182
2507599192cyclictest991850irq/53-eth0-rx-00:28:002
2503499190cyclictest47932sleep019:24:050
25075991817cyclictest0-21swapper/1023:30:132
25075991817cyclictest0-21swapper/1022:31:312
25075991816cyclictest24156-21ssh22:06:252
2507599181cyclictest991850irq/53-eth0-rx-23:40:252
2507599181cyclictest991850irq/53-eth0-rx-23:35:442
2507599181cyclictest991850irq/53-eth0-rx-23:28:482
2507599181cyclictest991850irq/53-eth0-rx-23:19:272
2507599181cyclictest991850irq/53-eth0-rx-23:14:412
2507599181cyclictest991850irq/53-eth0-rx-22:59:592
2507599181cyclictest991850irq/53-eth0-rx-22:54:272
2507599181cyclictest991850irq/53-eth0-rx-22:48:422
2507599181cyclictest991850irq/53-eth0-rx-22:10:422
2507599181cyclictest991850irq/53-eth0-rx-21:27:132
2507599181cyclictest991850irq/53-eth0-rx-21:15:242
2507599181cyclictest991850irq/53-eth0-rx-20:47:142
2507599181cyclictest991850irq/53-eth0-rx-20:47:142
2507599181cyclictest991850irq/53-eth0-rx-19:57:332
2507599181cyclictest991850irq/53-eth0-rx-00:12:192
2507599181cyclictest991850irq/53-eth0-rx-00:05:582
25071991816cyclictest24788-21qemu-kvm19:46:288
25071991816cyclictest24788-21qemu-kvm19:16:188
25071991816cyclictest24787-21qemu-kvm19:28:118
25071991816cyclictest16753-21qemu-kvm21:08:188
2503499182cyclictest0-21swapper/021:11:450
25075991716cyclictest17302-21kworker/10:123:50:002
25075991716cyclictest17302-21kworker/10:123:05:102
25075991716cyclictest0-21swapper/1023:01:132
25075991716cyclictest0-21swapper/1020:20:432
25075991716cyclictest0-21swapper/1020:15:162
25075991716cyclictest0-21swapper/1020:06:102
25075991716cyclictest0-21swapper/1019:52:072
25075991716cyclictest0-21swapper/1000:35:272
25075991716cyclictest0-21swapper/1000:30:372
25075991716cyclictest0-21swapper/1000:30:372
2507599170cyclictest991950irq/54-eth0-tx-23:56:112
2507599170cyclictest991850irq/53-eth0-rx-23:45:062
2507599170cyclictest991850irq/53-eth0-rx-23:20:132
2507599170cyclictest991850irq/53-eth0-rx-22:40:092
2507599170cyclictest991850irq/53-eth0-rx-22:35:122
2507599170cyclictest991850irq/53-eth0-rx-22:25:072
2507599170cyclictest991850irq/53-eth0-rx-22:15:082
2507599170cyclictest991850irq/53-eth0-rx-21:51:192
2507599170cyclictest991850irq/53-eth0-rx-21:46:172
2507599170cyclictest991850irq/53-eth0-rx-21:40:252
2507599170cyclictest991850irq/53-eth0-rx-21:36:202
2507599170cyclictest991850irq/53-eth0-rx-21:32:152
2507599170cyclictest991850irq/53-eth0-rx-21:07:202
2507599170cyclictest991850irq/53-eth0-rx-21:00:282
2507599170cyclictest991850irq/53-eth0-rx-21:00:282
2507599170cyclictest991850irq/53-eth0-rx-20:41:352
2507599170cyclictest991850irq/53-eth0-rx-20:37:352
2507599170cyclictest991850irq/53-eth0-rx-20:30:132
2507599170cyclictest991850irq/53-eth0-rx-19:46:292
2507599170cyclictest991850irq/53-eth0-rx-19:11:102
2507599170cyclictest991850irq/53-eth0-rx-00:21:322
2507599170cyclictest991850irq/53-eth0-rx-00:15:412
2507599170cyclictest991850irq/53-eth0-rx-00:00:092
2507599170cyclictest84362sleep1019:29:042
2507599170cyclictest8342sleep1019:16:142
2507599170cyclictest63872sleep1020:55:012
2507599170cyclictest45212sleep1019:20:262
2507599170cyclictest219342sleep1021:13:032
2507599170cyclictest191532sleep1019:41:052
2507599170cyclictest185492sleep1022:02:212
2507599170cyclictest155092sleep1019:36:042
2507599170cyclictest12850irq/42-ahci22:20:002
2507599170cyclictest12850irq/42-ahci20:14:142
2507599170cyclictest105702chrt21:55:202
25073991716cyclictest991850irq/53-eth0-rx-20:25:2210
25071991716cyclictest24788-21qemu-kvm19:41:258
2505199171cyclictest0-21swapper/221:47:594
25075991615cyclictest32352-21cat20:00:152
2507599160cyclictest991850irq/53-eth0-rx-20:53:242
2507399164cyclictest0-21swapper/823:30:0210
2507199162cyclictest0-21swapper/621:25:018
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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