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2026-01-14 - 15:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Jan 14, 2026 12:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17475211196sleep20-21swapper/207:06:084
17562210994sleep80-21swapper/807:07:1510
17449210995sleep40-21swapper/407:05:456
9918501050irq/53-eth0-rx-0-21swapper/107:08:171
128501030irq/42-ahci0-21swapper/307:09:085
9918501020irq/53-eth0-rx-0-21swapper/1007:05:342
991850910irq/53-eth0-rx-0-21swapper/707:08:089
991850810irq/53-eth0-rx-0-21swapper/507:07:527
1600027670sleep90-21swapper/907:05:1411
991850680irq/53-eth0-rx-0-21swapper/1107:08:033
1760826553sleep60-21swapper/607:07:498
1464526350sleep00-21swapper/007:05:060
1792799460cyclictest0-21swapper/010:10:280
1797499388cyclictest153142sleep1110:10:013
1797499378cyclictest206202sleep1110:14:023
17927993416cyclictest0-21swapper/008:30:160
17927993416cyclictest0-21swapper/008:30:150
17974993217cyclictest0-21swapper/1108:30:033
17974993217cyclictest0-21swapper/1108:30:023
17974992517cyclictest0-21swapper/1109:21:573
17974992316cyclictest0-21swapper/1109:08:293
1797299192cyclictest0-21swapper/910:17:3811
17927991918cyclictest0-21swapper/007:25:360
1797299181cyclictest761ksoftirqd/911:30:1211
1797299181cyclictest761ksoftirqd/910:08:0411
1797299181cyclictest761ksoftirqd/909:55:1211
1797299181cyclictest761ksoftirqd/908:15:0111
1797299181cyclictest32104-21ssh09:26:0911
1797299181cyclictest0-21swapper/912:31:2811
1797299181cyclictest0-21swapper/912:25:2411
1797299181cyclictest0-21swapper/912:19:5011
1797299181cyclictest0-21swapper/912:15:0011
1797299181cyclictest0-21swapper/911:59:4811
1797299181cyclictest0-21swapper/911:54:2711
1797299181cyclictest0-21swapper/911:45:3511
1797299181cyclictest0-21swapper/911:29:1911
1797299181cyclictest0-21swapper/911:20:0911
1797299181cyclictest0-21swapper/911:05:0611
1797299181cyclictest0-21swapper/911:05:0611
1797299181cyclictest0-21swapper/911:02:5711
1797299181cyclictest0-21swapper/911:02:5611
1797299181cyclictest0-21swapper/910:38:3511
1797299181cyclictest0-21swapper/909:04:0311
1797299181cyclictest0-21swapper/908:57:3811
1797299181cyclictest0-21swapper/907:55:0111
1795299180cyclictest0-21swapper/307:46:345
1797499173cyclictest0-21swapper/1111:40:013
1797299170cyclictest761ksoftirqd/911:35:1111
1797299170cyclictest761ksoftirqd/909:20:1411
1797299170cyclictest741rcuc/907:35:4211
1797299170cyclictest0-21swapper/912:02:3211
1797299170cyclictest0-21swapper/911:15:0611
1797299170cyclictest0-21swapper/910:27:1011
1797299170cyclictest0-21swapper/910:27:0911
1797299170cyclictest0-21swapper/910:00:1211
1797299170cyclictest0-21swapper/909:50:1411
1797299170cyclictest0-21swapper/909:12:0011
1797299170cyclictest0-21swapper/908:45:1811
17969991715cyclictest9623-21qemu-kvm09:20:148
1795299171cyclictest0-21swapper/309:10:295
1795299171cyclictest0-21swapper/308:33:265
1795299171cyclictest0-21swapper/308:33:265
1795299171cyclictest0-21swapper/307:51:235
1794299171cyclictest0-21swapper/212:30:184
1794299171cyclictest0-21swapper/210:50:144
991850160irq/53-eth0-rx-831ksoftirqd/1009:39:102
1797299165cyclictest0-21swapper/907:20:0111
17972991615cyclictest761ksoftirqd/910:50:1111
17972991615cyclictest741rcuc/910:22:1411
17972991615cyclictest741rcuc/910:22:1311
17972991615cyclictest741rcuc/908:26:5111
17972991615cyclictest741rcuc/908:26:5111
17972991615cyclictest0-21swapper/912:21:0911
17972991615cyclictest0-21swapper/912:08:2811
17972991615cyclictest0-21swapper/911:41:3711
17972991615cyclictest0-21swapper/910:46:2711
17972991615cyclictest0-21swapper/910:46:2611
17972991615cyclictest0-21swapper/910:30:0611
17972991615cyclictest0-21swapper/910:14:4711
17972991615cyclictest0-21swapper/909:45:1811
17972991615cyclictest0-21swapper/909:32:3311
17972991615cyclictest0-21swapper/908:20:1711
17972991614cyclictest21314-21chrt07:11:5111
17972991614cyclictest1765-21taskset08:13:3611
17966991615cyclictest28990-21ssh10:46:167
17966991615cyclictest28990-21ssh10:46:157
17966991615cyclictest19904-21ssh09:45:217
1796699160cyclictest0-21swapper/510:55:217
1796699160cyclictest0-21swapper/510:55:207
1796199160cyclictest0-21swapper/408:49:516
1795299161cyclictest0-21swapper/307:21:315
1795299161cyclictest0-21swapper/307:14:065
1795299160cyclictest0-21swapper/308:50:425
1795299160cyclictest0-21swapper/308:20:305
1795299160cyclictest0-21swapper/308:12:345
1794299161cyclictest0-21swapper/210:47:274
1794299161cyclictest0-21swapper/210:47:264
1794299161cyclictest0-21swapper/209:29:134
1794299160cyclictest0-21swapper/209:49:494
1792999161cyclictest0-21swapper/110:30:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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