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2026-02-04 - 07:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Feb 04, 2026 00:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29029210795sleep90-21swapper/919:06:2411
26180210793sleep10-21swapper/119:05:051
9918501000irq/53-eth0-rx-0-21swapper/1019:05:322
991850990irq/53-eth0-rx-0-21swapper/219:05:254
12850990irq/42-ahci0-21swapper/819:10:0010
991850950irq/53-eth0-rx-0-21swapper/719:05:599
991950930irq/54-eth0-tx-0-21swapper/319:05:165
991850930irq/53-eth0-rx-0-21swapper/419:07:016
991850890irq/53-eth0-rx-0-21swapper/519:08:037
2897326853sleep00-21swapper/019:05:400
2913626353sleep60-21swapper/619:07:458
2582826253sleep110-21swapper/1119:05:023
2946199330cyclictest0-21swapper/020:17:540
2950399310cyclictest0-21swapper/1120:28:063
29499993029cyclictest991850irq/53-eth0-rx-20:17:569
29502992912cyclictest831ksoftirqd/1021:45:012
2950299225cyclictest831ksoftirqd/1000:33:472
2949899220cyclictest0-21swapper/619:44:568
2950299214cyclictest831ksoftirqd/1000:03:062
2950299192cyclictest991850irq/53-eth0-rx-22:09:082
2950299192cyclictest991850irq/53-eth0-rx-00:39:332
2950299192cyclictest991850irq/53-eth0-rx-00:21:242
2950299192cyclictest991850irq/53-eth0-rx-00:18:062
2950199192cyclictest0-21swapper/921:46:3311
2950199192cyclictest0-21swapper/921:46:3211
2950299185cyclictest0-21swapper/1022:30:002
29502991817cyclictest831ksoftirqd/1020:10:272
29502991817cyclictest0-21swapper/1019:48:382
2950299181cyclictest991950irq/54-eth0-tx-23:42:252
2950299181cyclictest991950irq/54-eth0-tx-22:38:432
2950299181cyclictest991850irq/53-eth0-rx-22:22:322
2950299181cyclictest831ksoftirqd/1023:50:002
2950299181cyclictest831ksoftirqd/1022:29:352
2950299181cyclictest831ksoftirqd/1019:35:272
2950299181cyclictest831ksoftirqd/1019:10:132
2950299181cyclictest115050irq/18-i801_smb20:20:212
2950199181cyclictest0-21swapper/923:30:4311
2950199181cyclictest0-21swapper/923:15:2711
2950199181cyclictest0-21swapper/922:15:1911
2950199181cyclictest0-21swapper/922:14:2111
2950199181cyclictest0-21swapper/922:14:2011
2950199181cyclictest0-21swapper/921:55:3411
2950199181cyclictest0-21swapper/921:55:3311
2950199181cyclictest0-21swapper/921:15:0111
2949199180cyclictest0-21swapper/422:11:186
2949199180cyclictest0-21swapper/422:11:176
29502991716cyclictest831ksoftirqd/1020:35:112
29502991716cyclictest831ksoftirqd/1020:05:232
29502991716cyclictest811rcuc/1000:25:482
29502991716cyclictest28730-21cat22:10:192
29502991716cyclictest28730-21cat22:10:182
29502991716cyclictest0-21swapper/1023:20:082
29502991716cyclictest0-21swapper/1022:16:402
29502991716cyclictest0-21swapper/1021:05:132
29502991716cyclictest0-21swapper/1021:05:122
29502991715cyclictest4970-21snmp_rack3slot922:45:142
29502991715cyclictest2316-21diskstats20:45:142
29502991715cyclictest12586-21users19:25:262
2950299170cyclictest991850irq/53-eth0-rx-23:52:242
2950299170cyclictest991850irq/53-eth0-rx-23:35:032
2950299170cyclictest991850irq/53-eth0-rx-23:15:022
2950299170cyclictest991850irq/53-eth0-rx-23:06:022
2950299170cyclictest991850irq/53-eth0-rx-21:50:192
2950299170cyclictest991850irq/53-eth0-rx-21:20:282
2950299170cyclictest991850irq/53-eth0-rx-19:57:132
2950299170cyclictest98822sleep1022:50:022
2950299170cyclictest89582chrt19:20:262
2950299170cyclictest831ksoftirqd/1023:55:132
2950299170cyclictest831ksoftirqd/1023:25:092
2950299170cyclictest831ksoftirqd/1022:00:112
2950299170cyclictest831ksoftirqd/1021:55:112
2950299170cyclictest831ksoftirqd/1021:55:102
2950299170cyclictest831ksoftirqd/1021:25:222
2950299170cyclictest831ksoftirqd/1021:15:022
2950299170cyclictest831ksoftirqd/1021:10:312
2950299170cyclictest831ksoftirqd/1020:50:262
2950299170cyclictest831ksoftirqd/1020:30:112
2950299170cyclictest831ksoftirqd/1020:00:132
2950299170cyclictest831ksoftirqd/1019:30:102
2950299170cyclictest831ksoftirqd/1019:15:252
2950299170cyclictest831ksoftirqd/1000:14:502
2950299170cyclictest831ksoftirqd/1000:05:202
2950299170cyclictest312302sleep1021:45:192
2950299170cyclictest312302sleep1021:45:182
2950299170cyclictest308772sleep1019:50:552
2950299170cyclictest302182sleep1020:40:112
2950299170cyclictest250622sleep1023:30:082
2950299170cyclictest248302sleep1023:00:412
2950299170cyclictest223662sleep1019:40:162
2950299170cyclictest213102sleep1020:25:102
2950299170cyclictest205942sleep1021:35:412
2950299170cyclictest193582sleep1022:56:262
2950299170cyclictest168722sleep1020:16:202
2950299170cyclictest153172sleep1021:01:122
2950299170cyclictest144522sleep1021:30:282
2950299170cyclictest12122chrt23:10:042
2950299170cyclictest116942sleep1020:57:002
2950299170cyclictest10082sleep1022:40:512
29501991716cyclictest0-21swapper/923:25:1211
29501991715cyclictest27474-21ssh21:42:3111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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