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2026-01-25 - 07:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Jan 25, 2026 00:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501260irq/42-ahci0-21swapper/219:08:414
7566210894sleep50-21swapper/519:07:017
7477210892sleep00-21swapper/019:05:550
7528210391sleep110-21swapper/1119:06:313
9918501000irq/53-eth0-rx-0-21swapper/119:06:581
991850950irq/53-eth0-rx-0-21swapper/719:09:269
991850940irq/53-eth0-rx-0-21swapper/419:05:406
12850920irq/42-ahci0-21swapper/319:08:455
764829183sleep100-21swapper/1019:08:062
991850900irq/53-eth0-rx-0-21swapper/819:06:1610
748426756sleep60-21swapper/619:06:028
750526653sleep90-21swapper/919:06:1711
7975992625cyclictest2745-21runrttasks22:28:414
7956992514cyclictest0-21swapper/019:15:260
7987992423cyclictest0-21swapper/1122:28:403
12850230irq/42-ahci14028-21sh21:47:5411
7956992019cyclictest0-21swapper/021:19:310
798699192cyclictest991850irq/53-eth0-rx-23:32:112
798599192cyclictest0-21swapper/923:27:1411
798599192cyclictest0-21swapper/922:37:1411
798599192cyclictest0-21swapper/922:27:1411
798599192cyclictest0-21swapper/921:51:2811
798599192cyclictest0-21swapper/921:10:5311
798599192cyclictest0-21swapper/900:15:0811
7986991817cyclictest0-21swapper/1022:31:332
7986991817cyclictest0-21swapper/1022:12:292
7986991816cyclictest24994-21ssh21:55:572
7986991816cyclictest0-21swapper/1023:38:112
798699181cyclictest991950irq/54-eth0-tx-21:19:092
798699181cyclictest991950irq/54-eth0-tx-20:20:192
798699181cyclictest991850irq/53-eth0-rx-23:56:582
798699181cyclictest991850irq/53-eth0-rx-23:43:562
798699181cyclictest991850irq/53-eth0-rx-23:00:282
798699181cyclictest991850irq/53-eth0-rx-22:56:342
798699181cyclictest991850irq/53-eth0-rx-22:40:232
798699181cyclictest991850irq/53-eth0-rx-22:26:252
798699181cyclictest991850irq/53-eth0-rx-21:38:492
798699181cyclictest991850irq/53-eth0-rx-00:14:162
798699181cyclictest991850irq/53-eth0-rx-00:06:392
798699181cyclictest991850irq/53-eth0-rx-00:03:442
798699181cyclictest831ksoftirqd/1021:50:232
798599181cyclictest991850irq/53-eth0-rx-23:30:1811
798599181cyclictest24608-1kworker/9:2H21:34:5511
798599181cyclictest0-21swapper/923:50:1611
798599181cyclictest0-21swapper/923:43:5711
798599181cyclictest0-21swapper/923:08:0311
798599181cyclictest0-21swapper/922:42:1111
798599181cyclictest0-21swapper/921:29:0711
7981991816cyclictest5833-21qemu-kvm22:15:157
7981991816cyclictest5832-21qemu-kvm22:10:137
7981991816cyclictest5832-21qemu-kvm22:08:287
7987991715cyclictest0-21swapper/1119:30:413
798799170cyclictest0-21swapper/1122:08:163
7986991716cyclictest0-21swapper/1000:16:192
7986991715cyclictest14691-21diskstats20:00:102
7986991715cyclictest11122-21snmp_rack3slot921:45:152
798699170cyclictest991950irq/54-eth0-tx-22:06:532
798699170cyclictest991850irq/53-eth0-rx-23:51:202
798699170cyclictest991850irq/53-eth0-rx-23:46:032
798699170cyclictest991850irq/53-eth0-rx-23:20:422
798699170cyclictest991850irq/53-eth0-rx-23:07:002
798699170cyclictest991850irq/53-eth0-rx-22:50:242
798699170cyclictest991850irq/53-eth0-rx-22:36:072
798699170cyclictest991850irq/53-eth0-rx-22:21:002
798699170cyclictest991850irq/53-eth0-rx-21:40:012
798699170cyclictest991850irq/53-eth0-rx-21:30:172
798699170cyclictest991850irq/53-eth0-rx-21:25:442
798699170cyclictest991850irq/53-eth0-rx-21:20:332
798699170cyclictest991850irq/53-eth0-rx-20:46:452
798699170cyclictest991850irq/53-eth0-rx-20:46:452
798699170cyclictest991850irq/53-eth0-rx-20:17:192
798699170cyclictest991850irq/53-eth0-rx-20:05:062
798699170cyclictest991850irq/53-eth0-rx-00:33:052
798699170cyclictest991850irq/53-eth0-rx-00:25:312
798699170cyclictest991850irq/53-eth0-rx-00:20:322
798699170cyclictest50422chrt19:45:212
798699170cyclictest318312sleep1021:06:172
798699170cyclictest315912sleep1019:40:082
798699170cyclictest308472sleep1022:00:482
798699170cyclictest307862sleep1019:36:072
798699170cyclictest30622sleep1023:25:352
798699170cyclictest253242chrt21:00:042
798699170cyclictest246962sleep1020:58:302
798699170cyclictest242882chrt20:14:242
798699170cyclictest234572sleep1019:25:302
798699170cyclictest225042sleep1000:35:312
798699170cyclictest225042sleep1000:35:302
798699170cyclictest208852sleep1020:51:292
798699170cyclictest208852sleep1020:51:282
798699170cyclictest205132sleep1023:15:102
798699170cyclictest200682sleep1019:24:062
798699170cyclictest179992sleep1023:11:332
798699170cyclictest169162sleep1022:45:062
798699170cyclictest162162chrt19:16:172
798699170cyclictest135182chrt20:40:272
798699170cyclictest135182chrt20:40:262
798699170cyclictest134322sleep1022:15:042
798699170cyclictest129802sleep1019:55:462
798699170cyclictest12850irq/42-ahci21:10:012
798699170cyclictest12850irq/42-ahci19:34:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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