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2026-03-07 - 02:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Mar 06, 2026 12:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501070irq/53-eth0-rx-0-21swapper/107:08:271
1639210793sleep80-21swapper/807:06:3310
31223210391sleep40-21swapper/407:05:056
991850960irq/53-eth0-rx-0-21swapper/907:09:2911
991850940irq/53-eth0-rx-0-21swapper/507:07:067
991850940irq/53-eth0-rx-0-21swapper/307:09:265
991850940irq/53-eth0-rx-0-21swapper/207:06:394
12850880irq/42-ahci0-21swapper/707:08:279
162126553sleep60-21swapper/607:06:198
195026460sleep100-21swapper/1007:09:482
161325955sleep110-21swapper/1107:06:123
164425853sleep00-21swapper/007:06:370
2117992315cyclictest11540-21snmp_rack3slot910:15:1310
2117992315cyclictest11540-21snmp_rack3slot910:15:1310
210999225cyclictest0-21swapper/311:20:085
213199203cyclictest991850irq/53-eth0-rx-09:29:002
213199192cyclictest991850irq/53-eth0-rx-11:09:052
211899192cyclictest0-21swapper/911:46:2711
211899192cyclictest0-21swapper/910:18:0511
211899192cyclictest0-21swapper/910:18:0511
211899192cyclictest0-21swapper/909:25:2911
2131991817cyclictest0-21swapper/1011:46:392
2131991817cyclictest0-21swapper/1009:58:032
213199181cyclictest991950irq/54-eth0-tx-12:08:022
213199181cyclictest991850irq/53-eth0-rx-11:52:082
213199181cyclictest991850irq/53-eth0-rx-11:35:272
213199181cyclictest991850irq/53-eth0-rx-10:56:342
213199181cyclictest991850irq/53-eth0-rx-10:13:072
213199181cyclictest991850irq/53-eth0-rx-09:53:322
213199181cyclictest991850irq/53-eth0-rx-09:49:112
213199181cyclictest991850irq/53-eth0-rx-09:36:392
213199181cyclictest991850irq/53-eth0-rx-09:33:532
213199181cyclictest991850irq/53-eth0-rx-07:13:142
213199181cyclictest12850irq/42-ahci08:20:072
213199181cyclictest12850irq/42-ahci07:57:322
211899181cyclictest0-21swapper/912:06:4511
211899181cyclictest0-21swapper/911:37:3911
211899181cyclictest0-21swapper/911:10:1911
211899181cyclictest0-21swapper/910:22:1011
211899181cyclictest0-21swapper/909:47:1411
211899181cyclictest0-21swapper/909:37:1511
211899181cyclictest0-21swapper/909:30:3811
211899181cyclictest0-21swapper/909:21:3211
2109991816cyclictest8825-21cpuspeed_turbos10:40:115
2109991816cyclictest8825-21cpuspeed_turbos10:40:115
2109991816cyclictest2435-21crond07:30:015
2109991816cyclictest2435-21crond07:30:015
2109991816cyclictest24086-21idleruntime08:20:165
2109991816cyclictest16023-21cpuspeed_turbos08:55:115
2131991716cyclictest0-21swapper/1010:45:082
2131991715cyclictest16269-21ssh10:20:042
213199170cyclictest991850irq/53-eth0-rx-12:37:042
213199170cyclictest991850irq/53-eth0-rx-12:30:212
213199170cyclictest991850irq/53-eth0-rx-12:20:072
213199170cyclictest991850irq/53-eth0-rx-12:15:092
213199170cyclictest991850irq/53-eth0-rx-12:00:082
213199170cyclictest991850irq/53-eth0-rx-11:31:212
213199170cyclictest991850irq/53-eth0-rx-11:27:352
213199170cyclictest991850irq/53-eth0-rx-11:21:052
213199170cyclictest991850irq/53-eth0-rx-11:02:152
213199170cyclictest991850irq/53-eth0-rx-10:50:272
213199170cyclictest991850irq/53-eth0-rx-10:50:272
213199170cyclictest991850irq/53-eth0-rx-10:40:142
213199170cyclictest991850irq/53-eth0-rx-10:40:142
213199170cyclictest991850irq/53-eth0-rx-10:30:132
213199170cyclictest991850irq/53-eth0-rx-10:25:172
213199170cyclictest991850irq/53-eth0-rx-10:25:172
213199170cyclictest991850irq/53-eth0-rx-10:05:192
213199170cyclictest991850irq/53-eth0-rx-10:00:332
213199170cyclictest991850irq/53-eth0-rx-09:20:192
213199170cyclictest991850irq/53-eth0-rx-09:05:132
213199170cyclictest991850irq/53-eth0-rx-08:27:192
213199170cyclictest991850irq/53-eth0-rx-08:00:032
213199170cyclictest991850irq/53-eth0-rx-07:32:082
213199170cyclictest991850irq/53-eth0-rx-07:15:262
213199170cyclictest77262sleep1008:40:572
213199170cyclictest71672sleep1011:55:572
213199170cyclictest54812sleep1010:35:362
213199170cyclictest48152sleep1009:17:262
213199170cyclictest36432sleep1007:52:162
213199170cyclictest307622sleep1007:45:152
213199170cyclictest3012chrt08:30:442
213199170cyclictest273562chrt09:10:122
213199170cyclictest263452chrt12:12:102
213199170cyclictest223552sleep1009:01:122
213199170cyclictest223502sleep1011:15:282
213199170cyclictest221392sleep1007:35:032
213199170cyclictest208152sleep1008:15:182
213199170cyclictest208082sleep1011:40:312
213199170cyclictest186842sleep1008:56:232
213199170cyclictest169912sleep1008:10:172
213199170cyclictest149822sleep1008:50:342
213199170cyclictest143362sleep1007:25:022
213199170cyclictest143362sleep1007:25:022
213199170cyclictest140262sleep1007:20:482
213199170cyclictest132152sleep1011:10:042
213199170cyclictest12850irq/42-ahci09:40:262
213199170cyclictest116742chrt12:25:482
213199170cyclictest116732sleep1008:05:052
213199170cyclictest11442chrt08:35:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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