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2026-08-11 - 11:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Aug 11, 2026 00:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501180irq/53-eth0-rx-0-21swapper/219:09:054
30549501110irq/53-eth0-rx-0-21swapper/319:05:155
122501100irq/42-ahci0-21swapper/119:09:391
4192210891sleep60-21swapper/619:07:518
4167210593sleep110-21swapper/1119:07:323
4158210491sleep50-21swapper/519:07:257
12250970irq/42-ahci0-21swapper/719:09:539
3054950940irq/53-eth0-rx-0-21swapper/419:06:246
3054950900irq/53-eth0-rx-0-21swapper/819:05:1310
410627969sleep00-21swapper/019:06:440
402127765sleep90-21swapper/919:05:4111
440127472sleep100-21swapper/1019:09:542
4526993717cyclictest0-21swapper/021:08:410
452699340cyclictest0-21swapper/021:14:030
4547993130cyclictest3054950irq/53-eth0-rx-21:13:516
3054950310irq/53-eth0-rx-0-21swapper/1021:14:052
4552993029cyclictest3054950irq/53-eth0-rx-21:14:0311
4551993029cyclictest3054950irq/53-eth0-rx-21:13:5910
3054950300irq/53-eth0-rx-0-21swapper/1121:14:013
4548992928cyclictest3055050irq/54-eth0-tx-21:13:487
4538992928cyclictest3054950irq/53-eth0-rx-21:13:484
4550992827cyclictest3055050irq/54-eth0-tx-21:13:549
452699260cyclictest19140-21chrt20:10:270
4544992524cyclictest3054950irq/53-eth0-rx-21:14:045
4526992510cyclictest0-21swapper/022:17:530
4531992019cyclictest3054950irq/53-eth0-rx-21:13:561
4553991917cyclictest7111-1kworker/10:0H00:11:402
4553991917cyclictest7111-1kworker/10:0H00:11:392
4553991817cyclictest9417-21kworker/10:223:49:092
4553991817cyclictest0-21swapper/1023:28:012
4553991817cyclictest0-21swapper/1022:37:572
4553991817cyclictest0-21swapper/1022:05:092
4553991817cyclictest0-21swapper/1021:33:012
4553991816cyclictest7111-1kworker/10:0H21:09:372
4553991816cyclictest21794-21if_eth100:30:162
4553991816cyclictest0-21swapper/1022:42:342
4553991816cyclictest0-21swapper/1020:58:052
4553991816cyclictest0-21swapper/1000:05:492
4538991816cyclictest4861-21snmp_rack3slot919:51:494
4553991716cyclictest9417-21kworker/10:221:39:282
4553991716cyclictest7111-1kworker/10:0H23:41:182
4553991716cyclictest7111-1kworker/10:0H22:45:052
4553991716cyclictest7111-1kworker/10:0H20:26:092
4553991716cyclictest26505-21ssh23:15:512
4553991716cyclictest22777-21ssh22:21:492
4553991716cyclictest0-21swapper/1023:20:172
4553991716cyclictest0-21swapper/1023:11:062
4553991716cyclictest0-21swapper/1023:03:322
4553991716cyclictest0-21swapper/1022:54:312
4553991716cyclictest0-21swapper/1022:13:142
4553991716cyclictest0-21swapper/1021:18:152
4553991716cyclictest0-21swapper/1000:39:572
4553991716cyclictest0-21swapper/1000:25:352
4553991716cyclictest0-21swapper/1000:20:562
455299170cyclictest7632-21sh21:19:4211
455099173cyclictest0-21swapper/722:25:199
4538991715cyclictest2305-21snmpd23:07:554
4538991715cyclictest2305-21snmpd00:09:554
4538991715cyclictest19749-21snmp_rack3slot923:36:494
4538991715cyclictest19749-21snmp_rack3slot923:36:484
3055050170irq/54-eth0-tx-27468-21qemu-kvm21:13:528
4553991615cyclictest811rcuc/1021:24:462
4553991615cyclictest811rcuc/1021:24:452
4553991615cyclictest7111-1kworker/10:0H19:48:312
4553991615cyclictest108222sleep1023:05:112
4553991615cyclictest0-21swapper/1023:56:462
4553991615cyclictest0-21swapper/1023:36:072
4553991615cyclictest0-21swapper/1023:36:062
4553991615cyclictest0-21swapper/1022:58:402
4553991615cyclictest0-21swapper/1022:34:262
4553991615cyclictest0-21swapper/1022:17:192
4553991615cyclictest0-21swapper/1022:03:172
4553991615cyclictest0-21swapper/1021:50:352
4553991615cyclictest0-21swapper/1000:02:522
4553991614cyclictest268872sleep1020:22:512
455099165cyclictest0-21swapper/700:20:029
455099164cyclictest0-21swapper/722:45:009
453899163cyclictest0-21swapper/220:40:164
4538991614cyclictest24618-21snmp_rack3slot921:05:124
4538991614cyclictest2305-21snmpd20:00:394
453899161cyclictest0-21swapper/223:53:034
453899161cyclictest0-21swapper/223:42:584
4531991615cyclictest27624-21diskmemload22:55:181
4531991615cyclictest27624-21diskmemload22:48:481
4531991615cyclictest27624-21diskmemload22:23:561
4531991615cyclictest27624-21diskmemload00:17:261
455399153cyclictest3054950irq/53-eth0-rx-23:33:322
4553991514cyclictest0-21swapper/1022:28:472
4553991514cyclictest0-21swapper/1021:46:312
4553991514cyclictest0-21swapper/1021:27:122
4553991514cyclictest0-21swapper/1020:05:012
4553991514cyclictest0-21swapper/1000:15:192
455199155cyclictest0-21swapper/800:35:0210
455199154cyclictest0-21swapper/820:20:0110
4551991514cyclictest6362-21smartctl19:10:1410
4551991514cyclictest6362-21smartctl19:10:1410
4551991514cyclictest5917-21smartctl23:00:1510
4551991514cyclictest3876-21smartctl20:35:1510
455099154cyclictest0-21swapper/723:50:019
455099154cyclictest0-21swapper/719:30:029
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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