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2026-06-08 - 19:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Jun 08, 2026 12:46:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501110irq/42-ahci0-21swapper/107:09:121
24968210992sleep00-21swapper/007:06:110
30549501030irq/53-eth0-rx-0-21swapper/207:09:124
25023210086sleep50-21swapper/507:06:537
3054950950irq/53-eth0-rx-0-21swapper/307:05:165
3054950950irq/53-eth0-rx-0-21swapper/1007:05:362
3054950920irq/53-eth0-rx-0-21swapper/707:05:429
3054950920irq/53-eth0-rx-0-21swapper/407:06:256
2528027977sleep90-21swapper/907:09:3411
119150690irq/18-parport00-21swapper/1107:07:303
12250670irq/42-ahci0-21swapper/807:05:5110
2499426353sleep60-21swapper/607:06:308
25476993617cyclictest0-21swapper/1110:25:233
25451992928cyclictest2318-21sshd07:24:130
2547599192cyclictest3054950irq/53-eth0-rx-12:34:542
2547599192cyclictest3054950irq/53-eth0-rx-12:09:002
2547599192cyclictest3054950irq/53-eth0-rx-11:37:082
2547599192cyclictest3054950irq/53-eth0-rx-11:10:232
2547599192cyclictest3054950irq/53-eth0-rx-10:38:562
2547599192cyclictest3054950irq/53-eth0-rx-10:09:322
2547599192cyclictest3054950irq/53-eth0-rx-09:25:022
2547399192cyclictest0-21swapper/911:38:3211
2547399192cyclictest0-21swapper/910:10:2211
2547399192cyclictest0-21swapper/909:18:5911
25475991817cyclictest0-21swapper/1011:27:582
25475991817cyclictest0-21swapper/1009:51:262
25475991817cyclictest0-21swapper/1009:36:572
25475991817cyclictest0-21swapper/1009:21:012
2547599181cyclictest3055050irq/54-eth0-tx-12:12:362
2547599181cyclictest3055050irq/54-eth0-tx-12:01:392
2547599181cyclictest3055050irq/54-eth0-tx-11:07:122
2547599181cyclictest3055050irq/54-eth0-tx-10:10:252
2547599181cyclictest3054950irq/53-eth0-rx-12:38:022
2547599181cyclictest3054950irq/53-eth0-rx-12:20:372
2547599181cyclictest3054950irq/53-eth0-rx-12:16:192
2547599181cyclictest3054950irq/53-eth0-rx-11:55:472
2547599181cyclictest3054950irq/53-eth0-rx-11:51:452
2547599181cyclictest3054950irq/53-eth0-rx-11:22:032
2547599181cyclictest3054950irq/53-eth0-rx-10:59:422
2547599181cyclictest3054950irq/53-eth0-rx-10:52:212
2547599181cyclictest3054950irq/53-eth0-rx-10:48:062
2547599181cyclictest3054950irq/53-eth0-rx-10:27:202
2547599181cyclictest3054950irq/53-eth0-rx-10:00:222
2547599181cyclictest3054950irq/53-eth0-rx-09:56:532
2547599181cyclictest3054950irq/53-eth0-rx-09:30:492
2547599181cyclictest3054950irq/53-eth0-rx-09:17:272
2547599181cyclictest3054950irq/53-eth0-rx-09:11:412
2547599181cyclictest3054950irq/53-eth0-rx-08:05:122
2547599181cyclictest3054950irq/53-eth0-rx-07:12:102
2547399181cyclictest3055050irq/54-eth0-tx-11:12:4011
2547399181cyclictest20132-21ssh11:00:1011
2547399181cyclictest1850-21kworker/9:011:20:0111
2547399181cyclictest0-21swapper/912:00:4411
2547399181cyclictest0-21swapper/911:56:5311
2547399181cyclictest0-21swapper/911:54:4311
2547399181cyclictest0-21swapper/911:48:5511
2547399181cyclictest0-21swapper/911:21:4211
2547399181cyclictest0-21swapper/910:25:2511
2547399181cyclictest0-21swapper/910:23:0911
2547399181cyclictest0-21swapper/910:16:3011
2547399181cyclictest0-21swapper/909:14:1411
25460991816cyclictest27083-21perl07:10:144
25460991816cyclictest2305-21snmpd10:55:414
25460991816cyclictest2305-21snmpd08:49:554
25460991816cyclictest2305-21snmpd08:49:554
25460991816cyclictest19987-21snmp_easybox.os11:25:234
25460991816cyclictest16963-21snmp_rack3slot909:05:484
25460991816cyclictest12838-21snmp_rack3slot911:46:494
25460991816cyclictest10028-21snmp_rack3slot912:11:354
2545199180cyclictest0-21swapper/009:08:160
25475991716cyclictest2446-1kworker/10:0H10:20:032
2547599170cyclictest91862sleep1011:45:062
2547599170cyclictest60152sleep1008:50:572
2547599170cyclictest313282chrt08:00:032
2547599170cyclictest310982sleep1008:41:192
2547599170cyclictest305642sleep1007:56:512
2547599170cyclictest3055050irq/54-eth0-tx-10:15:392
2547599170cyclictest3054950irq/53-eth0-rx-12:25:042
2547599170cyclictest3054950irq/53-eth0-rx-11:40:112
2547599170cyclictest3054950irq/53-eth0-rx-11:15:032
2547599170cyclictest3054950irq/53-eth0-rx-11:00:192
2547599170cyclictest3054950irq/53-eth0-rx-10:40:272
2547599170cyclictest3054950irq/53-eth0-rx-10:30:232
2547599170cyclictest3054950irq/53-eth0-rx-09:45:032
2547599170cyclictest3054950irq/53-eth0-rx-09:40:052
2547599170cyclictest3054950irq/53-eth0-rx-09:05:352
2547599170cyclictest3054950irq/53-eth0-rx-08:57:132
2547599170cyclictest3054950irq/53-eth0-rx-08:45:142
2547599170cyclictest3054950irq/53-eth0-rx-08:45:142
2547599170cyclictest3054950irq/53-eth0-rx-08:36:002
2547599170cyclictest3054950irq/53-eth0-rx-08:11:022
2547599170cyclictest3054950irq/53-eth0-rx-07:30:382
2547599170cyclictest3054950irq/53-eth0-rx-07:25:222
2547599170cyclictest268112sleep1007:50:272
2547599170cyclictest266892sleep1011:30:412
2547599170cyclictest266892sleep1011:30:412
2547599170cyclictest239692sleep1008:33:432
2547599170cyclictest20712sleep1007:20:102
2547599170cyclictest175072chrt07:40:132
2547599170cyclictest172942chrt08:25:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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