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2025-08-30 - 01:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Aug 29, 2025 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18605211297sleep40-21swapper/407:06:336
30663501090irq/52-eth0-rx-0-21swapper/707:09:179
122501020irq/42-ahci0-21swapper/107:09:081
12250970irq/42-ahci0-21swapper/207:08:464
3066350950irq/52-eth0-rx-0-21swapper/1107:06:523
3066350930irq/52-eth0-rx-0-21swapper/507:05:547
3066350920irq/52-eth0-rx-0-21swapper/307:05:195
1890129185sleep100-21swapper/1007:09:512
1575727565sleep90-21swapper/907:05:1411
1854426353sleep60-21swapper/607:05:478
1866325955sleep00-21swapper/007:07:170
1860925955sleep80-21swapper/807:06:3710
1906999330cyclictest0-21swapper/1110:14:013
1906999330cyclictest0-21swapper/1110:14:003
19017992812cyclictest0-21swapper/009:18:450
1901799280cyclictest0-21swapper/009:13:460
19033992113cyclictest2406-21snmpd10:07:554
19033992012cyclictest2406-21snmpd12:10:554
1906699192cyclictest3066350irq/52-eth0-rx-09:35:232
19017991918cyclictest0-21swapper/007:13:150
19066991817cyclictest0-21swapper/1010:10:162
19066991817cyclictest0-21swapper/1010:10:162
1906699181cyclictest3066450irq/53-eth0-tx-07:50:252
1906699181cyclictest3066450irq/53-eth0-tx-07:50:252
1906699181cyclictest3066350irq/52-eth0-rx-11:39:022
1906699181cyclictest3066350irq/52-eth0-rx-09:34:482
1906699181cyclictest3066350irq/52-eth0-rx-08:40:312
1906699181cyclictest215122sleep1009:22:302
1906699181cyclictest12250irq/42-ahci12:02:542
1906699181cyclictest12250irq/42-ahci11:59:132
1906699181cyclictest12250irq/42-ahci08:47:302
1906699181cyclictest12250irq/42-ahci07:10:062
1906699180cyclictest12250irq/42-ahci09:50:342
1906699180cyclictest12250irq/42-ahci09:46:412
1906599181cyclictest0-21swapper/912:25:2211
1906599181cyclictest0-21swapper/910:10:0111
19064991816cyclictest9277-21perl09:50:1610
19064991816cyclictest4100-21ntp_states11:55:2210
19064991816cyclictest29504-21snmp_easybox.os09:35:1210
19064991816cyclictest27955-21perl11:00:1610
19064991816cyclictest23592-21snmp_rack3slot910:10:1310
19064991816cyclictest23592-21snmp_rack3slot910:10:1310
19064991816cyclictest1646-21snmp_rack3slot912:37:0310
19064991816cyclictest13489-21diskstats11:25:1410
19064991816cyclictest10786-21memory11:20:2110
19057991816cyclictest18779-21qemu-kvm07:33:208
19017991817cyclictest0-21swapper/007:27:240
1901799180cyclictest0-21swapper/009:09:530
1906999170cyclictest0-21swapper/1108:15:493
19066991716cyclictest8943-21smartctl09:05:162
1906699170cyclictest97392sleep1007:39:532
1906699170cyclictest8572sleep1011:06:412
1906699170cyclictest77442sleep1010:30:482
1906699170cyclictest62962chrt08:15:332
1906699170cyclictest61252sleep1009:00:262
1906699170cyclictest53572sleep1011:15:052
1906699170cyclictest47312sleep1011:13:302
1906699170cyclictest35862sleep1009:40:432
1906699170cyclictest308082sleep1011:50:092
1906699170cyclictest3066350irq/52-eth0-rx-12:15:122
1906699170cyclictest3066350irq/52-eth0-rx-10:55:162
1906699170cyclictest3066350irq/52-eth0-rx-10:25:242
1906699170cyclictest3066350irq/52-eth0-rx-08:55:292
1906699170cyclictest3066350irq/52-eth0-rx-08:25:142
1906699170cyclictest3066350irq/52-eth0-rx-07:42:222
1906699170cyclictest3066350irq/52-eth0-rx-07:30:322
1906699170cyclictest3066350irq/52-eth0-rx-07:25:202
1906699170cyclictest300132sleep1011:46:212
1906699170cyclictest298432chrt11:03:532
1906699170cyclictest293872sleep1010:18:472
1906699170cyclictest289882sleep1008:50:022
1906699170cyclictest273462sleep1007:17:032
1906699170cyclictest264452sleep1011:42:082
1906699170cyclictest240862sleep1007:56:442
1906699170cyclictest230812sleep1012:20:372
1906699170cyclictest222182sleep1009:25:052
1906699170cyclictest208842sleep1008:35:482
1906699170cyclictest202842sleep1010:50:152
1906699170cyclictest193642chrt11:34:442
1906699170cyclictest177402sleep1009:15:532
1906699170cyclictest174932sleep1008:34:232
1906699170cyclictest17172chrt12:38:032
1906699170cyclictest169562sleep1010:00:212
1906699170cyclictest141422sleep1011:25:182
1906699170cyclictest130622sleep1010:40:152
1906699170cyclictest130162sleep1012:10:132
1906699170cyclictest123872sleep1012:08:362
1906699170cyclictest12250irq/42-ahci12:30:572
1906699170cyclictest12250irq/42-ahci12:26:122
1906699170cyclictest12250irq/42-ahci11:20:432
1906699170cyclictest12250irq/42-ahci10:45:152
1906699170cyclictest12250irq/42-ahci10:21:212
1906699170cyclictest12250irq/42-ahci10:21:212
1906699170cyclictest12250irq/42-ahci10:08:342
1906699170cyclictest12250irq/42-ahci09:57:142
1906699170cyclictest12250irq/42-ahci08:20:122
1906699170cyclictest12250irq/42-ahci08:10:222
1906699170cyclictest12250irq/42-ahci08:08:282
1906699170cyclictest12250irq/42-ahci07:46:322
1906699170cyclictest116032chrt10:39:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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