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2026-02-07 - 04:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Feb 07, 2026 00:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501130irq/53-eth0-rx-0-21swapper/819:09:1710
9918501120irq/53-eth0-rx-0-21swapper/219:09:134
82542111101sleep100-21swapper/1019:05:012
11756210894sleep40-21swapper/419:08:076
128501050irq/42-ahci0-21swapper/319:09:125
9918501010irq/53-eth0-rx-0-21swapper/119:08:041
991850930irq/53-eth0-rx-0-21swapper/719:05:329
12850910irq/42-ahci0-21swapper/519:05:037
991850870irq/53-eth0-rx-0-21swapper/1119:06:463
1162427874sleep90-21swapper/919:06:2411
1098626550sleep00-21swapper/019:05:270
1165126353sleep60-21swapper/619:06:458
12092992214cyclictest0-21swapper/921:16:1011
1205299220cyclictest0-21swapper/022:12:320
12092992113cyclictest0-21swapper/922:24:0111
1205299210cyclictest0-21swapper/021:55:080
1205299210cyclictest0-21swapper/020:55:210
1205299210cyclictest0-21swapper/020:45:220
1205299210cyclictest0-21swapper/020:19:520
1205299210cyclictest0-21swapper/020:19:520
1205299210cyclictest0-21swapper/000:06:120
12092992014cyclictest27432-21sh00:15:0111
12092992014cyclictest0-21swapper/922:01:2411
12092992013cyclictest0-21swapper/923:50:0311
12092992013cyclictest0-21swapper/921:54:3311
12092992013cyclictest0-21swapper/921:39:4111
12092992013cyclictest0-21swapper/919:52:0311
1209299201cyclictest0-21swapper/922:10:1811
1209299201cyclictest0-21swapper/900:31:2011
1205299200cyclictest0-21swapper/023:55:220
1205299200cyclictest0-21swapper/023:20:310
1205299200cyclictest0-21swapper/023:00:230
1205299200cyclictest0-21swapper/022:00:220
1205299200cyclictest0-21swapper/020:54:580
1205299200cyclictest0-21swapper/020:54:580
1205299200cyclictest0-21swapper/020:39:550
1205299200cyclictest0-21swapper/020:39:550
1205299200cyclictest0-21swapper/020:24:530
1205299200cyclictest0-21swapper/019:55:220
1205299200cyclictest0-21swapper/019:15:000
1205299200cyclictest0-21swapper/000:01:120
12092991913cyclictest0-21swapper/922:40:0011
12092991913cyclictest0-21swapper/900:16:0211
12092991913cyclictest0-21swapper/900:04:0411
12092991911cyclictest0-21swapper/921:13:3911
1209299191cyclictest0-21swapper/920:08:2311
1205299190cyclictest0-21swapper/021:10:430
1205299190cyclictest0-21swapper/021:04:590
1205299190cyclictest0-21swapper/021:04:590
1205299190cyclictest0-21swapper/020:08:450
1209399181cyclictest991850irq/53-eth0-rx-23:36:312
1209399181cyclictest991850irq/53-eth0-rx-23:15:462
12092991811cyclictest0-21swapper/919:20:2211
1209299181cyclictest0-21swapper/923:40:0911
1209299181cyclictest0-21swapper/923:40:0911
1209299181cyclictest0-21swapper/923:35:2611
1209299181cyclictest0-21swapper/922:53:0911
1209299181cyclictest0-21swapper/922:48:1911
1209299181cyclictest0-21swapper/921:58:1911
1209299181cyclictest0-21swapper/921:20:4311
1209299181cyclictest0-21swapper/900:26:3511
12052991812cyclictest0-21swapper/023:30:220
12052991812cyclictest0-21swapper/023:30:220
1205299181cyclictest3944-21diskmemload22:20:130
1209499170cyclictest0-21swapper/1121:29:223
1209499170cyclictest0-21swapper/1121:10:233
12093991716cyclictest0-21swapper/1021:50:182
12093991716cyclictest0-21swapper/1021:48:112
1209399170cyclictest991950irq/54-eth0-tx-23:20:032
1209399170cyclictest991950irq/54-eth0-tx-22:31:562
1209399170cyclictest991950irq/54-eth0-tx-22:15:522
1209399170cyclictest991950irq/54-eth0-tx-21:57:242
1209399170cyclictest991950irq/54-eth0-tx-21:36:592
1209399170cyclictest991950irq/54-eth0-tx-21:11:242
1209399170cyclictest991950irq/54-eth0-tx-00:25:572
1209399170cyclictest991950irq/54-eth0-tx-00:22:372
1209399170cyclictest991950irq/54-eth0-tx-00:01:002
1209399170cyclictest991850irq/53-eth0-rx-23:56:122
1209399170cyclictest991850irq/53-eth0-rx-23:53:102
1209399170cyclictest991850irq/53-eth0-rx-23:47:042
1209399170cyclictest991850irq/53-eth0-rx-23:41:152
1209399170cyclictest991850irq/53-eth0-rx-23:41:152
1209399170cyclictest991850irq/53-eth0-rx-23:32:492
1209399170cyclictest991850irq/53-eth0-rx-23:32:492
1209399170cyclictest991850irq/53-eth0-rx-23:26:222
1209399170cyclictest991850irq/53-eth0-rx-22:58:382
1209399170cyclictest991850irq/53-eth0-rx-22:50:072
1209399170cyclictest991850irq/53-eth0-rx-22:25:372
1209399170cyclictest991850irq/53-eth0-rx-22:14:272
1209399170cyclictest991850irq/53-eth0-rx-22:07:372
1209399170cyclictest991850irq/53-eth0-rx-22:01:302
1209399170cyclictest991850irq/53-eth0-rx-21:40:312
1209399170cyclictest991850irq/53-eth0-rx-21:30:172
1209399170cyclictest991850irq/53-eth0-rx-21:21:442
1209399170cyclictest991850irq/53-eth0-rx-21:15:302
1209399170cyclictest991850irq/53-eth0-rx-19:13:592
1209399170cyclictest991850irq/53-eth0-rx-00:30:222
1209399170cyclictest991850irq/53-eth0-rx-00:15:092
1209399170cyclictest84102sleep1019:45:162
1209399170cyclictest36272sleep1021:06:372
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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