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2026-07-11 - 11:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Jul 11, 2026 00:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11269210894sleep80-21swapper/819:06:4810
11199210795sleep30-21swapper/319:05:545
30549501030irq/53-eth0-rx-0-21swapper/119:05:191
3054950980irq/53-eth0-rx-0-21swapper/719:08:169
3054950960irq/53-eth0-rx-0-21swapper/419:06:046
1156429692sleep90-21swapper/919:10:0111
3054950940irq/53-eth0-rx-0-21swapper/519:08:047
3054950910irq/53-eth0-rx-0-21swapper/219:06:254
3054950880irq/53-eth0-rx-0-21swapper/1119:06:423
119150790irq/18-parport00-21swapper/1019:09:302
1124726553sleep60-21swapper/619:06:338
1119626553sleep00-21swapper/019:05:510
11670993820cyclictest0-21swapper/019:12:410
1167099330cyclictest0-21swapper/019:20:000
1167099320cyclictest0-21swapper/019:30:000
1167099320cyclictest0-21swapper/019:25:210
1167099320cyclictest0-21swapper/019:20:060
11716993130cyclictest0-21swapper/1121:11:193
11716993130cyclictest0-21swapper/1121:11:183
11716993014cyclictest27402-21chrt19:28:393
1171699267cyclictest151472sleep1119:13:143
1171699210cyclictest0-21swapper/1119:21:243
1171699210cyclictest0-21swapper/1119:15:263
1171699200cyclictest0-21swapper/1120:08:163
11715992013cyclictest1654-1kworker/10:0H21:38:102
11715992012cyclictest0-21swapper/1023:46:422
11715992012cyclictest0-21swapper/1022:55:332
11715992012cyclictest0-21swapper/1022:29:282
11715992012cyclictest0-21swapper/1019:26:552
11715992012cyclictest0-21swapper/1000:16:262
11715992011cyclictest0-21swapper/1021:53:222
1171599192cyclictest3054950irq/53-eth0-rx-00:02:222
11715991913cyclictest0-21swapper/1022:06:332
11715991913cyclictest0-21swapper/1021:31:592
11715991913cyclictest0-21swapper/1021:25:202
11715991913cyclictest0-21swapper/1000:05:092
11715991913cyclictest0-21swapper/1000:05:082
11715991912cyclictest32447-21ssh00:10:222
11715991912cyclictest32447-21ssh00:10:212
11715991912cyclictest1654-1kworker/10:0H22:39:512
11715991912cyclictest0-21swapper/1023:18:502
11715991912cyclictest0-21swapper/1023:08:542
11715991912cyclictest0-21swapper/1022:48:472
11715991912cyclictest0-21swapper/1022:10:342
11715991912cyclictest0-21swapper/1021:44:412
11715991912cyclictest0-21swapper/1021:24:322
11715991912cyclictest0-21swapper/1000:31:352
11715991912cyclictest0-21swapper/1000:20:262
11715991911cyclictest0-21swapper/1023:40:282
11715991910cyclictest0-21swapper/1023:00:312
11715991910cyclictest0-21swapper/1021:57:562
11715991910cyclictest0-21swapper/1000:35:212
1171499192cyclictest0-21swapper/923:27:3111
1171499192cyclictest0-21swapper/921:49:4911
1171499192cyclictest0-21swapper/921:25:3511
11716991817cyclictest901ksoftirqd/1121:17:293
11716991816cyclictest20021-21ssh21:21:353
11715991817cyclictest0-21swapper/1021:49:492
11715991817cyclictest0-21swapper/1020:31:082
11715991812cyclictest0-21swapper/1022:54:262
11715991812cyclictest0-21swapper/1022:01:292
11715991812cyclictest0-21swapper/1021:10:322
11715991812cyclictest0-21swapper/1021:10:312
11715991812cyclictest0-21swapper/1021:05:222
11715991812cyclictest0-21swapper/1021:05:212
11715991812cyclictest0-21swapper/1019:31:022
11715991811cyclictest0-21swapper/1022:31:102
11715991810cyclictest0-21swapper/1020:35:112
1171599181cyclictest3054950irq/53-eth0-rx-23:59:102
1171599181cyclictest3054950irq/53-eth0-rx-23:53:372
1171599181cyclictest3054950irq/53-eth0-rx-23:37:232
1171599181cyclictest3054950irq/53-eth0-rx-23:23:472
1171599181cyclictest3054950irq/53-eth0-rx-22:20:042
1171599181cyclictest3054950irq/53-eth0-rx-22:16:262
1171599181cyclictest3054950irq/53-eth0-rx-00:25:512
1171599181cyclictest12250irq/42-ahci19:36:472
11714991816cyclictest9726-21ssh21:15:0111
11714991816cyclictest9726-21ssh21:15:0111
1171499181cyclictest9886-21ssh22:05:3811
1171499181cyclictest9354-21snmp_rack3slot923:51:3611
1171499181cyclictest9135-21ssh22:32:1311
1171499181cyclictest8015-21ssh00:17:3811
1171499181cyclictest761ksoftirqd/923:00:2611
1171499181cyclictest761ksoftirqd/922:45:0011
1171499181cyclictest761ksoftirqd/922:40:2111
1171499181cyclictest761ksoftirqd/922:23:5711
1171499181cyclictest761ksoftirqd/921:40:1911
1171499181cyclictest761ksoftirqd/920:15:2411
1171499181cyclictest741rcuc/920:55:0011
1171499181cyclictest3054950irq/53-eth0-rx-19:48:3211
1171499181cyclictest29834-21iostat00:35:1611
1171499181cyclictest28482-21ssh00:08:0611
1171499181cyclictest28482-21ssh00:08:0511
1171499181cyclictest25017-21ssh21:52:3611
1171499181cyclictest21806-21ssh23:10:0911
1171499181cyclictest18572-21if_err_eth119:15:1511
1171499181cyclictest18503-21cut20:45:1211
1171499181cyclictest17411-21ssh23:31:3411
1171499181cyclictest16823-21ssh22:11:5611
1171499181cyclictest0-21swapper/923:05:1611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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