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2026-08-31 - 00:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Aug 30, 2026 12:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25533210994sleep90-21swapper/907:06:2611
30549501080irq/53-eth0-rx-0-21swapper/207:07:014
25460210694sleep10-21swapper/107:05:311
22157210489sleep80-21swapper/807:05:0210
122501030irq/42-ahci0-21swapper/307:08:495
3054950980irq/53-eth0-rx-0-21swapper/407:05:246
3054950930irq/53-eth0-rx-0-21swapper/1107:05:453
3054950910irq/53-eth0-rx-0-21swapper/707:06:149
3054950890irq/53-eth0-rx-0-21swapper/507:05:037
2548427162sleep100-21swapper/1007:05:512
2564726653sleep60-21swapper/607:07:598
2545726553sleep00-21swapper/007:05:300
25998993029cyclictest3054950irq/53-eth0-rx-10:10:353
25998993029cyclictest3054950irq/53-eth0-rx-10:10:343
25968993028cyclictest3055050irq/54-eth0-tx-10:10:384
25968993028cyclictest3055050irq/54-eth0-tx-10:10:374
25994992928cyclictest3054950irq/53-eth0-rx-10:10:359
25994992928cyclictest3054950irq/53-eth0-rx-10:10:349
25957992928cyclictest3054950irq/53-eth0-rx-10:10:321
25957992928cyclictest3054950irq/53-eth0-rx-10:10:321
25995992827cyclictest3055050irq/54-eth0-tx-10:10:3310
25995992827cyclictest3055050irq/54-eth0-tx-10:10:3310
25998992116cyclictest0-21swapper/1110:08:453
25956992018cyclictest0-21swapper/010:10:340
25956992018cyclictest0-21swapper/010:10:330
2599799192cyclictest3054950irq/53-eth0-rx-12:28:552
2599799192cyclictest3054950irq/53-eth0-rx-11:05:352
2599799192cyclictest3054950irq/53-eth0-rx-10:27:272
25956991917cyclictest0-21swapper/010:08:440
2595699190cyclictest0-21swapper/009:12:330
2599799184cyclictest0-21swapper/1008:25:162
2599799181cyclictest3055050irq/54-eth0-tx-09:53:102
2599799181cyclictest3055050irq/54-eth0-tx-09:18:362
2599799181cyclictest3054950irq/53-eth0-rx-12:12:262
2599799181cyclictest3054950irq/53-eth0-rx-11:35:442
2599799181cyclictest3054950irq/53-eth0-rx-11:21:562
2599799181cyclictest3054950irq/53-eth0-rx-10:40:542
2599799181cyclictest3054950irq/53-eth0-rx-10:37:532
2599799181cyclictest3054950irq/53-eth0-rx-10:33:562
2599799181cyclictest3054950irq/53-eth0-rx-09:46:582
2599799181cyclictest3054950irq/53-eth0-rx-09:10:072
2599699181cyclictest761ksoftirqd/907:50:2411
2599699181cyclictest19801-21perl10:55:1411
2599699181cyclictest12-21rcu_preempt07:20:2111
2599699181cyclictest0-21swapper/912:35:5611
2599699181cyclictest0-21swapper/912:26:0911
2599699181cyclictest0-21swapper/912:20:2111
2599699181cyclictest0-21swapper/912:15:5411
2599699181cyclictest0-21swapper/912:08:1411
2599699181cyclictest0-21swapper/912:01:4211
2599699181cyclictest0-21swapper/911:48:5411
2599699181cyclictest0-21swapper/911:30:1311
2599699181cyclictest0-21swapper/911:24:2611
2599699181cyclictest0-21swapper/911:00:3611
2599699181cyclictest0-21swapper/910:45:2011
2599699181cyclictest0-21swapper/910:31:1811
2599699181cyclictest0-21swapper/910:17:2011
2599699181cyclictest0-21swapper/910:13:4611
2599699181cyclictest0-21swapper/910:13:4511
2599699181cyclictest0-21swapper/909:35:4611
25993991816cyclictest25715-21qemu-kvm07:30:138
25993991816cyclictest25715-21qemu-kvm07:20:118
25993991816cyclictest25715-21qemu-kvm07:19:328
2595699185cyclictest0-21swapper/010:25:220
25956991816cyclictest172882sleep008:24:380
25997991716cyclictest0-21swapper/1011:45:462
2599799170cyclictest99082chrt12:05:262
2599799170cyclictest96912chrt08:10:332
2599799170cyclictest65432chrt08:50:502
2599799170cyclictest63382sleep1009:25:182
2599799170cyclictest63272chrt07:25:062
2599799170cyclictest63102sleep1008:09:102
2599799170cyclictest55482sleep1007:21:282
2599799170cyclictest46132sleep1010:15:362
2599799170cyclictest4162sleep1007:15:152
2599799170cyclictest311832chrt07:57:562
2599799170cyclictest307862chrt09:20:062
2599799170cyclictest305952sleep1011:55:372
2599799170cyclictest3055050irq/54-eth0-tx-11:51:042
2599799170cyclictest3055050irq/54-eth0-tx-10:23:202
2599799170cyclictest3054950irq/53-eth0-rx-12:30:382
2599799170cyclictest3054950irq/53-eth0-rx-12:20:292
2599799170cyclictest3054950irq/53-eth0-rx-12:15:222
2599799170cyclictest3054950irq/53-eth0-rx-11:40:102
2599799170cyclictest3054950irq/53-eth0-rx-11:15:202
2599799170cyclictest3054950irq/53-eth0-rx-11:10:102
2599799170cyclictest3054950irq/53-eth0-rx-11:00:372
2599799170cyclictest3054950irq/53-eth0-rx-10:45:342
2599799170cyclictest3054950irq/53-eth0-rx-10:05:062
2599799170cyclictest3054950irq/53-eth0-rx-10:01:272
2599799170cyclictest3054950irq/53-eth0-rx-09:57:472
2599799170cyclictest3054950irq/53-eth0-rx-09:57:462
2599799170cyclictest3054950irq/53-eth0-rx-09:37:052
2599799170cyclictest29952sleep1008:47:272
2599799170cyclictest292492chrt07:10:402
2599799170cyclictest288432sleep1010:10:132
2599799170cyclictest288432sleep1010:10:122
2599799170cyclictest280142chrt08:36:362
2599799170cyclictest275432chrt07:52:572
2599799170cyclictest275272sleep1009:42:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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