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2026-02-02 - 13:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Feb 02, 2026 12:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501020irq/53-eth0-rx-0-21swapper/407:06:026
128501020irq/42-ahci0-21swapper/307:09:485
9918501000irq/53-eth0-rx-0-21swapper/207:05:234
991850980irq/53-eth0-rx-0-21swapper/107:06:161
12850960irq/42-ahci0-21swapper/907:05:1811
991850930irq/53-eth0-rx-0-21swapper/1107:05:063
307728882sleep80-21swapper/807:07:4110
172450810irq/56-eth1-rx-0-21swapper/707:07:299
991850800irq/53-eth0-rx-0-21swapper/507:05:227
301826965sleep100-21swapper/1007:06:552
3248826853sleep00-21swapper/007:05:080
293325955sleep60-21swapper/607:05:518
3453992710cyclictest831ksoftirqd/1012:25:192
3421992524cyclictest31ksoftirqd/010:17:560
3452992215cyclictest0-21swapper/910:05:3111
3452992214cyclictest13044-21diskmemload09:24:5011
345299221cyclictest0-21swapper/911:37:0011
345299220cyclictest991950irq/54-eth0-tx-09:40:3211
3452992115cyclictest23332-1kworker/9:0H07:40:4511
3452992114cyclictest18301-21chrt12:14:5311
3452992114cyclictest0-21swapper/910:38:2911
3452992114cyclictest0-21swapper/907:15:1611
3452992113cyclictest0-21swapper/912:30:2311
3452992113cyclictest0-21swapper/912:09:4011
3452992113cyclictest0-21swapper/910:46:2511
3452992113cyclictest0-21swapper/910:46:2511
3452992112cyclictest0-21swapper/909:48:4111
345299210cyclictest0-21swapper/908:26:3111
345299202cyclictest0-21swapper/911:18:1511
3452992014cyclictest0-21swapper/912:25:2611
3452992014cyclictest0-21swapper/910:10:0711
3452992013cyclictest0-21swapper/911:48:1211
3452992013cyclictest0-21swapper/911:30:2611
345299201cyclictest0-21swapper/912:19:4011
345299200cyclictest0-21swapper/912:22:2611
345299200cyclictest0-21swapper/911:26:5511
345299200cyclictest0-21swapper/910:23:1611
345299200cyclictest0-21swapper/909:27:3711
3451992018cyclictest7576-21fschecks_time11:10:1410
3451992018cyclictest3586-21fschecks_count08:35:1310
3451992018cyclictest19914-21fschecks_count12:15:1310
345399192cyclictest991850irq/53-eth0-rx-12:10:172
345399192cyclictest991850irq/53-eth0-rx-11:52:422
345399192cyclictest991850irq/53-eth0-rx-11:12:542
345399192cyclictest991850irq/53-eth0-rx-11:05:012
345399192cyclictest991850irq/53-eth0-rx-10:38:272
345399192cyclictest991850irq/53-eth0-rx-10:17:552
345399192cyclictest991850irq/53-eth0-rx-10:06:182
345399192cyclictest831ksoftirqd/1011:05:172
345399192cyclictest831ksoftirqd/1009:45:132
345299192cyclictest0-21swapper/911:59:3611
345299191cyclictest0-21swapper/907:13:2811
342199190cyclictest0-21swapper/010:08:450
3453991817cyclictest831ksoftirqd/1009:35:112
3453991817cyclictest831ksoftirqd/1007:40:012
3453991817cyclictest831ksoftirqd/1007:34:082
3453991817cyclictest12914-21snmp_rack3slot911:40:482
3453991817cyclictest0-21swapper/1012:34:282
3453991817cyclictest0-21swapper/1012:15:032
3453991817cyclictest0-21swapper/1012:07:392
3453991817cyclictest0-21swapper/1012:03:512
3453991817cyclictest0-21swapper/1011:47:472
3453991817cyclictest0-21swapper/1011:23:292
3453991817cyclictest0-21swapper/1010:58:562
3453991817cyclictest0-21swapper/1010:58:562
3453991817cyclictest0-21swapper/1010:50:562
3453991817cyclictest0-21swapper/1010:50:562
3453991817cyclictest0-21swapper/1010:46:302
3453991817cyclictest0-21swapper/1010:46:302
345399181cyclictest991950irq/54-eth0-tx-10:14:402
345399181cyclictest991950irq/54-eth0-tx-09:42:062
345399181cyclictest991850irq/53-eth0-rx-12:39:362
345399181cyclictest991850irq/53-eth0-rx-11:36:092
345399181cyclictest991850irq/53-eth0-rx-11:30:302
345399181cyclictest991850irq/53-eth0-rx-10:42:362
345399181cyclictest991850irq/53-eth0-rx-10:42:362
345399181cyclictest991850irq/53-eth0-rx-10:33:102
345399181cyclictest991850irq/53-eth0-rx-10:26:412
345399181cyclictest991850irq/53-eth0-rx-10:21:012
345399181cyclictest991850irq/53-eth0-rx-09:50:462
345399181cyclictest991850irq/53-eth0-rx-09:30:422
345399181cyclictest991850irq/53-eth0-rx-09:15:492
345399181cyclictest991850irq/53-eth0-rx-09:12:592
345399181cyclictest991850irq/53-eth0-rx-08:10:482
345399181cyclictest831ksoftirqd/1012:20:212
345399181cyclictest831ksoftirqd/1009:25:012
345399181cyclictest831ksoftirqd/1009:25:002
345399181cyclictest831ksoftirqd/1009:00:072
345399181cyclictest831ksoftirqd/1007:45:122
345399181cyclictest811rcuc/1011:55:152
345399181cyclictest12850irq/42-ahci11:18:272
345399181cyclictest12850irq/42-ahci08:47:352
345399180cyclictest12850irq/42-ahci07:56:292
345399180cyclictest12850irq/42-ahci07:16:062
345299181cyclictest23332-1kworker/9:0H07:57:3911
345299181cyclictest0-21swapper/912:37:0311
345299181cyclictest0-21swapper/912:04:0211
345299181cyclictest0-21swapper/911:21:5911
345299181cyclictest0-21swapper/911:11:2611
345299181cyclictest0-21swapper/911:05:2011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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