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2026-02-11 - 18:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Feb 11, 2026 12:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501160irq/42-ahci0-21swapper/307:09:075
128501130irq/42-ahci0-21swapper/107:09:121
128501120irq/42-ahci0-21swapper/807:09:0110
128501090irq/42-ahci0-21swapper/207:09:284
991850950irq/53-eth0-rx-0-21swapper/707:08:419
991850940irq/53-eth0-rx-0-21swapper/907:05:4311
991850940irq/53-eth0-rx-0-21swapper/507:06:257
991850900irq/53-eth0-rx-0-21swapper/1107:05:523
991850890irq/53-eth0-rx-0-21swapper/407:06:216
477428070sleep60-21swapper/607:07:058
504426664sleep100-21swapper/1007:09:582
179925753sleep00-21swapper/007:05:100
515299330cyclictest0-21swapper/009:23:570
5193993231cyclictest991850irq/53-eth0-rx-09:24:032
5194993125cyclictest991950irq/54-eth0-tx-09:24:043
12850300irq/42-ahci0-21swapper/909:24:1111
5184992927cyclictest991950irq/54-eth0-tx-09:24:017
515399291cyclictest0-21swapper/111:57:171
5170992827cyclictest12850irq/42-ahci09:24:105
5153992827cyclictest991850irq/53-eth0-rx-09:24:061
5163992625cyclictest991850irq/53-eth0-rx-09:23:564
5177992524cyclictest991850irq/53-eth0-rx-09:24:046
515299238cyclictest21262-21chrt08:11:160
5152992221cyclictest0-21swapper/007:22:080
5191992119cyclictest991950irq/54-eth0-tx-09:24:1510
515299210cyclictest0-21swapper/012:32:520
515299200cyclictest0-21swapper/011:32:420
519399195cyclictest0-21swapper/1012:00:012
519399192cyclictest991850irq/53-eth0-rx-12:11:062
519399192cyclictest991850irq/53-eth0-rx-11:40:532
519399192cyclictest991850irq/53-eth0-rx-11:17:502
519399192cyclictest991850irq/53-eth0-rx-11:10:442
519399192cyclictest991850irq/53-eth0-rx-10:44:172
519399192cyclictest991850irq/53-eth0-rx-10:01:092
519399192cyclictest991850irq/53-eth0-rx-09:47:252
519399192cyclictest991850irq/53-eth0-rx-09:40:202
519399192cyclictest991850irq/53-eth0-rx-09:32:382
519399192cyclictest991850irq/53-eth0-rx-09:32:372
519299192cyclictest0-21swapper/910:50:1011
519299192cyclictest0-21swapper/909:13:5911
519299192cyclictest0-21swapper/908:25:1111
5193991817cyclictest0-21swapper/1009:10:102
5193991817cyclictest0-21swapper/1007:26:392
5193991816cyclictest6115-21ssh12:26:582
5193991816cyclictest21664-21snmp_rack3slot908:55:372
519399181cyclictest991950irq/54-eth0-tx-10:49:152
519399181cyclictest991850irq/53-eth0-rx-12:36:132
519399181cyclictest991850irq/53-eth0-rx-12:30:382
519399181cyclictest991850irq/53-eth0-rx-12:19:452
519399181cyclictest991850irq/53-eth0-rx-12:07:032
519399181cyclictest991850irq/53-eth0-rx-11:50:522
519399181cyclictest991850irq/53-eth0-rx-11:35:182
519399181cyclictest991850irq/53-eth0-rx-11:31:362
519399181cyclictest991850irq/53-eth0-rx-11:26:582
519399181cyclictest991850irq/53-eth0-rx-11:20:162
519399181cyclictest991850irq/53-eth0-rx-11:05:512
519399181cyclictest991850irq/53-eth0-rx-10:56:292
519399181cyclictest991850irq/53-eth0-rx-10:39:592
519399181cyclictest991850irq/53-eth0-rx-10:31:232
519399181cyclictest991850irq/53-eth0-rx-10:11:392
519399181cyclictest991850irq/53-eth0-rx-10:07:072
519399181cyclictest991850irq/53-eth0-rx-09:50:482
519399181cyclictest991850irq/53-eth0-rx-09:36:332
519399181cyclictest991850irq/53-eth0-rx-09:25:392
519399181cyclictest991850irq/53-eth0-rx-08:15:182
519399181cyclictest991850irq/53-eth0-rx-07:24:402
519399181cyclictest12850irq/42-ahci09:08:472
519399181cyclictest12850irq/42-ahci09:08:472
519399181cyclictest12850irq/42-ahci08:47:312
519399181cyclictest107912chrt08:41:182
519299181cyclictest991850irq/53-eth0-rx-12:39:5511
519299181cyclictest16899-21kworker/9:110:10:4111
519299181cyclictest0-21swapper/912:29:2711
519299181cyclictest0-21swapper/911:57:1711
519299181cyclictest0-21swapper/911:45:1911
519299181cyclictest0-21swapper/911:15:1211
519299181cyclictest0-21swapper/910:27:3911
519299181cyclictest0-21swapper/910:24:4111
519299181cyclictest0-21swapper/909:37:3511
519299181cyclictest0-21swapper/909:25:1911
519299181cyclictest0-21swapper/908:30:3611
519299181cyclictest0-21swapper/907:15:1411
5189991816cyclictest17753-21qemu-kvm08:26:388
519499170cyclictest0-21swapper/1107:21:153
5193991716cyclictest0-21swapper/1012:00:022
5193991716cyclictest0-21swapper/1007:35:322
5193991715cyclictest9863-21snmp_rack3slot907:15:142
519399170cyclictest991850irq/53-eth0-rx-11:45:162
519399170cyclictest991850irq/53-eth0-rx-11:01:152
519399170cyclictest991850irq/53-eth0-rx-10:51:412
519399170cyclictest991850irq/53-eth0-rx-10:25:322
519399170cyclictest991850irq/53-eth0-rx-10:15:062
519399170cyclictest991850irq/53-eth0-rx-09:55:532
519399170cyclictest991850irq/53-eth0-rx-09:15:082
519399170cyclictest991850irq/53-eth0-rx-09:00:112
519399170cyclictest991850irq/53-eth0-rx-08:30:102
519399170cyclictest991850irq/53-eth0-rx-08:10:222
519399170cyclictest991850irq/53-eth0-rx-07:55:112
519399170cyclictest84772sleep1007:11:082
519399170cyclictest72972sleep1008:38:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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