You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-17 - 16:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Jan 17, 2026 12:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9919501160irq/54-eth0-tx-0-21swapper/107:07:001
9918501160irq/53-eth0-rx-0-21swapper/207:09:104
29593211296sleep80-21swapper/807:06:1710
29658210794sleep90-21swapper/907:07:0611
29611210492sleep110-21swapper/1107:06:323
29559210491sleep60-21swapper/607:05:518
991850960irq/53-eth0-rx-0-21swapper/307:05:135
991850920irq/53-eth0-rx-0-21swapper/407:08:046
991850910irq/53-eth0-rx-0-21swapper/707:05:319
119350910irq/18-parport00-21swapper/507:07:237
991850880irq/53-eth0-rx-0-21swapper/1007:06:222
2972025955sleep00-21swapper/007:07:580
3004799340cyclictest0-21swapper/008:10:380
3004799330cyclictest0-21swapper/009:21:170
991950280irq/54-eth0-tx-0-21swapper/909:21:1511
991850280irq/53-eth0-rx-0-21swapper/709:21:209
991850280irq/53-eth0-rx-0-21swapper/309:21:175
991850280irq/53-eth0-rx-0-21swapper/209:21:254
991850280irq/53-eth0-rx-0-21swapper/1009:21:222
991850280irq/53-eth0-rx-0-21swapper/109:21:291
3008599192cyclictest991850irq/53-eth0-rx-12:22:392
3008499192cyclictest21436-21gltestperf10:30:1311
30047991917cyclictest6092-21chrt07:18:090
30085991817cyclictest0-21swapper/1012:00:452
30085991816cyclictest17517-21munin-node10:00:122
3008599181cyclictest991950irq/54-eth0-tx-11:27:412
3008599181cyclictest991950irq/54-eth0-tx-11:27:402
3008599181cyclictest991950irq/54-eth0-tx-10:32:022
3008599181cyclictest991850irq/53-eth0-rx-12:07:432
3008599181cyclictest991850irq/53-eth0-rx-11:50:372
3008599181cyclictest991850irq/53-eth0-rx-11:40:192
3008599181cyclictest991850irq/53-eth0-rx-11:40:182
3008599181cyclictest991850irq/53-eth0-rx-11:35:142
3008599181cyclictest991850irq/53-eth0-rx-11:35:142
3008599181cyclictest991850irq/53-eth0-rx-11:23:392
3008599181cyclictest991850irq/53-eth0-rx-11:06:382
3008599181cyclictest991850irq/53-eth0-rx-10:59:072
3008599181cyclictest991850irq/53-eth0-rx-10:28:052
3008599181cyclictest991850irq/53-eth0-rx-10:16:592
3008599181cyclictest991850irq/53-eth0-rx-10:13:282
3008599181cyclictest991850irq/53-eth0-rx-09:38:272
3008599181cyclictest991850irq/53-eth0-rx-09:25:502
3008599181cyclictest991850irq/53-eth0-rx-09:15:192
3008599181cyclictest139272chrt08:13:132
3008499181cyclictest991950irq/54-eth0-tx-09:16:4311
3008499181cyclictest991850irq/53-eth0-rx-10:48:3911
3008499181cyclictest761ksoftirqd/911:45:2511
3008499181cyclictest761ksoftirqd/911:20:2411
3008499181cyclictest761ksoftirqd/911:12:5311
3008499181cyclictest761ksoftirqd/910:11:3611
3008499181cyclictest761ksoftirqd/907:35:1911
3008499181cyclictest741rcuc/912:13:0711
3008499181cyclictest741rcuc/910:07:0011
3008499181cyclictest0-21swapper/912:26:3811
3008499181cyclictest0-21swapper/911:40:0411
3008499181cyclictest0-21swapper/911:40:0311
3008499181cyclictest0-21swapper/911:38:3511
3008499181cyclictest0-21swapper/911:38:3511
3008499181cyclictest0-21swapper/911:30:0911
3008499181cyclictest0-21swapper/911:30:0911
3008499181cyclictest0-21swapper/911:16:3611
3008499181cyclictest0-21swapper/910:00:4711
3008499181cyclictest0-21swapper/909:50:1711
3008499181cyclictest0-21swapper/909:45:2911
3008499181cyclictest0-21swapper/909:33:4211
3008499181cyclictest0-21swapper/909:07:1611
3008499181cyclictest0-21swapper/907:47:2911
3006099180cyclictest0-21swapper/107:15:001
30047991817cyclictest991850irq/53-eth0-rx-10:28:070
991950170irq/54-eth0-tx-0-21swapper/409:21:206
30085991716cyclictest132192sleep1007:25:582
30085991716cyclictest0-21swapper/1010:40:022
30085991716cyclictest0-21swapper/1008:01:582
3008599170cyclictest991850irq/53-eth0-rx-12:35:082
3008599170cyclictest991850irq/53-eth0-rx-12:31:212
3008599170cyclictest991850irq/53-eth0-rx-12:26:342
3008599170cyclictest991850irq/53-eth0-rx-12:15:322
3008599170cyclictest991850irq/53-eth0-rx-12:10:212
3008599170cyclictest991850irq/53-eth0-rx-11:55:172
3008599170cyclictest991850irq/53-eth0-rx-11:45:092
3008599170cyclictest991850irq/53-eth0-rx-11:00:412
3008599170cyclictest991850irq/53-eth0-rx-10:50:472
3008599170cyclictest991850irq/53-eth0-rx-10:45:022
3008599170cyclictest991850irq/53-eth0-rx-10:21:172
3008599170cyclictest991850irq/53-eth0-rx-09:51:342
3008599170cyclictest991850irq/53-eth0-rx-09:46:082
3008599170cyclictest991850irq/53-eth0-rx-09:40:102
3008599170cyclictest991850irq/53-eth0-rx-09:10:142
3008599170cyclictest991850irq/53-eth0-rx-08:40:132
3008599170cyclictest991850irq/53-eth0-rx-08:35:422
3008599170cyclictest991850irq/53-eth0-rx-08:35:412
3008599170cyclictest991850irq/53-eth0-rx-07:43:062
3008599170cyclictest991850irq/53-eth0-rx-07:30:322
3008599170cyclictest9602sleep1007:11:552
3008599170cyclictest87822sleep1007:20:202
3008599170cyclictest77532chrt08:50:062
3008599170cyclictest77532chrt08:50:062
3008599170cyclictest69142sleep1008:45:552
3008599170cyclictest60552sleep1011:11:122
3008599170cyclictest44722sleep1007:15:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional