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2026-02-08 - 05:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Feb 08, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501180irq/53-eth0-rx-0-21swapper/819:09:0310
9918501180irq/53-eth0-rx-0-21swapper/119:09:521
128501130irq/42-ahci0-21swapper/319:09:295
9918501110irq/53-eth0-rx-0-21swapper/719:09:419
991850990irq/53-eth0-rx-0-21swapper/219:06:554
429529082sleep90-21swapper/919:07:1111
991850890irq/53-eth0-rx-0-21swapper/1019:07:512
991850870irq/53-eth0-rx-0-21swapper/519:07:217
991850870irq/53-eth0-rx-0-21swapper/1119:08:103
991850860irq/53-eth0-rx-0-21swapper/419:06:156
83025853sleep00-21swapper/019:05:020
426325853sleep60-21swapper/619:06:448
467799320cyclictest0-21swapper/021:16:000
4677993114cyclictest0-21swapper/021:26:410
470699280cyclictest0-21swapper/1120:10:033
470699280cyclictest0-21swapper/1120:10:033
470699280cyclictest0-21swapper/1120:09:593
467799230cyclictest0-21swapper/023:10:210
467799220cyclictest0-21swapper/023:45:210
467799213cyclictest0-21swapper/022:14:040
467799210cyclictest0-21swapper/023:55:220
467799210cyclictest0-21swapper/021:20:210
467799210cyclictest0-21swapper/020:30:240
4677992018cyclictest0-21swapper/022:08:300
467799200cyclictest0-21swapper/021:10:220
467799200cyclictest0-21swapper/020:45:030
467799200cyclictest0-21swapper/019:14:450
467799200cyclictest0-21swapper/000:20:450
470599192cyclictest991850irq/53-eth0-rx-23:37:122
470599192cyclictest991850irq/53-eth0-rx-23:28:412
470599192cyclictest991850irq/53-eth0-rx-23:28:412
470599192cyclictest991850irq/53-eth0-rx-23:01:342
470599192cyclictest991850irq/53-eth0-rx-22:51:202
470599192cyclictest991850irq/53-eth0-rx-22:37:342
470599192cyclictest991850irq/53-eth0-rx-22:25:302
470599192cyclictest991850irq/53-eth0-rx-21:53:022
470599192cyclictest991850irq/53-eth0-rx-21:45:042
470599192cyclictest991850irq/53-eth0-rx-19:18:082
470599192cyclictest991850irq/53-eth0-rx-00:11:072
470599192cyclictest991850irq/53-eth0-rx-00:08:472
470499192cyclictest0-21swapper/923:57:2711
470499192cyclictest0-21swapper/923:36:3111
470499192cyclictest0-21swapper/921:52:3511
470499192cyclictest0-21swapper/900:31:3111
4677991917cyclictest312962chrt20:29:460
4677991917cyclictest2308-21snmpd20:10:460
4677991917cyclictest2308-21snmpd20:10:460
4677991915cyclictest0-21swapper/022:25:220
467799190cyclictest0-21swapper/023:15:230
467799190cyclictest0-21swapper/023:15:230
467799190cyclictest0-21swapper/022:55:280
467799190cyclictest0-21swapper/020:19:580
467799190cyclictest0-21swapper/019:30:210
467799190cyclictest0-21swapper/000:10:200
4705991817cyclictest0-21swapper/1021:15:382
4705991817cyclictest0-21swapper/1020:19:132
470599181cyclictest991950irq/54-eth0-tx-23:30:092
470599181cyclictest991950irq/54-eth0-tx-22:05:182
470599181cyclictest991950irq/54-eth0-tx-22:02:592
470599181cyclictest991850irq/53-eth0-rx-23:56:512
470599181cyclictest991850irq/53-eth0-rx-23:54:172
470599181cyclictest991850irq/53-eth0-rx-23:54:162
470599181cyclictest991850irq/53-eth0-rx-23:45:502
470599181cyclictest991850irq/53-eth0-rx-23:15:072
470599181cyclictest991850irq/53-eth0-rx-23:15:072
470599181cyclictest991850irq/53-eth0-rx-23:14:312
470599181cyclictest991850irq/53-eth0-rx-22:55:472
470599181cyclictest991850irq/53-eth0-rx-22:46:112
470599181cyclictest991850irq/53-eth0-rx-22:32:162
470599181cyclictest991850irq/53-eth0-rx-22:20:032
470599181cyclictest991850irq/53-eth0-rx-22:16:522
470599181cyclictest991850irq/53-eth0-rx-21:55:482
470599181cyclictest991850irq/53-eth0-rx-21:42:512
470599181cyclictest991850irq/53-eth0-rx-21:35:102
470599181cyclictest991850irq/53-eth0-rx-21:31:062
470599181cyclictest991850irq/53-eth0-rx-21:20:132
470599181cyclictest991850irq/53-eth0-rx-21:12:242
470599181cyclictest991850irq/53-eth0-rx-00:37:152
470599181cyclictest991850irq/53-eth0-rx-00:30:442
470599181cyclictest991850irq/53-eth0-rx-00:20:342
470599181cyclictest991850irq/53-eth0-rx-00:00:122
470599181cyclictest12850irq/42-ahci23:40:132
470599181cyclictest12850irq/42-ahci23:40:132
470599181cyclictest12850irq/42-ahci20:30:282
470599181cyclictest12850irq/42-ahci20:08:332
470499181cyclictest991850irq/53-eth0-rx-22:10:3211
470499181cyclictest991850irq/53-eth0-rx-21:22:3411
470499181cyclictest6494-21sh00:01:2911
470499181cyclictest3478-21rm23:31:2511
470499181cyclictest0-21swapper/923:47:4011
470499181cyclictest0-21swapper/923:41:0911
470499181cyclictest0-21swapper/923:41:0911
470499181cyclictest0-21swapper/923:13:4311
470499181cyclictest0-21swapper/922:53:0011
470499181cyclictest0-21swapper/922:41:3011
470499181cyclictest0-21swapper/922:36:5111
470499181cyclictest0-21swapper/922:21:0311
470499181cyclictest0-21swapper/922:08:2611
470499181cyclictest0-21swapper/921:31:5211
470499181cyclictest0-21swapper/921:17:2611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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