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2025-11-27 - 07:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Nov 27, 2025 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16520210892sleep00-21swapper/019:05:510
16693210795sleep30-21swapper/319:08:065
16608210694sleep70-21swapper/719:06:589
16611210390sleep100-21swapper/1019:07:012
3066350980irq/52-eth0-rx-0-21swapper/519:05:237
3066450960irq/53-eth0-tx-0-21swapper/919:05:1311
3066350960irq/52-eth0-rx-0-21swapper/119:05:161
12250960irq/42-ahci0-21swapper/219:09:224
3066350870irq/52-eth0-rx-0-21swapper/419:05:306
1663727364sleep80-21swapper/819:07:2310
124050650irq/18-i801_smb0-21swapper/1119:05:263
1662125955sleep60-21swapper/619:07:098
1698999320cyclictest0-21swapper/021:14:450
17031993014cyclictest0-21swapper/1119:15:473
1698999290cyclictest0-21swapper/022:26:040
1698999290cyclictest0-21swapper/019:13:120
12250280irq/42-ahci0-21swapper/1022:26:022
17029992214cyclictest0-21swapper/923:40:0111
17029992214cyclictest0-21swapper/923:40:0011
17029992114cyclictest0-21swapper/922:43:4411
17029992114cyclictest0-21swapper/922:10:1811
17029992114cyclictest0-21swapper/922:07:5711
17029992114cyclictest0-21swapper/922:02:1311
17029992114cyclictest0-21swapper/921:59:4911
17029992114cyclictest0-21swapper/920:02:3411
17029992114cyclictest0-21swapper/900:38:1211
17029992114cyclictest0-21swapper/900:32:0211
17029992114cyclictest0-21swapper/900:23:3611
17029992113cyclictest0-21swapper/921:22:1011
17029992014cyclictest0-21swapper/922:30:5711
17029992014cyclictest0-21swapper/922:22:2711
17029992014cyclictest0-21swapper/921:34:1511
17029992014cyclictest0-21swapper/920:45:1011
17029992014cyclictest0-21swapper/920:23:2411
17029992014cyclictest0-21swapper/920:16:2111
17029992014cyclictest0-21swapper/919:51:4811
17029992013cyclictest0-21swapper/923:00:0611
17029992013cyclictest0-21swapper/920:43:5511
17029992013cyclictest0-21swapper/920:31:5211
17029992013cyclictest0-21swapper/920:27:2711
17029992013cyclictest0-21swapper/920:14:2711
17029992013cyclictest0-21swapper/919:19:2711
1703099192cyclictest87522chrt20:25:092
17029991913cyclictest0-21swapper/922:46:5411
17029991913cyclictest0-21swapper/922:38:1211
17029991913cyclictest0-21swapper/919:28:5611
1703099181cyclictest3066350irq/52-eth0-rx-20:40:142
17029991812cyclictest0-21swapper/923:32:4811
1702999181cyclictest0-21swapper/923:56:2911
1702999181cyclictest0-21swapper/923:56:2811
1702999181cyclictest0-21swapper/923:05:2311
17028991816cyclictest404-21snmp_easybox.os21:50:1110
17028991816cyclictest30605-21snmp_rack3slot922:30:1610
17028991816cyclictest29569-21df_inode21:00:1310
17028991816cyclictest26946-21snmp_rack3slot919:20:1710
17028991816cyclictest24102-21df_inode23:50:1610
17028991816cyclictest2259-21snmp_rack3slot920:15:1510
17028991816cyclictest2065-21snmp_rack3slot919:30:1410
17028991816cyclictest19958-21snmp_easybox.os21:30:2310
17028991816cyclictest18518-21snmp_rack3slot900:25:2510
17028991816cyclictest13023-21snmp_easybox.os21:20:2410
17028991816cyclictest11649-21snmp_easybox.os20:30:1910
17028991816cyclictest10279-21ntp_states19:40:2310
1702699183cyclictest0-21swapper/620:24:028
1703199170cyclictest0-21swapper/1120:30:083
17030991716cyclictest65352sleep1021:10:512
17030991716cyclictest242282sleep1020:50:372
17030991716cyclictest0-21swapper/1023:45:562
17030991716cyclictest0-21swapper/1021:35:172
17030991715cyclictest25456-21python23:50:292
1703099170cyclictest9672chrt00:01:462
1703099170cyclictest9672chrt00:01:452
1703099170cyclictest83062chrt00:11:222
1703099170cyclictest83062chrt00:11:222
1703099170cyclictest831ksoftirqd/1019:30:142
1703099170cyclictest80772chrt20:22:572
1703099170cyclictest79772sleep1023:27:192
1703099170cyclictest7822sleep1020:14:072
1703099170cyclictest69792sleep1021:56:192
1703099170cyclictest68522sleep1022:40:242
1703099170cyclictest4902chrt23:15:522
1703099170cyclictest45152chrt23:24:402
1703099170cyclictest42932sleep1020:15:552
1703099170cyclictest34252sleep1021:52:192
1703099170cyclictest322962chrt21:49:312
1703099170cyclictest3066350irq/52-eth0-rx-23:37:032
1703099170cyclictest3066350irq/52-eth0-rx-23:37:022
1703099170cyclictest3066350irq/52-eth0-rx-22:30:202
1703099170cyclictest3066350irq/52-eth0-rx-22:10:132
1703099170cyclictest3066350irq/52-eth0-rx-19:55:222
1703099170cyclictest3066350irq/52-eth0-rx-19:14:242
1703099170cyclictest297702chrt23:56:582
1703099170cyclictest297702chrt23:56:572
1703099170cyclictest294732chrt23:12:512
1703099170cyclictest289902chrt19:22:382
1703099170cyclictest286932sleep1020:05:312
1703099170cyclictest283872sleep1021:40:542
1703099170cyclictest282682sleep1021:00:012
1703099170cyclictest280362sleep1020:58:002
1703099170cyclictest27932sleep1021:05:372
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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