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2026-06-15 - 03:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Jun 15, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501130irq/53-eth0-rx-0-21swapper/119:09:561
10255210891sleep00-21swapper/019:08:050
10310210695sleep70-21swapper/719:08:119
122501010irq/42-ahci0-21swapper/819:08:5410
12250980irq/42-ahci0-21swapper/319:08:155
1008729887sleep60-21swapper/619:05:598
3055050950irq/54-eth0-tx-0-21swapper/1019:07:242
12250940irq/42-ahci0-21swapper/219:06:284
3054950930irq/53-eth0-rx-0-21swapper/919:05:1411
3054950930irq/53-eth0-rx-0-21swapper/419:07:136
3054950680irq/53-eth0-rx-0-21swapper/519:06:037
3054950620irq/53-eth0-rx-0-21swapper/1119:05:183
10552994544cyclictest0-21swapper/022:14:370
10594993920cyclictest0-21swapper/1120:12:023
10552993914cyclictest0-21swapper/020:09:460
10552992914cyclictest0-21swapper/020:10:010
3054950280irq/53-eth0-rx-0-21swapper/722:14:339
3054950280irq/53-eth0-rx-0-21swapper/222:14:324
12250280irq/42-ahci0-21swapper/422:14:306
10594992726cyclictest0-21swapper/1121:13:183
1059299240cyclictest0-21swapper/900:24:5511
10594992120cyclictest0-21swapper/1120:19:233
1059399192cyclictest3054950irq/53-eth0-rx-23:10:162
1055299190cyclictest0-21swapper/021:17:550
1059399181cyclictest3055050irq/54-eth0-tx-00:22:152
1059399181cyclictest3054950irq/53-eth0-rx-23:51:502
1059399181cyclictest3054950irq/53-eth0-rx-23:46:162
1059399181cyclictest3054950irq/53-eth0-rx-23:07:532
1059399181cyclictest3054950irq/53-eth0-rx-21:10:272
1059399181cyclictest3054950irq/53-eth0-rx-00:11:452
1059399181cyclictest12250irq/42-ahci23:28:402
1059399181cyclictest12250irq/42-ahci22:47:342
1059399181cyclictest12250irq/42-ahci20:00:122
1059299181cyclictest13386-21smartctl23:05:2511
1059299181cyclictest0-21swapper/923:21:0211
1059299181cyclictest0-21swapper/923:15:1211
1059299181cyclictest0-21swapper/922:44:0311
1059299181cyclictest0-21swapper/922:44:0311
1059299181cyclictest0-21swapper/922:39:3711
1059299181cyclictest0-21swapper/921:55:1111
1059299180cyclictest0-21swapper/920:40:1411
10554991816cyclictest14258-21snmp_rack3slot920:40:134
3055050170irq/54-eth0-tx-8521-21qemu-kvm22:14:347
3055050170irq/54-eth0-tx-0-21swapper/922:14:3511
10594991715cyclictest18192sleep1120:24:593
1059399170cyclictest3055050irq/54-eth0-tx-23:56:202
1059399170cyclictest3055050irq/54-eth0-tx-23:35:272
1059399170cyclictest3055050irq/54-eth0-tx-23:31:032
1059399170cyclictest3055050irq/54-eth0-tx-22:55:182
1059399170cyclictest3055050irq/54-eth0-tx-22:35:582
1059399170cyclictest3055050irq/54-eth0-tx-22:32:232
1059399170cyclictest3055050irq/54-eth0-tx-22:32:232
1059399170cyclictest3055050irq/54-eth0-tx-22:23:132
1059399170cyclictest3055050irq/54-eth0-tx-22:12:292
1059399170cyclictest3055050irq/54-eth0-tx-21:45:162
1059399170cyclictest3055050irq/54-eth0-tx-21:20:572
1059399170cyclictest3055050irq/54-eth0-tx-00:27:592
1059399170cyclictest3055050irq/54-eth0-tx-00:15:232
1059399170cyclictest3055050irq/54-eth0-tx-00:01:252
1059399170cyclictest3054950irq/53-eth0-rx-23:40:582
1059399170cyclictest3054950irq/53-eth0-rx-23:21:092
1059399170cyclictest3054950irq/53-eth0-rx-23:18:252
1059399170cyclictest3054950irq/53-eth0-rx-23:00:412
1059399170cyclictest3054950irq/53-eth0-rx-22:40:182
1059399170cyclictest3054950irq/53-eth0-rx-22:40:182
1059399170cyclictest3054950irq/53-eth0-rx-22:27:362
1059399170cyclictest3054950irq/53-eth0-rx-22:16:582
1059399170cyclictest3054950irq/53-eth0-rx-22:16:582
1059399170cyclictest3054950irq/53-eth0-rx-22:07:082
1059399170cyclictest3054950irq/53-eth0-rx-22:01:082
1059399170cyclictest3054950irq/53-eth0-rx-21:50:062
1059399170cyclictest3054950irq/53-eth0-rx-21:42:202
1059399170cyclictest3054950irq/53-eth0-rx-21:36:562
1059399170cyclictest3054950irq/53-eth0-rx-21:30:122
1059399170cyclictest3054950irq/53-eth0-rx-21:25:112
1059399170cyclictest3054950irq/53-eth0-rx-21:15:092
1059399170cyclictest3054950irq/53-eth0-rx-20:47:322
1059399170cyclictest3054950irq/53-eth0-rx-20:16:362
1059399170cyclictest3054950irq/53-eth0-rx-19:48:332
1059399170cyclictest3054950irq/53-eth0-rx-19:17:442
1059399170cyclictest3054950irq/53-eth0-rx-19:11:142
1059399170cyclictest3054950irq/53-eth0-rx-00:37:422
1059399170cyclictest3054950irq/53-eth0-rx-00:06:152
1059399170cyclictest12250irq/42-ahci20:08:512
1059399170cyclictest12250irq/42-ahci19:25:352
1059399170cyclictest12250irq/42-ahci19:25:342
1059299173cyclictest0-21swapper/922:52:5611
10592991716cyclictest0-21swapper/923:02:3111
10592991715cyclictest28998-21needreboot21:30:2011
10592991715cyclictest17133-21ssh21:48:3011
1059299171cyclictest0-21swapper/920:25:1311
1059299171cyclictest0-21swapper/919:30:1511
1059299170cyclictest3054950irq/53-eth0-rx-23:45:0511
1059299170cyclictest0-21swapper/923:51:5611
1059299170cyclictest0-21swapper/922:45:0311
1059299170cyclictest0-21swapper/900:30:2511
1059299170cyclictest0-21swapper/900:25:2111
1059299170cyclictest0-21swapper/900:14:0911
1055799171cyclictest0-21swapper/320:20:205
1055499171cyclictest0-21swapper/221:55:194
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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