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2026-02-01 - 06:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Feb 01, 2026 00:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501090irq/53-eth0-rx-0-21swapper/219:09:144
18928210895sleep90-21swapper/919:07:1511
9918501070irq/53-eth0-rx-0-21swapper/419:07:286
12850980irq/42-ahci0-21swapper/119:09:541
12850960irq/42-ahci0-21swapper/319:08:555
991850910irq/53-eth0-rx-0-21swapper/819:05:3110
991850900irq/53-eth0-rx-0-21swapper/719:07:129
991850900irq/53-eth0-rx-0-21swapper/519:06:257
1884929079sleep100-21swapper/1019:06:162
1891027161sleep60-21swapper/619:06:598
1883725955sleep00-21swapper/019:06:050
1885125853sleep110-21swapper/1119:06:163
1933599300cyclictest105182sleep1122:30:023
1931199280cyclictest0-21swapper/123:56:301
19311992726cyclictest991850irq/53-eth0-rx-21:29:211
19326992521cyclictest2805-21snmp_rack3slot923:15:585
19326992521cyclictest2805-21snmp_rack3slot923:15:585
19326992319cyclictest12129-21ssh22:04:295
1930599238cyclictest0-21swapper/022:16:330
19326992016cyclictest14871-21ssh21:10:515
1933499192cyclictest991850irq/53-eth0-rx-23:52:252
1933499192cyclictest991850irq/53-eth0-rx-23:18:572
1933499192cyclictest991850irq/53-eth0-rx-23:18:572
1933499192cyclictest991850irq/53-eth0-rx-23:10:512
1933499192cyclictest991850irq/53-eth0-rx-23:06:202
1933499192cyclictest991850irq/53-eth0-rx-22:50:382
1933499192cyclictest991850irq/53-eth0-rx-22:35:142
1933499192cyclictest991850irq/53-eth0-rx-22:31:392
1933499192cyclictest991850irq/53-eth0-rx-22:17:472
1933499192cyclictest991850irq/53-eth0-rx-22:13:112
1933499192cyclictest991850irq/53-eth0-rx-21:58:562
1933499192cyclictest991850irq/53-eth0-rx-00:36:522
1933499192cyclictest991850irq/53-eth0-rx-00:16:492
1933499192cyclictest991850irq/53-eth0-rx-00:13:532
1933499192cyclictest991850irq/53-eth0-rx-00:06:012
1933399192cyclictest0-21swapper/923:52:2411
1933399192cyclictest0-21swapper/923:36:4911
1933399192cyclictest0-21swapper/922:55:2711
1933399192cyclictest0-21swapper/921:36:0111
1933399192cyclictest0-21swapper/900:32:2711
19326991915cyclictest7859-21snmp_rack3slot900:17:015
19334991817cyclictest0-21swapper/1023:03:302
19334991817cyclictest0-21swapper/1021:22:292
19334991816cyclictest13867-21df_inode22:05:122
1933499181cyclictest991950irq/54-eth0-tx-23:42:002
1933499181cyclictest991950irq/54-eth0-tx-23:41:592
1933499181cyclictest991850irq/53-eth0-rx-23:30:482
1933499181cyclictest991850irq/53-eth0-rx-23:24:382
1933499181cyclictest991850irq/53-eth0-rx-22:57:082
1933499181cyclictest991850irq/53-eth0-rx-22:45:322
1933499181cyclictest991850irq/53-eth0-rx-22:43:092
1933499181cyclictest991850irq/53-eth0-rx-22:26:222
1933499181cyclictest991850irq/53-eth0-rx-22:20:342
1933499181cyclictest991850irq/53-eth0-rx-22:00:512
1933499181cyclictest991850irq/53-eth0-rx-21:45:492
1933499181cyclictest991850irq/53-eth0-rx-21:41:002
1933499181cyclictest991850irq/53-eth0-rx-21:38:102
1933499181cyclictest991850irq/53-eth0-rx-21:26:332
1933499181cyclictest991850irq/53-eth0-rx-21:10:172
1933499181cyclictest991850irq/53-eth0-rx-00:31:262
1933499181cyclictest991850irq/53-eth0-rx-00:29:452
1933499181cyclictest991850irq/53-eth0-rx-00:21:502
1933499181cyclictest53452chrt23:45:222
1933499181cyclictest12850irq/42-ahci23:58:102
1933499181cyclictest12850irq/42-ahci20:28:522
1933499180cyclictest991850irq/53-eth0-rx-00:02:202
1933399181cyclictest991950irq/54-eth0-tx-23:43:2311
1933399181cyclictest991950irq/54-eth0-tx-23:43:2211
1933399181cyclictest22306-21cpuspeed_turbos20:40:1011
1933399181cyclictest0-21swapper/923:34:3911
1933399181cyclictest0-21swapper/923:27:0611
1933399181cyclictest0-21swapper/923:18:2511
1933399181cyclictest0-21swapper/923:18:2411
1933399181cyclictest0-21swapper/923:03:5311
1933399181cyclictest0-21swapper/922:54:2811
1933399181cyclictest0-21swapper/922:25:2111
1933399181cyclictest0-21swapper/922:23:1011
1933399181cyclictest0-21swapper/922:05:0111
1933399181cyclictest0-21swapper/921:57:0111
1933399181cyclictest0-21swapper/900:37:5411
991950170irq/54-eth0-tx-0-21swapper/221:11:554
19334991716cyclictest0-21swapper/1021:15:062
19334991716cyclictest0-21swapper/1019:50:432
1933499170cyclictest991850irq/53-eth0-rx-23:25:102
1933499170cyclictest991850irq/53-eth0-rx-21:50:232
1933499170cyclictest991850irq/53-eth0-rx-21:30:002
1933499170cyclictest991850irq/53-eth0-rx-21:05:192
1933499170cyclictest991850irq/53-eth0-rx-21:00:322
1933499170cyclictest991850irq/53-eth0-rx-20:50:522
1933499170cyclictest991850irq/53-eth0-rx-20:50:522
1933499170cyclictest991850irq/53-eth0-rx-20:41:102
1933499170cyclictest991850irq/53-eth0-rx-20:35:162
1933499170cyclictest991850irq/53-eth0-rx-20:21:002
1933499170cyclictest991850irq/53-eth0-rx-19:57:002
1933499170cyclictest991850irq/53-eth0-rx-19:35:162
1933499170cyclictest991850irq/53-eth0-rx-19:30:132
1933499170cyclictest991850irq/53-eth0-rx-19:25:382
1933499170cyclictest991850irq/53-eth0-rx-19:10:142
1933499170cyclictest38032sleep1020:15:092
1933499170cyclictest34252sleep1020:55:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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