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2026-08-15 - 08:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Aug 15, 2026 00:46:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501150irq/53-eth0-rx-0-21swapper/119:09:261
122501130irq/42-ahci0-21swapper/219:09:084
32311210995sleep100-21swapper/1019:05:562
32444210293sleep40-21swapper/419:07:396
3054950980irq/53-eth0-rx-0-21swapper/1119:07:133
3054950960irq/53-eth0-rx-0-21swapper/519:07:087
3054950900irq/53-eth0-rx-0-21swapper/319:07:215
114150900irq/18-i801_smb0-21swapper/819:09:3510
119150860irq/18-parport00-21swapper/919:09:3411
3055050740irq/54-eth0-tx-0-21swapper/019:05:370
3054950730irq/53-eth0-rx-0-21swapper/719:05:129
3235026553sleep60-21swapper/619:06:298
351993617cyclictest0-21swapper/1120:09:053
32699280cyclictest0-21swapper/021:13:590
347992726cyclictest15710-21ssh21:27:309
345992725cyclictest24582-21qemu-kvm21:09:177
326992726cyclictest12250irq/42-ahci21:09:130
348992625cyclictest3054950irq/53-eth0-rx-21:09:2410
326992221cyclictest0-21swapper/022:20:010
32699220cyclictest0-21swapper/019:30:080
35099192cyclictest3054950irq/53-eth0-rx-20:15:212
35099192cyclictest3054950irq/53-eth0-rx-00:31:552
35099192cyclictest3054950irq/53-eth0-rx-00:23:592
35099192cyclictest3054950irq/53-eth0-rx-00:04:402
34999192cyclictest0-21swapper/923:39:4911
34999192cyclictest0-21swapper/922:07:2011
34999192cyclictest0-21swapper/922:00:3911
34699195cyclictest0-21swapper/600:05:188
350991817cyclictest1666-21ssh21:42:082
350991817cyclictest10701-21kworker/10:222:46:432
350991817cyclictest0-21swapper/1023:52:172
350991817cyclictest0-21swapper/1023:31:212
350991817cyclictest0-21swapper/1022:00:122
350991817cyclictest0-21swapper/1019:16:192
35099181cyclictest3055050irq/54-eth0-tx-23:56:222
35099181cyclictest3055050irq/54-eth0-tx-21:45:062
35099181cyclictest3055050irq/54-eth0-tx-21:32:232
35099181cyclictest3054950irq/53-eth0-rx-23:45:032
35099181cyclictest3054950irq/53-eth0-rx-23:38:092
35099181cyclictest3054950irq/53-eth0-rx-23:28:432
35099181cyclictest3054950irq/53-eth0-rx-23:20:192
35099181cyclictest3054950irq/53-eth0-rx-23:10:382
35099181cyclictest3054950irq/53-eth0-rx-23:09:002
35099181cyclictest3054950irq/53-eth0-rx-23:04:392
35099181cyclictest3054950irq/53-eth0-rx-22:54:452
35099181cyclictest3054950irq/53-eth0-rx-22:41:422
35099181cyclictest3054950irq/53-eth0-rx-22:26:032
35099181cyclictest3054950irq/53-eth0-rx-22:22:412
35099181cyclictest3054950irq/53-eth0-rx-22:15:032
35099181cyclictest3054950irq/53-eth0-rx-22:11:402
35099181cyclictest3054950irq/53-eth0-rx-22:08:232
35099181cyclictest3054950irq/53-eth0-rx-21:35:242
35099181cyclictest3054950irq/53-eth0-rx-21:22:212
35099181cyclictest3054950irq/53-eth0-rx-21:15:412
35099181cyclictest3054950irq/53-eth0-rx-21:10:122
35099181cyclictest3054950irq/53-eth0-rx-19:59:522
35099181cyclictest3054950irq/53-eth0-rx-00:15:282
35099181cyclictest3054950irq/53-eth0-rx-00:06:492
35099181cyclictest12250irq/42-ahci19:44:112
349991816cyclictest32246-21cstates_1121:15:1311
34999181cyclictest761ksoftirqd/923:55:0111
34999181cyclictest761ksoftirqd/922:10:0211
34999181cyclictest761ksoftirqd/920:55:1611
34999181cyclictest761ksoftirqd/900:00:2711
34999181cyclictest4603-21gltestperf20:40:1411
34999181cyclictest3054950irq/53-eth0-rx-21:23:3711
34999181cyclictest29333-21irqstats19:45:1411
34999181cyclictest19225-21ssh22:49:3711
34999181cyclictest0-21swapper/923:58:2711
34999181cyclictest0-21swapper/923:05:4211
34999181cyclictest0-21swapper/923:04:0511
34999181cyclictest0-21swapper/922:39:0411
34999181cyclictest0-21swapper/921:30:2811
34999181cyclictest0-21swapper/921:14:5411
34999181cyclictest0-21swapper/920:26:2211
34999181cyclictest0-21swapper/920:15:1211
34999181cyclictest0-21swapper/920:05:2311
34999181cyclictest0-21swapper/900:38:0211
34999181cyclictest0-21swapper/900:17:0811
34999181cyclictest0-21swapper/900:06:5111
346991816cyclictest13050-21qemu-kvm20:47:268
346991816cyclictest13050-21qemu-kvm20:15:128
346991816cyclictest13049-21qemu-kvm20:40:128
346991816cyclictest13049-21qemu-kvm20:34:468
346991816cyclictest13049-21qemu-kvm20:12:548
346991816cyclictest13049-21qemu-kvm20:08:258
346991816cyclictest1019-21qemu-kvm22:12:228
32699182cyclictest0-21swapper/022:10:250
326991817cyclictest16622-21chrt20:12:050
326991817cyclictest0-21swapper/020:22:110
32699180cyclictest0-21swapper/019:30:000
350991716cyclictest0-21swapper/1020:21:042
350991716cyclictest0-21swapper/1020:07:502
35099170cyclictest97832sleep1020:46:452
35099170cyclictest91502sleep1020:00:502
35099170cyclictest37362chrt19:10:452
35099170cyclictest3055050irq/54-eth0-tx-23:15:092
35099170cyclictest3055050irq/54-eth0-tx-22:55:272
35099170cyclictest3055050irq/54-eth0-tx-21:55:082
35099170cyclictest3055050irq/54-eth0-tx-21:55:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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