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2026-07-26 - 19:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Jul 26, 2026 12:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4872115106sleep100-21swapper/1007:08:392
30549501100irq/53-eth0-rx-0-21swapper/807:08:5210
32686210996sleep20-21swapper/207:05:554
308210290sleep110-21swapper/1107:07:053
122501010irq/42-ahci0-21swapper/107:08:581
3054950950irq/53-eth0-rx-0-21swapper/707:09:199
12250910irq/42-ahci0-21swapper/307:08:235
3054950880irq/53-eth0-rx-0-21swapper/507:05:287
3054950870irq/53-eth0-rx-0-21swapper/407:07:246
3266527869sleep90-21swapper/907:05:3711
3274927058sleep00-21swapper/007:06:410
36326553sleep60-21swapper/607:07:488
736993316cyclictest831ksoftirqd/1011:45:192
69599320cyclictest0-21swapper/008:14:470
73799290cyclictest0-21swapper/1107:22:323
73699236cyclictest831ksoftirqd/1009:53:302
73699214cyclictest831ksoftirqd/1010:33:192
73699214cyclictest831ksoftirqd/1010:04:532
73699214cyclictest831ksoftirqd/1009:22:192
73699192cyclictest831ksoftirqd/1010:25:192
73699192cyclictest3054950irq/53-eth0-rx-12:07:432
73699192cyclictest3054950irq/53-eth0-rx-11:52:152
73699192cyclictest3054950irq/53-eth0-rx-10:16:402
73599192cyclictest0-21swapper/910:25:4411
736991817cyclictest811rcuc/1009:33:242
736991817cyclictest0-21swapper/1012:15:142
736991817cyclictest0-21swapper/1011:06:352
736991817cyclictest0-21swapper/1007:58:272
73699181cyclictest831ksoftirqd/1012:30:562
73699181cyclictest831ksoftirqd/1010:50:132
73699181cyclictest831ksoftirqd/1009:00:202
73699181cyclictest831ksoftirqd/1009:00:192
73699181cyclictest831ksoftirqd/1007:20:212
73699181cyclictest3055050irq/54-eth0-tx-09:11:102
73699181cyclictest3054950irq/53-eth0-rx-12:20:042
73699181cyclictest3054950irq/53-eth0-rx-12:01:092
73699181cyclictest3054950irq/53-eth0-rx-11:39:152
73699181cyclictest3054950irq/53-eth0-rx-11:11:342
73699181cyclictest3054950irq/53-eth0-rx-10:56:392
73699181cyclictest3054950irq/53-eth0-rx-10:35:562
73699181cyclictest3054950irq/53-eth0-rx-09:40:152
73699181cyclictest3054950irq/53-eth0-rx-09:35:442
73699181cyclictest3054950irq/53-eth0-rx-09:17:342
73699180cyclictest12250irq/42-ahci09:47:332
73599181cyclictest0-21swapper/911:58:2211
73599181cyclictest0-21swapper/910:23:2011
73599181cyclictest0-21swapper/910:08:3511
73599181cyclictest0-21swapper/910:01:4511
712991816cyclictest29004-21snmp_rack3slot910:30:154
712991816cyclictest22561-21snmp_rack3slot908:20:134
712991816cyclictest2139-21snmp_easybox.os08:35:254
712991816cyclictest2139-21snmp_easybox.os08:35:254
69599182cyclictest0-21swapper/010:11:470
695991817cyclictest9107-21taskset07:16:280
695991817cyclictest165952sleep007:29:060
695991814cyclictest0-21swapper/007:20:330
736991716cyclictest831ksoftirqd/1009:05:092
736991716cyclictest0-21swapper/1010:05:052
73699170cyclictest91312sleep1007:16:512
73699170cyclictest831ksoftirqd/1011:15:022
73699170cyclictest831ksoftirqd/1011:15:012
73699170cyclictest831ksoftirqd/1008:40:122
73699170cyclictest831ksoftirqd/1007:45:102
73699170cyclictest67302sleep1008:00:082
73699170cyclictest43002sleep1007:13:142
73699170cyclictest3055050irq/54-eth0-tx-10:45:012
73699170cyclictest3054950irq/53-eth0-rx-11:55:052
73699170cyclictest3054950irq/53-eth0-rx-11:40:032
73699170cyclictest3054950irq/53-eth0-rx-11:30:112
73699170cyclictest3054950irq/53-eth0-rx-11:30:102
73699170cyclictest3054950irq/53-eth0-rx-11:20:092
73699170cyclictest3054950irq/53-eth0-rx-11:00:202
73699170cyclictest3054950irq/53-eth0-rx-10:20:042
73699170cyclictest3054950irq/53-eth0-rx-09:55:032
73699170cyclictest3054950irq/53-eth0-rx-09:25:232
73699170cyclictest3054950irq/53-eth0-rx-08:05:202
73699170cyclictest279822sleep1008:27:362
73699170cyclictest27882chrt08:35:472
73699170cyclictest27882chrt08:35:472
73699170cyclictest273712sleep1007:42:072
73699170cyclictest241992sleep1008:20:472
73699170cyclictest24172sleep1011:26:082
73699170cyclictest236552sleep1007:36:052
73699170cyclictest22772chrt07:52:072
73699170cyclictest223682chrt12:10:022
73699170cyclictest208182chrt08:19:222
73699170cyclictest188072sleep1007:30:172
73699170cyclictest174952sleep1008:57:142
73699170cyclictest170412sleep1008:12:332
73699170cyclictest135322chrt07:25:042
73699170cyclictest12250irq/42-ahci12:35:022
73699170cyclictest12250irq/42-ahci10:10:102
73699170cyclictest12250irq/42-ahci08:30:252
73699170cyclictest109342sleep1008:50:022
73699170cyclictest104292sleep1010:40:272
73699170cyclictest100982sleep1008:45:492
73699170cyclictest100982sleep1008:45:492
73699170cyclictest100562sleep1012:25:162
735991716cyclictest0-21swapper/910:41:4211
735991715cyclictest11862-21if_err_eth108:05:1811
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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