You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-10 - 14:08
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Apr 10, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501140irq/53-eth0-rx-0-21swapper/1107:06:433
9918501140irq/53-eth0-rx-0-21swapper/1107:06:433
9918501090irq/53-eth0-rx-0-21swapper/707:05:369
9918501090irq/53-eth0-rx-0-21swapper/707:05:359
318042105100sleep30-21swapper/307:09:205
318042105100sleep30-21swapper/307:09:195
31787210498sleep40-21swapper/407:09:096
31787210498sleep40-21swapper/407:09:086
31584210391sleep60-21swapper/607:07:098
31584210391sleep60-21swapper/607:07:098
128501020irq/42-ahci0-21swapper/207:09:384
128501020irq/42-ahci0-21swapper/207:09:374
9918501000irq/53-eth0-rx-0-21swapper/107:09:281
9918501000irq/53-eth0-rx-0-21swapper/107:09:271
991850900irq/53-eth0-rx-0-21swapper/1007:06:042
991850900irq/53-eth0-rx-0-21swapper/1007:06:032
991850670irq/53-eth0-rx-0-21swapper/507:06:407
991850670irq/53-eth0-rx-0-21swapper/507:06:397
991850650irq/53-eth0-rx-0-21swapper/807:05:3110
991850650irq/53-eth0-rx-0-21swapper/807:05:3010
3157326354sleep90-21swapper/907:07:0111
3157326354sleep90-21swapper/907:07:0011
3156425853sleep00-21swapper/007:06:520
3156425853sleep00-21swapper/007:06:510
31988994544cyclictest0-21swapper/008:20:470
32006993130cyclictest0-21swapper/1107:27:343
3200699220cyclictest0-21swapper/1110:26:413
3200699220cyclictest0-21swapper/1110:26:403
3198899220cyclictest0-21swapper/007:19:530
3200499192cyclictest0-21swapper/909:17:0811
3200499181cyclictest0-21swapper/912:35:1311
3200499181cyclictest0-21swapper/910:25:2411
3200499181cyclictest0-21swapper/910:25:2311
3200499181cyclictest0-21swapper/910:20:1211
3200499181cyclictest0-21swapper/910:03:1511
3200399185cyclictest0-21swapper/812:15:0010
32001991816cyclictest12197-21qemu-kvm08:08:458
32001991816cyclictest12196-21qemu-kvm08:10:558
32001991816cyclictest12196-21qemu-kvm08:10:558
3198899180cyclictest0-21swapper/007:20:060
3200499170cyclictest31955-21cyclictest09:22:1711
3200499170cyclictest17320-21runrttasks10:49:4111
3200499170cyclictest0-21swapper/911:57:5611
3200499170cyclictest0-21swapper/911:23:5511
3200499170cyclictest0-21swapper/910:19:3811
32001991715cyclictest12197-21qemu-kvm08:47:238
32001991715cyclictest12196-21qemu-kvm08:36:588
3199899171cyclictest2534-21snmp_rack3slot912:20:595
3199899171cyclictest0-21swapper/312:14:485
31997991715cyclictest2308-21snmpd08:32:514
31997991715cyclictest2308-21snmpd07:47:354
31988991713cyclictest991850irq/53-eth0-rx-09:15:230
3200499164cyclictest0-21swapper/908:30:0111
3200499162cyclictest0-21swapper/912:27:4711
3200499162cyclictest0-21swapper/912:10:2411
32004991615cyclictest0-21swapper/912:33:2011
32004991615cyclictest0-21swapper/911:25:1411
32004991615cyclictest0-21swapper/911:15:5111
32004991615cyclictest0-21swapper/910:50:1711
32004991615cyclictest0-21swapper/910:50:1611
32004991615cyclictest0-21swapper/909:30:1111
32004991615cyclictest0-21swapper/909:26:4411
32004991614cyclictest16992-21chrt12:06:4711
3200499161cyclictest0-21swapper/912:20:2311
32001991615cyclictest12197-21qemu-kvm08:25:148
32001991614cyclictest19179-21python09:00:218
32000991615cyclictest20638-21ssh09:32:177
3199899161cyclictest23838-21diskmemload10:33:365
3199899160cyclictest23838-21diskmemload10:20:215
31997991614cyclictest2308-21snmpd07:25:064
3199799161cyclictest0-21swapper/212:10:474
31988991614cyclictest991850irq/53-eth0-rx-10:26:130
31988991614cyclictest991850irq/53-eth0-rx-10:26:120
31988991614cyclictest991850irq/53-eth0-rx-10:09:220
31988991614cyclictest991850irq/53-eth0-rx-10:09:210
31988991614cyclictest991850irq/53-eth0-rx-09:13:090
831150ksoftirqd/100-21swapper/1011:24:572
551150ksoftirqd/60-21swapper/611:24:568
481150ksoftirqd/50-21swapper/511:39:187
3200699154cyclictest0-21swapper/1112:20:013
32006991514cyclictest991850irq/53-eth0-rx-10:09:493
32006991514cyclictest991850irq/53-eth0-rx-10:09:483
3200499155cyclictest0-21swapper/909:05:0111
3200499154cyclictest0-21swapper/911:40:0111
3200499154cyclictest0-21swapper/909:05:0111
3200499154cyclictest0-21swapper/908:30:0111
3200499154cyclictest0-21swapper/908:20:0211
3200499154cyclictest0-21swapper/907:55:0111
3200499154cyclictest0-21swapper/907:15:0011
32004991514cyclictest0-21swapper/909:52:4511
32004991514cyclictest0-21swapper/909:11:2711
32004991514cyclictest0-21swapper/908:55:1211
32004991514cyclictest0-21swapper/907:15:1211
3200399154cyclictest0-21swapper/810:10:0210
3200199153cyclictest0-21swapper/610:11:138
32001991513cyclictest31959-21qemu-kvm10:08:358
32001991513cyclictest31959-21qemu-kvm10:08:348
3200099150cyclictest0-21swapper/511:05:127
3199899155cyclictest0-21swapper/311:51:375
3199899155cyclictest0-21swapper/311:48:405
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional