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2026-05-11 - 20:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon May 11, 2026 12:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501180irq/53-eth0-rx-0-21swapper/207:09:364
9918501120irq/53-eth0-rx-0-21swapper/707:09:309
9918501120irq/53-eth0-rx-0-21swapper/307:05:285
30652210993sleep00-21swapper/007:07:520
30824210296sleep100-21swapper/1007:09:262
991850980irq/53-eth0-rx-0-21swapper/107:05:131
991850920irq/53-eth0-rx-0-21swapper/907:05:3011
3080029185sleep40-21swapper/407:09:086
991850900irq/53-eth0-rx-0-21swapper/807:07:3810
991850650irq/53-eth0-rx-0-21swapper/507:06:027
3050426353sleep60-21swapper/607:05:578
991850620irq/53-eth0-rx-0-21swapper/1107:07:163
31011994227cyclictest0-21swapper/1110:27:243
31011993425cyclictest31560-21tail09:15:203
31011993326cyclictest12850irq/42-ahci07:13:203
31011993326cyclictest12850irq/42-ahci07:13:193
31011993313cyclictest71022sleep1107:19:163
30969993231cyclictest0-21swapper/007:13:170
30969993231cyclictest0-21swapper/007:13:170
31007992928cyclictest991850irq/53-eth0-rx-07:13:199
31007992928cyclictest991850irq/53-eth0-rx-07:13:199
991850280irq/53-eth0-rx-0-21swapper/307:11:485
991850280irq/53-eth0-rx-0-21swapper/307:11:485
3101199232cyclictest0-21swapper/1109:08:383
3096999230cyclictest0-21swapper/008:25:220
31005992120cyclictest12850irq/42-ahci07:13:067
31005992120cyclictest12850irq/42-ahci07:13:067
3096999201cyclictest0-21swapper/010:10:360
3096999200cyclictest0-21swapper/009:22:460
3101099192cyclictest991850irq/53-eth0-rx-09:31:092
3100999192cyclictest0-21swapper/911:49:0411
3100999192cyclictest0-21swapper/909:27:3411
31010991817cyclictest0-21swapper/1007:57:252
31010991816cyclictest13535-21sensors_temp07:25:222
31010991816cyclictest10649-21ssh10:46:262
3101099181cyclictest991950irq/54-eth0-tx-11:05:102
3101099181cyclictest991950irq/54-eth0-tx-09:13:402
3101099181cyclictest991850irq/53-eth0-rx-12:37:502
3101099181cyclictest991850irq/53-eth0-rx-12:02:512
3101099181cyclictest991850irq/53-eth0-rx-11:43:182
3101099181cyclictest991850irq/53-eth0-rx-11:21:192
3101099181cyclictest991850irq/53-eth0-rx-11:15:512
3101099181cyclictest991850irq/53-eth0-rx-11:10:362
3101099181cyclictest991850irq/53-eth0-rx-10:51:242
3101099181cyclictest991850irq/53-eth0-rx-10:39:282
3101099181cyclictest991850irq/53-eth0-rx-09:58:312
3101099181cyclictest991850irq/53-eth0-rx-09:54:422
3101099181cyclictest991850irq/53-eth0-rx-09:48:172
3101099181cyclictest991850irq/53-eth0-rx-09:40:162
3101099181cyclictest991850irq/53-eth0-rx-09:35:072
3101099181cyclictest991850irq/53-eth0-rx-09:29:562
3101099181cyclictest991850irq/53-eth0-rx-09:19:402
3101099181cyclictest12850irq/42-ahci12:17:332
3100999181cyclictest991850irq/53-eth0-rx-11:35:0311
3100999181cyclictest991850irq/53-eth0-rx-09:49:4611
3100999181cyclictest0-21swapper/912:17:1211
3100999181cyclictest0-21swapper/912:09:2811
3100999181cyclictest0-21swapper/911:25:0111
3100999181cyclictest0-21swapper/911:14:2711
3100999181cyclictest0-21swapper/910:51:0411
3100999181cyclictest0-21swapper/910:20:0011
3100999181cyclictest0-21swapper/910:16:3711
3100999181cyclictest0-21swapper/909:56:4411
3100999181cyclictest0-21swapper/908:00:0111
15050180irq/18-uhci_hcd22754-21qemu-kvm09:15:237
3101199170cyclictest0-21swapper/1110:15:503
3101199170cyclictest0-21swapper/1107:21:523
31010991716cyclictest0-21swapper/1010:55:362
31010991715cyclictest17672-21memory10:25:202
3101099170cyclictest991950irq/54-eth0-tx-12:20:012
3101099170cyclictest991950irq/54-eth0-tx-12:20:012
3101099170cyclictest991950irq/54-eth0-tx-10:31:292
3101099170cyclictest991850irq/53-eth0-rx-12:26:202
3101099170cyclictest991850irq/53-eth0-rx-11:55:112
3101099170cyclictest991850irq/53-eth0-rx-11:45:462
3101099170cyclictest991850irq/53-eth0-rx-11:30:132
3101099170cyclictest991850irq/53-eth0-rx-10:40:022
3101099170cyclictest991850irq/53-eth0-rx-10:20:282
3101099170cyclictest991850irq/53-eth0-rx-10:10:022
3101099170cyclictest991850irq/53-eth0-rx-10:00:182
3101099170cyclictest991850irq/53-eth0-rx-09:20:472
3101099170cyclictest991850irq/53-eth0-rx-08:50:502
3101099170cyclictest991850irq/53-eth0-rx-08:16:502
3101099170cyclictest991850irq/53-eth0-rx-07:40:212
3101099170cyclictest991850irq/53-eth0-rx-07:15:282
3101099170cyclictest85492sleep1007:20:162
3101099170cyclictest74372chrt08:01:432
3101099170cyclictest73842sleep1012:05:242
3101099170cyclictest68852sleep1010:15:352
3101099170cyclictest4882sleep1008:35:342
3101099170cyclictest43012chrt08:41:232
3101099170cyclictest324172sleep1007:51:062
3101099170cyclictest31632sleep1012:30:162
3101099170cyclictest287692sleep1007:46:172
3101099170cyclictest285652sleep1008:30:222
3101099170cyclictest279822sleep1011:00:292
3101099170cyclictest257232sleep1008:26:342
3101099170cyclictest243982sleep1010:05:102
3101099170cyclictest225742sleep1009:06:262
3101099170cyclictest222332sleep1008:23:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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