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2026-06-30 - 18:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Jun 30, 2026 12:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501140irq/42-ahci0-21swapper/207:09:094
30549501130irq/53-eth0-rx-0-21swapper/707:09:369
30549501100irq/53-eth0-rx-0-21swapper/107:09:321
18936210997sleep30-21swapper/307:05:405
18942210794sleep90-21swapper/907:05:4611
19034210190sleep40-21swapper/407:06:536
3054950990irq/53-eth0-rx-0-21swapper/807:09:4110
3054950900irq/53-eth0-rx-0-21swapper/1107:06:013
3054950860irq/53-eth0-rx-0-21swapper/507:05:467
1901826753sleep60-21swapper/607:06:438
1904026553sleep100-21swapper/1007:06:592
1894726553sleep00-21swapper/007:05:490
1943799332cyclictest0-21swapper/009:14:440
19460992315cyclictest6240-21snmp_easybox.os08:15:264
19460992315cyclictest17177-21snmp_easybox.os08:30:254
19471992214cyclictest0-21swapper/912:38:0411
19471992214cyclictest0-21swapper/911:31:3311
19471992214cyclictest0-21swapper/911:21:1211
19471992214cyclictest0-21swapper/911:11:4911
19471992214cyclictest0-21swapper/911:04:4711
19471992214cyclictest0-21swapper/909:44:3911
19471992214cyclictest0-21swapper/908:50:4511
19471992213cyclictest0-21swapper/910:06:1011
19460992215cyclictest4317-21snmp_rack3slot907:30:144
19460992215cyclictest2064-21snmp_rack3slot912:11:484
19460992213cyclictest12092-21snmp_rack3slot908:25:114
19471992114cyclictest23067-21ssh12:02:2811
19471992114cyclictest0-21swapper/912:17:2011
19471992114cyclictest0-21swapper/912:06:3711
19471992114cyclictest0-21swapper/910:57:2811
19471992114cyclictest0-21swapper/910:54:5411
19471992114cyclictest0-21swapper/910:48:1711
19471992114cyclictest0-21swapper/910:17:2511
19471992114cyclictest0-21swapper/910:04:0811
19471992114cyclictest0-21swapper/909:56:0511
19471992114cyclictest0-21swapper/909:54:5511
19471992114cyclictest0-21swapper/909:37:5111
19471992114cyclictest0-21swapper/909:37:5111
19471992114cyclictest0-21swapper/909:25:1111
19471992114cyclictest0-21swapper/909:25:1111
19471992114cyclictest0-21swapper/909:22:5411
19471992114cyclictest0-21swapper/907:50:1911
19471992114cyclictest0-21swapper/907:28:4311
19471992114cyclictest0-21swapper/907:20:2811
19471992113cyclictest3054950irq/53-eth0-rx-11:17:5711
19471992113cyclictest0-21swapper/912:11:4311
19471992113cyclictest0-21swapper/910:43:2111
19471992113cyclictest0-21swapper/910:25:2911
19471992113cyclictest0-21swapper/907:59:2711
19471992113cyclictest0-21swapper/907:38:3711
1947199210cyclictest0-21swapper/910:10:4511
19460992112cyclictest28740-21snmp_rack3slot910:45:164
19471992014cyclictest0-21swapper/911:27:4411
19471992014cyclictest0-21swapper/910:24:1511
19471992014cyclictest0-21swapper/908:26:2511
19471992013cyclictest0-21swapper/909:14:1911
19471992013cyclictest0-21swapper/909:00:3111
19471992013cyclictest0-21swapper/908:45:3411
19471992013cyclictest0-21swapper/908:33:3711
19471992013cyclictest0-21swapper/908:16:2611
19471992013cyclictest0-21swapper/908:05:5311
19471992012cyclictest0-21swapper/911:05:1411
19471992012cyclictest0-21swapper/908:10:2311
19471992012cyclictest0-21swapper/907:43:0411
1947199201cyclictest0-21swapper/912:29:2711
1947199201cyclictest0-21swapper/908:57:1511
1947199200cyclictest0-21swapper/911:52:2811
19460992015cyclictest31106-21snmp_rack3slot911:41:134
19460992013cyclictest465-21snmp_rack3slot907:25:134
1947799195cyclictest0-21swapper/1008:05:182
1947799192cyclictest3054950irq/53-eth0-rx-12:36:192
1947799192cyclictest3054950irq/53-eth0-rx-11:44:292
1947799192cyclictest3054950irq/53-eth0-rx-10:38:102
1947799192cyclictest3054950irq/53-eth0-rx-10:17:112
1947799192cyclictest3054950irq/53-eth0-rx-09:23:562
1947799192cyclictest3054950irq/53-eth0-rx-09:10:282
1947199192cyclictest0-21swapper/911:41:2611
1947199192cyclictest0-21swapper/909:16:1911
1947199192cyclictest0-21swapper/909:16:1811
19471991913cyclictest0-21swapper/910:30:4211
19471991913cyclictest0-21swapper/908:22:1311
19471991913cyclictest0-21swapper/907:47:5211
19471991913cyclictest0-21swapper/907:31:2511
19471991913cyclictest0-21swapper/907:17:5811
19471991912cyclictest0-21swapper/909:46:4111
19471991912cyclictest0-21swapper/908:42:5811
1947199191cyclictest0-21swapper/909:34:3111
1947199191cyclictest0-21swapper/909:34:3111
19468991916cyclictest11214-21qemu-kvm09:15:118
19468991916cyclictest11214-21qemu-kvm09:15:118
1944999192cyclictest26185-21gltestperf07:15:151
1943799190cyclictest0-21swapper/009:08:440
1943799190cyclictest0-21swapper/009:08:440
19477991817cyclictest0-21swapper/1009:49:002
19477991817cyclictest0-21swapper/1007:25:002
1947799181cyclictest3055050irq/54-eth0-tx-12:10:362
1947799181cyclictest3055050irq/54-eth0-tx-12:07:322
1947799181cyclictest3055050irq/54-eth0-tx-12:01:192
1947799181cyclictest3055050irq/54-eth0-tx-11:55:442
1947799181cyclictest3055050irq/54-eth0-tx-11:46:482
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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