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2026-02-22 - 19:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Feb 22, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501080irq/53-eth0-rx-0-21swapper/207:07:254
9918501060irq/53-eth0-rx-0-21swapper/407:06:336
9918501050irq/53-eth0-rx-0-21swapper/107:09:261
991950950irq/54-eth0-tx-0-21swapper/307:08:225
991850900irq/53-eth0-rx-0-21swapper/707:06:549
172450900irq/56-eth1-rx-0-21swapper/807:05:2610
991850890irq/53-eth0-rx-0-21swapper/507:05:177
261228078sleep100-21swapper/1007:09:322
258027876sleep90-21swapper/907:09:0711
991850730irq/53-eth0-rx-0-21swapper/1107:07:123
228925955sleep60-21swapper/607:06:288
228125853sleep00-21swapper/007:06:220
2755994023cyclictest0-21swapper/010:28:120
2799993130cyclictest0-21swapper/1108:25:373
2755993013cyclictest0-21swapper/010:10:300
2799992726cyclictest0-21swapper/1110:21:323
2799992511cyclictest0-21swapper/1110:10:403
2799992414cyclictest0-21swapper/1107:15:143
2799992414cyclictest0-21swapper/1107:15:143
275599230cyclictest0-21swapper/010:15:090
279899192cyclictest991850irq/53-eth0-rx-12:32:332
279899192cyclictest991850irq/53-eth0-rx-11:21:152
279899192cyclictest991850irq/53-eth0-rx-11:11:572
279899192cyclictest991850irq/53-eth0-rx-11:04:092
279899192cyclictest991850irq/53-eth0-rx-10:59:042
279899192cyclictest991850irq/53-eth0-rx-10:33:372
279899192cyclictest991850irq/53-eth0-rx-10:00:322
279899192cyclictest991850irq/53-eth0-rx-10:00:322
279899192cyclictest991850irq/53-eth0-rx-09:58:432
279899192cyclictest991850irq/53-eth0-rx-09:58:432
279899192cyclictest991850irq/53-eth0-rx-09:20:582
279899192cyclictest991850irq/53-eth0-rx-09:19:012
279899192cyclictest991850irq/53-eth0-rx-09:14:512
279899192cyclictest12850irq/42-ahci09:08:562
279899192cyclictest12850irq/42-ahci09:08:562
279799192cyclictest0-21swapper/912:31:0511
279799192cyclictest0-21swapper/911:34:3111
279799192cyclictest0-21swapper/911:11:5211
279799192cyclictest0-21swapper/910:04:4111
279799192cyclictest0-21swapper/910:04:4011
279799192cyclictest0-21swapper/909:52:4311
279699191cyclictest0-21swapper/808:40:1510
2798991817cyclictest811rcuc/1007:10:312
2798991817cyclictest17779-1kworker/10:0H11:52:132
2798991817cyclictest1319-21kworker/10:211:25:122
2798991817cyclictest0-21swapper/1011:48:542
2798991817cyclictest0-21swapper/1011:30:582
2798991817cyclictest0-21swapper/1008:45:182
2798991817cyclictest0-21swapper/1008:07:562
2798991817cyclictest0-21swapper/1007:45:132
2798991817cyclictest0-21swapper/1007:45:132
279899181cyclictest991950irq/54-eth0-tx-12:09:442
279899181cyclictest991950irq/54-eth0-tx-10:13:282
279899181cyclictest991950irq/54-eth0-tx-09:35:122
279899181cyclictest991950irq/54-eth0-tx-09:27:362
279899181cyclictest991850irq/53-eth0-rx-12:35:182
279899181cyclictest991850irq/53-eth0-rx-12:29:482
279899181cyclictest991850irq/53-eth0-rx-12:20:392
279899181cyclictest991850irq/53-eth0-rx-12:16:062
279899181cyclictest991850irq/53-eth0-rx-12:00:582
279899181cyclictest991850irq/53-eth0-rx-11:56:422
279899181cyclictest991850irq/53-eth0-rx-11:16:002
279899181cyclictest991850irq/53-eth0-rx-11:07:012
279899181cyclictest991850irq/53-eth0-rx-10:50:182
279899181cyclictest991850irq/53-eth0-rx-10:40:072
279899181cyclictest991850irq/53-eth0-rx-10:37:442
279899181cyclictest991850irq/53-eth0-rx-10:25:392
279899181cyclictest991850irq/53-eth0-rx-10:20:552
279899181cyclictest991850irq/53-eth0-rx-10:15:442
279899181cyclictest991850irq/53-eth0-rx-09:52:142
279899181cyclictest991850irq/53-eth0-rx-09:40:112
279899181cyclictest991850irq/53-eth0-rx-09:33:342
279899181cyclictest991850irq/53-eth0-rx-07:52:532
279899181cyclictest991850irq/53-eth0-rx-07:52:532
279899181cyclictest991850irq/53-eth0-rx-07:43:552
279899181cyclictest991850irq/53-eth0-rx-07:27:462
279899181cyclictest139002chrt11:35:152
279899181cyclictest12850irq/42-ahci10:08:582
279899181cyclictest12850irq/42-ahci09:47:322
279899181cyclictest12850irq/42-ahci09:47:312
279899180cyclictest12850irq/42-ahci08:15:192
279799181cyclictest991850irq/53-eth0-rx-12:00:1411
279799181cyclictest0-21swapper/912:25:2711
279799181cyclictest0-21swapper/912:23:1811
279799181cyclictest0-21swapper/912:11:3611
279799181cyclictest0-21swapper/911:42:4511
279799181cyclictest0-21swapper/911:36:2611
279799181cyclictest0-21swapper/910:26:2611
279799181cyclictest0-21swapper/908:55:1211
279999170cyclictest18988-21taskset09:29:243
279999170cyclictest0-21swapper/1109:16:313
279899170cyclictest991950irq/54-eth0-tx-12:10:242
279899170cyclictest991850irq/53-eth0-rx-11:40:062
279899170cyclictest991850irq/53-eth0-rx-10:45:362
279899170cyclictest991850irq/53-eth0-rx-08:25:122
279899170cyclictest991850irq/53-eth0-rx-07:21:352
279899170cyclictest54742sleep1007:55:132
279899170cyclictest47432sleep1008:35:542
279899170cyclictest262402sleep1008:22:042
279899170cyclictest256552chrt07:36:342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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