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2026-01-31 - 15:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Jan 31, 2026 12:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
77402121107sleep80-21swapper/807:08:0210
9918501050irq/53-eth0-rx-0-21swapper/107:08:211
128501020irq/42-ahci0-21swapper/207:08:344
9918501010irq/53-eth0-rx-0-21swapper/707:09:469
991850990irq/53-eth0-rx-0-21swapper/307:05:255
760529988sleep90-21swapper/907:06:1311
991850880irq/53-eth0-rx-0-21swapper/507:07:477
991850730irq/53-eth0-rx-0-21swapper/1107:06:573
991850720irq/53-eth0-rx-0-21swapper/407:06:216
764926858sleep60-21swapper/607:06:478
791826765sleep100-21swapper/1007:09:392
768925853sleep00-21swapper/007:07:180
805799320cyclictest0-21swapper/010:28:090
805799320cyclictest0-21swapper/010:28:080
805799320cyclictest0-21swapper/007:10:320
8091993129cyclictest165542chrt07:19:163
8091992914cyclictest0-21swapper/1107:27:203
8090992912cyclictest831ksoftirqd/1008:10:112
8090992811cyclictest831ksoftirqd/1011:00:282
809199270cyclictest0-21swapper/1109:30:203
809199248cyclictest3470-21chrt09:10:283
809099247cyclictest831ksoftirqd/1010:09:342
809099225cyclictest831ksoftirqd/1012:30:392
809099225cyclictest831ksoftirqd/1010:54:182
809099225cyclictest831ksoftirqd/1008:55:542
809199214cyclictest0-21swapper/1107:32:093
8091992120cyclictest0-21swapper/1108:21:253
805799210cyclictest0-21swapper/008:25:220
809099203cyclictest991850irq/53-eth0-rx-10:29:432
809099203cyclictest991850irq/53-eth0-rx-10:29:422
809099203cyclictest991850irq/53-eth0-rx-09:40:482
8085992016cyclictest20656-21qemu-kvm08:20:107
8091991917cyclictest0-21swapper/1108:08:403
809099192cyclictest991850irq/53-eth0-rx-12:35:062
809099192cyclictest991850irq/53-eth0-rx-11:43:412
809099192cyclictest991850irq/53-eth0-rx-11:13:142
809099192cyclictest831ksoftirqd/1011:20:142
809099192cyclictest831ksoftirqd/1010:47:342
809099192cyclictest252932sleep1009:56:222
8090991917cyclictest10221-21kworker/10:111:26:212
808999192cyclictest0-21swapper/911:31:1211
808999192cyclictest0-21swapper/911:21:0011
8090991817cyclictest14497-21sshd08:45:102
8090991816cyclictest831ksoftirqd/1009:05:202
8090991816cyclictest32109-21ssh10:02:502
8090991816cyclictest11690-21ssh11:06:072
809099181cyclictest991950irq/54-eth0-tx-12:25:142
809099181cyclictest991850irq/53-eth0-rx-12:14:522
809099181cyclictest991850irq/53-eth0-rx-11:37:412
809099181cyclictest991850irq/53-eth0-rx-10:56:202
809099181cyclictest991850irq/53-eth0-rx-10:37:452
809099181cyclictest991850irq/53-eth0-rx-10:14:542
809099181cyclictest991850irq/53-eth0-rx-09:26:352
809099181cyclictest831ksoftirqd/1011:47:042
809099181cyclictest831ksoftirqd/1010:20:002
809099181cyclictest831ksoftirqd/1010:20:002
809099181cyclictest831ksoftirqd/1009:35:202
809099181cyclictest831ksoftirqd/1009:20:132
809099181cyclictest831ksoftirqd/1008:50:252
809099181cyclictest831ksoftirqd/1007:40:102
809099181cyclictest831ksoftirqd/1007:40:092
809099181cyclictest831ksoftirqd/1007:30:172
809099181cyclictest68442chrt11:56:362
808999182cyclictest0-21swapper/909:53:4511
808999181cyclictest0-21swapper/912:26:2411
808999181cyclictest0-21swapper/912:06:1811
808999181cyclictest0-21swapper/911:56:1511
808999181cyclictest0-21swapper/911:52:4011
808999181cyclictest0-21swapper/910:24:4111
808999181cyclictest0-21swapper/909:40:1511
808999181cyclictest0-21swapper/909:33:1411
808999181cyclictest0-21swapper/909:25:2311
808999181cyclictest0-21swapper/908:55:2611
808999181cyclictest0-21swapper/908:30:2611
808999181cyclictest0-21swapper/908:25:1411
8090991716cyclictest831ksoftirqd/1010:40:122
8090991716cyclictest831ksoftirqd/1009:00:142
8090991716cyclictest831ksoftirqd/1008:15:012
8090991716cyclictest28974-21latency12:15:202
8090991716cyclictest0-21swapper/1009:50:132
8090991715cyclictest13605-21snmp_rack3slot907:15:162
8090991715cyclictest12279-21ssh12:00:452
809099170cyclictest991850irq/53-eth0-rx-12:06:092
809099170cyclictest991850irq/53-eth0-rx-11:16:032
809099170cyclictest991850irq/53-eth0-rx-10:20:512
809099170cyclictest991850irq/53-eth0-rx-09:45:212
809099170cyclictest991850irq/53-eth0-rx-09:30:582
809099170cyclictest85832sleep1007:50:192
809099170cyclictest831ksoftirqd/1012:20:112
809099170cyclictest831ksoftirqd/1009:15:022
809099170cyclictest831ksoftirqd/1008:40:002
809099170cyclictest831ksoftirqd/1008:25:162
809099170cyclictest831ksoftirqd/1008:00:142
809099170cyclictest831ksoftirqd/1007:55:252
809099170cyclictest831ksoftirqd/1007:35:162
809099170cyclictest831ksoftirqd/1007:35:152
809099170cyclictest72042sleep1008:35:112
809099170cyclictest63842chrt08:31:112
809099170cyclictest58072sleep1011:30:092
809099170cyclictest323042sleep1010:30:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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