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2026-03-28 - 05:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Mar 28, 2026 00:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501070irq/42-ahci0-21swapper/719:09:029
15267210593sleep10-21swapper/119:07:291
991850960irq/53-eth0-rx-0-21swapper/819:08:2410
991850950irq/53-eth0-rx-0-21swapper/219:07:124
991850910irq/53-eth0-rx-0-21swapper/419:07:366
991850890irq/53-eth0-rx-0-21swapper/1119:06:143
991850870irq/53-eth0-rx-0-21swapper/519:05:327
12850810irq/42-ahci0-21swapper/319:08:375
1548328076sleep90-21swapper/919:09:3711
1548426765sleep100-21swapper/1019:09:382
1516826753sleep00-21swapper/019:06:160
1511625955sleep60-21swapper/619:05:348
1561399330cyclictest0-21swapper/021:10:310
1565599320cyclictest0-21swapper/1122:18:043
1565599320cyclictest0-21swapper/1120:13:203
991950300irq/54-eth0-tx-0-21swapper/421:10:296
15655993028cyclictest991850irq/53-eth0-rx-21:10:243
15654993013cyclictest831ksoftirqd/1023:07:592
15653993029cyclictest991850irq/53-eth0-rx-21:10:3111
15633992928cyclictest991850irq/53-eth0-rx-21:10:255
15654992811cyclictest831ksoftirqd/1023:44:072
15654992811cyclictest831ksoftirqd/1021:44:242
15655992726cyclictest991850irq/53-eth0-rx-22:23:353
15617992726cyclictest991950irq/54-eth0-tx-21:10:301
15655992524cyclictest0-21swapper/1119:17:253
15613992118cyclictest0-21swapper/022:19:230
1565499203cyclictest831ksoftirqd/1000:14:092
1565499203cyclictest831ksoftirqd/1000:14:092
15653992019cyclictest18547-21vmstat22:10:2711
1565499192cyclictest991850irq/53-eth0-rx-21:39:142
1565499192cyclictest991850irq/53-eth0-rx-00:05:092
1565499192cyclictest831ksoftirqd/1023:53:202
1565499192cyclictest831ksoftirqd/1023:45:172
1565499192cyclictest831ksoftirqd/1023:33:092
1565499192cyclictest831ksoftirqd/1022:43:382
1565499192cyclictest831ksoftirqd/1022:35:212
1565499192cyclictest831ksoftirqd/1022:30:232
1565499192cyclictest831ksoftirqd/1022:20:552
1565499192cyclictest831ksoftirqd/1021:50:232
1565499192cyclictest831ksoftirqd/1021:30:172
1565499192cyclictest831ksoftirqd/1000:28:552
1565599180cyclictest0-21swapper/1122:08:153
15654991817cyclictest831ksoftirqd/1021:55:282
15654991817cyclictest831ksoftirqd/1021:25:102
15654991817cyclictest0-21swapper/1023:35:252
15654991817cyclictest0-21swapper/1020:25:272
1565499181cyclictest991850irq/53-eth0-rx-22:15:122
1565499181cyclictest831ksoftirqd/1023:55:382
1565499181cyclictest831ksoftirqd/1023:55:382
1565499181cyclictest831ksoftirqd/1023:25:252
1565499181cyclictest831ksoftirqd/1023:22:342
1565499181cyclictest831ksoftirqd/1023:15:182
1565499181cyclictest831ksoftirqd/1023:12:052
1565499181cyclictest831ksoftirqd/1023:00:132
1565499181cyclictest831ksoftirqd/1022:55:252
1565499181cyclictest831ksoftirqd/1022:50:152
1565499181cyclictest831ksoftirqd/1022:45:392
1565499181cyclictest831ksoftirqd/1022:25:562
1565499181cyclictest831ksoftirqd/1022:11:272
1565499181cyclictest831ksoftirqd/1022:09:182
1565499181cyclictest831ksoftirqd/1022:01:142
1565499181cyclictest831ksoftirqd/1021:45:132
1565499181cyclictest831ksoftirqd/1021:20:372
1565499181cyclictest831ksoftirqd/1021:10:332
1565499181cyclictest831ksoftirqd/1021:05:232
1565499181cyclictest831ksoftirqd/1020:45:212
1565499181cyclictest831ksoftirqd/1020:20:122
1565499181cyclictest831ksoftirqd/1020:15:012
1565499181cyclictest831ksoftirqd/1020:10:162
1565499181cyclictest831ksoftirqd/1020:06:242
1565499181cyclictest831ksoftirqd/1020:00:252
1565499181cyclictest831ksoftirqd/1019:55:142
1565499181cyclictest831ksoftirqd/1019:45:182
1565499181cyclictest831ksoftirqd/1019:35:162
1565499181cyclictest831ksoftirqd/1019:25:132
1565499181cyclictest831ksoftirqd/1019:10:252
1565499181cyclictest831ksoftirqd/1000:35:392
1565499181cyclictest831ksoftirqd/1000:31:232
1565499181cyclictest831ksoftirqd/1000:21:272
1565499181cyclictest831ksoftirqd/1000:00:132
1565499181cyclictest831ksoftirqd/1000:00:122
1565499181cyclictest12850irq/42-ahci21:16:092
1565499181cyclictest12850irq/42-ahci00:15:442
15650991816cyclictest13957-21qemu-kvm22:08:458
15648991816cyclictest21898-21ssh23:33:457
15654991716cyclictest831ksoftirqd/1020:30:162
15654991716cyclictest0-21swapper/1020:55:252
1565499170cyclictest991850irq/53-eth0-rx-19:15:132
1565499170cyclictest831ksoftirqd/1021:00:202
1565499170cyclictest831ksoftirqd/1021:00:202
1565499170cyclictest831ksoftirqd/1020:50:162
1565499170cyclictest831ksoftirqd/1020:40:162
1565499170cyclictest831ksoftirqd/1020:35:012
1565499170cyclictest831ksoftirqd/1019:50:142
1565499170cyclictest831ksoftirqd/1019:30:132
1565499170cyclictest831ksoftirqd/1019:20:212
1565499170cyclictest68992chrt19:40:042
1565299174cyclictest0-21swapper/819:15:2310
15648991715cyclictest28218-21qemu-kvm20:45:157
15648991715cyclictest28218-21qemu-kvm20:08:157
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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