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2026-02-09 - 19:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Feb 09, 2026 12:46:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12649210894sleep20-21swapper/207:06:284
12638210691sleep60-21swapper/607:06:208
991850990irq/53-eth0-rx-0-21swapper/107:06:461
991850980irq/53-eth0-rx-0-21swapper/307:07:455
991850980irq/53-eth0-rx-0-21swapper/1107:05:173
991850920irq/53-eth0-rx-0-21swapper/407:07:046
991850870irq/53-eth0-rx-0-21swapper/507:07:407
991850860irq/53-eth0-rx-0-21swapper/707:05:379
991850790irq/53-eth0-rx-0-21swapper/807:06:5310
1294227977sleep90-21swapper/907:09:3611
991850690irq/53-eth0-rx-0-21swapper/1007:05:062
1262826553sleep00-21swapper/007:06:140
901320ksoftirqd/110-21swapper/1107:12:283
1311099215cyclictest0-21swapper/708:50:189
13093992019cyclictest2745-21runrttasks09:48:105
1311399192cyclictest991850irq/53-eth0-rx-12:06:182
1311399192cyclictest991850irq/53-eth0-rx-11:32:562
1311399192cyclictest991850irq/53-eth0-rx-11:05:082
1311399192cyclictest991850irq/53-eth0-rx-09:28:382
1311399192cyclictest991850irq/53-eth0-rx-09:20:432
1311399192cyclictest12850irq/42-ahci11:24:412
1311299192cyclictest0-21swapper/911:24:1211
1311299192cyclictest0-21swapper/909:15:5911
991850180irq/53-eth0-rx-1311399cyclictest09:30:352
13113991817cyclictest0-21swapper/1011:18:552
13113991817cyclictest0-21swapper/1010:22:412
13113991817cyclictest0-21swapper/1009:44:132
13113991816cyclictest10887-21ssh11:59:522
13113991816cyclictest10411-21df10:10:142
1311399181cyclictest991950irq/54-eth0-tx-10:52:472
1311399181cyclictest991850irq/53-eth0-rx-12:31:312
1311399181cyclictest991850irq/53-eth0-rx-12:29:142
1311399181cyclictest991850irq/53-eth0-rx-12:16:582
1311399181cyclictest991850irq/53-eth0-rx-12:12:562
1311399181cyclictest991850irq/53-eth0-rx-11:50:282
1311399181cyclictest991850irq/53-eth0-rx-11:25:432
1311399181cyclictest991850irq/53-eth0-rx-11:11:022
1311399181cyclictest991850irq/53-eth0-rx-10:59:322
1311399181cyclictest991850irq/53-eth0-rx-10:32:562
1311399181cyclictest991850irq/53-eth0-rx-10:15:042
1311399181cyclictest991850irq/53-eth0-rx-10:07:072
1311399181cyclictest991850irq/53-eth0-rx-09:58:322
1311399181cyclictest991850irq/53-eth0-rx-09:46:172
1311399181cyclictest991850irq/53-eth0-rx-09:38:572
1311399181cyclictest991850irq/53-eth0-rx-09:17:142
1311299181cyclictest8416-21kworker/9:212:10:1411
1311299181cyclictest0-21swapper/912:32:1211
1311299181cyclictest0-21swapper/912:08:4911
1311299181cyclictest0-21swapper/911:53:3811
1311299181cyclictest0-21swapper/911:05:1211
1311299181cyclictest0-21swapper/910:48:5811
1311299181cyclictest0-21swapper/910:25:3411
1311299181cyclictest0-21swapper/910:07:4011
1311299181cyclictest0-21swapper/909:51:1411
1311299181cyclictest0-21swapper/909:47:5611
1311299181cyclictest0-21swapper/909:11:2211
1311299181cyclictest0-21swapper/908:25:2811
13088991816cyclictest2308-21snmpd10:24:584
8999170migration/111156-21turbostat09:09:553
13113991716cyclictest0-21swapper/1011:45:192
13113991716cyclictest0-21swapper/1010:25:062
13113991715cyclictest14977-21ssh10:40:222
1311399170cyclictest991850irq/53-eth0-rx-12:01:122
1311399170cyclictest991850irq/53-eth0-rx-11:41:202
1311399170cyclictest991850irq/53-eth0-rx-11:35:042
1311399170cyclictest991850irq/53-eth0-rx-11:00:272
1311399170cyclictest991850irq/53-eth0-rx-10:45:052
1311399170cyclictest991850irq/53-eth0-rx-10:35:142
1311399170cyclictest991850irq/53-eth0-rx-10:00:012
1311399170cyclictest991850irq/53-eth0-rx-09:50:122
1311399170cyclictest991850irq/53-eth0-rx-09:10:102
1311399170cyclictest991850irq/53-eth0-rx-09:01:112
1311399170cyclictest991850irq/53-eth0-rx-08:51:112
1311399170cyclictest991850irq/53-eth0-rx-07:45:272
1311399170cyclictest991850irq/53-eth0-rx-07:38:102
1311399170cyclictest991850irq/53-eth0-rx-07:15:302
1311399170cyclictest991850irq/53-eth0-rx-07:10:442
1311399170cyclictest78092sleep1008:26:452
1311399170cyclictest42332sleep1008:22:442
1311399170cyclictest3522chrt08:16:072
1311399170cyclictest322212sleep1007:30:272
1311399170cyclictest271622sleep1007:25:152
1311399170cyclictest257012sleep1008:08:202
1311399170cyclictest250392chrt07:21:492
1311399170cyclictest238562chrt12:35:502
1311399170cyclictest23542sleep1012:20:022
1311399170cyclictest224862sleep1008:47:482
1311399170cyclictest218662sleep1008:01:292
1311399170cyclictest19922sleep1009:08:252
1311399170cyclictest158762sleep1008:40:102
1311399170cyclictest153212sleep1007:55:062
1311399170cyclictest150552sleep1008:35:582
1311399170cyclictest12850irq/42-ahci07:41:002
1311399170cyclictest114112sleep1008:31:082
13112991716cyclictest0-21swapper/912:20:5711
13112991716cyclictest0-21swapper/911:11:3211
1311299170cyclictest0-21swapper/911:40:1711
1311299170cyclictest0-21swapper/909:36:5511
1311299170cyclictest0-21swapper/907:50:2411
1311099174cyclictest0-21swapper/709:55:009
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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