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2025-12-01 - 07:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Dec 01, 2025 00:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501110irq/42-ahci0-21swapper/119:08:241
27221210694sleep70-21swapper/719:07:329
27212210694sleep110-21swapper/1119:07:243
3066350990irq/52-eth0-rx-0-21swapper/419:06:266
12250970irq/42-ahci0-21swapper/219:09:434
3066350890irq/52-eth0-rx-0-21swapper/519:05:217
2715128274sleep00-21swapper/019:06:370
12250800irq/42-ahci0-21swapper/319:08:105
2736826558sleep80-21swapper/819:08:4710
2712626553sleep60-21swapper/619:06:198
2711526455sleep90-21swapper/919:06:1011
2708826355sleep100-21swapper/1019:05:472
2760899380cyclictest0-21swapper/1119:17:513
27608993113cyclictest207362sleep1120:25:203
27608992711cyclictest134302chrt20:15:193
2760899210cyclictest0-21swapper/1120:20:173
2760899210cyclictest0-21swapper/1120:09:333
2760899200cyclictest115162sleep1120:14:553
2760699190cyclictest0-21swapper/922:14:5611
2759799194cyclictest0-21swapper/720:50:019
2759499190cyclictest0-21swapper/421:30:166
3066350180irq/52-eth0-rx-0-21swapper/920:26:1211
27608991817cyclictest0-21swapper/1119:21:563
27607991817cyclictest0-21swapper/1022:45:292
2760799181cyclictest3066350irq/52-eth0-rx-20:36:232
2760799181cyclictest12250irq/42-ahci21:06:542
2760799181cyclictest12250irq/42-ahci21:01:372
2760799181cyclictest12250irq/42-ahci00:20:162
2760699181cyclictest0-21swapper/923:30:1311
2760699181cyclictest0-21swapper/923:30:1211
2760699181cyclictest0-21swapper/922:55:1311
2760699181cyclictest0-21swapper/922:25:3811
27598991816cyclictest6482-21df21:35:1410
27598991816cyclictest6177-21snmp_rack3slot923:45:4810
27598991816cyclictest30964-21snmp_rack3slot922:52:0510
27598991816cyclictest2876-21snmp_rack3slot920:45:1810
27598991816cyclictest24062-21snmp_rack3slot923:26:5210
27598991816cyclictest22635-21snmp_rack3slot919:45:1110
27598991816cyclictest18075-21snmp_rack3slot921:05:2710
27598991816cyclictest16468-21snmp_rack3slot920:20:1510
27598991816cyclictest13424-21snmp_rack3slot921:45:1310
27598991816cyclictest13406-21hddtemp_smartct20:15:1810
27598991816cyclictest11661-21snmp_rack3slot920:56:1410
2759499189cyclictest18347-21sensors21:05:326
2759499180cyclictest0-21swapper/419:10:166
12250180irq/42-ahci0-21swapper/420:27:326
12250180irq/42-ahci0-21swapper/120:26:531
3066350170irq/52-eth0-rx-2760799cyclictest22:05:222
31170ksoftirqd/00-21swapper/022:30:300
27608991715cyclictest30238-21chrt21:24:513
27607991716cyclictest6927-21python20:05:292
27607991716cyclictest27318-1kworker/10:1H00:30:312
27607991716cyclictest23388-21python23:25:312
27607991716cyclictest0-21swapper/1023:15:362
27607991716cyclictest0-21swapper/1021:10:122
2760799170cyclictest77382sleep1000:39:472
2760799170cyclictest61372sleep1023:45:292
2760799170cyclictest57922sleep1023:00:492
2760799170cyclictest56052sleep1022:18:562
2760799170cyclictest48862sleep1021:30:522
2760799170cyclictest32572chrt20:00:292
2760799170cyclictest313322chrt23:36:412
2760799170cyclictest311452sleep1019:14:352
2760799170cyclictest310852sleep1022:53:482
2760799170cyclictest307672sleep1021:25:022
2760799170cyclictest3066450irq/53-eth0-tx-22:20:162
2760799170cyclictest3066350irq/52-eth0-rx-22:30:162
2760799170cyclictest3066350irq/52-eth0-rx-22:13:162
2760799170cyclictest3066350irq/52-eth0-rx-21:50:042
2760799170cyclictest3066350irq/52-eth0-rx-21:45:232
2760799170cyclictest3066350irq/52-eth0-rx-20:55:352
2760799170cyclictest3066350irq/52-eth0-rx-20:10:332
2760799170cyclictest3066350irq/52-eth0-rx-19:52:292
2760799170cyclictest3066350irq/52-eth0-rx-19:35:132
2760799170cyclictest3066350irq/52-eth0-rx-19:30:192
2760799170cyclictest302552sleep1020:40:092
2760799170cyclictest297522chrt19:55:042
2760799170cyclictest297292sleep1000:25:112
2760799170cyclictest28452sleep1019:15:352
2760799170cyclictest280082sleep1021:20:132
2760799170cyclictest27832sleep1023:44:182
2760799170cyclictest27832sleep1023:44:172
2760799170cyclictest261532sleep1023:30:182
2760799170cyclictest261532sleep1023:30:172
2760799170cyclictest253802chrt22:00:172
2760799170cyclictest253532sleep1000:17:092
2760799170cyclictest252722sleep1019:45:502
2760799170cyclictest236592sleep1021:15:132
2760799170cyclictest231552sleep1021:57:062
2760799170cyclictest221502sleep1020:25:552
2760799170cyclictest216622sleep1000:11:212
2760799170cyclictest216482sleep1019:41:032
2760799170cyclictest21122sleep1022:56:252
2760799170cyclictest186782chrt22:35:222
2760799170cyclictest181042sleep1000:07:212
2760799170cyclictest173522sleep1000:03:562
2760799170cyclictest148942sleep1020:16:192
2760799170cyclictest14492sleep1020:45:112
2760799170cyclictest135932sleep1023:57:432
2760799170cyclictest122502sleep1021:42:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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