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2026-05-29 - 19:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri May 29, 2026 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13637210795sleep40-21swapper/407:07:526
13484210693sleep80-21swapper/807:05:4410
30549501000irq/53-eth0-rx-0-21swapper/107:09:111
3054950990irq/53-eth0-rx-0-21swapper/207:06:004
3054950950irq/53-eth0-rx-0-21swapper/707:09:469
1346929583sleep60-21swapper/607:05:298
3054950900irq/53-eth0-rx-0-21swapper/307:07:015
3054950890irq/53-eth0-rx-0-21swapper/1107:05:063
3054950860irq/53-eth0-rx-0-21swapper/507:05:417
3054950840irq/53-eth0-rx-0-21swapper/1007:06:342
171450730irq/56-eth1-rx-0-21swapper/907:09:5511
1359025853sleep00-21swapper/007:07:110
13966994945cyclictest0-21swapper/009:18:350
13966993229cyclictest0-21swapper/010:17:310
14007993015cyclictest14936-21kworker/11:210:17:293
13996993029cyclictest3054950irq/53-eth0-rx-09:18:319
13994993028cyclictest3054950irq/53-eth0-rx-09:18:477
13990993029cyclictest3054950irq/53-eth0-rx-09:18:375
13976993029cyclictest3054950irq/53-eth0-rx-09:18:341
14005992726cyclictest3054950irq/53-eth0-rx-09:18:3711
14004992726cyclictest3054950irq/53-eth0-rx-09:18:3910
13983992422cyclictest3054950irq/53-eth0-rx-09:18:384
1396699220cyclictest0-21swapper/009:21:570
14007991918cyclictest3055050irq/54-eth0-tx-09:18:463
14006991918cyclictest3054950irq/53-eth0-rx-09:18:362
1400599192cyclictest3054950irq/53-eth0-rx-12:13:2211
1400599192cyclictest3054950irq/53-eth0-rx-12:13:2111
1400599192cyclictest0-21swapper/912:29:1711
1400599192cyclictest0-21swapper/910:58:1511
1400599192cyclictest0-21swapper/910:17:0711
14006991817cyclictest9114-21kworker/10:111:19:112
14006991817cyclictest811rcuc/1011:09:352
14006991817cyclictest0-21swapper/1012:26:472
14006991817cyclictest0-21swapper/1010:48:062
1400699181cyclictest3055050irq/54-eth0-tx-11:29:392
1400699181cyclictest3055050irq/54-eth0-tx-10:50:292
1400699181cyclictest3054950irq/53-eth0-rx-12:37:542
1400699181cyclictest3054950irq/53-eth0-rx-11:46:052
1400699181cyclictest3054950irq/53-eth0-rx-11:11:042
1400699181cyclictest3054950irq/53-eth0-rx-09:24:572
1400599181cyclictest761ksoftirqd/910:45:2211
1400599181cyclictest741rcuc/909:46:1411
1400599181cyclictest32301-21kworker/9:011:57:4711
1400599181cyclictest32301-21kworker/9:011:57:4611
1400599181cyclictest0-21swapper/912:17:2411
1400599181cyclictest0-21swapper/912:07:1511
1400599181cyclictest0-21swapper/912:03:4911
1400599181cyclictest0-21swapper/911:53:2511
1400599181cyclictest0-21swapper/911:49:0211
1400599181cyclictest0-21swapper/911:05:2711
1400599181cyclictest0-21swapper/911:02:0411
1400599181cyclictest0-21swapper/910:25:1211
1400599181cyclictest0-21swapper/909:41:0611
1400599181cyclictest0-21swapper/909:26:1311
1400599181cyclictest0-21swapper/909:23:2911
1400599181cyclictest0-21swapper/909:10:5911
13993991817cyclictest3054950irq/53-eth0-rx-09:18:396
1396699180cyclictest0-21swapper/009:08:140
14006991716cyclictest0-21swapper/1008:00:022
1400699170cyclictest98832sleep1009:55:282
1400699170cyclictest57732sleep1010:20:072
1400699170cyclictest5272sleep1007:45:372
1400699170cyclictest49812sleep1012:30:102
1400699170cyclictest43742sleep1007:51:372
1400699170cyclictest324402sleep1012:00:072
1400699170cyclictest322442sleep1007:42:252
1400699170cyclictest307542sleep1008:46:322
1400699170cyclictest3055050irq/54-eth0-tx-12:15:152
1400699170cyclictest3055050irq/54-eth0-tx-11:00:262
1400699170cyclictest3055050irq/54-eth0-tx-09:25:392
1400699170cyclictest3054950irq/53-eth0-rx-12:21:112
1400699170cyclictest3054950irq/53-eth0-rx-12:21:112
1400699170cyclictest3054950irq/53-eth0-rx-12:10:032
1400699170cyclictest3054950irq/53-eth0-rx-12:10:022
1400699170cyclictest3054950irq/53-eth0-rx-12:06:252
1400699170cyclictest3054950irq/53-eth0-rx-11:58:232
1400699170cyclictest3054950irq/53-eth0-rx-11:58:222
1400699170cyclictest3054950irq/53-eth0-rx-11:50:382
1400699170cyclictest3054950irq/53-eth0-rx-11:40:172
1400699170cyclictest3054950irq/53-eth0-rx-11:31:002
1400699170cyclictest3054950irq/53-eth0-rx-10:55:192
1400699170cyclictest3054950irq/53-eth0-rx-10:40:352
1400699170cyclictest3054950irq/53-eth0-rx-10:10:182
1400699170cyclictest3054950irq/53-eth0-rx-10:02:442
1400699170cyclictest3054950irq/53-eth0-rx-09:51:252
1400699170cyclictest3054950irq/53-eth0-rx-09:45:442
1400699170cyclictest3054950irq/53-eth0-rx-09:31:432
1400699170cyclictest3054950irq/53-eth0-rx-09:14:382
1400699170cyclictest3054950irq/53-eth0-rx-08:52:372
1400699170cyclictest3054950irq/53-eth0-rx-08:52:362
1400699170cyclictest3054950irq/53-eth0-rx-08:25:152
1400699170cyclictest3054950irq/53-eth0-rx-07:56:532
1400699170cyclictest284372sleep1007:35:112
1400699170cyclictest278212sleep1007:33:482
1400699170cyclictest270612sleep1008:40:552
1400699170cyclictest270612sleep1008:40:542
1400699170cyclictest25472chrt10:15:302
1400699170cyclictest241892sleep1007:29:002
1400699170cyclictest233802chrt07:24:592
1400699170cyclictest218712sleep1009:40:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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