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2026-02-24 - 11:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Feb 24, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501160irq/53-eth0-rx-0-21swapper/119:09:441
9918501160irq/53-eth0-rx-0-21swapper/119:09:431
9918501110irq/53-eth0-rx-0-21swapper/219:09:004
9918501110irq/53-eth0-rx-0-21swapper/219:09:004
5296210995sleep100-21swapper/1019:06:422
5296210995sleep100-21swapper/1019:06:422
9918501000irq/53-eth0-rx-0-21swapper/519:06:097
9918501000irq/53-eth0-rx-0-21swapper/519:06:097
991850960irq/53-eth0-rx-0-21swapper/419:05:506
991850960irq/53-eth0-rx-0-21swapper/419:05:506
12850940irq/42-ahci0-21swapper/719:09:379
12850940irq/42-ahci0-21swapper/719:09:379
991850930irq/53-eth0-rx-0-21swapper/819:08:2310
991850930irq/53-eth0-rx-0-21swapper/819:08:2210
991850930irq/53-eth0-rx-0-21swapper/319:07:375
991850930irq/53-eth0-rx-0-21swapper/319:07:365
991850900irq/53-eth0-rx-0-21swapper/919:07:4211
991850900irq/53-eth0-rx-0-21swapper/919:07:4211
528228274sleep110-21swapper/1119:06:313
528228274sleep110-21swapper/1119:06:303
541026553sleep00-21swapper/019:08:080
541026553sleep00-21swapper/019:08:080
537025853sleep60-21swapper/619:07:388
537025853sleep60-21swapper/619:07:378
5749993014cyclictest0-21swapper/1122:27:383
571699290cyclictest0-21swapper/020:11:140
5749992221cyclictest0-21swapper/1119:26:013
5716992221cyclictest0-21swapper/021:28:430
574899192cyclictest991850irq/53-eth0-rx-21:21:302
574899192cyclictest991850irq/53-eth0-rx-00:35:112
574899192cyclictest991850irq/53-eth0-rx-00:23:372
574899192cyclictest991850irq/53-eth0-rx-00:18:292
574899192cyclictest991850irq/53-eth0-rx-00:13:082
574799192cyclictest0-21swapper/922:25:2911
5747991918cyclictest30361-21cstates20:25:1311
5749991817cyclictest12850irq/42-ahci20:26:433
5748991817cyclictest0-21swapper/1000:34:432
574899181cyclictest991950irq/54-eth0-tx-21:36:212
574899181cyclictest991850irq/53-eth0-rx-23:52:412
574899181cyclictest991850irq/53-eth0-rx-23:48:522
574899181cyclictest991850irq/53-eth0-rx-23:39:542
574899181cyclictest991850irq/53-eth0-rx-23:17:412
574899181cyclictest991850irq/53-eth0-rx-23:08:462
574899181cyclictest991850irq/53-eth0-rx-23:08:462
574899181cyclictest991850irq/53-eth0-rx-23:01:062
574899181cyclictest991850irq/53-eth0-rx-23:01:052
574899181cyclictest991850irq/53-eth0-rx-22:52:232
574899181cyclictest991850irq/53-eth0-rx-22:35:562
574899181cyclictest991850irq/53-eth0-rx-22:30:482
574899181cyclictest991850irq/53-eth0-rx-22:29:142
574899181cyclictest991850irq/53-eth0-rx-22:17:122
574899181cyclictest991850irq/53-eth0-rx-22:17:122
574899181cyclictest991850irq/53-eth0-rx-22:13:362
574899181cyclictest991850irq/53-eth0-rx-22:06:242
574899181cyclictest991850irq/53-eth0-rx-22:06:232
574899181cyclictest991850irq/53-eth0-rx-21:25:122
574899181cyclictest991850irq/53-eth0-rx-21:19:292
574899181cyclictest991850irq/53-eth0-rx-20:45:362
574899181cyclictest991850irq/53-eth0-rx-00:05:442
574899181cyclictest12850irq/42-ahci23:33:372
574899181cyclictest12850irq/42-ahci22:41:392
574899181cyclictest12850irq/42-ahci22:22:072
574899181cyclictest12850irq/42-ahci21:58:052
574899181cyclictest12850irq/42-ahci21:47:282
574899181cyclictest12850irq/42-ahci19:51:312
574899181cyclictest12850irq/42-ahci19:15:582
574799181cyclictest0-21swapper/923:45:0211
574799181cyclictest0-21swapper/923:42:1711
574799181cyclictest0-21swapper/923:02:0611
574799181cyclictest0-21swapper/923:02:0611
574799181cyclictest0-21swapper/922:35:3511
574799181cyclictest0-21swapper/922:19:0011
574799181cyclictest0-21swapper/922:19:0011
574799181cyclictest0-21swapper/922:06:0811
574799181cyclictest0-21swapper/922:06:0711
574799181cyclictest0-21swapper/921:55:3411
574799181cyclictest0-21swapper/921:50:0411
574799181cyclictest0-21swapper/921:40:4011
574799181cyclictest0-21swapper/921:37:4111
574799181cyclictest0-21swapper/921:32:3011
574799181cyclictest0-21swapper/921:22:2411
574799181cyclictest0-21swapper/900:39:0411
574799181cyclictest0-21swapper/900:25:1511
574799181cyclictest0-21swapper/900:22:2811
574799181cyclictest0-21swapper/900:16:2311
574799181cyclictest0-21swapper/900:11:2911
574799181cyclictest0-21swapper/900:00:5711
5743991816cyclictest5944-21qemu-kvm22:30:117
5743991816cyclictest5943-21qemu-kvm22:20:127
5748991716cyclictest0-21swapper/1020:05:252
574899170cyclictest991950irq/54-eth0-tx-22:55:122
574899170cyclictest991850irq/53-eth0-rx-23:55:062
574899170cyclictest991850irq/53-eth0-rx-23:40:012
574899170cyclictest991850irq/53-eth0-rx-23:25:092
574899170cyclictest991850irq/53-eth0-rx-23:20:372
574899170cyclictest991850irq/53-eth0-rx-23:10:182
574899170cyclictest991850irq/53-eth0-rx-22:45:092
574899170cyclictest991850irq/53-eth0-rx-22:45:092
574899170cyclictest991850irq/53-eth0-rx-22:00:222
574899170cyclictest991850irq/53-eth0-rx-21:50:502
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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