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2026-02-01 - 19:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Feb 01, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6982211195sleep10-21swapper/107:07:191
991850950irq/53-eth0-rx-0-21swapper/207:07:364
991850930irq/53-eth0-rx-0-21swapper/507:07:187
991950920irq/54-eth0-tx-0-21swapper/307:07:035
991850920irq/53-eth0-rx-0-21swapper/707:05:029
991850920irq/53-eth0-rx-0-21swapper/407:05:496
991850850irq/53-eth0-rx-0-21swapper/1107:05:133
991850810irq/53-eth0-rx-0-21swapper/1007:06:532
991850700irq/53-eth0-rx-0-21swapper/807:07:1110
686726354sleep90-21swapper/907:05:5011
691025955sleep60-21swapper/607:06:238
406525955sleep00-21swapper/007:05:050
7390993617cyclictest0-21swapper/1108:20:043
7390993617cyclictest0-21swapper/1108:19:553
7344993028cyclictest0-21swapper/007:11:140
734499290cyclictest5047-21rs:main0
7385992710cyclictest831ksoftirqd/1009:00:152
7390992321cyclictest237022chrt08:14:353
7344992321cyclictest22267-21nscd09:24:020
738599203cyclictest831ksoftirqd/1010:05:122
739099190cyclictest20093-21turbostat08:10:013
738599192cyclictest991850irq/53-eth0-rx-12:30:572
738599192cyclictest991850irq/53-eth0-rx-12:27:022
738599192cyclictest991850irq/53-eth0-rx-10:49:192
738599192cyclictest991850irq/53-eth0-rx-10:39:592
738599192cyclictest991850irq/53-eth0-rx-09:11:582
738499192cyclictest0-21swapper/910:49:2011
738499192cyclictest0-21swapper/909:14:2711
7385991817cyclictest831ksoftirqd/1011:46:422
7385991817cyclictest0-21swapper/1012:17:512
7385991817cyclictest0-21swapper/1011:21:202
7385991817cyclictest0-21swapper/1011:15:132
7385991817cyclictest0-21swapper/1010:20:252
7385991817cyclictest0-21swapper/1009:32:522
7385991817cyclictest0-21swapper/1009:32:522
7385991817cyclictest0-21swapper/1009:26:362
7385991817cyclictest0-21swapper/1009:26:362
7385991817cyclictest0-21swapper/1009:05:202
7385991817cyclictest0-21swapper/1008:56:202
738599181cyclictest991950irq/54-eth0-tx-12:35:562
738599181cyclictest991950irq/54-eth0-tx-12:21:412
738599181cyclictest991850irq/53-eth0-rx-12:05:032
738599181cyclictest991850irq/53-eth0-rx-12:00:182
738599181cyclictest991850irq/53-eth0-rx-11:57:232
738599181cyclictest991850irq/53-eth0-rx-11:13:112
738599181cyclictest991850irq/53-eth0-rx-10:57:432
738599181cyclictest991850irq/53-eth0-rx-10:53:052
738599181cyclictest991850irq/53-eth0-rx-10:40:022
738599181cyclictest991850irq/53-eth0-rx-10:15:532
738599181cyclictest991850irq/53-eth0-rx-09:59:462
738599181cyclictest991850irq/53-eth0-rx-09:52:252
738599181cyclictest991850irq/53-eth0-rx-09:49:472
738599181cyclictest991850irq/53-eth0-rx-09:42:322
738599181cyclictest991850irq/53-eth0-rx-09:42:322
738599181cyclictest991850irq/53-eth0-rx-09:37:582
738599181cyclictest991850irq/53-eth0-rx-07:20:432
738599181cyclictest12850irq/42-ahci08:21:352
738499181cyclictest0-21swapper/912:28:0611
738499181cyclictest0-21swapper/912:18:0511
738499181cyclictest0-21swapper/911:14:1611
738499181cyclictest0-21swapper/911:05:3511
738499181cyclictest0-21swapper/910:56:5811
738499181cyclictest0-21swapper/910:19:1911
738499181cyclictest0-21swapper/910:11:0111
738499181cyclictest0-21swapper/910:02:3111
738499181cyclictest0-21swapper/909:55:2611
738499181cyclictest0-21swapper/909:36:3811
738499181cyclictest0-21swapper/909:26:1611
738499181cyclictest0-21swapper/909:26:1611
738499181cyclictest0-21swapper/909:22:4911
738499181cyclictest0-21swapper/908:25:2611
738499181cyclictest0-21swapper/907:33:1411
738499181cyclictest0-21swapper/907:15:2411
7381991816cyclictest4987-21qemu-kvm10:35:308
7381991816cyclictest4987-21qemu-kvm10:25:158
7381991816cyclictest31428-21qemu-kvm09:14:538
7381991816cyclictest31427-21qemu-kvm09:08:388
737299180cyclictest0-21swapper/411:45:126
734499182cyclictest0-21swapper/008:30:030
7385991716cyclictest0-21swapper/1008:30:022
7385991716cyclictest0-21swapper/1007:35:192
738599170cyclictest991850irq/53-eth0-rx-11:40:052
738599170cyclictest991850irq/53-eth0-rx-11:35:152
738599170cyclictest991850irq/53-eth0-rx-11:30:012
738599170cyclictest991850irq/53-eth0-rx-11:05:172
738599170cyclictest991850irq/53-eth0-rx-11:00:032
738599170cyclictest991850irq/53-eth0-rx-10:30:092
738599170cyclictest991850irq/53-eth0-rx-10:25:362
738599170cyclictest991850irq/53-eth0-rx-10:00:432
738599170cyclictest991850irq/53-eth0-rx-09:15:042
738599170cyclictest991850irq/53-eth0-rx-09:15:042
738599170cyclictest991850irq/53-eth0-rx-08:51:132
738599170cyclictest991850irq/53-eth0-rx-08:40:552
738599170cyclictest991850irq/53-eth0-rx-08:25:172
738599170cyclictest991850irq/53-eth0-rx-08:11:062
738599170cyclictest991850irq/53-eth0-rx-08:02:122
738599170cyclictest991850irq/53-eth0-rx-07:48:212
738599170cyclictest991850irq/53-eth0-rx-07:40:142
738599170cyclictest991850irq/53-eth0-rx-07:25:192
738599170cyclictest991850irq/53-eth0-rx-07:11:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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