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2026-01-27 - 19:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Jan 27, 2026 12:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501040irq/53-eth0-rx-0-21swapper/207:06:104
9918501010irq/53-eth0-rx-0-21swapper/707:09:469
12850990irq/42-ahci0-21swapper/107:09:441
991950950irq/54-eth0-tx-0-21swapper/507:05:187
991850920irq/53-eth0-rx-0-21swapper/807:06:5810
991850920irq/53-eth0-rx-0-21swapper/407:06:196
991850920irq/53-eth0-rx-0-21swapper/307:06:385
172450880irq/56-eth1-rx-0-21swapper/907:09:1911
991850800irq/53-eth0-rx-0-21swapper/1107:07:483
1372926455sleep100-21swapper/1007:05:392
1373826151sleep60-21swapper/607:05:478
1388725955sleep00-21swapper/007:07:410
14217993635cyclictest0-21swapper/009:16:460
14217993431cyclictest0-21swapper/009:10:370
962823029sleep110-21swapper/1109:10:293
14258993016cyclictest831ksoftirqd/1009:48:352
14258992913cyclictest831ksoftirqd/1010:16:432
14258992710cyclictest831ksoftirqd/1012:08:262
1425899225cyclictest831ksoftirqd/1009:04:502
14254992214cyclictest11585-21snmp_rack3slot909:40:138
1425899203cyclictest831ksoftirqd/1012:33:302
1425899203cyclictest831ksoftirqd/1010:30:212
1425899203cyclictest831ksoftirqd/1009:58:312
1425899192cyclictest831ksoftirqd/1012:25:152
1425899192cyclictest831ksoftirqd/1012:15:242
1425899192cyclictest831ksoftirqd/1011:51:422
1425899192cyclictest831ksoftirqd/1011:51:422
1425899192cyclictest831ksoftirqd/1011:46:582
1425899192cyclictest831ksoftirqd/1011:46:572
1425899192cyclictest831ksoftirqd/1011:34:082
1425899192cyclictest831ksoftirqd/1011:28:052
1425899192cyclictest831ksoftirqd/1011:28:042
1425899192cyclictest831ksoftirqd/1011:00:022
1425899192cyclictest831ksoftirqd/1010:25:272
1425899192cyclictest831ksoftirqd/1010:24:502
1425899192cyclictest831ksoftirqd/1010:14:472
1425899192cyclictest831ksoftirqd/1010:00:072
1425899192cyclictest831ksoftirqd/1009:41:142
1425899192cyclictest831ksoftirqd/1009:38:312
1425899192cyclictest831ksoftirqd/1009:30:222
1425899192cyclictest831ksoftirqd/1009:29:312
1425899192cyclictest831ksoftirqd/1009:22:582
1425899192cyclictest831ksoftirqd/1009:15:302
1425899192cyclictest831ksoftirqd/1009:10:522
1425899192cyclictest831ksoftirqd/1007:30:152
1425799192cyclictest0-21swapper/909:49:4411
1425799192cyclictest0-21swapper/909:22:1711
14258991817cyclictest831ksoftirqd/1008:50:122
1425899181cyclictest991850irq/53-eth0-rx-12:10:142
1425899181cyclictest991850irq/53-eth0-rx-12:00:202
1425899181cyclictest991850irq/53-eth0-rx-12:00:202
1425899181cyclictest991850irq/53-eth0-rx-11:35:032
1425899181cyclictest831ksoftirqd/1012:35:072
1425899181cyclictest831ksoftirqd/1012:20:232
1425899181cyclictest831ksoftirqd/1011:55:152
1425899181cyclictest831ksoftirqd/1011:40:072
1425899181cyclictest831ksoftirqd/1011:20:122
1425899181cyclictest831ksoftirqd/1011:15:502
1425899181cyclictest831ksoftirqd/1011:10:442
1425899181cyclictest831ksoftirqd/1011:05:082
1425899181cyclictest831ksoftirqd/1010:55:172
1425899181cyclictest831ksoftirqd/1010:50:202
1425899181cyclictest831ksoftirqd/1010:48:532
1425899181cyclictest831ksoftirqd/1010:40:142
1425899181cyclictest831ksoftirqd/1010:35:032
1425899181cyclictest831ksoftirqd/1010:06:052
1425899181cyclictest831ksoftirqd/1009:50:182
1425899181cyclictest831ksoftirqd/1008:55:132
1425899181cyclictest831ksoftirqd/1008:32:012
1425899181cyclictest831ksoftirqd/1008:20:262
1425899181cyclictest831ksoftirqd/1008:10:162
1425899181cyclictest831ksoftirqd/1008:05:212
1425899181cyclictest831ksoftirqd/1007:49:102
1425899181cyclictest831ksoftirqd/1007:40:152
1425899181cyclictest831ksoftirqd/1007:25:222
1425899181cyclictest831ksoftirqd/1007:20:132
1425899181cyclictest831ksoftirqd/1007:15:152
14257991817cyclictest29315-21hwlatdetect08:55:1611
1425799181cyclictest761ksoftirqd/912:30:1311
1425799181cyclictest761ksoftirqd/911:15:1111
1425799181cyclictest761ksoftirqd/910:35:0111
1425799181cyclictest761ksoftirqd/910:15:1411
1425799181cyclictest761ksoftirqd/909:10:1111
1425799181cyclictest761ksoftirqd/908:15:1111
1425799181cyclictest27065-21perl10:20:1411
1425799181cyclictest10418-21kworker/9:010:48:3511
1425799181cyclictest0-21swapper/912:27:4711
1425799181cyclictest0-21swapper/911:40:3611
1425799181cyclictest0-21swapper/911:38:5111
1425799181cyclictest0-21swapper/911:10:5711
1425799181cyclictest0-21swapper/911:08:1411
1425799181cyclictest0-21swapper/910:44:2711
1425799181cyclictest0-21swapper/910:08:2411
1425799181cyclictest0-21swapper/909:55:4111
1425799181cyclictest0-21swapper/909:28:2711
1425799181cyclictest0-21swapper/908:40:2511
1425799181cyclictest0-21swapper/908:40:2511
14217991816cyclictest291342sleep009:28:200
14258991716cyclictest0-21swapper/1008:35:072
14258991716cyclictest0-21swapper/1008:35:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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