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2026-05-15 - 06:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri May 15, 2026 00:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501090irq/53-eth0-rx-0-21swapper/219:06:334
24420210792sleep110-21swapper/1119:07:163
9918501050irq/53-eth0-rx-0-21swapper/119:07:281
128501010irq/42-ahci0-21swapper/319:09:595
991850970irq/53-eth0-rx-0-21swapper/719:07:439
991850920irq/53-eth0-rx-0-21swapper/419:07:116
991850880irq/53-eth0-rx-0-21swapper/819:09:4910
991850850irq/53-eth0-rx-0-21swapper/519:06:237
2463428581sleep90-21swapper/919:09:2611
2462527362sleep00-21swapper/019:09:180
991850680irq/53-eth0-rx-0-21swapper/1019:06:372
2428125753sleep60-21swapper/619:05:358
2478199290cyclictest0-21swapper/020:26:410
12850280irq/42-ahci0-21swapper/720:26:549
2478199238cyclictest0-21swapper/021:25:220
991850210irq/53-eth0-rx-0-21swapper/220:26:544
2478199200cyclictest0-21swapper/019:30:220
2482399192cyclictest991850irq/53-eth0-rx-21:42:552
2482399192cyclictest991850irq/53-eth0-rx-21:42:542
24821991917cyclictest0-21swapper/822:49:5910
2478199190cyclictest0-21swapper/022:20:200
24823991817cyclictest0-21swapper/1022:37:502
24823991817cyclictest0-21swapper/1022:16:002
24823991817cyclictest0-21swapper/1022:01:252
24823991816cyclictest25481-21ssh23:30:442
2482399181cyclictest991850irq/53-eth0-rx-23:28:132
2482399181cyclictest991850irq/53-eth0-rx-22:42:552
2482399181cyclictest991850irq/53-eth0-rx-22:09:142
2482399181cyclictest991850irq/53-eth0-rx-21:16:492
2482399181cyclictest991850irq/53-eth0-rx-21:16:492
2482399181cyclictest991850irq/53-eth0-rx-00:33:402
2482399181cyclictest991850irq/53-eth0-rx-00:16:082
2482399181cyclictest991850irq/53-eth0-rx-00:00:282
2482399180cyclictest991850irq/53-eth0-rx-22:33:012
24819991816cyclictest16558-21qemu-kvm21:41:548
24819991816cyclictest16558-21qemu-kvm21:41:538
24819991816cyclictest16558-21qemu-kvm21:25:128
24819991816cyclictest16558-21qemu-kvm21:16:478
24819991816cyclictest16558-21qemu-kvm21:16:468
24819991816cyclictest16558-21qemu-kvm21:11:458
24819991811cyclictest32598-21snmp_rack3slot900:31:378
24781991817cyclictest22268-21nscd22:19:150
2478199180cyclictest0-21swapper/023:00:270
24823991715cyclictest13406-21ssh23:20:292
2482399170cyclictest991950irq/54-eth0-tx-21:36:092
2482399170cyclictest991950irq/54-eth0-tx-21:36:082
2482399170cyclictest991950irq/54-eth0-tx-00:20:312
2482399170cyclictest991850irq/53-eth0-rx-23:50:202
2482399170cyclictest991850irq/53-eth0-rx-23:06:012
2482399170cyclictest991850irq/53-eth0-rx-22:50:472
2482399170cyclictest991850irq/53-eth0-rx-22:47:052
2482399170cyclictest991850irq/53-eth0-rx-22:26:592
2482399170cyclictest991850irq/53-eth0-rx-22:11:002
2482399170cyclictest991850irq/53-eth0-rx-21:56:542
2482399170cyclictest991850irq/53-eth0-rx-21:00:132
2482399170cyclictest991850irq/53-eth0-rx-20:16:582
2482399170cyclictest991850irq/53-eth0-rx-19:26:522
2482399170cyclictest86512sleep1000:11:142
2482399170cyclictest85012sleep1020:10:332
2482399170cyclictest80262sleep1023:16:322
2482399170cyclictest7842sleep1019:18:512
2482399170cyclictest58922sleep1000:36:052
2482399170cyclictest57532sleep1021:25:312
2482399170cyclictest5752chrt21:22:052
2482399170cyclictest53562sleep1020:50:512
2482399170cyclictest49972sleep1022:20:132
2482399170cyclictest49532sleep1023:40:342
2482399170cyclictest47842sleep1020:05:332
2482399170cyclictest42812chrt19:20:282
2482399170cyclictest324282sleep1023:10:182
2482399170cyclictest305332sleep1020:42:262
2482399170cyclictest304032sleep1023:35:222
2482399170cyclictest299312chrt19:56:562
2482399170cyclictest296932sleep1021:45:452
2482399170cyclictest28592sleep1000:06:372
2482399170cyclictest274242sleep1000:28:062
2482399170cyclictest268502sleep1020:36:482
2482399170cyclictest263812sleep1019:53:092
2482399170cyclictest252722sleep1019:10:032
2482399170cyclictest235032sleep1023:57:012
2482399170cyclictest232092sleep1020:32:002
2482399170cyclictest22972sleep1021:50:212
2482399170cyclictest227972chrt23:01:542
2482399170cyclictest225502sleep1019:45:542
2482399170cyclictest194712sleep1020:25:482
2482399170cyclictest189492sleep1019:41:312
2482399170cyclictest17072chrt20:47:022
2482399170cyclictest164262sleep1021:07:042
2482399170cyclictest160492sleep1022:55:292
2482399170cyclictest152912sleep1019:36:182
2482399170cyclictest12850irq/42-ahci21:11:022
2482399170cyclictest12850irq/42-ahci20:58:092
2482399170cyclictest12850irq/42-ahci20:20:092
2482399170cyclictest123442sleep1021:31:422
2482399170cyclictest117222sleep1019:32:182
2482399170cyclictest115762sleep1023:46:472
2482399170cyclictest11202sleep1020:01:342
2482199170cyclictest0-21swapper/820:40:0110
24819991716cyclictest16558-21qemu-kvm21:45:148
24819991716cyclictest16558-21qemu-kvm21:36:528
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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