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2026-06-29 - 03:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Jun 29, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5047210894sleep80-21swapper/819:07:4610
4990210894sleep20-21swapper/219:07:044
4870210893sleep70-21swapper/719:05:339
5053210492sleep10-21swapper/119:07:521
3054950930irq/53-eth0-rx-0-21swapper/419:07:436
3054950910irq/53-eth0-rx-0-21swapper/319:06:345
3054950880irq/53-eth0-rx-0-21swapper/519:05:207
3054950790irq/53-eth0-rx-0-21swapper/1119:06:263
521927068sleep100-21swapper/1019:09:252
490326961sleep90-21swapper/919:05:5911
489425955sleep00-21swapper/019:05:500
200825753sleep60-21swapper/619:05:088
5369994326cyclictest0-21swapper/021:20:460
5369993015cyclictest2292-21nscd21:17:100
5382992826cyclictest29640-21diskmemload22:23:575
3054950280irq/53-eth0-rx-0-21swapper/721:20:379
12250280irq/42-ahci0-21swapper/121:20:371
5411992018cyclictest0-21swapper/1119:19:113
541099192cyclictest3054950irq/53-eth0-rx-23:21:302
540999192cyclictest0-21swapper/923:16:3811
5410991817cyclictest0-21swapper/1023:07:332
5410991817cyclictest0-21swapper/1023:07:332
5410991817cyclictest0-21swapper/1023:01:012
5410991817cyclictest0-21swapper/1022:02:272
5410991817cyclictest0-21swapper/1021:35:282
5410991817cyclictest0-21swapper/1000:20:102
5410991817cyclictest0-21swapper/1000:03:532
541099181cyclictest3054950irq/53-eth0-rx-23:38:262
541099181cyclictest3054950irq/53-eth0-rx-23:38:262
541099181cyclictest3054950irq/53-eth0-rx-23:16:312
541099181cyclictest3054950irq/53-eth0-rx-22:51:512
541099181cyclictest3054950irq/53-eth0-rx-22:26:352
541099181cyclictest3054950irq/53-eth0-rx-21:44:312
541099181cyclictest3054950irq/53-eth0-rx-21:25:342
541099181cyclictest3054950irq/53-eth0-rx-21:17:232
541099181cyclictest3054950irq/53-eth0-rx-20:26:202
541099181cyclictest3054950irq/53-eth0-rx-20:13:152
541099181cyclictest3054950irq/53-eth0-rx-20:13:152
541099181cyclictest3054950irq/53-eth0-rx-00:39:222
541099181cyclictest3054950irq/53-eth0-rx-00:05:402
541099181cyclictest12250irq/42-ahci20:46:262
541099181cyclictest12250irq/42-ahci20:09:302
540999189cyclictest11917-21if_err_eth122:15:1611
5409991810cyclictest30370-21ssh23:25:1311
5409991810cyclictest30370-21ssh23:25:1311
5409991810cyclictest0-21swapper/900:24:3111
540999181cyclictest0-21swapper/923:31:4911
540999181cyclictest0-21swapper/923:00:3011
540999181cyclictest0-21swapper/922:05:3711
540999181cyclictest0-21swapper/921:43:5411
540999181cyclictest0-21swapper/921:17:1111
540999181cyclictest0-21swapper/900:29:5911
540999181cyclictest0-21swapper/900:15:1911
540799184cyclictest0-21swapper/719:35:189
536999180cyclictest0-21swapper/019:47:210
5411991715cyclictest11778-21snmp_rack3slot922:15:153
541199170cyclictest0-21swapper/1121:08:283
5410991716cyclictest0-21swapper/1023:51:452
5410991716cyclictest0-21swapper/1023:40:292
5410991716cyclictest0-21swapper/1023:40:292
5410991716cyclictest0-21swapper/1023:30:092
5410991716cyclictest0-21swapper/1022:45:322
5410991716cyclictest0-21swapper/1019:57:032
5410991716cyclictest0-21swapper/1019:16:042
541099170cyclictest3482sleep1023:27:062
541099170cyclictest3482sleep1023:27:062
541099170cyclictest315282sleep1022:30:592
541099170cyclictest3055050irq/54-eth0-tx-00:25:052
541099170cyclictest3054950irq/53-eth0-rx-23:55:412
541099170cyclictest3054950irq/53-eth0-rx-23:45:132
541099170cyclictest3054950irq/53-eth0-rx-23:10:512
541099170cyclictest3054950irq/53-eth0-rx-22:55:202
541099170cyclictest3054950irq/53-eth0-rx-22:42:022
541099170cyclictest3054950irq/53-eth0-rx-22:20:492
541099170cyclictest3054950irq/53-eth0-rx-22:10:042
541099170cyclictest3054950irq/53-eth0-rx-22:05:582
541099170cyclictest3054950irq/53-eth0-rx-21:56:032
541099170cyclictest3054950irq/53-eth0-rx-21:45:422
541099170cyclictest3054950irq/53-eth0-rx-21:30:082
541099170cyclictest3054950irq/53-eth0-rx-21:11:102
541099170cyclictest3054950irq/53-eth0-rx-21:07:292
541099170cyclictest3054950irq/53-eth0-rx-20:55:262
541099170cyclictest3054950irq/53-eth0-rx-20:50:062
541099170cyclictest3054950irq/53-eth0-rx-20:40:372
541099170cyclictest3054950irq/53-eth0-rx-20:39:502
541099170cyclictest3054950irq/53-eth0-rx-20:34:332
541099170cyclictest3054950irq/53-eth0-rx-20:15:052
541099170cyclictest3054950irq/53-eth0-rx-19:52:492
541099170cyclictest3054950irq/53-eth0-rx-19:30:182
541099170cyclictest3054950irq/53-eth0-rx-19:10:242
541099170cyclictest3054950irq/53-eth0-rx-00:10:342
541099170cyclictest290152chrt19:40:032
541099170cyclictest281772chrt19:35:392
541099170cyclictest259432sleep1020:20:092
541099170cyclictest258712sleep1000:15:232
541099170cyclictest255962sleep1021:01:002
541099170cyclictest204532sleep1019:25:262
541099170cyclictest130712sleep1021:50:072
541099170cyclictest128862sleep1021:20:512
541099170cyclictest12250irq/42-ahci19:47:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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