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2026-02-21 - 07:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Feb 21, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20287210693sleep10-21swapper/119:07:381
20287210693sleep10-21swapper/119:07:371
991850980irq/53-eth0-rx-0-21swapper/419:08:526
991850980irq/53-eth0-rx-0-21swapper/419:08:516
991850980irq/53-eth0-rx-0-21swapper/319:09:325
991850980irq/53-eth0-rx-0-21swapper/319:09:315
991850980irq/53-eth0-rx-0-21swapper/219:07:024
991850980irq/53-eth0-rx-0-21swapper/219:07:014
991850970irq/53-eth0-rx-0-21swapper/819:08:1510
991850970irq/53-eth0-rx-0-21swapper/819:08:1510
1939229682sleep100-21swapper/1019:05:232
1939229682sleep100-21swapper/1019:05:222
991850920irq/53-eth0-rx-0-21swapper/719:06:169
991850920irq/53-eth0-rx-0-21swapper/719:06:159
991850890irq/53-eth0-rx-0-21swapper/519:07:467
991850890irq/53-eth0-rx-0-21swapper/519:07:467
2026828270sleep00-21swapper/019:07:250
2026828270sleep00-21swapper/019:07:240
2050127876sleep90-21swapper/919:09:4611
2050127876sleep90-21swapper/919:09:4511
2028426658sleep110-21swapper/1119:07:353
2028426658sleep110-21swapper/1119:07:353
2011925955sleep60-21swapper/619:05:308
2011925955sleep60-21swapper/619:05:308
2063099320cyclictest0-21swapper/021:19:160
20630993129cyclictest33502chrt21:27:270
2066499290cyclictest0-21swapper/1119:25:563
20630992910cyclictest991850irq/53-eth0-rx-22:21:570
20659992418cyclictest20976-21qemu-kvm22:20:008
20662992119cyclictest18910-21latency_hist21:15:0111
20662992019cyclictest7304-21latency_hist00:35:0111
2066399192cyclictest831ksoftirqd/1022:45:122
2066399192cyclictest831ksoftirqd/1022:45:112
2066399192cyclictest831ksoftirqd/1022:41:102
2066399192cyclictest831ksoftirqd/1021:48:372
2066399192cyclictest831ksoftirqd/1021:10:592
2066399192cyclictest153122sleep1020:26:192
2066299192cyclictest0-21swapper/922:26:5311
2066299192cyclictest0-21swapper/922:26:5211
2066299192cyclictest0-21swapper/921:59:4511
991850180irq/53-eth0-rx-0-21swapper/822:13:1610
991850180irq/53-eth0-rx-0-21swapper/822:13:1510
2066399181cyclictest991950irq/54-eth0-tx-21:23:292
2066399181cyclictest991850irq/53-eth0-rx-23:55:522
2066399181cyclictest991850irq/53-eth0-rx-22:29:142
2066399181cyclictest991850irq/53-eth0-rx-22:29:142
2066399181cyclictest991850irq/53-eth0-rx-00:25:112
2066399181cyclictest991850irq/53-eth0-rx-00:07:142
2066399181cyclictest831ksoftirqd/1023:28:382
2066399181cyclictest831ksoftirqd/1023:15:082
2066399181cyclictest831ksoftirqd/1022:12:012
2066399181cyclictest831ksoftirqd/1022:12:002
2066399181cyclictest831ksoftirqd/1021:41:362
2066399181cyclictest831ksoftirqd/1021:35:142
2066399181cyclictest831ksoftirqd/1021:31:132
2066399181cyclictest831ksoftirqd/1019:35:182
2066399181cyclictest831ksoftirqd/1019:25:122
2066399181cyclictest831ksoftirqd/1000:38:372
2066399181cyclictest831ksoftirqd/1000:20:202
2066399181cyclictest811rcuc/1000:10:122
2066299181cyclictest761ksoftirqd/922:51:0911
2066299181cyclictest761ksoftirqd/921:50:1111
2066299181cyclictest0-21swapper/923:59:4911
2066299181cyclictest0-21swapper/922:10:4811
2066299181cyclictest0-21swapper/922:10:4711
2066299181cyclictest0-21swapper/922:05:1311
2066299181cyclictest0-21swapper/921:30:1111
2066299181cyclictest0-21swapper/921:29:4311
2066299181cyclictest0-21swapper/921:22:5911
2066299181cyclictest0-21swapper/921:00:2511
2066299181cyclictest0-21swapper/919:15:2511
2066299181cyclictest0-21swapper/900:11:1311
2066299181cyclictest0-21swapper/900:05:4211
20630991814cyclictest991850irq/53-eth0-rx-22:28:560
20630991814cyclictest991850irq/53-eth0-rx-22:28:550
2066399170cyclictest991850irq/53-eth0-rx-23:45:342
2066399170cyclictest991850irq/53-eth0-rx-23:36:432
2066399170cyclictest991850irq/53-eth0-rx-23:20:072
2066399170cyclictest991850irq/53-eth0-rx-23:10:312
2066399170cyclictest991850irq/53-eth0-rx-23:05:092
2066399170cyclictest991850irq/53-eth0-rx-23:00:102
2066399170cyclictest991850irq/53-eth0-rx-23:00:092
2066399170cyclictest991850irq/53-eth0-rx-22:56:112
2066399170cyclictest991850irq/53-eth0-rx-22:50:442
2066399170cyclictest991850irq/53-eth0-rx-22:31:502
2066399170cyclictest991850irq/53-eth0-rx-19:56:502
2066399170cyclictest991850irq/53-eth0-rx-19:30:562
2066399170cyclictest991850irq/53-eth0-rx-00:02:232
2066399170cyclictest86252chrt21:02:332
2066399170cyclictest831ksoftirqd/1023:50:502
2066399170cyclictest831ksoftirqd/1023:40:192
2066399170cyclictest831ksoftirqd/1023:30:122
2066399170cyclictest831ksoftirqd/1022:35:202
2066399170cyclictest831ksoftirqd/1022:20:142
2066399170cyclictest831ksoftirqd/1022:06:112
2066399170cyclictest831ksoftirqd/1022:00:142
2066399170cyclictest831ksoftirqd/1021:55:122
2066399170cyclictest831ksoftirqd/1021:25:002
2066399170cyclictest831ksoftirqd/1021:15:262
2066399170cyclictest831ksoftirqd/1020:45:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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