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2026-04-04 - 18:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sat Apr 04, 2026 12:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501120irq/53-eth0-rx-0-21swapper/107:09:081
128501110irq/42-ahci0-21swapper/707:09:099
12074210893sleep20-21swapper/207:07:074
12138210492sleep60-21swapper/607:07:598
9918501020irq/53-eth0-rx-0-21swapper/307:09:535
12850920irq/42-ahci0-21swapper/407:08:386
1208329281sleep80-21swapper/807:07:1410
1231528884sleep100-21swapper/1007:09:402
1199727769sleep50-21swapper/507:06:107
1203927666sleep00-21swapper/007:06:420
991850740irq/53-eth0-rx-0-21swapper/1107:07:413
1214526253sleep90-21swapper/907:08:0211
1245399390cyclictest0-21swapper/010:18:380
1248999310cyclictest0-21swapper/1110:16:423
12482993029cyclictest991950irq/54-eth0-tx-10:18:406
12465993029cyclictest991950irq/54-eth0-tx-10:18:331
12474992928cyclictest991850irq/53-eth0-rx-10:18:334
12488992827cyclictest25164-21ssh10:18:342
12485992624cyclictest991950irq/54-eth0-tx-10:18:339
12479992625cyclictest991850irq/53-eth0-rx-10:18:375
12488992516cyclictest0-21swapper/1011:54:582
12488992416cyclictest0-21swapper/1012:36:112
12488992416cyclictest0-21swapper/1011:40:512
12488992416cyclictest0-21swapper/1008:55:472
12488992415cyclictest0-21swapper/1012:27:182
1248899240cyclictest269912chrt11:11:202
1248899240cyclictest269912chrt11:11:192
12487992423cyclictest991850irq/53-eth0-rx-10:18:3811
12488992317cyclictest0-21swapper/1011:30:302
12488992317cyclictest0-21swapper/1010:32:042
12488992316cyclictest31788-1kworker/10:1H10:46:262
12488992316cyclictest31788-1kworker/10:1H10:46:252
12488992316cyclictest31788-1kworker/10:1H08:47:332
12488992316cyclictest0-21swapper/1011:02:262
12488992316cyclictest0-21swapper/1009:36:162
12488992316cyclictest0-21swapper/1009:29:362
12488992316cyclictest0-21swapper/1009:16:372
12488992315cyclictest0-21swapper/1011:55:242
12488992315cyclictest0-21swapper/1010:06:232
12488992315cyclictest0-21swapper/1009:53:502
12488992216cyclictest0-21swapper/1010:20:382
12488992215cyclictest0-21swapper/1011:45:402
12488992116cyclictest0-21swapper/1012:13:112
12488992116cyclictest0-21swapper/1011:16:552
12488992115cyclictest31788-1kworker/10:1H09:47:262
12488992115cyclictest31788-1kworker/10:1H09:08:532
12488992115cyclictest0-21swapper/1012:03:332
12453992018cyclictest0-21swapper/010:08:260
1245399200cyclictest3214-21latency_hist07:40:020
1248899192cyclictest991850irq/53-eth0-rx-11:06:372
1248899192cyclictest991850irq/53-eth0-rx-11:06:362
1248899192cyclictest991850irq/53-eth0-rx-10:59:452
1248899192cyclictest991850irq/53-eth0-rx-10:59:442
12487991917cyclictest2042-21sh10:51:0011
1247999192cyclictest0-21swapper/307:43:105
12453991917cyclictest4373-21chrt10:27:150
1248999180cyclictest0-21swapper/1109:08:173
12488991817cyclictest0-21swapper/1011:28:332
12488991817cyclictest0-21swapper/1009:57:442
12488991817cyclictest0-21swapper/1008:01:232
12488991817cyclictest0-21swapper/1007:31:012
12488991816cyclictest30918-21ssh12:08:022
1248899181cyclictest991850irq/53-eth0-rx-10:43:322
1248899181cyclictest991850irq/53-eth0-rx-10:00:062
1248899181cyclictest991850irq/53-eth0-rx-09:43:082
1248899181cyclictest991850irq/53-eth0-rx-09:21:482
1248899181cyclictest991850irq/53-eth0-rx-09:10:352
12487991817cyclictest4645-21latency_hist09:10:0111
12487991817cyclictest30769-21idleruntime08:15:1511
12487991810cyclictest0-21swapper/911:43:2611
1248799181cyclictest3412-21if_err_tap011:45:1411
1248799181cyclictest0-21swapper/912:26:1711
1248799181cyclictest0-21swapper/912:23:1711
1248799181cyclictest0-21swapper/912:18:2211
1248799181cyclictest0-21swapper/911:53:3811
1248799181cyclictest0-21swapper/911:36:3111
1248799181cyclictest0-21swapper/911:31:4211
1248799181cyclictest0-21swapper/911:27:0611
1248799181cyclictest0-21swapper/911:19:0511
1248799181cyclictest0-21swapper/911:00:0211
1248799181cyclictest0-21swapper/910:57:5411
1248799181cyclictest0-21swapper/910:57:5311
1248799181cyclictest0-21swapper/910:26:3911
1248799181cyclictest0-21swapper/909:50:2211
1248799181cyclictest0-21swapper/909:41:1411
1248799181cyclictest0-21swapper/909:30:2911
1248799181cyclictest0-21swapper/907:11:3211
1248799180cyclictest0-21swapper/912:00:2411
1248599180cyclictest0-21swapper/711:49:569
1247999182cyclictest0-21swapper/310:39:365
1247999182cyclictest0-21swapper/309:21:035
1247999182cyclictest0-21swapper/309:06:315
1247999182cyclictest0-21swapper/308:58:355
1247999182cyclictest0-21swapper/308:50:365
1247999182cyclictest0-21swapper/308:48:385
1247999182cyclictest0-21swapper/308:38:485
1247999182cyclictest0-21swapper/308:30:515
1247999182cyclictest0-21swapper/308:27:225
1247999182cyclictest0-21swapper/308:19:045
1247999182cyclictest0-21swapper/308:07:175
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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