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2026-03-24 - 00:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Mar 23, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501110irq/53-eth0-rx-0-21swapper/707:09:189
9210210894sleep90-21swapper/907:08:0311
9176210290sleep50-21swapper/507:07:347
12850990irq/42-ahci0-21swapper/107:09:091
782729485sleep20-21swapper/207:05:184
991850920irq/53-eth0-rx-0-21swapper/1007:08:092
991850910irq/53-eth0-rx-0-21swapper/807:06:2710
991850910irq/53-eth0-rx-0-21swapper/307:05:305
12850850irq/42-ahci0-21swapper/407:05:256
905328173sleep110-21swapper/1107:06:043
907226453sleep00-21swapper/007:06:170
908025853sleep60-21swapper/607:06:238
960099320cyclictest0-21swapper/1108:28:453
959599192cyclictest991850irq/53-eth0-rx-09:30:402
958799192cyclictest0-21swapper/910:30:5511
958799192cyclictest0-21swapper/910:21:3811
958799192cyclictest0-21swapper/909:35:1711
958199193cyclictest0-21swapper/807:30:1710
9595991817cyclictest0-21swapper/1012:00:222
9595991817cyclictest0-21swapper/1011:08:592
9595991817cyclictest0-21swapper/1007:50:162
9595991817cyclictest0-21swapper/1007:50:162
959599181cyclictest991950irq/54-eth0-tx-12:29:562
959599181cyclictest991950irq/54-eth0-tx-11:56:122
959599181cyclictest991950irq/54-eth0-tx-10:30:162
959599181cyclictest991950irq/54-eth0-tx-09:15:362
959599181cyclictest991850irq/53-eth0-rx-11:52:172
959599181cyclictest991850irq/53-eth0-rx-10:47:202
959599181cyclictest991850irq/53-eth0-rx-10:23:162
959599181cyclictest991850irq/53-eth0-rx-10:15:272
959599181cyclictest991850irq/53-eth0-rx-10:10:242
959599181cyclictest991850irq/53-eth0-rx-09:46:422
959599181cyclictest991850irq/53-eth0-rx-09:42:092
959599181cyclictest991850irq/53-eth0-rx-09:36:042
959599181cyclictest991850irq/53-eth0-rx-09:26:422
959599181cyclictest991850irq/53-eth0-rx-08:10:252
959599181cyclictest12850irq/42-ahci10:55:172
958799181cyclictest0-21swapper/912:37:2711
958799181cyclictest0-21swapper/910:18:0511
958799181cyclictest0-21swapper/909:50:2011
958799181cyclictest0-21swapper/909:20:1811
958799181cyclictest0-21swapper/907:50:1211
958799181cyclictest0-21swapper/907:50:1211
958799181cyclictest0-21swapper/907:47:3811
958799181cyclictest0-21swapper/907:47:3811
9567991816cyclictest9271-21qemu-kvm07:20:118
9567991816cyclictest9270-21qemu-kvm07:46:068
9567991816cyclictest9270-21qemu-kvm07:46:068
9546991817cyclictest991850irq/53-eth0-rx-10:12:460
9600991716cyclictest991850irq/53-eth0-rx-10:28:013
9595991716cyclictest26011-21unixbench-2d12:05:242
9595991715cyclictest32359-21perl10:00:142
959599170cyclictest991850irq/53-eth0-rx-12:35:082
959599170cyclictest991850irq/53-eth0-rx-12:21:332
959599170cyclictest991850irq/53-eth0-rx-12:16:142
959599170cyclictest991850irq/53-eth0-rx-12:11:242
959599170cyclictest991850irq/53-eth0-rx-11:45:112
959599170cyclictest991850irq/53-eth0-rx-11:40:092
959599170cyclictest991850irq/53-eth0-rx-11:35:052
959599170cyclictest991850irq/53-eth0-rx-11:30:222
959599170cyclictest991850irq/53-eth0-rx-11:25:282
959599170cyclictest991850irq/53-eth0-rx-11:12:222
959599170cyclictest991850irq/53-eth0-rx-11:12:222
959599170cyclictest991850irq/53-eth0-rx-10:40:052
959599170cyclictest991850irq/53-eth0-rx-10:35:022
959599170cyclictest991850irq/53-eth0-rx-10:35:022
959599170cyclictest991850irq/53-eth0-rx-10:05:052
959599170cyclictest991850irq/53-eth0-rx-10:05:052
959599170cyclictest991850irq/53-eth0-rx-09:55:052
959599170cyclictest991850irq/53-eth0-rx-08:25:212
959599170cyclictest991850irq/53-eth0-rx-08:00:282
959599170cyclictest991850irq/53-eth0-rx-07:40:472
959599170cyclictest991850irq/53-eth0-rx-07:35:162
959599170cyclictest991850irq/53-eth0-rx-07:25:492
959599170cyclictest991850irq/53-eth0-rx-07:20:192
959599170cyclictest991850irq/53-eth0-rx-07:10:372
959599170cyclictest9752sleep1009:06:392
959599170cyclictest74392sleep1007:48:072
959599170cyclictest74392sleep1007:48:062
959599170cyclictest51612sleep1009:10:532
959599170cyclictest322842chrt08:20:232
959599170cyclictest304392chrt11:17:072
959599170cyclictest296912sleep1009:00:392
959599170cyclictest295992sleep1010:25:012
959599170cyclictest293552sleep1008:17:232
959599170cyclictest288192sleep1007:32:292
959599170cyclictest280762sleep1010:50:032
959599170cyclictest254802sleep1008:55:282
959599170cyclictest23512sleep1011:20:202
959599170cyclictest224662chrt09:51:332
959599170cyclictest224042sleep1008:50:392
959599170cyclictest215952sleep1012:30:052
959599170cyclictest190912sleep1008:05:092
959599170cyclictest176382sleep1009:21:062
959599170cyclictest171632sleep1007:15:272
959599170cyclictest145612sleep1007:55:442
959599170cyclictest145612sleep1007:55:442
959599170cyclictest12850irq/42-ahci08:30:472
959599170cyclictest117132sleep1008:39:002
959599170cyclictest112772sleep1011:00:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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