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2026-02-17 - 08:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Feb 17, 2026 00:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8394210894sleep30-21swapper/319:07:375
8345210893sleep20-21swapper/219:06:594
8261210791sleep00-21swapper/019:05:570
8397210693sleep60-21swapper/619:07:398
9918501030irq/53-eth0-rx-0-21swapper/819:08:1910
991850960irq/53-eth0-rx-0-21swapper/119:05:581
991850950irq/53-eth0-rx-0-21swapper/719:09:439
991850950irq/53-eth0-rx-0-21swapper/519:05:037
991850910irq/53-eth0-rx-0-21swapper/419:07:246
12850800irq/42-ahci0-21swapper/919:08:4711
991850770irq/53-eth0-rx-0-21swapper/1119:05:243
860427573sleep100-21swapper/1019:09:432
8770993314cyclictest0-21swapper/1121:22:413
877099330cyclictest0-21swapper/1122:09:233
877099330cyclictest0-21swapper/1122:09:223
877099320cyclictest0-21swapper/1120:30:203
8770992928cyclictest18790-1kworker/11:0H20:15:133
8715992814cyclictest0-21swapper/022:11:480
871599220cyclictest0-21swapper/022:22:000
871599220cyclictest0-21swapper/021:25:300
8715992012cyclictest122252sleep019:13:210
871599200cyclictest0-21swapper/023:55:220
876999192cyclictest991850irq/53-eth0-rx-23:20:012
876999192cyclictest991850irq/53-eth0-rx-20:38:132
8769991917cyclictest3397-21perl00:20:162
876899192cyclictest0-21swapper/922:35:0611
876899192cyclictest0-21swapper/921:22:2211
876899192cyclictest0-21swapper/900:30:4211
876899192cyclictest0-21swapper/900:01:1211
8754991910cyclictest22458-21ssh22:48:355
871599190cyclictest0-21swapper/023:30:210
871599190cyclictest0-21swapper/020:25:230
8769991817cyclictest811rcuc/1023:39:382
8769991817cyclictest7739-21ssh23:03:022
8769991817cyclictest0-21swapper/1021:16:102
876999181cyclictest991950irq/54-eth0-tx-23:27:452
876999181cyclictest991950irq/54-eth0-tx-21:50:272
876999181cyclictest991850irq/53-eth0-rx-23:43:372
876999181cyclictest991850irq/53-eth0-rx-23:32:042
876999181cyclictest991850irq/53-eth0-rx-23:06:042
876999181cyclictest991850irq/53-eth0-rx-22:40:252
876999181cyclictest991850irq/53-eth0-rx-22:40:242
876999181cyclictest991850irq/53-eth0-rx-22:30:182
876999181cyclictest991850irq/53-eth0-rx-22:21:212
876999181cyclictest115050irq/18-i801_smb22:50:152
876999181cyclictest115050irq/18-i801_smb22:50:152
876899181cyclictest991950irq/54-eth0-tx-23:54:1911
876899181cyclictest991950irq/54-eth0-tx-23:25:1511
876899181cyclictest991850irq/53-eth0-rx-23:10:3411
876899181cyclictest3545-21sh21:38:3111
876899181cyclictest10692-1kworker/9:1H21:09:2411
876899181cyclictest0-21swapper/923:55:3811
876899181cyclictest0-21swapper/923:45:1811
876899181cyclictest0-21swapper/923:36:5111
876899181cyclictest0-21swapper/922:55:4611
876899181cyclictest0-21swapper/922:17:3311
876899181cyclictest0-21swapper/922:17:3311
876899181cyclictest0-21swapper/922:14:3111
876899181cyclictest0-21swapper/922:05:4111
876899181cyclictest0-21swapper/922:05:4111
876899181cyclictest0-21swapper/922:01:2911
876899181cyclictest0-21swapper/921:55:2111
876899181cyclictest0-21swapper/921:52:5711
876899181cyclictest0-21swapper/919:48:3011
876899181cyclictest0-21swapper/919:35:2711
876899181cyclictest0-21swapper/900:37:0911
876899181cyclictest0-21swapper/900:19:3111
876899181cyclictest0-21swapper/900:11:1311
876899181cyclictest0-21swapper/900:07:5111
871599180cyclictest0-21swapper/022:45:140
871599180cyclictest0-21swapper/000:35:220
8769991716cyclictest0-21swapper/1022:47:212
8769991716cyclictest0-21swapper/1022:26:172
8769991716cyclictest0-21swapper/1022:26:172
8769991715cyclictest8282-21snmp_rack3slot923:56:502
876999170cyclictest991850irq/53-eth0-rx-22:55:192
876999170cyclictest991850irq/53-eth0-rx-22:11:062
876999170cyclictest991850irq/53-eth0-rx-22:01:122
876999170cyclictest991850irq/53-eth0-rx-21:45:062
876999170cyclictest991850irq/53-eth0-rx-21:25:342
876999170cyclictest991850irq/53-eth0-rx-21:10:102
876999170cyclictest991850irq/53-eth0-rx-20:20:232
876999170cyclictest991850irq/53-eth0-rx-20:16:232
876999170cyclictest991850irq/53-eth0-rx-19:45:142
876999170cyclictest991850irq/53-eth0-rx-00:35:112
876999170cyclictest991850irq/53-eth0-rx-00:16:452
876999170cyclictest991850irq/53-eth0-rx-00:12:112
876999170cyclictest991850irq/53-eth0-rx-00:00:062
876999170cyclictest94882sleep1022:36:432
876999170cyclictest88192sleep1021:42:122
876999170cyclictest72772chrt22:08:512
876999170cyclictest72772chrt22:08:512
876999170cyclictest69972sleep1020:30:272
876999170cyclictest4652sleep1020:25:042
876999170cyclictest315842sleep1019:36:102
876999170cyclictest297942chrt21:05:072
876999170cyclictest287572sleep1021:31:222
876999170cyclictest286732sleep1023:46:502
876999170cyclictest281122sleep1021:00:212
876999170cyclictest279242sleep1019:30:572
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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