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2026-02-27 - 21:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Feb 27, 2026 12:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27928211195sleep30-21swapper/307:07:475
128501090irq/42-ahci0-21swapper/207:08:584
27816210692sleep10-21swapper/107:06:211
27819210593sleep40-21swapper/407:06:246
9918501010irq/53-eth0-rx-0-21swapper/1007:06:262
991850940irq/53-eth0-rx-0-21swapper/707:06:019
991850930irq/53-eth0-rx-0-21swapper/507:07:157
991850870irq/53-eth0-rx-0-21swapper/1107:07:163
2792528275sleep00-21swapper/007:07:440
2793128172sleep60-21swapper/607:07:508
991850800irq/53-eth0-rx-0-21swapper/807:05:2510
991850660irq/53-eth0-rx-0-21swapper/907:06:2411
2825799320cyclictest0-21swapper/010:22:060
2825799320cyclictest0-21swapper/009:22:380
991950280irq/54-eth0-tx-0-21swapper/209:22:444
991950280irq/54-eth0-tx-0-21swapper/1009:22:392
991850280irq/53-eth0-rx-0-21swapper/709:22:519
991850280irq/53-eth0-rx-0-21swapper/109:22:391
12850280irq/42-ahci0-21swapper/409:22:506
2825799227cyclictest0-21swapper/010:28:160
2829199192cyclictest991850irq/53-eth0-rx-12:37:222
2829199192cyclictest991850irq/53-eth0-rx-12:32:052
2829199192cyclictest991850irq/53-eth0-rx-12:14:372
2829199192cyclictest991850irq/53-eth0-rx-11:47:532
2829199192cyclictest991850irq/53-eth0-rx-11:31:412
2829199192cyclictest991850irq/53-eth0-rx-11:28:432
2829199192cyclictest991850irq/53-eth0-rx-10:38:572
2829199192cyclictest991850irq/53-eth0-rx-10:29:592
2829199192cyclictest991850irq/53-eth0-rx-09:55:392
2829199192cyclictest991850irq/53-eth0-rx-09:46:062
2829199192cyclictest991850irq/53-eth0-rx-09:12:012
2829099192cyclictest0-21swapper/912:33:4611
2829099192cyclictest0-21swapper/912:26:3611
2829099192cyclictest0-21swapper/910:31:3011
2829099192cyclictest0-21swapper/909:20:4611
28289991917cyclictest4510-21awk11:35:0210
28257991917cyclictest42072chrt07:16:440
2825799190cyclictest0-21swapper/012:21:050
991850180irq/53-eth0-rx-0-21swapper/1110:24:093
28291991817cyclictest28462-1kworker/10:2H08:39:372
28291991817cyclictest0-21swapper/1012:15:112
28291991817cyclictest0-21swapper/1012:05:162
28291991817cyclictest0-21swapper/1011:42:352
28291991817cyclictest0-21swapper/1010:55:302
28291991817cyclictest0-21swapper/1010:55:292
28291991817cyclictest0-21swapper/1010:15:022
28291991817cyclictest0-21swapper/1010:04:352
28291991817cyclictest0-21swapper/1008:16:302
2829199181cyclictest991850irq/53-eth0-rx-12:29:232
2829199181cyclictest991850irq/53-eth0-rx-12:21:212
2829199181cyclictest991850irq/53-eth0-rx-11:00:222
2829199181cyclictest991850irq/53-eth0-rx-10:50:332
2829199181cyclictest991850irq/53-eth0-rx-10:42:282
2829199181cyclictest991850irq/53-eth0-rx-10:30:442
2829199181cyclictest991850irq/53-eth0-rx-10:23:142
2829199181cyclictest991850irq/53-eth0-rx-10:10:562
2829199181cyclictest991850irq/53-eth0-rx-09:52:302
2829199181cyclictest991850irq/53-eth0-rx-09:44:062
2829199181cyclictest991850irq/53-eth0-rx-09:32:162
2829199181cyclictest991850irq/53-eth0-rx-09:28:442
2829199181cyclictest991850irq/53-eth0-rx-09:15:262
2829199181cyclictest991850irq/53-eth0-rx-08:10:162
2829199181cyclictest991850irq/53-eth0-rx-07:16:522
2829199181cyclictest12850irq/42-ahci10:08:302
2829199181cyclictest12850irq/42-ahci09:35:162
2829199181cyclictest12850irq/42-ahci08:46:372
2829199181cyclictest12850irq/42-ahci07:23:242
28290991816cyclictest1151-21chrt07:59:4711
2829099181cyclictest0-21swapper/912:15:3211
2829099181cyclictest0-21swapper/911:55:3411
2829099181cyclictest0-21swapper/911:26:4511
2829099181cyclictest0-21swapper/910:40:3811
2829099181cyclictest0-21swapper/909:40:1911
2829099181cyclictest0-21swapper/909:16:1611
2828799186cyclictest0-21swapper/608:45:018
2828799186cyclictest0-21swapper/608:45:018
28257991816cyclictest25101-21chrt09:12:570
2825799180cyclictest0-21swapper/009:25:210
28292991715cyclictest28182sleep1109:20:213
28291991716cyclictest28462-1kworker/10:2H07:10:162
28291991716cyclictest0-21swapper/1011:15:132
28291991716cyclictest0-21swapper/1011:15:122
28291991716cyclictest0-21swapper/1008:05:112
2829199170cyclictest991850irq/53-eth0-rx-11:55:152
2829199170cyclictest991850irq/53-eth0-rx-11:21:232
2829199170cyclictest991850irq/53-eth0-rx-11:21:222
2829199170cyclictest991850irq/53-eth0-rx-11:10:372
2829199170cyclictest991850irq/53-eth0-rx-11:05:052
2829199170cyclictest991850irq/53-eth0-rx-10:45:012
2829199170cyclictest991850irq/53-eth0-rx-09:00:072
2829199170cyclictest991850irq/53-eth0-rx-08:57:072
2829199170cyclictest991850irq/53-eth0-rx-08:24:402
2829199170cyclictest991850irq/53-eth0-rx-08:00:162
2829199170cyclictest991850irq/53-eth0-rx-07:45:062
2829199170cyclictest991850irq/53-eth0-rx-07:40:172
2829199170cyclictest991850irq/53-eth0-rx-07:30:302
2829199170cyclictest87992sleep1008:50:532
2829199170cyclictest87992sleep1008:50:532
2829199170cyclictest74242chrt11:35:242
2829199170cyclictest33922sleep1012:00:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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