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2026-05-25 - 14:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon May 25, 2026 12:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501070irq/42-ahci0-21swapper/207:08:514
122501070irq/42-ahci0-21swapper/207:08:514
2857210192sleep80-21swapper/807:07:0010
2857210192sleep80-21swapper/807:07:0010
3054950990irq/53-eth0-rx-0-21swapper/107:09:391
3054950990irq/53-eth0-rx-0-21swapper/107:09:391
3054950950irq/53-eth0-rx-0-21swapper/707:09:479
3054950950irq/53-eth0-rx-0-21swapper/707:09:479
3054950950irq/53-eth0-rx-0-21swapper/307:08:465
3054950950irq/53-eth0-rx-0-21swapper/307:08:455
3054950950irq/53-eth0-rx-0-21swapper/1007:05:302
3054950950irq/53-eth0-rx-0-21swapper/1007:05:292
3054950860irq/53-eth0-rx-0-21swapper/1107:05:203
3054950860irq/53-eth0-rx-0-21swapper/1107:05:203
12250770irq/42-ahci0-21swapper/507:05:177
12250770irq/42-ahci0-21swapper/507:05:177
313927674sleep90-21swapper/907:09:4911
313927674sleep90-21swapper/907:09:4911
3054950730irq/53-eth0-rx-0-21swapper/407:05:226
3054950730irq/53-eth0-rx-0-21swapper/407:05:226
122727161sleep00-21swapper/007:05:150
122727161sleep00-21swapper/007:05:150
277425955sleep60-21swapper/607:05:588
277425955sleep60-21swapper/607:05:588
329099280cyclictest0-21swapper/312:27:015
326599248cyclictest20369-21kworker/0:110:22:410
326599220cyclictest0-21swapper/009:13:080
3265992019cyclictest0-21swapper/008:09:550
329999192cyclictest3054950irq/53-eth0-rx-09:51:152
329899192cyclictest0-21swapper/912:32:2111
329899192cyclictest0-21swapper/910:24:0811
3299991817cyclictest811rcuc/1011:32:202
3299991817cyclictest0-21swapper/1012:20:532
329999181cyclictest3055050irq/54-eth0-tx-12:04:102
329999181cyclictest3055050irq/54-eth0-tx-09:57:262
329999181cyclictest3055050irq/54-eth0-tx-09:45:592
329999181cyclictest3054950irq/53-eth0-rx-12:34:212
329999181cyclictest3054950irq/53-eth0-rx-11:55:022
329999181cyclictest3054950irq/53-eth0-rx-11:17:292
329999181cyclictest3054950irq/53-eth0-rx-11:13:352
329999181cyclictest3054950irq/53-eth0-rx-11:13:352
329999181cyclictest3054950irq/53-eth0-rx-10:42:112
329999181cyclictest3054950irq/53-eth0-rx-10:01:172
329999181cyclictest3054950irq/53-eth0-rx-09:35:432
329899184cyclictest0-21swapper/912:10:0711
329899181cyclictest3054950irq/53-eth0-rx-11:31:0111
329899181cyclictest0-21swapper/912:29:5411
329899181cyclictest0-21swapper/912:22:4711
329899181cyclictest0-21swapper/912:15:3811
329899181cyclictest0-21swapper/912:08:5311
329899181cyclictest0-21swapper/910:10:3511
329899181cyclictest0-21swapper/909:24:4911
3295991816cyclictest27377-21qemu-kvm09:25:128
3294991816cyclictest2994-21qemu-kvm07:32:367
330099170cyclictest0-21swapper/1107:47:203
3299991716cyclictest0-21swapper/1010:05:432
329999170cyclictest90732sleep1008:43:112
329999170cyclictest84452sleep1010:35:252
329999170cyclictest82342chrt11:00:282
329999170cyclictest75952sleep1007:15:012
329999170cyclictest68272chrt11:50:462
329999170cyclictest53132sleep1008:36:352
329999170cyclictest47052sleep1007:51:072
329999170cyclictest32822chrt10:31:242
329999170cyclictest321582sleep1007:45:172
329999170cyclictest315182sleep1012:36:152
329999170cyclictest3055050irq/54-eth0-tx-10:15:292
329999170cyclictest3054950irq/53-eth0-rx-12:12:032
329999170cyclictest3054950irq/53-eth0-rx-11:35:032
329999170cyclictest3054950irq/53-eth0-rx-11:27:492
329999170cyclictest3054950irq/53-eth0-rx-11:20:302
329999170cyclictest3054950irq/53-eth0-rx-11:06:282
329999170cyclictest3054950irq/53-eth0-rx-10:10:242
329999170cyclictest3054950irq/53-eth0-rx-09:41:122
329999170cyclictest3054950irq/53-eth0-rx-09:31:062
329999170cyclictest3054950irq/53-eth0-rx-09:26:492
329999170cyclictest3054950irq/53-eth0-rx-09:20:502
329999170cyclictest3054950irq/53-eth0-rx-09:18:182
329999170cyclictest3054950irq/53-eth0-rx-09:10:572
329999170cyclictest3054950irq/53-eth0-rx-08:55:412
329999170cyclictest3054950irq/53-eth0-rx-08:15:402
329999170cyclictest302892chrt08:25:462
329999170cyclictest298412sleep1007:42:282
329999170cyclictest296812sleep1010:27:002
329999170cyclictest28042sleep1012:15:012
329999170cyclictest278772sleep1010:50:272
329999170cyclictest271472sleep1009:05:502
329999170cyclictest266832sleep1008:21:212
329999170cyclictest260822sleep1007:35:522
329999170cyclictest258942sleep1012:06:012
329999170cyclictest228942sleep1010:21:112
329999170cyclictest224272chrt07:30:402
329999170cyclictest222382sleep1010:46:262
329999170cyclictest22112chrt10:56:032
329999170cyclictest206682sleep1009:00:022
329999170cyclictest194512sleep1008:12:082
329999170cyclictest194512sleep1008:12:082
329999170cyclictest188492sleep1007:26:392
329999170cyclictest16182sleep1008:32:222
329999170cyclictest157792sleep1008:07:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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