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2026-05-22 - 14:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri May 22, 2026 12:46:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501130irq/42-ahci0-21swapper/207:08:414
5600211095sleep80-21swapper/807:06:4110
5616210895sleep90-21swapper/907:06:5411
2713210891sleep00-21swapper/007:05:100
30549501050irq/53-eth0-rx-0-21swapper/107:09:061
3054950930irq/53-eth0-rx-0-21swapper/407:07:086
3054950900irq/53-eth0-rx-0-21swapper/707:06:209
3054950900irq/53-eth0-rx-0-21swapper/307:07:355
3054950880irq/53-eth0-rx-0-21swapper/507:07:397
3054950880irq/53-eth0-rx-0-21swapper/1107:06:323
564528069sleep60-21swapper/607:07:158
552227365sleep100-21swapper/1007:05:432
6047993332cyclictest0-21swapper/1108:26:403
604799227cyclictest0-21swapper/1107:20:363
6005992019cyclictest0-21swapper/007:10:370
6005992019cyclictest0-21swapper/007:10:370
604699192cyclictest3054950irq/53-eth0-rx-12:16:232
604699192cyclictest3054950irq/53-eth0-rx-12:00:362
604699192cyclictest3054950irq/53-eth0-rx-11:30:392
604699192cyclictest3054950irq/53-eth0-rx-11:20:412
604699192cyclictest3054950irq/53-eth0-rx-10:59:492
604699192cyclictest3054950irq/53-eth0-rx-10:43:202
604699192cyclictest3054950irq/53-eth0-rx-10:28:502
604699192cyclictest3054950irq/53-eth0-rx-10:22:342
604699192cyclictest3054950irq/53-eth0-rx-10:15:442
604699192cyclictest3054950irq/53-eth0-rx-10:11:272
604699192cyclictest3054950irq/53-eth0-rx-09:47:042
604699192cyclictest3054950irq/53-eth0-rx-09:44:012
604699192cyclictest3054950irq/53-eth0-rx-09:16:212
6044991917cyclictest0-21swapper/811:34:5510
6046991817cyclictest0-21swapper/1011:55:242
6046991817cyclictest0-21swapper/1011:18:482
6046991817cyclictest0-21swapper/1008:07:262
604699181cyclictest3054950irq/53-eth0-rx-12:33:242
604699181cyclictest3054950irq/53-eth0-rx-12:33:232
604699181cyclictest3054950irq/53-eth0-rx-12:25:172
604699181cyclictest3054950irq/53-eth0-rx-12:21:312
604699181cyclictest3054950irq/53-eth0-rx-12:13:472
604699181cyclictest3054950irq/53-eth0-rx-12:07:362
604699181cyclictest3054950irq/53-eth0-rx-11:52:032
604699181cyclictest3054950irq/53-eth0-rx-11:45:082
604699181cyclictest3054950irq/53-eth0-rx-11:43:432
604699181cyclictest3054950irq/53-eth0-rx-11:36:502
604699181cyclictest3054950irq/53-eth0-rx-11:25:392
604699181cyclictest3054950irq/53-eth0-rx-11:14:252
604699181cyclictest3054950irq/53-eth0-rx-10:54:252
604699181cyclictest3054950irq/53-eth0-rx-10:36:222
604699181cyclictest3054950irq/53-eth0-rx-10:33:352
604699181cyclictest3054950irq/53-eth0-rx-10:07:242
604699181cyclictest3054950irq/53-eth0-rx-10:01:142
604699181cyclictest3054950irq/53-eth0-rx-09:50:312
604699181cyclictest3054950irq/53-eth0-rx-09:39:322
604699181cyclictest3054950irq/53-eth0-rx-09:26:442
604699181cyclictest3054950irq/53-eth0-rx-09:24:232
604699181cyclictest3054950irq/53-eth0-rx-09:24:222
604699181cyclictest3054950irq/53-eth0-rx-09:10:332
604699181cyclictest12250irq/42-ahci11:05:122
604699181cyclictest12250irq/42-ahci09:08:562
6045991816cyclictest20331-21ssh12:23:5911
6045991816cyclictest19121-21ssh11:30:4011
604599181cyclictest8717-21ssh09:16:4811
604599181cyclictest761ksoftirqd/912:25:4111
604599181cyclictest761ksoftirqd/911:25:1711
604599181cyclictest761ksoftirqd/909:40:2611
604599181cyclictest761ksoftirqd/908:35:1211
604599181cyclictest761ksoftirqd/907:10:1311
604599181cyclictest761ksoftirqd/907:10:1311
604599181cyclictest741rcuc/911:45:1011
604599181cyclictest31485-21snmp_rack3slot908:25:1511
604599181cyclictest3128-21iostat_ios08:30:1711
604599181cyclictest30629-21cpuspeed09:35:1111
604599181cyclictest14411-21kworker/9:207:25:1211
604599181cyclictest13136-21ssh12:17:3911
604599181cyclictest0-21swapper/912:32:3111
604599181cyclictest0-21swapper/912:32:3011
604599181cyclictest0-21swapper/912:10:0211
604599181cyclictest0-21swapper/912:05:0711
604599181cyclictest0-21swapper/911:22:1611
604599181cyclictest0-21swapper/911:15:1511
604599181cyclictest0-21swapper/911:01:5911
604599181cyclictest0-21swapper/910:50:1511
604599181cyclictest0-21swapper/910:31:5911
604599181cyclictest0-21swapper/909:57:2511
604599181cyclictest0-21swapper/909:51:1611
604599181cyclictest0-21swapper/909:48:5911
604599181cyclictest0-21swapper/909:32:4311
604599181cyclictest0-21swapper/909:05:1311
6037991816cyclictest18614-21qemu-kvm08:47:258
6031991816cyclictest18614-21qemu-kvm08:14:527
602599180cyclictest0-21swapper/407:10:386
602599180cyclictest0-21swapper/407:10:376
601899180cyclictest0-21swapper/307:10:355
601899180cyclictest0-21swapper/307:10:355
6008991816cyclictest6258-21iostat_ios09:40:164
6008991816cyclictest31022-21snmp_rack3slot907:40:154
6008991816cyclictest28742-21ssh09:58:364
6008991816cyclictest25534-21snmp_rack3slot912:01:254
6008991816cyclictest2305-21snmpd12:27:334
6008991816cyclictest20426-21ssh11:32:464
6008991816cyclictest20007-21ssh12:23:264
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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