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2026-08-06 - 03:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Thu Aug 06, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127052111104sleep70-21swapper/719:05:479
12746211097sleep30-21swapper/319:06:195
12855210291sleep50-21swapper/519:07:467
30549501000irq/53-eth0-rx-0-21swapper/119:05:231
122501000irq/42-ahci0-21swapper/419:06:296
3054950960irq/53-eth0-rx-0-21swapper/219:07:334
1286527972sleep110-21swapper/1119:07:523
1267527971sleep00-21swapper/019:05:280
3054950780irq/53-eth0-rx-0-21swapper/819:08:3510
3054950720irq/53-eth0-rx-0-21swapper/919:05:3011
1274026653sleep100-21swapper/1019:06:152
1279925955sleep60-21swapper/619:06:598
1319599320cyclictest0-21swapper/020:26:410
1323799310cyclictest0-21swapper/1121:28:503
1319599290cyclictest0-21swapper/019:17:550
1323799210cyclictest0-21swapper/1122:28:133
1323699192cyclictest3055050irq/54-eth0-tx-23:17:182
1323699192cyclictest3054950irq/53-eth0-rx-22:21:032
1323599192cyclictest0-21swapper/921:50:4511
1323599192cyclictest0-21swapper/921:18:0211
1323599192cyclictest0-21swapper/920:10:1211
1323599192cyclictest0-21swapper/900:39:1011
13236991817cyclictest0-21swapper/1023:05:112
13236991817cyclictest0-21swapper/1022:27:372
13236991817cyclictest0-21swapper/1021:41:502
13236991817cyclictest0-21swapper/1019:20:012
13236991817cyclictest0-21swapper/1019:10:222
1323699181cyclictest8472chrt23:41:102
1323699181cyclictest5932chrt20:17:342
1323699181cyclictest3055050irq/54-eth0-tx-22:44:282
1323699181cyclictest3055050irq/54-eth0-tx-22:36:062
1323699181cyclictest3055050irq/54-eth0-tx-21:32:152
1323699181cyclictest3054950irq/53-eth0-rx-23:30:122
1323699181cyclictest3054950irq/53-eth0-rx-23:13:012
1323699181cyclictest3054950irq/53-eth0-rx-22:07:212
1323699181cyclictest3054950irq/53-eth0-rx-22:07:212
1323699181cyclictest3054950irq/53-eth0-rx-20:31:162
1323699181cyclictest3054950irq/53-eth0-rx-00:11:222
1323699181cyclictest3054950irq/53-eth0-rx-00:05:202
1323699181cyclictest12250irq/42-ahci20:46:342
1323699181cyclictest12250irq/42-ahci20:26:002
1323599181cyclictest741rcuc/921:00:1311
1323599181cyclictest32340-21ssh22:23:0111
1323599181cyclictest3054950irq/53-eth0-rx-23:36:4811
1323599181cyclictest30479-21ssh21:30:0711
1323599181cyclictest18520-21ssh22:37:5011
1323599181cyclictest0-21swapper/923:51:4711
1323599181cyclictest0-21swapper/922:49:3711
1323599181cyclictest0-21swapper/922:15:3511
1323599181cyclictest0-21swapper/921:46:3211
1323599181cyclictest0-21swapper/921:27:3411
1323599181cyclictest0-21swapper/921:12:3511
1323599181cyclictest0-21swapper/900:13:4711
13224991816cyclictest6679-21snmp_rack3slot922:01:377
1319599180cyclictest0-21swapper/020:13:190
13237991716cyclictest1914-21rs:main3
13236991716cyclictest16538-1kworker/10:2H20:20:082
1323699170cyclictest76812sleep1021:36:072
1323699170cyclictest71492sleep1023:46:112
1323699170cyclictest323402chrt19:30:292
1323699170cyclictest320102sleep1021:00:142
1323699170cyclictest313852sleep1000:32:402
1323699170cyclictest308622sleep1021:55:222
1323699170cyclictest3055050irq/54-eth0-tx-23:00:142
1323699170cyclictest3054950irq/53-eth0-rx-23:55:322
1323699170cyclictest3054950irq/53-eth0-rx-23:50:342
1323699170cyclictest3054950irq/53-eth0-rx-23:35:122
1323699170cyclictest3054950irq/53-eth0-rx-23:27:032
1323699170cyclictest3054950irq/53-eth0-rx-23:21:212
1323699170cyclictest3054950irq/53-eth0-rx-22:56:072
1323699170cyclictest3054950irq/53-eth0-rx-22:51:542
1323699170cyclictest3054950irq/53-eth0-rx-22:15:272
1323699170cyclictest3054950irq/53-eth0-rx-22:10:022
1323699170cyclictest3054950irq/53-eth0-rx-22:10:022
1323699170cyclictest3054950irq/53-eth0-rx-21:45:092
1323699170cyclictest3054950irq/53-eth0-rx-21:20:162
1323699170cyclictest3054950irq/53-eth0-rx-21:10:112
1323699170cyclictest3054950irq/53-eth0-rx-20:11:462
1323699170cyclictest3054950irq/53-eth0-rx-20:05:232
1323699170cyclictest3054950irq/53-eth0-rx-19:42:382
1323699170cyclictest3054950irq/53-eth0-rx-00:35:212
1323699170cyclictest299822sleep1022:46:162
1323699170cyclictest291572sleep1020:55:262
1323699170cyclictest287182sleep1019:25:522
1323699170cyclictest278312sleep1021:26:292
1323699170cyclictest264192sleep1021:51:212
1323699170cyclictest262442sleep1020:52:262
1323699170cyclictest254722sleep1000:00:482
1323699170cyclictest247242sleep1000:26:532
1323699170cyclictest247242sleep1000:26:532
1323699170cyclictest191052sleep1020:00:092
1323699170cyclictest191052sleep1020:00:092
1323699170cyclictest153262sleep1021:16:172
1323699170cyclictest151652sleep1020:35:352
1323699170cyclictest147572chrt19:52:432
1323699170cyclictest147232sleep1000:20:042
1323699170cyclictest12250irq/42-ahci20:40:282
1323699170cyclictest116122sleep1000:15:382
1323699170cyclictest115842sleep1022:31:382
1323699170cyclictest114150irq/18-i801_smb19:55:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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