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2026-03-05 - 00:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Mar 04, 2026 12:46:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31692210792sleep110-21swapper/1107:06:223
128501030irq/42-ahci0-21swapper/107:09:031
32009210295sleep80-21swapper/807:09:4210
9918501000irq/53-eth0-rx-0-21swapper/207:07:244
991850950irq/53-eth0-rx-0-21swapper/507:06:387
991850950irq/53-eth0-rx-0-21swapper/307:05:335
991850930irq/53-eth0-rx-0-21swapper/407:06:266
991850920irq/53-eth0-rx-0-21swapper/707:06:569
3201128381sleep100-21swapper/1007:09:442
3183926754sleep00-21swapper/007:08:100
3175326353sleep60-21swapper/607:07:058
3163226354sleep90-21swapper/907:05:3111
32144993330cyclictest991850irq/53-eth0-rx-09:29:391
3213399330cyclictest0-21swapper/009:29:230
32169993129cyclictest991950irq/54-eth0-tx-09:29:377
991850300irq/53-eth0-rx-0-21swapper/909:29:3411
32174993029cyclictest991850irq/53-eth0-rx-09:29:212
32166993029cyclictest991850irq/53-eth0-rx-09:29:316
32158992928cyclictest16015-21ssh09:29:285
32171992827cyclictest991850irq/53-eth0-rx-09:29:349
32133992813cyclictest0-21swapper/010:15:130
32152992423cyclictest991950irq/54-eth0-tx-09:29:254
3217899220cyclictest0-21swapper/1110:12:063
32178992114cyclictest0-21swapper/1108:08:423
32178991918cyclictest991950irq/54-eth0-tx-09:29:363
3217499192cyclictest991950irq/54-eth0-tx-10:59:512
3217499192cyclictest991850irq/53-eth0-rx-12:24:142
3217499192cyclictest991850irq/53-eth0-rx-12:12:282
3217499192cyclictest991850irq/53-eth0-rx-12:12:282
3217499192cyclictest991850irq/53-eth0-rx-11:59:472
3217499192cyclictest991850irq/53-eth0-rx-11:29:222
3217499192cyclictest991850irq/53-eth0-rx-11:05:272
3217499192cyclictest991850irq/53-eth0-rx-11:00:332
3217499192cyclictest991850irq/53-eth0-rx-10:12:452
3217499192cyclictest991850irq/53-eth0-rx-09:53:272
3217499192cyclictest991850irq/53-eth0-rx-09:21:312
3217499192cyclictest991850irq/53-eth0-rx-09:16:212
3217399192cyclictest991950irq/54-eth0-tx-12:24:4411
3217399192cyclictest0-21swapper/912:13:2411
3217399192cyclictest0-21swapper/912:13:2411
3217399192cyclictest0-21swapper/912:03:4511
3217399192cyclictest0-21swapper/912:03:4411
3217399192cyclictest0-21swapper/909:43:2311
3217399192cyclictest0-21swapper/909:32:3211
3217399192cyclictest0-21swapper/908:42:4111
32169991916cyclictest32348-21qemu-kvm10:12:487
3217899183cyclictest0-21swapper/1109:56:513
32174991817cyclictest31048-21kworker/10:212:25:092
32174991817cyclictest0-21swapper/1012:00:342
32174991817cyclictest0-21swapper/1012:00:332
32174991817cyclictest0-21swapper/1011:53:352
32174991817cyclictest0-21swapper/1011:45:202
32174991817cyclictest0-21swapper/1011:15:422
32174991817cyclictest0-21swapper/1009:06:432
3217499181cyclictest991950irq/54-eth0-tx-12:35:072
3217499181cyclictest991950irq/54-eth0-tx-11:35:022
3217499181cyclictest991950irq/54-eth0-tx-09:33:052
3217499181cyclictest991950irq/54-eth0-tx-09:11:302
3217499181cyclictest991850irq/53-eth0-rx-12:32:092
3217499181cyclictest991850irq/53-eth0-rx-12:15:472
3217499181cyclictest991850irq/53-eth0-rx-12:07:122
3217499181cyclictest991850irq/53-eth0-rx-11:40:192
3217499181cyclictest991850irq/53-eth0-rx-11:30:232
3217499181cyclictest991850irq/53-eth0-rx-11:20:482
3217499181cyclictest991850irq/53-eth0-rx-11:11:332
3217499181cyclictest991850irq/53-eth0-rx-10:50:012
3217499181cyclictest991850irq/53-eth0-rx-10:45:592
3217499181cyclictest991850irq/53-eth0-rx-10:41:592
3217499181cyclictest991850irq/53-eth0-rx-10:35:142
3217499181cyclictest991850irq/53-eth0-rx-10:25:122
3217499181cyclictest991850irq/53-eth0-rx-10:20:112
3217499181cyclictest991850irq/53-eth0-rx-10:15:162
3217499181cyclictest991850irq/53-eth0-rx-10:06:142
3217499181cyclictest991850irq/53-eth0-rx-10:02:142
3217499181cyclictest991850irq/53-eth0-rx-09:56:102
3217499181cyclictest991850irq/53-eth0-rx-09:46:562
3217499181cyclictest991850irq/53-eth0-rx-09:40:342
3217499181cyclictest991850irq/53-eth0-rx-09:38:422
3217499181cyclictest991850irq/53-eth0-rx-08:53:322
3217499181cyclictest991850irq/53-eth0-rx-08:45:212
3217499181cyclictest991850irq/53-eth0-rx-08:40:182
3217499181cyclictest991850irq/53-eth0-rx-08:22:202
3217499181cyclictest991850irq/53-eth0-rx-07:57:552
3217499181cyclictest991850irq/53-eth0-rx-07:52:292
3217499181cyclictest991850irq/53-eth0-rx-07:31:182
3217499181cyclictest991850irq/53-eth0-rx-07:26:032
3217499181cyclictest991850irq/53-eth0-rx-07:15:042
3217499181cyclictest831ksoftirqd/1008:30:162
3217499181cyclictest12850irq/42-ahci08:08:562
3217499181cyclictest12850irq/42-ahci07:41:392
3217399181cyclictest28019-21diskmemload09:11:1811
3217399181cyclictest0-21swapper/912:31:1511
3217399181cyclictest0-21swapper/912:05:2011
3217399181cyclictest0-21swapper/911:48:2811
3217399181cyclictest0-21swapper/911:28:5111
3217399181cyclictest0-21swapper/911:19:1011
3217399181cyclictest0-21swapper/911:10:2711
3217399181cyclictest0-21swapper/911:02:5911
3217399181cyclictest0-21swapper/910:29:3211
3217399181cyclictest0-21swapper/910:16:4611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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