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2026-05-05 - 05:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue May 05, 2026 00:46:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501160irq/53-eth0-rx-0-21swapper/319:09:235
9918501140irq/53-eth0-rx-0-21swapper/119:08:151
3396210793sleep80-21swapper/819:08:0010
3300210391sleep50-21swapper/519:06:457
9918501000irq/53-eth0-rx-0-21swapper/219:08:134
3507210088sleep40-21swapper/419:08:446
991850970irq/53-eth0-rx-0-21swapper/1119:07:103
991850910irq/53-eth0-rx-0-21swapper/719:05:199
12850890irq/42-ahci0-21swapper/919:08:2211
321326553sleep00-21swapper/019:05:410
333826257sleep100-21swapper/1019:07:142
320525753sleep60-21swapper/619:05:338
3703992812cyclictest0-21swapper/019:10:010
3745992524cyclictest0-21swapper/1122:11:583
374499192cyclictest991850irq/53-eth0-rx-21:57:102
374499192cyclictest991850irq/53-eth0-rx-21:49:202
374499190cyclictest0-21swapper/1022:11:452
374399192cyclictest0-21swapper/923:08:1411
374399192cyclictest0-21swapper/922:40:5411
374399192cyclictest0-21swapper/900:00:1711
3745991817cyclictest991850irq/53-eth0-rx-22:28:063
3744991817cyclictest27997-1kworker/10:0H22:25:272
3744991817cyclictest0-21swapper/1023:40:062
3744991817cyclictest0-21swapper/1000:14:412
3744991816cyclictest26829-21ssh22:56:322
374499181cyclictest991950irq/54-eth0-tx-21:21:462
374499181cyclictest991950irq/54-eth0-tx-00:06:372
374499181cyclictest991850irq/53-eth0-rx-23:48:532
374499181cyclictest991850irq/53-eth0-rx-23:35:142
374499181cyclictest991850irq/53-eth0-rx-23:29:132
374499181cyclictest991850irq/53-eth0-rx-23:19:062
374499181cyclictest991850irq/53-eth0-rx-23:12:552
374499181cyclictest991850irq/53-eth0-rx-23:07:212
374499181cyclictest991850irq/53-eth0-rx-22:36:422
374499181cyclictest991850irq/53-eth0-rx-22:20:382
374499181cyclictest991850irq/53-eth0-rx-22:19:122
374499181cyclictest991850irq/53-eth0-rx-22:06:252
374499181cyclictest991850irq/53-eth0-rx-21:27:122
374499181cyclictest991850irq/53-eth0-rx-21:15:062
374499181cyclictest991850irq/53-eth0-rx-00:30:202
374499181cyclictest991850irq/53-eth0-rx-00:02:242
374499181cyclictest59672sleep1019:55:072
374399181cyclictest991950irq/54-eth0-tx-23:57:0411
374399181cyclictest7024-21ssh22:13:4111
374399181cyclictest11744-21ssh00:05:3711
374399181cyclictest0-21swapper/923:46:2011
374399181cyclictest0-21swapper/923:29:4311
374399181cyclictest0-21swapper/923:04:1211
374399181cyclictest0-21swapper/922:26:5811
374399181cyclictest0-21swapper/922:23:3111
374399181cyclictest0-21swapper/922:05:2611
374399181cyclictest0-21swapper/921:22:1111
374399181cyclictest0-21swapper/900:20:0411
3739991816cyclictest3459-21qemu-kvm19:10:137
374599170cyclictest0-21swapper/1121:14:303
3744991716cyclictest0-21swapper/1023:20:252
3744991716cyclictest0-21swapper/1023:00:182
3744991715cyclictest1039-21snmp_rack3slot921:40:152
3744991715cyclictest1039-21snmp_rack3slot921:40:152
374499170cyclictest991950irq/54-eth0-tx-22:50:102
374499170cyclictest991850irq/53-eth0-rx-23:55:022
374499170cyclictest991850irq/53-eth0-rx-23:51:112
374499170cyclictest991850irq/53-eth0-rx-22:45:012
374499170cyclictest991850irq/53-eth0-rx-22:40:492
374499170cyclictest991850irq/53-eth0-rx-22:30:422
374499170cyclictest991850irq/53-eth0-rx-21:50:272
374499170cyclictest991850irq/53-eth0-rx-21:35:172
374499170cyclictest991850irq/53-eth0-rx-21:35:162
374499170cyclictest991850irq/53-eth0-rx-20:27:142
374499170cyclictest991850irq/53-eth0-rx-20:21:312
374499170cyclictest991850irq/53-eth0-rx-20:15:252
374499170cyclictest991850irq/53-eth0-rx-19:35:062
374499170cyclictest991850irq/53-eth0-rx-19:25:192
374499170cyclictest991850irq/53-eth0-rx-00:35:182
374499170cyclictest991850irq/53-eth0-rx-00:20:552
374499170cyclictest991850irq/53-eth0-rx-00:15:122
374499170cyclictest87292sleep1020:40:232
374499170cyclictest72082sleep1019:13:262
374499170cyclictest39202sleep1019:50:192
374499170cyclictest33482sleep1020:35:102
374499170cyclictest323622sleep1000:25:032
374499170cyclictest301882sleep1019:40:532
374499170cyclictest284812sleep1021:10:022
374499170cyclictest275972sleep1021:06:152
374499170cyclictest266462sleep1022:01:322
374499170cyclictest221962sleep1021:00:142
374499170cyclictest203492sleep1020:57:012
374499170cyclictest200742sleep1019:30:042
374499170cyclictest200262chrt20:13:442
374499170cyclictest19462sleep1020:30:462
374499170cyclictest18122chrt23:30:202
374499170cyclictest166312chrt20:51:012
374499170cyclictest161932sleep1020:06:552
374499170cyclictest14492sleep1019:46:412
374499170cyclictest12850irq/42-ahci21:30:232
374499170cyclictest12850irq/42-ahci21:30:232
374499170cyclictest12850irq/42-ahci19:20:412
374499170cyclictest12850irq/42-ahci19:15:152
374499170cyclictest112272sleep1020:00:202
374499170cyclictest108462sleep1020:45:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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