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2026-03-08 - 04:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Mar 08, 2026 00:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2281210893sleep10-21swapper/119:07:351
2256210893sleep70-21swapper/719:07:179
2228210892sleep00-21swapper/019:06:580
128501070irq/42-ahci0-21swapper/219:08:564
31754210693sleep80-21swapper/819:05:0610
2148210290sleep40-21swapper/419:06:036
991850930irq/53-eth0-rx-0-21swapper/319:06:595
991850900irq/53-eth0-rx-0-21swapper/519:06:587
991850770irq/53-eth0-rx-0-21swapper/1119:09:143
991850720irq/53-eth0-rx-0-21swapper/1019:05:452
15050670irq/18-uhci_hcd0-21swapper/919:09:5511
3175225753sleep60-21swapper/619:05:058
263999321cyclictest0-21swapper/022:13:530
263999320cyclictest0-21swapper/019:26:020
2639992813cyclictest0-21swapper/019:10:310
263999230cyclictest0-21swapper/019:15:140
269699205cyclictest0-21swapper/1119:16:073
269599192cyclictest991850irq/53-eth0-rx-23:48:372
269599192cyclictest991850irq/53-eth0-rx-23:32:562
269599192cyclictest991850irq/53-eth0-rx-23:21:442
269599192cyclictest991850irq/53-eth0-rx-22:47:512
269599192cyclictest991850irq/53-eth0-rx-22:17:532
269599192cyclictest991850irq/53-eth0-rx-22:02:482
269599192cyclictest991850irq/53-eth0-rx-21:36:382
269599192cyclictest991850irq/53-eth0-rx-21:21:442
269599192cyclictest991850irq/53-eth0-rx-20:05:132
2695991917cyclictest7011-21kworker/10:122:59:072
269499192cyclictest0-21swapper/923:12:2011
269499192cyclictest0-21swapper/922:17:3111
269499192cyclictest0-21swapper/922:07:4711
2696991817cyclictest991850irq/53-eth0-rx-20:25:123
2696991817cyclictest183342sleep1119:27:233
2695991817cyclictest0-21swapper/1022:06:512
2695991817cyclictest0-21swapper/1021:33:272
2695991817cyclictest0-21swapper/1019:41:232
2695991817cyclictest0-21swapper/1019:20:202
2695991817cyclictest0-21swapper/1000:28:032
2695991816cyclictest31986-21ssh22:30:422
2695991816cyclictest19218-21ssh00:05:392
269599181cyclictest991850irq/53-eth0-rx-23:55:332
269599181cyclictest991850irq/53-eth0-rx-23:50:362
269599181cyclictest991850irq/53-eth0-rx-23:42:322
269599181cyclictest991850irq/53-eth0-rx-23:36:262
269599181cyclictest991850irq/53-eth0-rx-23:29:502
269599181cyclictest991850irq/53-eth0-rx-23:15:252
269599181cyclictest991850irq/53-eth0-rx-23:06:542
269599181cyclictest991850irq/53-eth0-rx-23:01:032
269599181cyclictest991850irq/53-eth0-rx-22:50:272
269599181cyclictest991850irq/53-eth0-rx-22:42:112
269599181cyclictest991850irq/53-eth0-rx-22:39:392
269599181cyclictest991850irq/53-eth0-rx-22:26:382
269599181cyclictest991850irq/53-eth0-rx-22:20:262
269599181cyclictest991850irq/53-eth0-rx-22:10:232
269599181cyclictest991850irq/53-eth0-rx-21:58:002
269599181cyclictest991850irq/53-eth0-rx-21:50:122
269599181cyclictest991850irq/53-eth0-rx-21:48:072
269599181cyclictest991850irq/53-eth0-rx-21:40:242
269599181cyclictest991850irq/53-eth0-rx-21:28:362
269599181cyclictest991850irq/53-eth0-rx-21:18:212
269599181cyclictest991850irq/53-eth0-rx-21:10:592
269599181cyclictest991850irq/53-eth0-rx-21:10:582
269599181cyclictest991850irq/53-eth0-rx-19:19:182
269599181cyclictest991850irq/53-eth0-rx-00:17:172
269599181cyclictest991850irq/53-eth0-rx-00:01:472
269599181cyclictest12850irq/42-ahci19:46:102
269599181cyclictest12850irq/42-ahci19:38:512
269599180cyclictest218872chrt19:31:112
269499181cyclictest0-21swapper/922:26:0511
269499181cyclictest0-21swapper/921:55:4911
269499181cyclictest0-21swapper/921:25:3411
269499181cyclictest0-21swapper/900:20:0611
2691991816cyclictest2661-21qemu-kvm22:15:118
269699170cyclictest0-21swapper/1119:30:413
2695991716cyclictest0-21swapper/1020:47:032
269599170cyclictest991950irq/54-eth0-tx-00:32:552
269599170cyclictest991850irq/53-eth0-rx-23:10:082
269599170cyclictest991850irq/53-eth0-rx-21:05:242
269599170cyclictest991850irq/53-eth0-rx-21:05:232
269599170cyclictest991850irq/53-eth0-rx-20:51:242
269599170cyclictest991850irq/53-eth0-rx-20:36:182
269599170cyclictest991850irq/53-eth0-rx-19:56:392
269599170cyclictest991850irq/53-eth0-rx-19:10:222
269599170cyclictest991850irq/53-eth0-rx-00:20:532
269599170cyclictest991850irq/53-eth0-rx-00:10:312
269599170cyclictest94572sleep1020:00:132
269599170cyclictest84862sleep1020:43:312
269599170cyclictest42562chrt19:53:012
269599170cyclictest321282sleep1020:30:172
269599170cyclictest298482sleep1020:27:522
269599170cyclictest260262chrt20:20:292
269599170cyclictest223972sleep1020:15:392
269599170cyclictest205982sleep1000:35:122
269599170cyclictest200692chrt21:00:092
269599170cyclictest187662sleep1020:10:512
269599170cyclictest12850irq/42-ahci19:26:532
269499172cyclictest0-21swapper/922:45:2111
269499170cyclictest26213-21kworker/9:120:30:1511
269499170cyclictest13471-1kworker/9:2H20:11:1811
269499170cyclictest0-21swapper/923:26:3511
269499170cyclictest0-21swapper/900:27:2011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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