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2026-01-18 - 17:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Jan 18, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501140irq/53-eth0-rx-0-21swapper/207:08:264
27198210792sleep70-21swapper/707:06:019
9918501030irq/53-eth0-rx-0-21swapper/107:09:081
9918501000irq/53-eth0-rx-0-21swapper/807:07:3710
991850940irq/53-eth0-rx-0-21swapper/307:05:245
991850920irq/53-eth0-rx-0-21swapper/407:08:036
2755029287sleep90-21swapper/907:09:5211
991850910irq/53-eth0-rx-0-21swapper/507:07:127
2438128881sleep100-21swapper/1007:05:052
991850780irq/53-eth0-rx-0-21swapper/1107:05:083
2721427060sleep60-21swapper/607:06:138
2727026653sleep00-21swapper/007:06:550
27697993029cyclictest991850irq/53-eth0-rx-07:12:267
27649993029cyclictest0-21swapper/007:12:390
27666992726cyclictest991850irq/53-eth0-rx-07:12:361
27649992320cyclictest0-21swapper/009:22:370
27649992314cyclictest0-21swapper/010:25:220
2771299191cyclictest0-21swapper/1110:08:163
2771299190cyclictest901ksoftirqd/1110:24:033
2771199192cyclictest991850irq/53-eth0-rx-11:56:102
2771199192cyclictest991850irq/53-eth0-rx-11:22:342
2771199192cyclictest991850irq/53-eth0-rx-11:06:542
2771199192cyclictest991850irq/53-eth0-rx-10:14:412
2771099192cyclictest0-21swapper/911:12:5211
2771099192cyclictest0-21swapper/909:55:1011
27666991915cyclictest29922-21snmp_rack3slot908:45:151
27712991817cyclictest9601-21kworker/11:009:11:573
27711991817cyclictest0-21swapper/1012:35:432
27711991817cyclictest0-21swapper/1011:51:122
27711991817cyclictest0-21swapper/1011:51:122
27711991817cyclictest0-21swapper/1011:49:582
27711991817cyclictest0-21swapper/1011:49:582
27711991817cyclictest0-21swapper/1011:18:442
27711991817cyclictest0-21swapper/1009:50:242
27711991817cyclictest0-21swapper/1009:11:442
27711991816cyclictest6777-21ssh12:17:012
2771199181cyclictest991950irq/54-eth0-tx-12:26:422
2771199181cyclictest991950irq/54-eth0-tx-11:31:452
2771199181cyclictest991950irq/54-eth0-tx-10:07:272
2771199181cyclictest991950irq/54-eth0-tx-10:01:142
2771199181cyclictest991850irq/53-eth0-rx-12:06:202
2771199181cyclictest991850irq/53-eth0-rx-11:37:232
2771199181cyclictest991850irq/53-eth0-rx-11:37:232
2771199181cyclictest991850irq/53-eth0-rx-11:01:452
2771199181cyclictest991850irq/53-eth0-rx-10:45:532
2771199181cyclictest991850irq/53-eth0-rx-10:26:302
2771199181cyclictest991850irq/53-eth0-rx-10:23:532
2771199181cyclictest991850irq/53-eth0-rx-10:15:082
2771199181cyclictest991850irq/53-eth0-rx-09:55:282
2771199181cyclictest991850irq/53-eth0-rx-09:44:082
2771199181cyclictest991850irq/53-eth0-rx-09:33:232
2771199181cyclictest991850irq/53-eth0-rx-09:23:042
2771199181cyclictest991850irq/53-eth0-rx-09:15:312
2771199181cyclictest991850irq/53-eth0-rx-07:37:322
2771099181cyclictest761ksoftirqd/910:55:0111
2771099181cyclictest761ksoftirqd/909:40:0111
2771099181cyclictest29839-21snmp_rack3slot909:51:1111
2771099181cyclictest27911-21ssh09:23:1211
2771099181cyclictest26934-21open_files08:40:2011
2771099181cyclictest23871-21sh12:31:0311
2771099181cyclictest18398-21df08:30:1411
2771099181cyclictest18398-21df08:30:1311
2771099181cyclictest12307-21cstates09:10:0911
2771099181cyclictest1021-21memory08:05:1911
2771099181cyclictest0-21swapper/912:38:0111
2771099181cyclictest0-21swapper/912:19:1211
2771099181cyclictest0-21swapper/910:28:5411
2771099181cyclictest0-21swapper/910:22:2611
2771099181cyclictest0-21swapper/910:18:2911
2771099181cyclictest0-21swapper/909:45:1211
2771099181cyclictest0-21swapper/907:30:2011
2769899180cyclictest0-21swapper/610:59:568
2764999182cyclictest0-21swapper/007:23:560
27711991716cyclictest0-21swapper/1010:40:282
27711991716cyclictest0-21swapper/1009:00:342
27711991716cyclictest0-21swapper/1008:54:172
27711991716cyclictest0-21swapper/1007:40:142
27711991715cyclictest1538-21snmp_rack3slot907:15:182
2771199170cyclictest991950irq/54-eth0-tx-11:26:002
2771199170cyclictest991950irq/54-eth0-tx-09:45:042
2771199170cyclictest991950irq/54-eth0-tx-09:35:152
2771199170cyclictest991850irq/53-eth0-rx-12:30:072
2771199170cyclictest991850irq/53-eth0-rx-12:20:342
2771199170cyclictest991850irq/53-eth0-rx-12:10:192
2771199170cyclictest991850irq/53-eth0-rx-12:00:062
2771199170cyclictest991850irq/53-eth0-rx-12:00:062
2771199170cyclictest991850irq/53-eth0-rx-11:40:182
2771199170cyclictest991850irq/53-eth0-rx-11:11:002
2771199170cyclictest991850irq/53-eth0-rx-10:51:542
2771199170cyclictest991850irq/53-eth0-rx-10:35:122
2771199170cyclictest991850irq/53-eth0-rx-10:31:222
2771199170cyclictest991850irq/53-eth0-rx-08:40:572
2771199170cyclictest991850irq/53-eth0-rx-08:10:052
2771199170cyclictest991850irq/53-eth0-rx-07:20:142
2771199170cyclictest98302chrt10:56:302
2771199170cyclictest95352chrt08:16:232
2771199170cyclictest37052chrt08:58:042
2771199170cyclictest313642chrt08:45:512
2771199170cyclictest309722sleep1007:10:512
2771199170cyclictest309612sleep1008:02:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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