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2026-04-03 - 23:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Apr 03, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501070irq/53-eth0-rx-0-21swapper/107:09:341
31579210793sleep20-21swapper/207:07:564
9918501020irq/53-eth0-rx-0-21swapper/307:05:195
31492210191sleep40-21swapper/407:06:456
991850990irq/53-eth0-rx-0-21swapper/507:05:227
991850930irq/53-eth0-rx-0-21swapper/807:06:2210
991850870irq/53-eth0-rx-0-21swapper/707:05:339
3176427570sleep100-21swapper/1007:09:402
3020727270sleep00-21swapper/007:05:180
3152826454sleep60-21swapper/607:07:128
991850600irq/53-eth0-rx-0-21swapper/1107:05:283
3145225853sleep90-21swapper/907:06:1411
3193499320cyclictest0-21swapper/1107:25:353
3193499290cyclictest0-21swapper/1109:15:493
3193499290cyclictest0-21swapper/1108:30:133
31892992510cyclictest776-21kworker/0:110:18:020
3191599204cyclictest0-21swapper/311:00:185
3193399192cyclictest991850irq/53-eth0-rx-11:15:492
3193399192cyclictest991850irq/53-eth0-rx-08:45:112
3193299192cyclictest0-21swapper/908:30:2011
31933991817cyclictest0-21swapper/1012:31:082
31933991817cyclictest0-21swapper/1010:46:582
31933991817cyclictest0-21swapper/1009:29:432
31933991817cyclictest0-21swapper/1009:29:422
31933991817cyclictest0-21swapper/1008:35:282
31933991817cyclictest0-21swapper/1007:36:022
3193399181cyclictest991950irq/54-eth0-tx-12:35:302
3193399181cyclictest991950irq/54-eth0-tx-12:35:292
3193399181cyclictest991950irq/54-eth0-tx-11:42:182
3193399181cyclictest991950irq/54-eth0-tx-11:07:542
3193399181cyclictest991950irq/54-eth0-tx-09:17:102
3193399181cyclictest991850irq/53-eth0-rx-12:29:252
3193399181cyclictest991850irq/53-eth0-rx-12:23:192
3193399181cyclictest991850irq/53-eth0-rx-12:19:112
3193399181cyclictest991850irq/53-eth0-rx-12:12:122
3193399181cyclictest991850irq/53-eth0-rx-12:09:222
3193399181cyclictest991850irq/53-eth0-rx-12:01:192
3193399181cyclictest991850irq/53-eth0-rx-11:48:382
3193399181cyclictest991850irq/53-eth0-rx-11:30:242
3193399181cyclictest991850irq/53-eth0-rx-11:10:222
3193399181cyclictest991850irq/53-eth0-rx-10:50:482
3193399181cyclictest991850irq/53-eth0-rx-10:43:162
3193399181cyclictest991850irq/53-eth0-rx-10:29:252
3193399181cyclictest991850irq/53-eth0-rx-10:19:112
3193399181cyclictest991850irq/53-eth0-rx-10:06:242
3193399181cyclictest991850irq/53-eth0-rx-09:51:442
3193399181cyclictest991850irq/53-eth0-rx-09:30:452
3193399181cyclictest991850irq/53-eth0-rx-09:11:282
3193399181cyclictest991850irq/53-eth0-rx-08:25:322
3193299181cyclictest0-21swapper/912:34:4411
3193299181cyclictest0-21swapper/912:27:4411
3193299181cyclictest0-21swapper/912:01:2811
3193299181cyclictest0-21swapper/911:48:2211
3193299181cyclictest0-21swapper/910:26:1211
3193299181cyclictest0-21swapper/910:23:2211
3193299181cyclictest0-21swapper/909:40:1511
3193299181cyclictest0-21swapper/909:40:1411
3193299181cyclictest0-21swapper/909:28:4911
3193299181cyclictest0-21swapper/909:28:4811
3193299181cyclictest0-21swapper/909:14:3211
3193299181cyclictest0-21swapper/907:15:2311
31909991816cyclictest2308-21snmpd10:17:334
31933991716cyclictest31449-1kworker/10:0H08:05:012
31933991716cyclictest0-21swapper/1010:55:582
3193399170cyclictest991950irq/54-eth0-tx-11:50:202
3193399170cyclictest991850irq/53-eth0-rx-11:55:182
3193399170cyclictest991850irq/53-eth0-rx-11:35:172
3193399170cyclictest991850irq/53-eth0-rx-11:25:542
3193399170cyclictest991850irq/53-eth0-rx-11:20:322
3193399170cyclictest991850irq/53-eth0-rx-10:30:212
3193399170cyclictest991850irq/53-eth0-rx-10:20:262
3193399170cyclictest991850irq/53-eth0-rx-09:55:032
3193399170cyclictest991850irq/53-eth0-rx-09:45:022
3193399170cyclictest991850irq/53-eth0-rx-09:41:212
3193399170cyclictest991850irq/53-eth0-rx-09:41:202
3193399170cyclictest991850irq/53-eth0-rx-09:37:122
3193399170cyclictest991850irq/53-eth0-rx-09:06:512
3193399170cyclictest991850irq/53-eth0-rx-09:06:502
3193399170cyclictest991850irq/53-eth0-rx-09:00:242
3193399170cyclictest991850irq/53-eth0-rx-08:57:492
3193399170cyclictest991850irq/53-eth0-rx-08:30:142
3193399170cyclictest991850irq/53-eth0-rx-08:10:132
3193399170cyclictest991850irq/53-eth0-rx-08:05:082
3193399170cyclictest991850irq/53-eth0-rx-07:34:372
3193399170cyclictest991850irq/53-eth0-rx-07:25:052
3193399170cyclictest991850irq/53-eth0-rx-07:15:022
3193399170cyclictest54302sleep1008:44:522
3193399170cyclictest45942sleep1010:11:012
3193399170cyclictest320702sleep1010:35:042
3193399170cyclictest296172chrt07:45:312
3193399170cyclictest27952sleep1007:10:282
3193399170cyclictest262712chrt07:44:312
3193399170cyclictest192542sleep1008:15:472
3193399170cyclictest16962chrt07:55:082
3193399170cyclictest12850irq/42-ahci10:00:292
3193399170cyclictest12850irq/42-ahci09:20:012
3193399170cyclictest12850irq/42-ahci08:20:012
3193399170cyclictest12850irq/42-ahci07:50:312
3193399170cyclictest125242sleep1008:52:032
3193399170cyclictest11872sleep1011:00:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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