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2026-01-27 - 03:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Jan 27, 2026 00:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501110irq/53-eth0-rx-0-21swapper/119:09:431
28830210893sleep20-21swapper/219:06:094
25928210592sleep70-21swapper/719:05:029
12850970irq/42-ahci0-21swapper/319:08:585
991850940irq/53-eth0-rx-0-21swapper/819:05:3710
991850930irq/53-eth0-rx-0-21swapper/519:05:267
991850890irq/53-eth0-rx-0-21swapper/1119:07:313
991850760irq/53-eth0-rx-0-21swapper/419:05:466
991850650irq/53-eth0-rx-0-21swapper/919:07:3511
2600225955sleep100-21swapper/1019:05:052
2886825853sleep60-21swapper/619:06:378
2878625753sleep00-21swapper/019:05:310
29323992827cyclictest0-21swapper/1122:27:283
2931999192cyclictest991850irq/53-eth0-rx-23:55:1311
2931999192cyclictest0-21swapper/923:41:3311
2931999192cyclictest0-21swapper/922:48:1411
2931999181cyclictest991850irq/53-eth0-rx-00:28:4411
2931999181cyclictest0-21swapper/923:39:1611
2931999181cyclictest0-21swapper/923:02:5911
2931999181cyclictest0-21swapper/922:55:1611
2931999181cyclictest0-21swapper/922:09:1511
2931999181cyclictest0-21swapper/921:26:2311
2931999181cyclictest0-21swapper/900:14:0711
29310991816cyclictest26361-21ssh23:02:517
29323991716cyclictest991850irq/53-eth0-rx-20:11:493
2932399170cyclictest0-21swapper/1121:14:083
2932399170cyclictest0-21swapper/1121:14:073
29322991715cyclictest6422-21kworker/10:222:47:552
29322991715cyclictest6422-21kworker/10:221:46:132
29322991715cyclictest32085-1kworker/10:2H20:44:272
29322991715cyclictest0-21swapper/1023:52:502
29322991715cyclictest0-21swapper/1023:07:452
29322991715cyclictest0-21swapper/1022:54:592
29322991715cyclictest0-21swapper/1021:20:272
29322991715cyclictest0-21swapper/1000:24:092
29319991716cyclictest0-21swapper/921:58:3311
29319991716cyclictest0-21swapper/900:36:1911
2931999170cyclictest0-21swapper/923:08:0311
2931999170cyclictest0-21swapper/921:42:5411
29310991716cyclictest20872-21qemu-kvm21:09:007
29310991716cyclictest20872-21qemu-kvm21:09:007
2931099171cyclictest0-21swapper/519:20:197
29302991715cyclictest2308-21snmpd22:22:104
2930299171cyclictest0-21swapper/219:10:204
29323991615cyclictest4611-21kworker/11:122:23:183
29322991615cyclictest8068-21ssh00:10:122
29322991615cyclictest6422-21kworker/10:220:45:012
29322991615cyclictest4392-21ssh23:10:332
29322991615cyclictest32085-1kworker/10:2H22:40:482
29322991615cyclictest32085-1kworker/10:2H22:15:172
29322991615cyclictest32085-1kworker/10:2H20:05:252
29322991615cyclictest19802-1kworker/10:1H00:15:202
29322991615cyclictest18868-21ssh21:35:012
29322991615cyclictest0-21swapper/1023:56:142
29322991615cyclictest0-21swapper/1023:45:372
29322991615cyclictest0-21swapper/1023:30:082
29322991615cyclictest0-21swapper/1023:21:082
29322991615cyclictest0-21swapper/1023:00:342
29322991615cyclictest0-21swapper/1022:36:042
29322991615cyclictest0-21swapper/1022:30:092
29322991615cyclictest0-21swapper/1022:25:012
29322991615cyclictest0-21swapper/1022:20:582
29322991615cyclictest0-21swapper/1022:10:372
29322991615cyclictest0-21swapper/1022:07:392
29322991615cyclictest0-21swapper/1022:00:172
29322991615cyclictest0-21swapper/1021:56:362
29322991615cyclictest0-21swapper/1021:50:062
29322991615cyclictest0-21swapper/1021:31:102
29322991615cyclictest0-21swapper/1021:10:022
29322991615cyclictest0-21swapper/1021:10:022
29322991615cyclictest0-21swapper/1021:07:262
29322991615cyclictest0-21swapper/1021:07:262
29322991615cyclictest0-21swapper/1021:02:322
29322991615cyclictest0-21swapper/1020:56:062
29322991615cyclictest0-21swapper/1020:50:512
29322991615cyclictest0-21swapper/1020:31:012
29322991615cyclictest0-21swapper/1020:26:522
29322991615cyclictest0-21swapper/1020:15:132
29322991615cyclictest0-21swapper/1020:01:102
29322991615cyclictest0-21swapper/1019:54:312
29322991615cyclictest0-21swapper/1019:38:512
29322991615cyclictest0-21swapper/1019:30:272
29322991615cyclictest0-21swapper/1019:29:532
29322991615cyclictest0-21swapper/1019:24:072
29322991615cyclictest0-21swapper/1019:18:082
29322991615cyclictest0-21swapper/1000:35:082
29322991615cyclictest0-21swapper/1000:30:272
29322991615cyclictest0-21swapper/1000:05:102
29322991615cyclictest0-21swapper/1000:00:132
29322991614cyclictest935-21ssh23:35:222
29322991614cyclictest8233-21ssh21:25:142
29322991614cyclictest5486-21df23:40:122
29322991614cyclictest28817-21ssh00:26:432
29322991614cyclictest27556-21ssh21:15:052
29322991614cyclictest0-21swapper/1023:25:182
29322991614cyclictest0-21swapper/1022:55:542
29322991614cyclictest0-21swapper/1021:40:392
29319991615cyclictest0-21swapper/923:54:0711
29319991615cyclictest0-21swapper/923:25:0011
29319991615cyclictest0-21swapper/922:16:5611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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