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2026-05-17 - 19:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun May 17, 2026 12:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501140irq/53-eth0-rx-0-21swapper/107:09:131
26883210995sleep40-21swapper/407:06:306
26940210895sleep100-21swapper/1007:07:122
9918501000irq/53-eth0-rx-0-21swapper/307:09:525
9918501000irq/53-eth0-rx-0-21swapper/207:07:014
991850930irq/53-eth0-rx-0-21swapper/507:07:197
991850890irq/53-eth0-rx-0-21swapper/907:09:5811
991850880irq/53-eth0-rx-0-21swapper/707:07:029
2683528273sleep60-21swapper/607:05:568
2689227158sleep00-21swapper/007:06:380
991850690irq/53-eth0-rx-0-21swapper/1107:05:513
991850660irq/53-eth0-rx-0-21swapper/807:06:0210
27308992422cyclictest0-21swapper/010:17:290
2734899220cyclictest0-21swapper/912:20:0011
2734999192cyclictest991850irq/53-eth0-rx-12:27:522
2734999192cyclictest991850irq/53-eth0-rx-12:15:432
2734999192cyclictest991850irq/53-eth0-rx-11:55:252
2734999192cyclictest991850irq/53-eth0-rx-11:44:552
2734999192cyclictest991850irq/53-eth0-rx-11:12:182
2734999192cyclictest991850irq/53-eth0-rx-10:37:332
2734899192cyclictest0-21swapper/912:03:0611
2734899192cyclictest0-21swapper/911:59:2611
2734899192cyclictest0-21swapper/909:49:4411
2734899192cyclictest0-21swapper/909:23:1411
2730899190cyclictest105462sleep007:26:400
2735099180cyclictest0-21swapper/1107:24:123
27349991817cyclictest0-21swapper/1010:40:062
27349991817cyclictest0-21swapper/1009:34:392
27349991817cyclictest0-21swapper/1008:20:082
27349991816cyclictest16219-21kworker/10:210:06:302
2734999181cyclictest991950irq/54-eth0-tx-11:51:182
2734999181cyclictest991950irq/54-eth0-tx-09:52:372
2734999181cyclictest991850irq/53-eth0-rx-12:36:072
2734999181cyclictest991850irq/53-eth0-rx-12:30:182
2734999181cyclictest991850irq/53-eth0-rx-12:20:272
2734999181cyclictest991850irq/53-eth0-rx-12:10:562
2734999181cyclictest991850irq/53-eth0-rx-12:00:502
2734999181cyclictest991850irq/53-eth0-rx-11:32:462
2734999181cyclictest991850irq/53-eth0-rx-11:05:372
2734999181cyclictest991850irq/53-eth0-rx-11:02:002
2734999181cyclictest991850irq/53-eth0-rx-10:50:212
2734999181cyclictest991850irq/53-eth0-rx-10:50:202
2734999181cyclictest991850irq/53-eth0-rx-10:31:102
2734999181cyclictest991850irq/53-eth0-rx-10:21:212
2734999181cyclictest991850irq/53-eth0-rx-10:16:142
2734999181cyclictest991850irq/53-eth0-rx-10:10:472
2734999181cyclictest991850irq/53-eth0-rx-09:59:172
2734999181cyclictest991850irq/53-eth0-rx-09:46:092
2734999181cyclictest991850irq/53-eth0-rx-09:37:562
2734999181cyclictest991850irq/53-eth0-rx-09:25:412
2734999181cyclictest991850irq/53-eth0-rx-09:13:172
2734999181cyclictest12850irq/42-ahci09:16:402
2734999181cyclictest115050irq/18-i801_smb07:30:212
2734899181cyclictest991850irq/53-eth0-rx-12:33:2911
2734899181cyclictest23179-1kworker/9:2H07:35:4811
2734899181cyclictest0-21swapper/912:37:1211
2734899181cyclictest0-21swapper/912:21:5811
2734899181cyclictest0-21swapper/912:11:3911
2734899181cyclictest0-21swapper/912:09:4911
2734899181cyclictest0-21swapper/911:48:5311
2734899181cyclictest0-21swapper/911:36:5011
2734899181cyclictest0-21swapper/911:31:3111
2734899181cyclictest0-21swapper/911:10:3611
2734899181cyclictest0-21swapper/911:04:2211
2734899181cyclictest0-21swapper/910:56:4411
2734899181cyclictest0-21swapper/910:23:2211
2734899181cyclictest0-21swapper/910:19:3511
2734899181cyclictest0-21swapper/910:10:2411
2734899181cyclictest0-21swapper/910:01:1211
2734899181cyclictest0-21swapper/909:38:1211
2734899181cyclictest0-21swapper/909:15:4711
2734899181cyclictest0-21swapper/907:45:1811
2734899181cyclictest0-21swapper/907:45:1811
2734899181cyclictest0-21swapper/907:30:1411
991850170irq/53-eth0-rx-8917-21ssh10:46:475
27350991715cyclictest269502chrt10:09:463
2734999179cyclictest12850irq/42-ahci09:20:012
27349991716cyclictest0-21swapper/1008:57:022
27349991715cyclictest4879-21snmp_rack3slot907:20:122
2734999170cyclictest991950irq/54-eth0-tx-12:05:142
2734999170cyclictest991950irq/54-eth0-tx-09:40:032
2734999170cyclictest991850irq/53-eth0-rx-11:45:042
2734999170cyclictest991850irq/53-eth0-rx-11:35:282
2734999170cyclictest991850irq/53-eth0-rx-11:25:462
2734999170cyclictest991850irq/53-eth0-rx-11:15:272
2734999170cyclictest991850irq/53-eth0-rx-10:55:212
2734999170cyclictest991850irq/53-eth0-rx-10:45:022
2734999170cyclictest991850irq/53-eth0-rx-10:25:222
2734999170cyclictest991850irq/53-eth0-rx-10:01:162
2734999170cyclictest991850irq/53-eth0-rx-09:05:112
2734999170cyclictest991850irq/53-eth0-rx-09:00:142
2734999170cyclictest991850irq/53-eth0-rx-08:25:392
2734999170cyclictest991850irq/53-eth0-rx-08:15:202
2734999170cyclictest991850irq/53-eth0-rx-08:05:132
2734999170cyclictest991850irq/53-eth0-rx-08:05:132
2734999170cyclictest85312sleep1007:25:142
2734999170cyclictest44002sleep1008:48:002
2734999170cyclictest323912chrt07:56:052
2734999170cyclictest323912chrt07:56:052
2734999170cyclictest32182sleep1007:16:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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