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2026-02-06 - 07:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Fri Feb 06, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501130irq/53-eth0-rx-0-21swapper/119:09:541
19939210894sleep90-21swapper/919:06:0311
20079210593sleep60-21swapper/619:07:498
9918501040irq/53-eth0-rx-0-21swapper/719:06:289
19926210393sleep100-21swapper/1019:05:522
9918501020irq/53-eth0-rx-0-21swapper/319:07:335
9918501020irq/53-eth0-rx-0-21swapper/219:09:344
17124210190sleep50-21swapper/519:05:117
991850970irq/53-eth0-rx-0-21swapper/819:06:4110
991850940irq/53-eth0-rx-0-21swapper/419:07:426
991850900irq/53-eth0-rx-0-21swapper/1119:07:043
1998126553sleep00-21swapper/019:06:300
20401993129cyclictest12733-21tail22:30:140
2043799260cyclictest0-21swapper/522:09:467
20438992524cyclictest24424-21ssh22:13:208
20443992322cyclictest0-21swapper/1121:22:363
20443992322cyclictest0-21swapper/1121:22:363
20443992221cyclictest0-21swapper/1119:15:133
20417992120cyclictest24369-21ssh22:13:144
2044399200cyclictest0-21swapper/1119:20:363
2044299192cyclictest991850irq/53-eth0-rx-23:53:562
2044299192cyclictest991850irq/53-eth0-rx-23:12:112
2044199192cyclictest0-21swapper/923:27:3011
2044199192cyclictest0-21swapper/921:14:0711
2044199192cyclictest0-21swapper/921:14:0611
2042599193cyclictest0-21swapper/321:38:105
2042599192cyclictest0-21swapper/322:19:375
20442991817cyclictest0-21swapper/1022:41:412
20442991817cyclictest0-21swapper/1020:35:332
20442991816cyclictest22877-21ssh23:08:392
2044299181cyclictest991850irq/53-eth0-rx-22:48:542
2044299181cyclictest991850irq/53-eth0-rx-22:32:302
2044299181cyclictest991850irq/53-eth0-rx-21:37:162
2044299181cyclictest991850irq/53-eth0-rx-19:42:062
2044299181cyclictest14050irq/18-ehci_hcd00:21:022
2044299181cyclictest12850irq/42-ahci22:08:252
2044199185cyclictest0-21swapper/919:15:0111
2044199181cyclictest991950irq/54-eth0-tx-22:30:2611
2044199181cyclictest991950irq/54-eth0-tx-00:06:1411
2044199181cyclictest4241-21ssh21:30:0511
2044199181cyclictest23792-1kworker/9:0H22:08:2611
2044199181cyclictest16924-21ssh23:56:4311
2044199181cyclictest0-21swapper/923:48:1211
2044199181cyclictest0-21swapper/923:11:2311
2044199181cyclictest0-21swapper/923:09:5311
2044199181cyclictest0-21swapper/922:48:0111
2044199181cyclictest0-21swapper/922:29:5411
2044199181cyclictest0-21swapper/921:44:1011
2044199181cyclictest0-21swapper/921:20:1911
2044199181cyclictest0-21swapper/921:20:1911
2044199181cyclictest0-21swapper/919:35:2511
2044199181cyclictest0-21swapper/900:36:4411
2044199181cyclictest0-21swapper/900:32:1111
2044199181cyclictest0-21swapper/900:32:1011
2044199181cyclictest0-21swapper/900:25:1211
2044199181cyclictest0-21swapper/900:25:1211
20437991816cyclictest542-21qemu-kvm20:08:407
20437991816cyclictest12134-21qemu-kvm21:30:137
2042599183cyclictest19621-21ssh00:25:445
2042599183cyclictest19621-21ssh00:25:445
2042599182cyclictest12283-21diskmemload21:40:165
2042599182cyclictest0-21swapper/323:55:095
2042599182cyclictest0-21swapper/323:54:045
2042599182cyclictest0-21swapper/323:45:345
2042599182cyclictest0-21swapper/323:40:435
2042599182cyclictest0-21swapper/323:37:515
2042599182cyclictest0-21swapper/323:30:115
2042599182cyclictest0-21swapper/323:25:585
2042599182cyclictest0-21swapper/323:21:535
2042599182cyclictest0-21swapper/323:11:275
2042599182cyclictest0-21swapper/323:05:505
2042599182cyclictest0-21swapper/323:00:365
2042599182cyclictest0-21swapper/322:57:555
2042599182cyclictest0-21swapper/322:50:555
2042599182cyclictest0-21swapper/322:47:255
2042599182cyclictest0-21swapper/322:40:375
2042599182cyclictest0-21swapper/322:35:405
2042599182cyclictest0-21swapper/322:30:455
2042599182cyclictest0-21swapper/322:25:075
2042599182cyclictest0-21swapper/322:20:485
2042599182cyclictest0-21swapper/322:13:405
2042599182cyclictest0-21swapper/322:08:085
2042599182cyclictest0-21swapper/322:01:035
2042599182cyclictest0-21swapper/321:57:435
2042599182cyclictest0-21swapper/321:50:375
2042599182cyclictest0-21swapper/321:45:405
2042599182cyclictest0-21swapper/321:28:035
2042599182cyclictest0-21swapper/321:21:595
2042599182cyclictest0-21swapper/321:21:595
2042599182cyclictest0-21swapper/321:18:475
2042599182cyclictest0-21swapper/321:18:475
2042599182cyclictest0-21swapper/321:10:505
2042599182cyclictest0-21swapper/321:10:505
2042599182cyclictest0-21swapper/321:09:065
2042599182cyclictest0-21swapper/321:01:075
2042599182cyclictest0-21swapper/320:50:405
2042599182cyclictest0-21swapper/320:26:365
2042599182cyclictest0-21swapper/320:22:165
2042599182cyclictest0-21swapper/320:19:245
2042599182cyclictest0-21swapper/320:00:565
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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