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2026-02-11 - 09:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Wed Feb 11, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14372210793sleep70-21swapper/719:07:419
991950990irq/54-eth0-tx-0-21swapper/819:07:1410
991850990irq/53-eth0-rx-0-21swapper/119:05:161
991850960irq/53-eth0-rx-0-21swapper/219:05:324
991850920irq/53-eth0-rx-0-21swapper/419:07:196
12850910irq/42-ahci0-21swapper/319:08:565
991850870irq/53-eth0-rx-0-21swapper/519:08:077
1456327875sleep90-21swapper/919:09:3111
1438927260sleep110-21swapper/1119:07:583
991850690irq/53-eth0-rx-0-21swapper/1019:07:272
1426926855sleep00-21swapper/019:06:220
1423026353sleep60-21swapper/619:05:528
14695995423cyclictest0-21swapper/021:27:260
14695993617cyclictest0-21swapper/020:20:140
1469599330cyclictest0-21swapper/020:19:560
14695993224cyclictest991850irq/53-eth0-rx-19:18:370
14740992928cyclictest991850irq/53-eth0-rx-21:27:3910
991850280irq/53-eth0-rx-0-21swapper/721:27:249
991850280irq/53-eth0-rx-0-21swapper/421:27:286
14740992625cyclictest991850irq/53-eth0-rx-19:18:3510
14747992423cyclictest991850irq/53-eth0-rx-20:11:203
14717992423cyclictest991850irq/53-eth0-rx-19:18:484
991950220irq/54-eth0-tx-0-21swapper/121:27:371
1469599213cyclictest0-21swapper/021:22:370
1474799190cyclictest0-21swapper/1119:10:003
1474199192cyclictest761ksoftirqd/923:42:0111
1474199192cyclictest761ksoftirqd/923:38:2711
1474199192cyclictest761ksoftirqd/923:38:2611
1474199192cyclictest761ksoftirqd/923:34:3411
1474199192cyclictest761ksoftirqd/923:26:1711
1474199192cyclictest761ksoftirqd/923:19:1411
1474199192cyclictest761ksoftirqd/923:19:1311
1474199192cyclictest761ksoftirqd/922:55:2111
1474199192cyclictest761ksoftirqd/922:50:4111
1474199192cyclictest761ksoftirqd/922:30:2611
1474199192cyclictest761ksoftirqd/921:51:1211
1474199192cyclictest761ksoftirqd/900:02:0811
1474199192cyclictest761ksoftirqd/900:02:0811
1474199192cyclictest0-21swapper/922:16:5411
14741991918cyclictest991850irq/53-eth0-rx-19:18:3211
1474299181cyclictest991950irq/54-eth0-tx-00:28:552
1474199181cyclictest761ksoftirqd/923:05:1611
1474199181cyclictest761ksoftirqd/922:40:0211
1474199181cyclictest761ksoftirqd/921:35:5411
1474199181cyclictest761ksoftirqd/921:25:1811
1474199181cyclictest761ksoftirqd/921:20:5011
1474199181cyclictest761ksoftirqd/920:55:0811
1474199181cyclictest761ksoftirqd/920:55:0811
1474199181cyclictest761ksoftirqd/920:50:1211
1474199181cyclictest761ksoftirqd/920:20:1511
1474199181cyclictest761ksoftirqd/920:00:1611
1474199181cyclictest761ksoftirqd/919:25:0111
1474199181cyclictest761ksoftirqd/900:10:0911
1474199181cyclictest761ksoftirqd/900:05:4011
1474199181cyclictest31684-21latency_hist22:25:0011
1474199181cyclictest16899-21kworker/9:121:16:2211
1474199181cyclictest0-21swapper/923:55:1611
1474199181cyclictest0-21swapper/923:55:1511
1474199181cyclictest0-21swapper/923:50:2311
1474199181cyclictest0-21swapper/923:50:2211
1474199181cyclictest0-21swapper/923:45:0411
1474199181cyclictest0-21swapper/923:45:0311
1474199181cyclictest0-21swapper/923:20:0811
1474199181cyclictest0-21swapper/923:10:0611
1474199181cyclictest0-21swapper/923:01:4011
1474199181cyclictest0-21swapper/922:45:2011
1474199181cyclictest0-21swapper/922:35:1511
1474199181cyclictest0-21swapper/922:21:3811
1474199181cyclictest0-21swapper/922:10:1711
1474199181cyclictest0-21swapper/922:05:2811
1474199181cyclictest0-21swapper/922:00:2111
1474199181cyclictest0-21swapper/921:55:4611
1474199181cyclictest0-21swapper/921:47:5011
1474199181cyclictest0-21swapper/921:40:4511
1474199181cyclictest0-21swapper/921:30:0811
1474199181cyclictest0-21swapper/921:12:2511
1474199181cyclictest0-21swapper/921:12:2511
1474199181cyclictest0-21swapper/921:00:1211
1474199181cyclictest0-21swapper/920:45:1111
1474199181cyclictest0-21swapper/920:40:0411
1474199181cyclictest0-21swapper/920:35:0311
1474199181cyclictest0-21swapper/920:30:0311
1474199181cyclictest0-21swapper/920:25:1711
1474199181cyclictest0-21swapper/920:15:2611
1474199181cyclictest0-21swapper/920:10:5011
1474199181cyclictest0-21swapper/920:05:0611
1474199181cyclictest0-21swapper/919:55:0811
1474199181cyclictest0-21swapper/919:51:3411
1474199181cyclictest0-21swapper/919:45:0411
1474199181cyclictest0-21swapper/919:40:0911
1474199181cyclictest0-21swapper/919:35:2411
1474199181cyclictest0-21swapper/919:30:0411
1474199181cyclictest0-21swapper/919:20:3511
1474199181cyclictest0-21swapper/919:10:0311
1474199181cyclictest0-21swapper/900:35:0411
1474199181cyclictest0-21swapper/900:30:1011
1474199181cyclictest0-21swapper/900:25:0811
1474199181cyclictest0-21swapper/900:20:4611
1474199181cyclictest0-21swapper/900:15:2811
1473999184cyclictest0-21swapper/721:22:209
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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