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2026-01-20 - 08:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Tue Jan 20, 2026 00:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501210irq/42-ahci0-21swapper/119:08:521
16071210992sleep110-21swapper/1119:05:523
9918501080irq/53-eth0-rx-0-21swapper/219:09:014
16107210895sleep40-21swapper/419:06:216
9918501040irq/53-eth0-rx-0-21swapper/819:05:5010
9918501020irq/53-eth0-rx-0-21swapper/1019:09:202
12850930irq/42-ahci0-21swapper/319:08:455
991850920irq/53-eth0-rx-0-21swapper/919:06:2911
991850890irq/53-eth0-rx-0-21swapper/719:05:089
991850880irq/53-eth0-rx-0-21swapper/519:05:237
1467026553sleep00-21swapper/019:05:180
1617325955sleep60-21swapper/619:07:128
1658999360cyclictest0-21swapper/1120:26:533
16589993331cyclictest0-21swapper/1119:16:353
16589993331cyclictest0-21swapper/1119:10:243
31320ksoftirqd/00-21swapper/020:25:320
991850300irq/53-eth0-rx-0-21swapper/020:22:370
991950280irq/54-eth0-tx-0-21swapper/822:18:4010
991950280irq/54-eth0-tx-0-21swapper/822:18:4010
991950280irq/54-eth0-tx-0-21swapper/422:18:326
991950280irq/54-eth0-tx-0-21swapper/422:18:326
991850280irq/53-eth0-rx-0-21swapper/922:18:3711
991850280irq/53-eth0-rx-0-21swapper/922:18:3611
991850280irq/53-eth0-rx-0-21swapper/820:22:3610
991850280irq/53-eth0-rx-0-21swapper/720:22:429
991850280irq/53-eth0-rx-0-21swapper/1122:18:413
991850280irq/53-eth0-rx-0-21swapper/1122:18:403
991850280irq/53-eth0-rx-0-21swapper/1022:18:392
991850280irq/53-eth0-rx-0-21swapper/1022:18:382
16547992614cyclictest0-21swapper/019:16:050
16577992315cyclictest8242-21qemu-kvm21:09:478
1658999220cyclictest0-21swapper/1120:23:223
1658999220cyclictest0-21swapper/1120:10:313
1658899225cyclictest991850irq/53-eth0-rx-21:15:142
16547992220cyclictest0-21swapper/021:15:220
16547992220cyclictest0-21swapper/019:10:410
16547992214cyclictest0-21swapper/019:26:400
1658999210cyclictest0-21swapper/1121:12:273
1658999210cyclictest0-21swapper/1120:30:253
1658999210cyclictest0-21swapper/1120:16:513
1658999210cyclictest0-21swapper/1120:09:333
1699210watchdog/00-21swapper/020:19:180
1654799200cyclictest0-21swapper/020:30:010
1658999190cyclictest0-21swapper/1121:08:463
1658899192cyclictest991850irq/53-eth0-rx-22:46:002
1658899192cyclictest991850irq/53-eth0-rx-22:40:232
1658899192cyclictest991850irq/53-eth0-rx-22:03:202
1658899192cyclictest991850irq/53-eth0-rx-21:38:242
1658899192cyclictest991850irq/53-eth0-rx-21:31:092
1658799192cyclictest0-21swapper/922:49:1211
16547991914cyclictest0-21swapper/019:20:040
1654799190cyclictest0-21swapper/020:10:400
12850190irq/42-ahci0-21swapper/020:09:100
991850180irq/53-eth0-rx-0-21swapper/1121:16:423
16588991817cyclictest0-21swapper/1023:59:532
16588991817cyclictest0-21swapper/1023:21:372
16588991817cyclictest0-21swapper/1023:06:082
16588991817cyclictest0-21swapper/1023:04:512
16588991817cyclictest0-21swapper/1022:08:132
1658899181cyclictest991950irq/54-eth0-tx-23:54:342
1658899181cyclictest991950irq/54-eth0-tx-22:32:542
1658899181cyclictest991850irq/53-eth0-rx-23:45:252
1658899181cyclictest991850irq/53-eth0-rx-23:35:192
1658899181cyclictest991850irq/53-eth0-rx-23:25:562
1658899181cyclictest991850irq/53-eth0-rx-23:17:332
1658899181cyclictest991850irq/53-eth0-rx-22:50:212
1658899181cyclictest991850irq/53-eth0-rx-22:35:332
1658899181cyclictest991850irq/53-eth0-rx-22:24:202
1658899181cyclictest991850irq/53-eth0-rx-22:12:012
1658899181cyclictest991850irq/53-eth0-rx-22:12:012
1658899181cyclictest991850irq/53-eth0-rx-21:50:432
1658899181cyclictest991850irq/53-eth0-rx-21:40:102
1658899181cyclictest991850irq/53-eth0-rx-21:25:142
1658899181cyclictest991850irq/53-eth0-rx-21:21:212
1658899181cyclictest991850irq/53-eth0-rx-21:12:522
1658899181cyclictest991850irq/53-eth0-rx-20:33:102
1658899181cyclictest991850irq/53-eth0-rx-20:16:012
1658899181cyclictest991850irq/53-eth0-rx-19:31:512
1658899181cyclictest991850irq/53-eth0-rx-00:36:482
1658899181cyclictest991850irq/53-eth0-rx-00:25:182
1658899181cyclictest991850irq/53-eth0-rx-00:23:462
1658899181cyclictest991850irq/53-eth0-rx-00:12:192
1658899181cyclictest991850irq/53-eth0-rx-00:08:592
1658899181cyclictest12850irq/42-ahci23:11:242
1658899181cyclictest12850irq/42-ahci20:38:132
1658899181cyclictest12850irq/42-ahci00:15:102
1658799181cyclictest991950irq/54-eth0-tx-21:32:2111
1658799181cyclictest7145-21ssh23:54:3311
1658799181cyclictest28787-21sendmail_mailtr20:50:2211
1658799181cyclictest0-21swapper/923:49:3211
1658799181cyclictest0-21swapper/923:43:3211
1658799181cyclictest0-21swapper/922:11:5611
1658799181cyclictest0-21swapper/922:11:5511
1658799181cyclictest0-21swapper/921:56:4311
1658799181cyclictest0-21swapper/921:41:2811
1658799181cyclictest0-21swapper/921:15:4511
1658799181cyclictest0-21swapper/921:03:5111
1658799181cyclictest0-21swapper/920:30:1211
1658799181cyclictest0-21swapper/919:21:4911
1658799181cyclictest0-21swapper/900:26:2611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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