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2026-01-19 - 18:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Jan 19, 2026 12:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30371211097sleep100-21swapper/1007:05:392
30401210995sleep90-21swapper/907:06:0211
291002109103sleep10-21swapper/107:05:171
128501040irq/42-ahci0-21swapper/207:08:444
30538210391sleep50-21swapper/507:07:477
9918501010irq/53-eth0-rx-0-21swapper/707:05:489
128501000irq/42-ahci0-21swapper/807:08:5410
991850980irq/53-eth0-rx-0-21swapper/1107:07:143
991850910irq/53-eth0-rx-0-21swapper/407:07:506
991850910irq/53-eth0-rx-0-21swapper/307:06:575
3053925955sleep60-21swapper/607:07:488
3040525853sleep00-21swapper/007:06:040
3091499500cyclictest0-21swapper/1109:10:043
3091499450cyclictest0-21swapper/1109:09:483
3086399440cyclictest0-21swapper/009:10:360
30914993617cyclictest0-21swapper/1110:21:173
3086399310cyclictest0-21swapper/007:20:490
3091499280cyclictest991850irq/53-eth0-rx-07:19:223
30863992827cyclictest0-21swapper/008:25:260
30863992827cyclictest0-21swapper/008:25:250
30863992711cyclictest128422sleep007:25:190
30914992320cyclictest0-21swapper/1110:08:293
30863992321cyclictest2345-21lldpd07:10:020
3090399220cyclictest3891-21munin-run08:00:009
3091499210cyclictest0-21swapper/1107:26:183
3086399210cyclictest0-21swapper/007:18:120
3091499200cyclictest0-21swapper/1107:23:073
3086399200cyclictest0-21swapper/007:30:510
3091499190cyclictest18112sleep1107:11:513
3091499190cyclictest0-21swapper/1107:30:013
3091399192cyclictest991850irq/53-eth0-rx-10:54:482
3091399192cyclictest991850irq/53-eth0-rx-10:20:342
30913991917cyclictest442-21kworker/10:011:05:212
30913991917cyclictest442-21kworker/10:011:05:202
3091299192cyclictest0-21swapper/909:27:4311
991850180irq/53-eth0-rx-0-21swapper/907:20:4511
991850180irq/53-eth0-rx-0-21swapper/207:27:244
991850180irq/53-eth0-rx-0-21swapper/107:24:421
30914991817cyclictest991850irq/53-eth0-rx-10:27:283
30914991817cyclictest991850irq/53-eth0-rx-10:12:283
30913991817cyclictest0-21swapper/1011:20:222
30913991817cyclictest0-21swapper/1011:20:212
30913991817cyclictest0-21swapper/1010:12:472
30913991817cyclictest0-21swapper/1008:53:042
30913991817cyclictest0-21swapper/1008:25:082
30913991817cyclictest0-21swapper/1008:25:072
30913991817cyclictest0-21swapper/1007:35:212
30913991816cyclictest8915-21ssh09:51:302
30913991816cyclictest30247-21ssh09:43:002
30913991816cyclictest19298-21ssh11:50:272
30913991816cyclictest15632-21iostat_ios10:25:162
3091399181cyclictest991950irq/54-eth0-tx-10:36:342
3091399181cyclictest991850irq/53-eth0-rx-12:25:262
3091399181cyclictest991850irq/53-eth0-rx-12:20:182
3091399181cyclictest991850irq/53-eth0-rx-11:27:372
3091399181cyclictest991850irq/53-eth0-rx-11:00:172
3091399181cyclictest991850irq/53-eth0-rx-10:45:382
3091399181cyclictest991850irq/53-eth0-rx-10:15:072
3091399181cyclictest991850irq/53-eth0-rx-10:02:022
3091399181cyclictest991850irq/53-eth0-rx-09:39:312
3091399181cyclictest991850irq/53-eth0-rx-09:25:052
3091399181cyclictest991850irq/53-eth0-rx-09:22:182
3091399181cyclictest991850irq/53-eth0-rx-07:44:522
3091399181cyclictest12850irq/42-ahci09:08:382
3091399181cyclictest12850irq/42-ahci08:08:562
3091399181cyclictest12850irq/42-ahci07:23:242
3091399180cyclictest12850irq/42-ahci09:46:102
3091299181cyclictest991950irq/54-eth0-tx-11:10:4111
3091299181cyclictest991950irq/54-eth0-tx-11:10:4111
3091299181cyclictest991850irq/53-eth0-rx-11:09:5611
3091299181cyclictest991850irq/53-eth0-rx-11:09:5511
3091299181cyclictest991850irq/53-eth0-rx-09:32:0611
3091299181cyclictest7852-21kworker/9:212:24:2811
3091299181cyclictest761ksoftirqd/912:35:2111
3091299181cyclictest761ksoftirqd/912:08:0711
3091299181cyclictest761ksoftirqd/911:55:2511
3091299181cyclictest761ksoftirqd/911:50:1411
3091299181cyclictest761ksoftirqd/910:35:2611
3091299181cyclictest761ksoftirqd/909:56:4811
3091299181cyclictest761ksoftirqd/909:20:0111
3091299181cyclictest761ksoftirqd/908:40:1811
3091299181cyclictest761ksoftirqd/908:40:1711
3091299181cyclictest761ksoftirqd/908:05:2411
3091299181cyclictest761ksoftirqd/907:30:0111
3091299181cyclictest6037-21cut08:45:1211
3091299181cyclictest5559-21ssh10:15:5111
3091299181cyclictest29999-21snmp_rack3slot909:15:1611
3091299181cyclictest29354-21ssh09:41:1911
3091299181cyclictest26660-21diskstats07:45:1111
3091299181cyclictest24667-21munin-node11:00:2211
3091299181cyclictest24310-21iostat_ios08:25:1611
3091299181cyclictest24310-21iostat_ios08:25:1511
3091299181cyclictest18806-21snmp_rack3slot909:01:5911
3091299181cyclictest12345-21ssh10:22:5611
3091299181cyclictest10433-21ssh12:10:3811
3091299181cyclictest0-21swapper/912:32:0311
3091299181cyclictest0-21swapper/912:25:3511
3091299181cyclictest0-21swapper/912:15:3311
3091299181cyclictest0-21swapper/912:00:1511
3091299181cyclictest0-21swapper/911:46:5411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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