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2026-09-14 - 23:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Mon Sep 14, 2026 12:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501150irq/53-eth0-rx-0-21swapper/107:09:221
30549501140irq/53-eth0-rx-0-21swapper/207:09:174
22102210995sleep80-21swapper/807:06:5910
22052210995sleep90-21swapper/907:06:2411
22085210491sleep60-21swapper/607:06:458
30549501020irq/53-eth0-rx-0-21swapper/307:09:255
30549501010irq/53-eth0-rx-0-21swapper/707:09:369
3054950930irq/53-eth0-rx-0-21swapper/407:08:006
3054950880irq/53-eth0-rx-0-21swapper/507:07:247
2228027573sleep100-21swapper/1007:08:382
2232826760sleep00-21swapper/007:09:170
3054950650irq/53-eth0-rx-0-21swapper/1107:07:063
22530992917cyclictest0-21swapper/1108:14:273
2253099290cyclictest0-21swapper/1110:20:333
3055050280irq/54-eth0-tx-0-21swapper/808:24:3810
3054950280irq/53-eth0-rx-0-21swapper/907:24:1411
3054950280irq/53-eth0-rx-0-21swapper/907:24:1411
3054950280irq/53-eth0-rx-0-21swapper/807:24:0910
3054950280irq/53-eth0-rx-0-21swapper/807:24:0910
3054950280irq/53-eth0-rx-0-21swapper/307:24:035
3054950280irq/53-eth0-rx-0-21swapper/307:24:025
3054950280irq/53-eth0-rx-0-21swapper/108:24:541
2253099256cyclictest0-21swapper/1110:27:363
2253099230cyclictest0-21swapper/1110:09:183
22530992120cyclictest881rcuc/1107:22:533
22530992120cyclictest881rcuc/1107:22:523
2253099210cyclictest0-21swapper/1110:30:253
2252899192cyclictest0-21swapper/911:28:2811
2252899192cyclictest0-21swapper/910:49:1811
22524991916cyclictest2744-21qemu-kvm08:39:477
2251299193cyclictest0-21swapper/308:56:295
2251299191cyclictest0-21swapper/307:55:095
2252899181cyclictest14624-1kworker/9:0H08:46:2511
2252899181cyclictest14276-1kworker/9:2H11:09:4711
2252899181cyclictest0-21swapper/911:23:3011
2252899181cyclictest0-21swapper/910:30:3011
2252899181cyclictest0-21swapper/910:28:5311
2252899181cyclictest0-21swapper/909:35:0111
2252899181cyclictest0-21swapper/909:35:0011
3055050170irq/54-eth0-tx-0-21swapper/010:25:170
2252999170cyclictest0-21swapper/1012:07:422
22528991716cyclictest0-21swapper/908:55:1011
22528991715cyclictest11991-21ssh11:40:2811
2252899170cyclictest32483-21ssh11:31:3411
2252899170cyclictest0-21swapper/912:39:4911
2252899170cyclictest0-21swapper/912:12:0511
2252899170cyclictest0-21swapper/911:36:1411
2252899170cyclictest0-21swapper/909:55:5711
2252899170cyclictest0-21swapper/909:28:3411
2252699171cyclictest0-21swapper/709:25:009
22525991716cyclictest14265-21qemu-kvm09:23:008
22524991715cyclictest27333-21snmp_rack3slot911:01:377
2251299172cyclictest0-21swapper/308:02:155
22505991715cyclictest2305-21snmpd10:39:264
2249999174cyclictest0-21swapper/111:43:141
14750170irq/18-uhci_hcd0-21swapper/009:15:230
14750170irq/18-uhci_hcd0-21swapper/009:15:220
22530991614cyclictest25352-21chrt07:10:263
22530991614cyclictest25352-21chrt07:10:263
2253099160cyclictest0-21swapper/1110:10:023
22528991615cyclictest741rcuc/907:44:1511
22528991615cyclictest0-21swapper/911:15:5311
22528991615cyclictest0-21swapper/910:50:1811
22528991615cyclictest0-21swapper/910:02:0411
22528991615cyclictest0-21swapper/909:40:0911
22528991614cyclictest6237-21chrt08:10:4211
22528991614cyclictest12956-21chrt07:35:3911
22524991615cyclictest4654-21snmp_rack3slot912:27:127
22524991615cyclictest2744-21qemu-kvm08:23:387
2251799160cyclictest12302-21ssh12:07:426
22512991614cyclictest27108-21hwlatdetect10:10:145
2251299161cyclictest0-21swapper/312:33:195
2251299161cyclictest0-21swapper/309:04:085
2251299160cyclictest0-21swapper/309:06:055
2251299160cyclictest0-21swapper/308:51:235
2251299160cyclictest0-21swapper/308:48:195
2251299160cyclictest0-21swapper/308:41:435
2251299160cyclictest0-21swapper/308:31:505
2251299160cyclictest0-21swapper/308:28:155
2251299160cyclictest0-21swapper/308:16:365
2251299160cyclictest0-21swapper/307:42:065
22505991614cyclictest2305-21snmpd10:57:244
22505991614cyclictest2305-21snmpd09:43:544
2249999160cyclictest0-21swapper/109:25:191
3054950150irq/53-eth0-rx-0-21swapper/008:24:420
2252999150cyclictest0-21swapper/1012:10:112
2252999150cyclictest0-21swapper/1011:27:032
2252999150cyclictest0-21swapper/1010:45:222
2252999150cyclictest0-21swapper/1007:40:162
2252899154cyclictest0-21swapper/911:55:0111
22528991514cyclictest3054950irq/53-eth0-rx-08:24:3811
22528991514cyclictest0-21swapper/912:30:1511
22528991514cyclictest0-21swapper/909:50:1211
22528991513cyclictest31027-21taskset07:19:4511
2252699153cyclictest0-21swapper/711:10:009
2252699153cyclictest0-21swapper/709:55:499
22524991514cyclictest510-21snmp_rack3slot911:05:357
22524991514cyclictest2744-21qemu-kvm08:19:417
22524991514cyclictest17258-21snmp_rack3slot912:10:337
2252499150cyclictest0-21swapper/512:10:007
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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