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2026-07-12 - 12:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot3.osadl.org (updated Sun Jul 12, 2026 00:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501120irq/53-eth0-rx-0-21swapper/219:09:354
12841210190sleep100-21swapper/1019:05:472
3054950980irq/53-eth0-rx-0-21swapper/119:05:131
3054950950irq/53-eth0-rx-0-21swapper/319:05:515
3054950920irq/53-eth0-rx-0-21swapper/419:07:306
3054950890irq/53-eth0-rx-0-21swapper/719:06:359
3054950880irq/53-eth0-rx-0-21swapper/1119:07:163
3055050760irq/54-eth0-tx-0-21swapper/819:08:2710
1290226960sleep90-21swapper/919:06:3411
3054950680irq/53-eth0-rx-0-21swapper/519:07:027
1291026553sleep00-21swapper/019:06:370
1283726353sleep60-21swapper/619:05:448
13372993029cyclictest3054950irq/53-eth0-rx-19:19:2411
13354992928cyclictest12250irq/42-ahci19:19:246
13374992827cyclictest12250irq/42-ahci19:19:203
13371992726cyclictest3054950irq/53-eth0-rx-19:19:1810
13349992625cyclictest3054950irq/53-eth0-rx-19:19:215
1337499220cyclictest0-21swapper/1121:08:413
1337499220cyclictest0-21swapper/1121:08:403
1333499221cyclictest0-21swapper/122:51:071
1337499200cyclictest0-21swapper/1122:13:153
13374991917cyclictest0-21swapper/1122:08:303
13374991917cyclictest0-21swapper/1122:08:293
13373991917cyclictest0-21swapper/1022:23:272
13373991917cyclictest0-21swapper/1021:11:142
1337299192cyclictest0-21swapper/923:35:4311
1337299192cyclictest0-21swapper/923:12:0911
1337299192cyclictest0-21swapper/922:48:4311
1337299192cyclictest0-21swapper/922:25:1011
1337299192cyclictest0-21swapper/922:00:1011
1337299192cyclictest0-21swapper/900:15:3711
1337299192cyclictest0-21swapper/900:02:4311
1337299192cyclictest0-21swapper/900:02:4211
13373991817cyclictest831ksoftirqd/1021:39:332
13373991817cyclictest811rcuc/1000:28:512
13373991817cyclictest6901-21ssh00:14:282
13373991817cyclictest6901-21ssh00:14:272
13373991817cyclictest0-21swapper/1023:55:252
13373991817cyclictest0-21swapper/1023:50:072
13373991817cyclictest0-21swapper/1023:32:552
13373991817cyclictest0-21swapper/1023:05:102
13373991817cyclictest0-21swapper/1022:55:182
13373991817cyclictest0-21swapper/1022:52:192
13373991817cyclictest0-21swapper/1022:45:532
13373991817cyclictest0-21swapper/1022:00:242
13373991817cyclictest0-21swapper/1021:56:022
13373991817cyclictest0-21swapper/1021:50:372
13373991817cyclictest0-21swapper/1021:26:302
13373991817cyclictest0-21swapper/1020:30:272
13373991817cyclictest0-21swapper/1020:18:122
13373991817cyclictest0-21swapper/1000:35:032
13373991817cyclictest0-21swapper/1000:16:392
13373991816cyclictest24232-21kworker/10:222:10:032
13373991816cyclictest24232-21kworker/10:221:41:432
1337299181cyclictest741rcuc/922:08:1911
1337299181cyclictest741rcuc/922:08:1811
1337299181cyclictest3055050irq/54-eth0-tx-22:40:4611
1337299181cyclictest0-21swapper/923:50:3811
1337299181cyclictest0-21swapper/923:19:0211
1337299181cyclictest0-21swapper/922:59:3911
1337299181cyclictest0-21swapper/922:50:1211
1337299181cyclictest0-21swapper/922:39:2111
1337299181cyclictest0-21swapper/922:30:3211
1337299181cyclictest0-21swapper/921:53:2511
1337299181cyclictest0-21swapper/921:45:4411
1337299181cyclictest0-21swapper/900:36:3411
1337299181cyclictest0-21swapper/900:26:0011
1337299181cyclictest0-21swapper/900:23:3511
1337199180cyclictest0-21swapper/822:29:5510
1336199180cyclictest0-21swapper/521:16:307
13342991816cyclictest2305-21snmpd22:29:524
13374991716cyclictest0-21swapper/1121:26:043
13373991716cyclictest831ksoftirqd/1023:35:272
13373991716cyclictest831ksoftirqd/1023:10:252
13373991716cyclictest831ksoftirqd/1022:37:582
13373991716cyclictest831ksoftirqd/1020:45:122
13373991716cyclictest831ksoftirqd/1019:50:152
13373991716cyclictest831ksoftirqd/1019:45:212
13373991716cyclictest811rcuc/1022:42:262
13373991716cyclictest2227-21df22:25:132
13373991716cyclictest1654-1kworker/10:0H19:10:232
13373991716cyclictest11698-21ssh22:05:272
13373991716cyclictest11698-21ssh22:05:262
13373991716cyclictest0-21swapper/1023:47:392
13373991716cyclictest0-21swapper/1023:40:022
13373991716cyclictest0-21swapper/1023:20:072
13373991716cyclictest0-21swapper/1023:15:392
13373991716cyclictest0-21swapper/1023:00:352
13373991716cyclictest0-21swapper/1022:15:482
13373991716cyclictest0-21swapper/1021:46:022
13373991716cyclictest0-21swapper/1021:31:262
13373991716cyclictest0-21swapper/1021:20:102
13373991716cyclictest0-21swapper/1021:18:302
13373991716cyclictest0-21swapper/1021:06:492
13373991716cyclictest0-21swapper/1021:06:482
13373991716cyclictest0-21swapper/1020:50:182
13373991716cyclictest0-21swapper/1020:00:162
13373991716cyclictest0-21swapper/1019:30:152
13373991716cyclictest0-21swapper/1019:20:462
13373991716cyclictest0-21swapper/1000:20:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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