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2025-12-01 - 05:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Mon Dec 01, 2025 00:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501110irq/42-ahci0-21swapper/119:08:241
27221210694sleep70-21swapper/719:07:329
27212210694sleep110-21swapper/1119:07:243
3066350990irq/52-eth0-rx-0-21swapper/419:06:266
12250970irq/42-ahci0-21swapper/219:09:434
3066350890irq/52-eth0-rx-0-21swapper/519:05:217
2715128274sleep00-21swapper/019:06:370
12250800irq/42-ahci0-21swapper/319:08:105
2736826558sleep80-21swapper/819:08:4710
2712626553sleep60-21swapper/619:06:198
2711526455sleep90-21swapper/919:06:1011
2708826355sleep100-21swapper/1019:05:472
2760899380cyclictest0-21swapper/1119:17:513
27608993113cyclictest207362sleep1120:25:203
27608992711cyclictest134302chrt20:15:193
2760899210cyclictest0-21swapper/1120:20:173
2760899210cyclictest0-21swapper/1120:09:333
2760899200cyclictest115162sleep1120:14:553
2760699190cyclictest0-21swapper/922:14:5611
2759799194cyclictest0-21swapper/720:50:019
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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