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2026-02-15 - 08:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Sun Feb 15, 2026 00:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501000irq/53-eth0-rx-0-21swapper/119:09:291
991850980irq/53-eth0-rx-0-21swapper/1119:08:043
12850980irq/42-ahci0-21swapper/919:08:2111
12850970irq/42-ahci0-21swapper/219:05:594
991850950irq/53-eth0-rx-0-21swapper/419:06:056
991850920irq/53-eth0-rx-0-21swapper/1019:06:492
12850920irq/42-ahci0-21swapper/319:09:045
991850880irq/53-eth0-rx-0-21swapper/819:09:3510
991850870irq/53-eth0-rx-0-21swapper/519:08:027
618228476sleep70-21swapper/719:07:339
623126653sleep60-21swapper/619:08:088
606225955sleep00-21swapper/019:06:020
6567992914cyclictest0-21swapper/1121:09:063
656799280cyclictest0-21swapper/1122:29:333
656799220cyclictest0-21swapper/1121:23:343
656799220cyclictest0-21swapper/1121:23:343
6525992019cyclictest0-21swapper/022:10:250
656699192cyclictest991850irq/53-eth0-rx-00:05:272
6566991817cyclictest0-21swapper/1023:19:252
6566991817cyclictest0-21swapper/1021:42:412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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