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2024-03-02 - 20:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Sat Mar 02, 2024 12:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120501390irq/42-ahci20513-21qemu-kvm07:08:105
120501130irq/42-ahci0-21swapper/207:08:574
20478210591sleep60-21swapper/607:07:538
18779501040irq/52-eth0-rx-0-21swapper/407:08:076
1877950960irq/52-eth0-rx-0-21swapper/107:09:311
1877950920irq/52-eth0-rx-0-21swapper/507:06:597
1877950790irq/52-eth0-rx-0-21swapper/1007:05:322
1878050750irq/53-eth0-tx-0-21swapper/707:05:369
12050750irq/42-ahci0-21swapper/807:06:4710
1878050730irq/53-eth0-tx-0-21swapper/1107:09:313
1831026955sleep00-21swapper/007:05:220
1877950680irq/52-eth0-rx-0-21swapper/907:08:1411
2079399320cyclictest0-21swapper/010:28:390
20793992524cyclictest0-21swapper/010:09:030
2079399250cyclictest0-21swapper/009:13:580
2084299190cyclictest0-21swapper/1107:27:353
2084299190cyclictest0-21swapper/1107:27:353
20841991913cyclictest13810-1kworker/10:1H08:08:302
20841991912cyclictest24744-21df07:15:012
20841991910cyclictest13810-1kworker/10:1H11:15:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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