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2026-01-01 - 07:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Thu Jan 01, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15796210794sleep20-21swapper/219:05:374
124501020irq/42-ahci0-21swapper/119:08:561
1581829685sleep70-21swapper/719:05:549
12450940irq/42-ahci0-21swapper/319:08:205
12450910irq/42-ahci0-21swapper/819:08:5710
2651150890irq/49-eth0-rx-0-21swapper/519:07:407
1585028879sleep110-21swapper/1119:06:223
1613828377sleep40-21swapper/419:09:286
1591827767sleep00-21swapper/019:07:120
1455127665sleep90-21swapper/919:05:2011
1300526858sleep60-21swapper/619:05:058
1611526764sleep100-21swapper/1019:09:102
16293993617cyclictest0-21swapper/019:27:300
1633199290cyclictest0-21swapper/1120:14:303
1633199230cyclictest0-21swapper/1119:28:523
1633199220cyclictest0-21swapper/1119:20:443
1633199220cyclictest0-21swapper/1119:16:043
16293992221cyclictest0-21swapper/019:17:570
1632999192cyclictest0-21swapper/923:57:0311
1632999192cyclictest0-21swapper/923:40:1211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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