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2026-08-29 - 22:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Sat Aug 29, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14607210994sleep100-21swapper/1007:05:522
14848210893sleep80-21swapper/807:08:1410
122501030irq/42-ahci0-21swapper/107:08:331
30549501000irq/53-eth0-rx-0-21swapper/707:08:169
3054950940irq/53-eth0-rx-0-21swapper/507:06:077
3054950940irq/53-eth0-rx-0-21swapper/207:08:024
3054950920irq/53-eth0-rx-0-21swapper/307:06:395
171450800irq/56-eth1-rx-0-21swapper/907:09:1511
3054950780irq/53-eth0-rx-0-21swapper/1107:05:043
12250740irq/42-ahci0-21swapper/407:08:556
1463725955sleep60-21swapper/607:06:138
1458025955sleep00-21swapper/007:05:310
15120994314cyclictest0-21swapper/1110:21:223
3055050280irq/54-eth0-tx-5858-21diskmemload09:19:156
3055050280irq/54-eth0-tx-0-21swapper/809:19:2610
3054950280irq/53-eth0-rx-0-21swapper/909:19:2111
3054950280irq/53-eth0-rx-0-21swapper/908:23:2511
3054950280irq/53-eth0-rx-0-21swapper/309:19:285
3054950280irq/53-eth0-rx-0-21swapper/208:23:234
3054950280irq/53-eth0-rx-0-21swapper/1109:19:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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