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2026-03-02 - 09:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Mon Mar 02, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501120irq/53-eth0-rx-0-21swapper/319:08:265
128501120irq/42-ahci0-21swapper/219:09:084
128501030irq/42-ahci0-21swapper/119:09:091
991850920irq/53-eth0-rx-0-21swapper/719:08:389
2144229287sleep100-21swapper/1019:09:382
991850900irq/53-eth0-rx-0-21swapper/419:08:496
991850840irq/53-eth0-rx-0-21swapper/819:08:4210
2126226961sleep90-21swapper/919:08:0111
991850670irq/53-eth0-rx-0-21swapper/519:07:487
2142026661sleep60-21swapper/619:09:218
2078426654sleep00-21swapper/019:05:280
2114026555sleep110-21swapper/1119:06:263
2161399330cyclictest0-21swapper/1121:26:583
2161399320cyclictest0-21swapper/1122:11:213
2157999268cyclictest991850irq/53-eth0-rx-21:13:580
21613992418cyclictest0-21swapper/1120:08:233
21579992117cyclictest991850irq/53-eth0-rx-21:19:330
21579992019cyclictest0-21swapper/022:25:580
21579992018cyclictest0-21swapper/020:08:220
2161199192cyclictest0-21swapper/921:35:5511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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