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2026-04-16 - 21:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Thu Apr 16, 2026 12:46:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501150irq/53-eth0-rx-0-21swapper/307:09:405
11084211095sleep20-21swapper/207:07:254
11103210793sleep80-21swapper/807:07:4210
128501040irq/42-ahci0-21swapper/107:09:501
11290210196sleep100-21swapper/1007:09:202
991850980irq/53-eth0-rx-0-21swapper/707:09:149
991850940irq/53-eth0-rx-0-21swapper/907:06:0711
991850920irq/53-eth0-rx-0-21swapper/407:07:396
991850880irq/53-eth0-rx-0-21swapper/507:07:257
12850850irq/42-ahci0-21swapper/1107:08:583
1095325853sleep60-21swapper/607:05:538
1093225853sleep00-21swapper/007:05:340
11485994021cyclictest0-21swapper/1108:22:383
11451993317cyclictest2745-21runrttasks10:19:570
11485993029cyclictest12850irq/42-ahci07:15:163
11485993029cyclictest12850irq/42-ahci07:11:173
11451993027cyclictest0-21swapper/010:10:360
11451993027cyclictest0-21swapper/010:10:350
11451993013cyclictest11022-1kworker/0:0H10:20:040
11451992928cyclictest31917-21md0_resync07:11:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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