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2025-07-19 - 01:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Fri Jul 18, 2025 12:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26657210791sleep00-21swapper/007:07:190
26633210592sleep70-21swapper/707:07:029
12850990irq/42-ahci0-21swapper/307:06:455
12850990irq/42-ahci0-21swapper/107:05:491
2014050980irq/53-eth0-rx-0-21swapper/407:05:206
2681729584sleep90-21swapper/907:08:3911
12850950irq/42-ahci0-21swapper/207:09:074
2684729186sleep100-21swapper/1007:09:042
2014050890irq/53-eth0-rx-0-21swapper/507:07:467
12850830irq/42-ahci0-21swapper/807:08:5810
2664128274sleep110-21swapper/1107:07:063
2664926653sleep60-21swapper/607:07:138
2706799310cyclictest0-21swapper/1109:26:373
27022993114cyclictest0-21swapper/009:17:490
27067992722cyclictest0-21swapper/1110:24:413
27022992726cyclictest597-21md0_raid107:28:520
27067992625cyclictest0-21swapper/1110:17:533
2706599250cyclictest12850irq/42-ahci12:14:0011
27067992322cyclictest12850irq/42-ahci07:28:423
27053992120cyclictest597-21md0_raid107:28:416
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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