You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-11-05 - 07:22
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Tue Nov 05, 2024 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126501120irq/42-ahci0-21swapper/119:08:261
1162501120irq/18-i801_smb0-21swapper/419:05:236
12550210089sleep90-21swapper/919:08:5011
12650990irq/42-ahci0-21swapper/319:07:465
2963350920irq/52-eth0-rx-0-21swapper/219:05:074
14950910irq/18-uhci_hcd0-21swapper/819:09:1610
116150900irq/18-parport00-21swapper/1019:08:382
2963350890irq/52-eth0-rx-0-21swapper/519:07:167
116150880irq/18-parport00-21swapper/719:09:179
116250760irq/18-i801_smb0-21swapper/1119:05:553
1227327261sleep00-21swapper/019:05:520
1231226758sleep60-21swapper/619:06:228
12782992928cyclictest0-21swapper/1122:24:373
1273899230cyclictest0-21swapper/019:29:330
12781991817cyclictest31307-1kworker/10:1H22:08:572
12781991816cyclictest8311-21snmp_rack3slot919:45:122
12781991816cyclictest6471-21snmp_rack3slot900:05:492
12781991816cyclictest28329-21snmp_rack3slot900:36:262
12781991816cyclictest2812-21hddtemp_smartct21:05:162
12781991816cyclictest25517-21snmp_easybox.os19:25:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional