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2025-05-03 - 01:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot3.osadl.org (updated Fri May 02, 2025 12:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30778210991sleep50-21swapper/507:06:187
30982210892sleep00-21swapper/007:08:150
122501010irq/42-ahci0-21swapper/107:09:471
3105129691sleep80-21swapper/807:09:1010
2963550950irq/54-eth0-tx-0-21swapper/307:05:265
12250940irq/42-ahci0-21swapper/207:09:204
2963450900irq/53-eth0-rx-0-21swapper/907:05:2111
12250890irq/42-ahci0-21swapper/407:06:266
3108128882sleep70-21swapper/707:09:349
3086728875sleep110-21swapper/1107:07:243
3086227667sleep60-21swapper/607:07:198
3097527268sleep100-21swapper/1007:08:122
31257996028cyclictest0-21swapper/1109:15:243
31257995926cyclictest0-21swapper/1109:09:483
31257995827cyclictest0-21swapper/1109:10:253
12250420irq/42-ahci0-21swapper/009:17:590
31226994135cyclictest30695-21md0_resync10:33:361
31226994135cyclictest30695-21md0_resync10:33:351
3125799371cyclictest0-21swapper/1112:24:373
3125399370cyclictest0-21swapper/710:59:379
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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