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2026-01-19 - 09:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Mon Jan 19, 2026 00:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9918501150irq/53-eth0-rx-0-21swapper/119:09:381
9918501150irq/53-eth0-rx-0-21swapper/119:09:371
128501140irq/42-ahci0-21swapper/219:09:244
128501140irq/42-ahci0-21swapper/219:09:234
128501080irq/42-ahci0-21swapper/819:08:5410
128501080irq/42-ahci0-21swapper/819:08:5310
128501040irq/42-ahci0-21swapper/319:09:285
128501040irq/42-ahci0-21swapper/319:09:275
4568210392sleep70-21swapper/719:07:029
4568210392sleep70-21swapper/719:07:029
9918501000irq/53-eth0-rx-0-21swapper/1019:05:302
9918501000irq/53-eth0-rx-0-21swapper/1019:05:302
991850860irq/53-eth0-rx-0-21swapper/1119:08:123
991850860irq/53-eth0-rx-0-21swapper/1119:08:113
991850840irq/53-eth0-rx-0-21swapper/419:06:236
991850840irq/53-eth0-rx-0-21swapper/419:06:226
479227267sleep60-21swapper/619:09:138
479227267sleep60-21swapper/619:09:128
991850710irq/53-eth0-rx-0-21swapper/519:08:017
991850710irq/53-eth0-rx-0-21swapper/519:08:017
457426957sleep00-21swapper/019:07:070
457426957sleep00-21swapper/019:07:070
157725955sleep90-21swapper/919:05:0411
157725955sleep90-21swapper/919:05:0411
496099460cyclictest0-21swapper/022:22:350
499299300cyclictest0-21swapper/921:30:1511
991850280irq/53-eth0-rx-0-21swapper/822:22:3410
991850280irq/53-eth0-rx-0-21swapper/222:22:474
4960992812cyclictest0-21swapper/019:22:060
4960992812cyclictest0-21swapper/019:22:060
5001992019cyclictest991850irq/53-eth0-rx-21:11:093
499299192cyclictest0-21swapper/923:37:1311
499299192cyclictest0-21swapper/923:26:2511
499299192cyclictest0-21swapper/923:17:5411
499299192cyclictest0-21swapper/922:08:5811
499299192cyclictest0-21swapper/922:08:5811
499299192cyclictest0-21swapper/921:57:2211
499299192cyclictest0-21swapper/921:20:2711
499299192cyclictest0-21swapper/921:12:3911
499299192cyclictest0-21swapper/900:34:3511
499499181cyclictest991950irq/54-eth0-tx-23:26:202
499499181cyclictest991850irq/53-eth0-rx-23:45:202
499499181cyclictest991850irq/53-eth0-rx-22:38:092
499499181cyclictest991850irq/53-eth0-rx-19:45:362
499499181cyclictest831ksoftirqd/1020:25:222
4992991816cyclictest24112-21taskset19:30:3411
4992991816cyclictest24112-21taskset19:30:3311
499299181cyclictest761ksoftirqd/922:25:1311
499299181cyclictest761ksoftirqd/922:10:1611
499299181cyclictest761ksoftirqd/922:10:1511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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