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2020-12-03 - 05:48

Intel(R) Core(TM) i7 CPU X 980 @ 3.33GHz, Linux 3.12.31-rt45 (Profile)

Latency plot of system in rack #3, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Wed Dec 02, 2020 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120501150irq/42-ahci0-21swapper/107:04:201
120501040irq/42-ahci0-21swapper/307:02:135
12050930irq/42-ahci0-21swapper/207:03:284
12050870irq/42-ahci0-21swapper/707:04:509
12050850irq/42-ahci0-21swapper/407:04:136
118650820irq/18-parport00-21swapper/1107:01:003
970027867sleep100-21swapper/1007:01:332
173650780irq/55-eth1-rx-0-21swapper/807:05:0910
12050720irq/42-ahci0-21swapper/907:05:3011
1004526967sleep50-21swapper/507:05:177
975426654sleep00-21swapper/007:02:110
969625955sleep60-21swapper/607:01:298
10165993617cyclictest0-21swapper/009:22:250
10191993316cyclictest831ksoftirqd/1010:00:492
1016599320cyclictest0-21swapper/008:21:420
12050300irq/42-ahci0-21swapper/108:21:461
10191993013cyclictest831ksoftirqd/1010:25:412
10191993013cyclictest831ksoftirqd/1009:06:012
10190993029cyclictest12050irq/42-ahci08:21:4611
10186993029cyclictest12050irq/42-ahci08:21:427
10185993029cyclictest12050irq/42-ahci08:21:476
10192992827cyclictest12050irq/42-ahci08:21:423
10191992726cyclictest12050irq/42-ahci08:21:522
10188992726cyclictest12050irq/42-ahci08:21:539
10165992711cyclictest0-21swapper/010:08:550
1019199269cyclictest831ksoftirqd/1007:41:102
1019199269cyclictest831ksoftirqd/1007:31:482
1019199269cyclictest831ksoftirqd/1007:31:482
1019199258cyclictest831ksoftirqd/1010:19:262
10191992524cyclictest0-21swapper/1009:55:302
1016599240cyclictest0-21swapper/008:32:060
1016599240cyclictest0-21swapper/008:32:060
1016599230cyclictest0-21swapper/009:37:180
1016599230cyclictest0-21swapper/007:11:000
1016599230cyclictest0-21swapper/007:11:000
1018799224cyclictest0-21swapper/610:25:378
1016599220cyclictest0-21swapper/010:47:310
1016599220cyclictest0-21swapper/008:40:580
1016599210cyclictest0-21swapper/011:20:490
1016599210cyclictest0-21swapper/010:55:520
1016599210cyclictest0-21swapper/010:27:260
1016599210cyclictest0-21swapper/007:40:570
1016599210cyclictest0-21swapper/007:36:540
1016599210cyclictest0-21swapper/007:36:540
1019099203cyclictest761ksoftirqd/911:36:1411
1019099203cyclictest761ksoftirqd/911:12:2211
1019099203cyclictest761ksoftirqd/910:48:2911
1019099203cyclictest761ksoftirqd/910:07:4111
1019099203cyclictest761ksoftirqd/909:46:4211
1019099203cyclictest761ksoftirqd/908:41:5711
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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