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2026-09-02 - 08:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Wed Sep 02, 2026 00:46:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549501120irq/53-eth0-rx-0-21swapper/719:09:179
30765210894sleep40-21swapper/419:06:316
30549501040irq/53-eth0-rx-0-21swapper/219:06:094
30549501020irq/53-eth0-rx-0-21swapper/519:06:567
12250960irq/42-ahci0-21swapper/119:09:061
3055050830irq/54-eth0-tx-0-21swapper/819:08:5410
12250800irq/42-ahci0-21swapper/319:05:235
3069927264sleep00-21swapper/019:05:390
3102326660sleep90-21swapper/919:09:1311
3075726657sleep110-21swapper/1119:06:263
3102426462sleep100-21swapper/1019:09:142
3081325853sleep60-21swapper/619:07:098
31187993617cyclictest0-21swapper/020:28:390
31187993115cyclictest0-21swapper/020:09:030
3118799300cyclictest2291-21nscd22:17:110
3118799260cyclictest0-21swapper/019:18:380
3123499192cyclictest3054950irq/53-eth0-rx-23:32:252
3123499192cyclictest3054950irq/53-eth0-rx-23:27:262
3123499192cyclictest3054950irq/53-eth0-rx-23:08:062
3123499192cyclictest3054950irq/53-eth0-rx-22:42:572
3123499192cyclictest3054950irq/53-eth0-rx-22:20:092
3123499192cyclictest3054950irq/53-eth0-rx-21:55:582
3123499192cyclictest3054950irq/53-eth0-rx-21:31:362
3123499192cyclictest3054950irq/53-eth0-rx-00:28:082
3123499192cyclictest3054950irq/53-eth0-rx-00:24:072
3123399192cyclictest0-21swapper/923:46:2311
3123399192cyclictest0-21swapper/923:37:2411
3123399192cyclictest0-21swapper/922:06:5711
3123399192cyclictest0-21swapper/921:54:1011
3123399192cyclictest0-21swapper/900:21:5711
31234991817cyclictest30258-1kworker/10:2H21:38:082
31234991817cyclictest20657-21ssh00:37:252
31234991817cyclictest0-21swapper/1023:10:342
31234991817cyclictest0-21swapper/1022:56:092
31234991817cyclictest0-21swapper/1022:45:202
31234991817cyclictest0-21swapper/1022:45:202
31234991817cyclictest0-21swapper/1022:27:332
31234991817cyclictest0-21swapper/1020:16:062
31234991817cyclictest0-21swapper/1019:20:542
31234991817cyclictest0-21swapper/1019:17:152
31234991817cyclictest0-21swapper/1000:05:222
31234991817cyclictest0-21swapper/1000:04:252
3123499181cyclictest3055050irq/54-eth0-tx-23:21:492
3123499181cyclictest3055050irq/54-eth0-tx-23:15:512
3123499181cyclictest3055050irq/54-eth0-tx-23:00:442
3123499181cyclictest3055050irq/54-eth0-tx-22:00:302
3123499181cyclictest3054950irq/53-eth0-rx-23:56:272
3123499181cyclictest3054950irq/53-eth0-rx-23:45:172
3123499181cyclictest3054950irq/53-eth0-rx-23:44:202
3123499181cyclictest3054950irq/53-eth0-rx-23:37:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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