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2026-06-04 - 01:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Wed Jun 03, 2026 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122501110irq/42-ahci0-21swapper/207:08:414
5925211097sleep90-21swapper/907:07:3911
30549501100irq/53-eth0-rx-0-21swapper/407:07:056
122501090irq/42-ahci0-21swapper/307:08:565
5911210891sleep00-21swapper/007:07:310
5891210492sleep70-21swapper/707:07:149
122501030irq/42-ahci0-21swapper/107:09:541
3054950950irq/53-eth0-rx-0-21swapper/807:05:3310
3054950950irq/53-eth0-rx-0-21swapper/507:05:117
3054950930irq/53-eth0-rx-0-21swapper/1107:05:523
3054950910irq/53-eth0-rx-0-21swapper/1007:05:082
579626855sleep60-21swapper/607:06:018
6309993621cyclictest0-21swapper/1110:16:473
6260993617cyclictest0-21swapper/010:16:330
630999290cyclictest0-21swapper/1109:11:453
626099248cyclictest31237-21kworker/0:209:17:200
6302992316cyclictest0-21swapper/609:20:018
630999210cyclictest0-21swapper/1107:11:323
630899192cyclictest3054950irq/53-eth0-rx-12:34:032
630899192cyclictest3054950irq/53-eth0-rx-12:02:532
630899192cyclictest3054950irq/53-eth0-rx-12:02:522
630899192cyclictest3054950irq/53-eth0-rx-10:47:392
630899192cyclictest3054950irq/53-eth0-rx-09:38:252
630899192cyclictest12250irq/42-ahci10:08:352
630799192cyclictest0-21swapper/912:36:4711
630799192cyclictest0-21swapper/912:32:2711
630799192cyclictest0-21swapper/911:22:2511
630799192cyclictest0-21swapper/911:07:2711
630799192cyclictest0-21swapper/910:04:3611
630299198cyclictest0-21swapper/610:05:018
630299192cyclictest0-21swapper/608:00:278
6260991917cyclictest0-21swapper/010:10:300
630899185cyclictest0-21swapper/1012:12:182
6308991817cyclictest28299-21ssh10:50:482
6308991817cyclictest0-21swapper/1012:19:112
6308991817cyclictest0-21swapper/1011:51:262
6308991817cyclictest0-21swapper/1011:51:262
6308991817cyclictest0-21swapper/1011:11:062
6308991817cyclictest0-21swapper/1011:08:062
6308991817cyclictest0-21swapper/1009:24:352
630899181cyclictest3055050irq/54-eth0-tx-10:57:012
630899181cyclictest3055050irq/54-eth0-tx-10:30:532
630899181cyclictest3055050irq/54-eth0-tx-10:29:522
630899181cyclictest3055050irq/54-eth0-tx-09:46:472
630899181cyclictest3054950irq/53-eth0-rx-12:36:502
630899181cyclictest3054950irq/53-eth0-rx-12:20:142
630899181cyclictest3054950irq/53-eth0-rx-11:57:032
630899181cyclictest3054950irq/53-eth0-rx-11:47:382
630899181cyclictest3054950irq/53-eth0-rx-11:28:462
630899181cyclictest3054950irq/53-eth0-rx-11:23:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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