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2026-04-19 - 23:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot3.osadl.org (updated Sun Apr 19, 2026 12:46:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128501190irq/42-ahci0-21swapper/207:08:234
9918501110irq/53-eth0-rx-0-21swapper/707:08:279
26471211095sleep80-21swapper/807:06:5710
26431210894sleep30-21swapper/307:06:285
26368210593sleep10-21swapper/107:05:381
991950950irq/54-eth0-tx-0-21swapper/407:05:136
991850880irq/53-eth0-rx-0-21swapper/1007:06:202
2577828877sleep110-21swapper/1107:05:243
991850870irq/53-eth0-rx-0-21swapper/507:05:447
2663228574sleep90-21swapper/907:08:2211
2645226353sleep60-21swapper/607:06:438
2639725955sleep00-21swapper/007:06:010
26910993718cyclictest0-21swapper/1109:08:433
26910993718cyclictest0-21swapper/1109:08:433
26873993720cyclictest4573-21kworker/0:009:12:330
26873993720cyclictest4573-21kworker/0:009:12:320
26873993217cyclictest0-21swapper/009:08:430
26873993217cyclictest0-21swapper/009:08:430
2691099240cyclictest0-21swapper/1108:28:423
26898992318cyclictest28348-21snmp_rack3slot907:51:369
26910992217cyclictest0-21swapper/1107:24:093
2690999204cyclictest0-21swapper/1008:53:322
26873992018cyclictest0-21swapper/008:08:290
2690999192cyclictest991850irq/53-eth0-rx-12:18:462
2690999192cyclictest991850irq/53-eth0-rx-12:08:202
2690999192cyclictest991850irq/53-eth0-rx-12:01:472
2690999192cyclictest991850irq/53-eth0-rx-11:30:412
2690999192cyclictest991850irq/53-eth0-rx-11:28:222
2690999192cyclictest991850irq/53-eth0-rx-11:02:022
2690999192cyclictest991850irq/53-eth0-rx-10:55:302
2690999192cyclictest991850irq/53-eth0-rx-10:41:312
2690999192cyclictest991850irq/53-eth0-rx-10:28:392
2690999192cyclictest991850irq/53-eth0-rx-10:09:032
2690999192cyclictest991850irq/53-eth0-rx-10:00:042
2690999192cyclictest991850irq/53-eth0-rx-09:56:292
2690999192cyclictest991850irq/53-eth0-rx-09:32:532
2690999192cyclictest991850irq/53-eth0-rx-09:22:112
2690999192cyclictest991850irq/53-eth0-rx-09:11:292
2690999192cyclictest991850irq/53-eth0-rx-09:11:292
2690899192cyclictest0-21swapper/910:49:3611
26909991817cyclictest0-21swapper/1011:44:242
26909991817cyclictest0-21swapper/1010:10:062
26909991817cyclictest0-21swapper/1009:50:562
2690999181cyclictest991850irq/53-eth0-rx-12:39:332
2690999181cyclictest991850irq/53-eth0-rx-12:39:332
2690999181cyclictest991850irq/53-eth0-rx-12:34:422
2690999181cyclictest991850irq/53-eth0-rx-12:25:372
2690999181cyclictest991850irq/53-eth0-rx-12:21:032
2690999181cyclictest991850irq/53-eth0-rx-11:51:082
2690999181cyclictest991850irq/53-eth0-rx-11:45:492
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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