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2026-05-21 - 00:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot4.osadl.org (updated Wed May 20, 2026 12:46:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
963532229922983,4sleep50-21swapper/507:05:495
96400899153117,28cyclictest1166402-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:08:330
9640089914670,51cyclictest1073102-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:21:160
96400899145108,29cyclictest1127733-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:43:270
96400899145108,29cyclictest1127733-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:43:270
96400899140107,26cyclictest1270939-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:38:540
9640089913580,48cyclictest1192458-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:29:250
9640089913463,48cyclictest968354-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
07:24:260
9640089913264,44cyclictest1073102-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:02:020
9640089913178,46cyclictest971672-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:31:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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