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2026-02-19 - 19:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot4.osadl.org (updated Thu Feb 19, 2026 12:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1231493212861259,17sleep40-21swapper/407:05:164
123329699137114,16cyclictest1481787-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:46:080
123329699132100,25cyclictest1225539-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:11:350
126353421150,5sleep30-21swapper/308:25:003
12332969911476,8cyclictest1359022-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:23:110
12332969911363,27cyclictest1436653-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:29:280
12332969911055,32cyclictest1253299-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
08:27:420
12332969910973,6cyclictest1481787-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:58:430
133458921050,5sleep00-21swapper/009:50:420
12332969910419,61cyclictest1414948-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:30:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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