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2025-08-26 - 21:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot4.osadl.org (updated Tue Aug 26, 2025 12:46:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3370746229372927,5sleep50-21swapper/507:09:045
3369144213841362,8sleep03368591-21kworker/0:1+events@
dbs_work_handler
07:05:140
33707002399375,14sleep40-21swapper/407:08:274
337097999167126,14cyclictest3420184-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:10:500
337097999160122,18cyclictest3614385-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:26:290
337097999137114,15cyclictest3505885-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:51:100
337097999137113,17cyclictest3392775-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
08:05:340
337097999131109,15cyclictest3563089-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:26:180
337097999131109,15cyclictest3563089-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:26:170
337099099121108,6cyclictest3392775-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
08:10:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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