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2026-01-05 - 15:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot4.osadl.org (updated Mon Jan 05, 2026 12:47:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226879799150134,7cyclictest2326784-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:30:332
22687879914380,26cyclictest2398789-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:40:000
226879799139124,7cyclictest2309047-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:00:282
226878799137102,27cyclictest2534364-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:36:130
22687879913663,18cyclictest2343910-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:13:120
226878799135109,18cyclictest2292719-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:15:160
22687879913274,25cyclictest2320726-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:14:400
226879199122105,8cyclictest2262196-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
07:35:011
22687879912194,6cyclictest2278484-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
07:45:050
22687879912092,8cyclictest2304815-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:15:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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