You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-05 - 12:45
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot4.osadl.org (updated Wed Nov 05, 2025 00:47:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
786645222382218,7sleep1755526-21kworker/1:2+events@
dbs_work_handler
19:05:191
78835299156121,26cyclictest921756-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:37:120
78835299153119,26cyclictest1046545-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:17:290
78835299141107,26cyclictest809984-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
20:11:530
78835299141107,26cyclictest809984-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
20:11:530
788352991301,68cyclictest0-21swapper/022:20:170
788352991301,68cyclictest0-21swapper/022:20:160
7883529912892,28cyclictest767231-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:16:440
7883529912794,26cyclictest819856-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:31:560
7883529912794,26cyclictest819856-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:31:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional