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2025-09-19 - 07:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack3slot4.osadl.org (updated Fri Sep 19, 2025 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3066344233193287,20sleep40-21swapper/419:05:204
3066344233193287,20sleep40-21swapper/419:05:204
306782599138124,7cyclictest3236203-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:08:032
306782999124111,6cyclictest3167248-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:02:523
306782999120106,7cyclictest3112216-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:13:083
30678299911399,7cyclictest3302619-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:33:463
30678299910895,6cyclictest3097745-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:32:593
30678299910895,6cyclictest3085614-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:02:533
30678299910692,7cyclictest3212556-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:53:003
30678299910590,8cyclictest3212556-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:43:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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