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2026-02-19 - 07:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Thu Feb 19, 2026 00:46:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2005799122107,8cyclictest287424-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:28:403
2005799122107,8cyclictest287424-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:28:393
200439911721,64cyclictest20292-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:21:290
200439911721,64cyclictest20292-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:21:290
14946121130,3sleep10-21swapper/122:12:131
200579911095,8cyclictest102033-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:40:543
200579910995,7cyclictest4185677-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:25:223
20043991081,85cyclictest13300-21snmpd21:45:440
20043991081,85cyclictest13300-21snmpd21:45:440
200439910727,41cyclictest20292-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:39:030
200439910727,41cyclictest20292-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:39:030
200579910590,7cyclictest261862-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:47:133
200669910397,2cyclictest0-21swapper/500:38:455
200439910327,54cyclictest34010-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:38:490
20043991020,86cyclictest0-21swapper/000:15:000
200579910086,6cyclictest102033-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:05:583
200439910021,58cyclictest229385-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:34:510
20043991001,84cyclictest0-21swapper/021:10:320
20043991001,84cyclictest0-21swapper/021:10:320
20057999985,6cyclictest20292-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:15:213
20043999925,42cyclictest269126-21kworker/u12:2+rpciod@
rpc_async_schedule
23:45:170
20057999884,7cyclictest73716-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:15:483
20057999884,7cyclictest73716-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:15:483
20043999766,17cyclictest69050irq/528-eth0-Tx23:52:530
20043999559,14cyclictest0-21swapper/023:03:010
20043999532,39cyclictest69050irq/528-eth0-Tx22:50:350
20057999463,7cyclictest261862-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:06:043
2004399942,77cyclictest0-21swapper/021:03:220
2004399940,78cyclictest108513-21ssh21:40:450
20057999380,6cyclictest102033-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:55:573
20057999380,6cyclictest102033-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:55:573
20057999378,8cyclictest314503-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:18:343
20057999278,7cyclictest34010-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:11:353
20057999260,8cyclictest190939-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:26:003
20052999279,7cyclictest52456-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:35:412
20043999134,38cyclictest68950irq/527-eth0-Tx22:35:280
20043999127,38cyclictest0-21swapper/023:35:180
20043999119,45cyclictest40227-21sed20:00:010
2004399911,72cyclictest261862-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:05:340
20066999085,2cyclictest0-21swapper/520:45:335
20057999074,8cyclictest34010-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:57:053
20057998976,7cyclictest190939-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:56:103
20043998975,7cyclictest287424-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:15:390
20057998874,7cyclictest73716-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:25:133
20057998874,7cyclictest229385-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:22:173
20057998873,7cyclictest131494-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:15:283
20043998864,12cyclictest68950irq/527-eth0-Tx20:50:030
2004399882,71cyclictest176165-21ssh22:32:440
2004399882,71cyclictest176165-21ssh22:32:440
20057998774,6cyclictest238910-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:34:083
20057998773,7cyclictest161352-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:53:473
20043998733,37cyclictest69150irq/529-eth0-Tx00:34:310
2004399871,73cyclictest0-21swapper/019:28:220
2004399871,68cyclictest198145-21cat22:50:010
20043998715,59cyclictest0-21swapper/023:55:370
20043998715,59cyclictest0-21swapper/023:55:360
20066998680,3cyclictest0-21swapper/523:11:115
20066998680,3cyclictest0-21swapper/523:11:105
20057998664,8cyclictest287424-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:03:163
20043998658,15cyclictest0-21swapper/020:03:310
20043998657,14cyclictest0-21swapper/020:17:410
20043998633,37cyclictest68950irq/527-eth0-Tx22:10:360
2004399861,80cyclictest0-21swapper/020:55:030
2004399860,67cyclictest0-21swapper/023:10:440
2004399860,67cyclictest0-21swapper/023:10:430
20057998575,7cyclictest210-21kswapd022:40:253
20057998571,7cyclictest60933-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:34:453
20057998570,8cyclictest238910-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:35:503
2004399851,73cyclictest0-21swapper/020:25:290
20057998470,7cyclictest34010-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:03:253
20057998470,7cyclictest330534-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:34:563
20057998468,8cyclictest131494-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:21:083
20043998419,27cyclictest0-21swapper/022:15:310
2004399841,66cyclictest0-21swapper/021:58:290
2004399841,66cyclictest0-21swapper/021:58:280
20057998370,6cyclictest339075-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:37:153
20057998370,6cyclictest190939-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:01:113
20043998374,6cyclictest34010-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:19:570
20043998374,6cyclictest34010-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:19:560
2004399832,77cyclictest0-21swapper/019:15:190
2004399832,72cyclictest0-21swapper/020:30:030
2004399831,74cyclictest0-21swapper/021:08:340
2004399831,67cyclictest0-21swapper/020:20:190
2004399831,67cyclictest0-21swapper/020:20:190
2004399831,65cyclictest0-21swapper/019:40:130
2004399831,57cyclictest0-21swapper/020:40:270
2004399830,68cyclictest102783-21rm21:36:380
1354582830,5sleep50-21swapper/522:01:225
20057998270,6cyclictest60933-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:05:473
20057998267,8cyclictest261862-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:10:523
20057998265,9cyclictest222518-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:10:333
20057998265,9cyclictest222518-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:10:323
20043998255,13cyclictest0-21swapper/020:08:530
20043998255,13cyclictest0-21swapper/020:08:530
20043998253,18cyclictest0-21swapper/023:19:070
20043998253,18cyclictest0-21swapper/023:19:060
20043998217,32cyclictest0-21swapper/021:30:140
2004399821,57cyclictest68647-21diskmemload22:00:300
2004399820,67cyclictest121459-21timerwakeupswit21:50:420
2004399820,65cyclictest270224-21latency_hist23:45:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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