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2026-02-07 - 08:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Sat Feb 07, 2026 00:46:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
548648213371311,16sleep40-21swapper/419:05:394
5492042283264,8sleep0549105-21kworker/0:1+events@
dbs_work_handler
19:07:430
5495369914413,80cyclictest581711-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:55:330
549536991382,104cyclictest555480-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:44:210
54955899127122,2cyclictest0-21swapper/522:01:475
54955899127122,2cyclictest0-21swapper/522:01:465
549536991262,5cyclictest703406-21ssh22:35:130
549536991262,5cyclictest703406-21ssh22:35:120
549536991242,96cyclictest0-21swapper/021:44:350
5495369912415,79cyclictest553424-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:23:230
5495369912415,79cyclictest553424-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:23:230
54954099122108,7cyclictest563262-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
19:51:121
5495369912028,59cyclictest69150irq/529-eth0-Tx22:25:300
5495369912011,81cyclictest0-21swapper/023:45:000
549536991201,100cyclictest0-21swapper/023:09:410
549536991185,100cyclictest48-21rcuop/421:26:350
5495369911845,13cyclictest0-21swapper/023:30:220
549536991181,103cyclictest0-21swapper/020:10:370
549536991172,105cyclictest0-21swapper/023:50:330
549536991172,105cyclictest0-21swapper/023:50:320
54954099116102,7cyclictest647809-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:17:021
54954099116102,7cyclictest647809-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:17:021
5495369911660,42cyclictest587501-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:20:220
5495369911660,42cyclictest587501-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:20:220
54954099114101,6cyclictest729450-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:57:001
5495369911472,38cyclictest14550irq/98-imx_mu_c00:00:300
5495369911434,58cyclictest647809-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:51:400
549536991141,95cyclictest0-21swapper/023:47:390
54954599113100,6cyclictest567382-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:56:122
5495409911299,6cyclictest695060-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:31:531
5495409911299,6cyclictest695060-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:31:521
5495369911263,39cyclictest69050irq/528-eth0-Tx19:55:030
549536991122,97cyclictest0-21swapper/023:38:430
549536991121,35cyclictest0-21swapper/023:03:160
54955899111104,3cyclictest0-21swapper/523:27:045
5495369911163,38cyclictest68950irq/527-eth0-Tx20:40:210
5495369911163,38cyclictest68950irq/527-eth0-Tx20:40:210
5495369911147,39cyclictest0-21swapper/020:49:110
5495369911127,30cyclictest69150irq/529-eth0-Tx21:45:310
549536991112,5cyclictest584910-21ntpq20:35:350
5495369911125,65cyclictest608494-21idleruntime-cro21:20:010
5495369911110,51cyclictest69250irq/530-eth0-Tx23:25:140
5495369911046,36cyclictest0-21swapper/019:50:210
549536991102,87cyclictest0-21swapper/019:45:270
549536991092,93cyclictest0-21swapper/019:15:370
549536991092,86cyclictest550037-21cat19:10:180
549536991092,85cyclictest815453-21ssh00:05:460
5495549910895,8cyclictest857064-21ssh00:40:014
5495369910871,25cyclictest0-21swapper/020:20:170
5495369910866,31cyclictest650-21jbd2/mmcblk1p3-19:30:140
5495369910821,39cyclictest0-21swapper/000:20:440
5495369910821,39cyclictest0-21swapper/000:20:430
5495369910764,34cyclictest69150irq/529-eth0-Tx20:15:130
5495369910764,29cyclictest69050irq/528-eth0-Tx21:05:230
5495369910763,29cyclictest0-21swapper/020:05:350
5495369910748,40cyclictest660432-21ntp_states22:00:360
5495369910748,40cyclictest660432-21ntp_states22:00:360
5495369910663,31cyclictest0-21swapper/000:00:010
5495369910663,30cyclictest69050irq/528-eth0-Tx20:00:360
5495369910658,29cyclictest68950irq/527-eth0-Tx21:55:200
5495369910658,29cyclictest68950irq/527-eth0-Tx21:55:200
5495369910649,40cyclictest0-21swapper/020:50:530
82873721050,3sleep30-21swapper/300:16:283
5495459910593,6cyclictest551400-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:16:062
549536991052,58cyclictest753294-21ssh23:15:290
549536991052,58cyclictest753294-21ssh23:15:280
549536991051,52cyclictest0-21swapper/000:30:330
5495409910482,8cyclictest750416-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:53:141
5495409910482,8cyclictest750416-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:53:131
549536991042,5cyclictest582431-21df_inode20:30:190
549536991041,84cyclictest0-21swapper/021:32:430
5495459910392,5cyclictest581711-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:51:212
5495369910366,25cyclictest68950irq/527-eth0-Tx22:16:140
5495369910359,33cyclictest0-21swapper/021:00:250
5495369910358,34cyclictest69050irq/528-eth0-Tx21:10:470
5495369910351,11cyclictest0-21swapper/020:25:330
5495369910351,11cyclictest0-21swapper/020:25:330
549536991031,59cyclictest48-21rcuop/421:51:340
5495369910258,28cyclictest0-21swapper/022:07:340
549536991021,86cyclictest0-21swapper/019:37:210
549536991021,86cyclictest0-21swapper/019:37:210
549536991021,61cyclictest0-21swapper/000:15:400
5495369910159,26cyclictest0-21swapper/022:24:120
5495369910146,37cyclictest0-21swapper/023:23:430
5495369910146,37cyclictest0-21swapper/023:23:420
5495369910129,55cyclictest69250irq/530-eth0-Tx00:11:240
549536991012,84cyclictest597972-21diskmemload00:25:440
549536991012,5cyclictest710560-21ntpq22:40:360
5495369910026,38cyclictest68950irq/527-eth0-Tx21:35:310
6845432990,4sleep30-21swapper/322:20:043
549554999993,3cyclictest0-21swapper/419:55:054
549554999989,5cyclictest847875-21ssh00:31:494
549536999955,5cyclictest597972-21diskmemload22:59:220
54953699991,64cyclictest852121-21/usr/sbin/munin00:35:250
54953699991,46cyclictest0-21swapper/022:10:100
549536999845,40cyclictest0-21swapper/019:26:270
54953699982,55cyclictest0-21swapper/022:45:410
54953699981,7cyclictest752588-21idleruntime-cro23:15:010
8043572970,4sleep20-21swapper/223:57:042
549536999754,31cyclictest0-21swapper/022:30:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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