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2026-02-26 - 09:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Thu Feb 26, 2026 00:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27887321005981,14sleep40-21swapper/419:05:554
27887321005981,14sleep40-21swapper/419:05:544
2793399915130,81cyclictest523798-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:50:200
27933999147112,28cyclictest370269-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:51:450
2793399913763,39cyclictest311417-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:40:530
2793399913763,39cyclictest311417-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:40:520
2793399913576,51cyclictest435561-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:35:050
2793399913398,15cyclictest297381-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:06:250
2793399913398,15cyclictest297381-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:06:240
2793399913296,15cyclictest303804-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:16:270
2793399912995,14cyclictest427977-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:02:030
2793399912995,14cyclictest427977-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:02:030
2793399912870,38cyclictest330892-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:21:180
2793399912869,40cyclictest541539-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:55:400
2793399912767,36cyclictest483317-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:39:240
2793399912756,39cyclictest427977-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:49:500
27934499122108,7cyclictest461112-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:12:041
2793399912266,36cyclictest553323-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:12:130
2793399911951,51cyclictest396457-21runrttasks22:03:190
2793399911858,37cyclictest390498-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:14:390
2793399911752,43cyclictest282944-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:18:330
2793399911657,37cyclictest279676-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:29:290
2793399911271,38cyclictest354092-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:32:550
279339991111,90cyclictest0-21swapper/022:55:370
2793399911050,41cyclictest0-21swapper/022:06:530
2793399911049,37cyclictest370269-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:32:460
41766421070,8sleep337-21ksoftirqd/322:19:443
2793399910767,37cyclictest361907-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:41:430
2793399910758,42cyclictest282944-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:55:340
2793589910599,3cyclictest0-21swapper/400:03:054
2793589910599,3cyclictest0-21swapper/400:03:054
2793399910583,15cyclictest327633-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:11:360
2793399910560,37cyclictest279676-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:35:360
2793399910465,24cyclictest461112-21kworker/u12:0+flush-179:96@
wb_workfn
23:10:410
2793399910461,36cyclictest344985-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:26:390
2793399910461,36cyclictest344985-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:26:380
2793399910358,38cyclictest449889-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:50:200
2793539910288,7cyclictest390498-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:11:513
2793399910282,16cyclictest533423-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:07:350
2793489910187,7cyclictest344985-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:26:432
2793489910187,7cyclictest344985-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:26:432
2793489910162,8cyclictest378087-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:57:272
2793399910179,14cyclictest461112-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:05:480
2793399910148,31cyclictest541539-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:01:140
2793399910148,31cyclictest541539-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:01:140
2793639910094,3cyclictest0-21swapper/522:46:585
2793399910080,15cyclictest327633-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:18:530
2793399910077,14cyclictest303804-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:30:410
2793399910076,15cyclictest561287-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:26:230
2793399910053,28cyclictest0-21swapper/020:10:240
279348999969,9cyclictest435561-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:00:392
279348999969,9cyclictest435561-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:00:382
279344999986,6cyclictest378087-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:06:501
27933999991,78cyclictest0-21swapper/023:27:050
279339999876,14cyclictest282944-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:23:380
279363999792,2cyclictest0-21swapper/519:15:345
279339999776,14cyclictest561287-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:22:330
279339999768,20cyclictest69050irq/528-eth0-Tx22:29:110
279339999766,21cyclictest68950irq/527-eth0-Tx22:18:440
279339999756,31cyclictest69050irq/528-eth0-Tx00:15:360
279339999743,31cyclictest0-21swapper/000:33:470
279339999673,15cyclictest370269-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:24:160
279339999672,15cyclictest279676-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:10:250
279339999659,25cyclictest361907-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:37:030
279339999659,25cyclictest361907-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:37:020
279339999656,37cyclictest483317-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:18:150
279339999655,38cyclictest502298-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:24:250
27933999961,75cyclictest0-21swapper/023:40:430
279339999574,14cyclictest513718-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:45:200
279339999571,16cyclictest442436-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:40:260
279339999550,28cyclictest0-21swapper/021:45:410
279344999470,6cyclictest513718-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:45:341
279339999470,16cyclictest325502-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:04:550
279339999459,21cyclictest0-21swapper/020:50:330
279348999380,7cyclictest502298-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:37:082
279344999357,8cyclictest442436-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:42:041
279339999371,15cyclictest370269-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:55:140
279339999361,22cyclictest68950irq/527-eth0-Tx19:50:270
279339999361,22cyclictest68950irq/527-eth0-Tx19:50:260
279348999278,7cyclictest449889-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:45:112
279348999278,7cyclictest321423-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:56:352
279348999262,7cyclictest327633-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:19:342
279339999251,27cyclictest0-21swapper/020:35:270
279348999077,7cyclictest370269-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:31:012
279348999076,7cyclictest561287-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:38:432
279339999073,14cyclictest306500-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:22:200
279339999066,16cyclictest502298-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:30:120
279339999066,12cyclictest0-21swapper/020:45:230
279339999049,27cyclictest0-21swapper/019:35:000
279344998975,7cyclictest279676-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:39:421
279339998966,15cyclictest533423-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:36:230
279348998874,7cyclictest370269-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:55:022
279348998863,9cyclictest583999-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:28:172
279344998873,8cyclictest378087-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:30:321
279344998873,8cyclictest378087-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:19:541
279339998867,16cyclictest303804-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:25:430
279348998773,7cyclictest483317-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:25:352
279348998773,7cyclictest461112-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:56:422
279348998754,8cyclictest370269-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:20:542
279344998774,6cyclictest483317-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:25:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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