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2026-02-06 - 09:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Fri Feb 06, 2026 00:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
250421221350,6sleep20-21swapper/222:57:522
250421221350,6sleep20-21swapper/222:57:512
232243699124111,7cyclictest2522731-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:12:422
232243099123107,8cyclictest2448326-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:27:351
2322425991192,91cyclictest2372010-21ssh21:10:270
23224259911818,59cyclictest2563836-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:55:180
232243699116103,6cyclictest2529519-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:22:442
232244699115101,8cyclictest2423268-21ssh21:52:274
232244699115101,8cyclictest2423268-21ssh21:52:274
23224309911594,8cyclictest2376912-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:37:261
2322425991151,4cyclictest0-21swapper/020:55:250
23224259911426,48cyclictest69050irq/528-eth0-Tx21:35:290
23224369910985,9cyclictest2609139-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:27:542
23224309910996,6cyclictest2599068-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:22:531
23224309910996,6cyclictest2599068-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:22:521
23224369910693,6cyclictest2357757-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:22:212
23224309910492,6cyclictest2538595-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:27:441
23224309910492,6cyclictest2538595-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:27:441
23224309910382,8cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:22:351
23224469910295,2cyclictest0-21swapper/423:52:484
2322425991004,67cyclictest2495161-21kworker/u12:1+rpciod@
rpc_async_schedule
22:55:290
2322425991004,67cyclictest2495161-21kworker/u12:1+rpciod@
rpc_async_schedule
22:55:290
2322436999969,7cyclictest2609139-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:38:342
2322425999931,60cyclictest2355116-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:30:350
2322425999931,60cyclictest2355116-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:30:350
232242599992,6cyclictest2625885-21munin-run00:35:010
232242599981,80cyclictest2506640-21ssh23:00:040
232242599981,80cyclictest2506640-21ssh23:00:040
232242599981,70cyclictest0-21swapper/022:24:500
2322430999785,6cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:37:371
232242599961,62cyclictest0-21swapper/022:31:390
2322441999472,9cyclictest2480083-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:40:533
2322441999472,9cyclictest2480083-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:40:523
2322436999480,7cyclictest2372806-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:11:352
2322430999480,7cyclictest2336419-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
20:02:101
2322430999480,7cyclictest2336419-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
20:02:101
2322425999458,7cyclictest2348491-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:15:370
2322425999372,7cyclictest2448326-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:17:340
2322425999353,14cyclictest0-21swapper/021:45:400
232242599932,73cyclictest0-21swapper/022:07:310
232242599931,81cyclictest0-21swapper/022:39:360
232242599931,72cyclictest2353414-21if_eth120:25:230
2322425999271,9cyclictest69050irq/528-eth0-Tx20:35:230
2322425999268,13cyclictest68950irq/527-eth0-Tx23:07:410
2322425999263,17cyclictest69050irq/528-eth0-Tx20:20:210
232242599921,3cyclictest0-21swapper/023:28:230
232242599921,3cyclictest0-21swapper/023:28:220
2322446999177,8cyclictest2468047-21ssh22:28:154
2322441999178,6cyclictest2623575-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:32:533
2322436999177,7cyclictest2563836-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:30:162
2322425999173,4cyclictest68950irq/527-eth0-Tx20:50:430
2322425999170,5cyclictest68950irq/527-eth0-Tx22:00:200
232242599911,79cyclictest0-21swapper/023:39:050
232242599911,75cyclictest0-21swapper/021:25:100
232242599911,73cyclictest2565755-21users23:45:490
2322446998982,4cyclictest0-21swapper/419:42:074
2322430998876,6cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:26:341
2322430998874,7cyclictest2357757-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:45:341
2322430998874,7cyclictest2357757-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:45:341
2322425998870,4cyclictest69050irq/528-eth0-Tx20:40:150
2322425998854,18cyclictest0-21swapper/023:10:300
232242599881,75cyclictest2421385-21chrt21:50:430
232242599881,75cyclictest2421385-21chrt21:50:420
232242599881,72cyclictest2362888-21cat20:50:010
232242599881,72cyclictest2362888-21cat20:50:010
2322430998773,7cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:55:231
2322430998773,7cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:55:231
2322430998773,7cyclictest2355116-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:33:341
2322430998773,7cyclictest2355116-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:33:341
232242599872,71cyclictest2326677-21/usr/sbin/munin19:20:450
232242599871,74cyclictest15-21rcuc/020:10:410
2322446998679,3cyclictest0-21swapper/422:51:364
2322446998679,3cyclictest0-21swapper/422:51:354
2322436998672,7cyclictest2348491-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:15:352
2322436998664,6cyclictest2585773-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:07:232
2322430998674,6cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:43:341
2322430998672,7cyclictest2352327-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:41:451
2322425998659,17cyclictest68950irq/527-eth0-Tx21:30:400
2322425998659,14cyclictest0-21swapper/021:55:190
2322425998659,14cyclictest0-21swapper/021:55:180
2322425998658,14cyclictest0-21swapper/019:45:380
2322425998654,17cyclictest0-21swapper/000:09:000
232242599862,70cyclictest0-21swapper/019:40:330
232242599861,70cyclictest2370854-21diskmemload00:00:430
232242599861,62cyclictest0-21swapper/022:49:500
2322446998577,4cyclictest0-21swapper/419:47:074
2322436998573,6cyclictest2395375-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:31:452
2322430998571,7cyclictest2522731-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:34:211
2322430998571,7cyclictest2522731-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:34:211
2322430998571,7cyclictest2495161-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:57:381
2322430998571,7cyclictest2495161-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:57:381
2322430998571,7cyclictest2324323-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:17:071
2322430998562,9cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:32:351
2322430998559,9cyclictest2434442-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:06:181
2322425998555,20cyclictest68950irq/527-eth0-Tx19:25:150
2322425998555,20cyclictest68950irq/527-eth0-Tx19:25:150
232242599851,63cyclictest2370854-21diskmemload21:42:120
2322436998471,6cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:11:352
2322430998472,6cyclictest2386684-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:47:271
2322430998471,7cyclictest2434442-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:16:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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