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2026-05-02 - 06:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Sat May 02, 2026 00:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2712881235683554,9sleep50-21swapper/519:09:065
2712881235683554,9sleep50-21swapper/519:09:055
2712000214671450,7sleep12684955-21kworker/1:0+events@
dbs_work_handler
19:05:281
2712000214671450,7sleep12684955-21kworker/1:0+events@
dbs_work_handler
19:05:281
271312899130118,6cyclictest2743354-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:21:543
271312899120106,7cyclictest2936317-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:47:023
271311799118104,7cyclictest2724983-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:41:511
27131129911734,49cyclictest2921813-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:29:050
27131129911734,49cyclictest2921813-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:29:050
27131129911577,12cyclictest69050irq/528-eth0-Tx00:10:330
27131289911096,7cyclictest2745530-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:45:353
27131289910185,8cyclictest2972298-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:05:333
27131129910178,16cyclictest2743366-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
20:28:240
28089952980,7sleep00-21swapper/021:48:460
271311299962,88cyclictest2823192-21/usr/sbin/munin22:00:160
2713112999546,18cyclictest2782253-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:28:570
2713112999546,18cyclictest2782253-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:28:560
271311299951,79cyclictest0-21swapper/021:35:330
271311299951,79cyclictest0-21swapper/021:35:320
2713112999481,4cyclictest69050irq/528-eth0-Tx22:51:450
2713112999469,15cyclictest69150irq/529-eth0-Tx20:05:280
2713112999375,4cyclictest69050irq/528-eth0-Tx23:00:210
2713112999368,15cyclictest68950irq/527-eth0-Tx21:57:480
271311299931,80cyclictest0-21swapper/022:55:250
2713112999268,15cyclictest68950irq/527-eth0-Tx00:22:130
2713112999268,15cyclictest68950irq/527-eth0-Tx00:22:130
2713112999268,12cyclictest68950irq/527-eth0-Tx20:10:320
2713112999267,15cyclictest68950irq/527-eth0-Tx23:44:070
2713112999266,16cyclictest69050irq/528-eth0-Tx22:31:390
2713112999266,16cyclictest69050irq/528-eth0-Tx22:31:380
2713112999261,14cyclictest0-21swapper/019:25:360
2713112999261,14cyclictest0-21swapper/019:25:360
2713112999171,5cyclictest2754740-21memory20:50:230
2713112999072,4cyclictest69150irq/529-eth0-Tx00:15:400
2713112999069,9cyclictest69050irq/528-eth0-Tx23:11:040
2713112998971,4cyclictest0-21swapper/019:17:230
271311299891,76cyclictest0-21swapper/019:20:350
2713112998870,4cyclictest69050irq/528-eth0-Tx23:45:150
2713112998867,6cyclictest2770597-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:18:170
2713112998865,12cyclictest69050irq/528-eth0-Tx23:30:150
2713112998864,15cyclictest69050irq/528-eth0-Tx00:37:290
2713112998864,15cyclictest69050irq/528-eth0-Tx00:37:290
2713112998863,6cyclictest2760850-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:50:080
2713112998762,4cyclictest0-21swapper/000:35:010
271311299872,70cyclictest0-21swapper/022:40:110
271311299872,70cyclictest0-21swapper/022:40:110
2713112998667,4cyclictest68950irq/527-eth0-Tx22:06:490
2713117998571,7cyclictest2915475-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:22:231
2713117998571,7cyclictest2915475-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:22:231
2713112998567,4cyclictest69150irq/529-eth0-Tx23:23:530
2713112998567,4cyclictest69150irq/529-eth0-Tx23:23:530
2713112998564,4cyclictest69050irq/528-eth0-Tx20:45:380
2713112998548,18cyclictest0-21swapper/000:00:360
271311299851,69cyclictest0-21swapper/019:35:330
2713112998467,3cyclictest0-21swapper/023:19:350
2713112998463,4cyclictest69050irq/528-eth0-Tx20:30:310
2713112998462,4cyclictest68950irq/527-eth0-Tx22:14:020
2713112998459,4cyclictest69150irq/529-eth0-Tx00:05:190
2713112998456,14cyclictest0-21swapper/020:40:300
2713112998445,15cyclictest0-21swapper/021:40:050
2713112998365,4cyclictest0-21swapper/022:20:290
2713112998362,4cyclictest69050irq/528-eth0-Tx21:30:440
2713112998362,4cyclictest69050irq/528-eth0-Tx21:30:440
2713112998356,3cyclictest0-21swapper/022:45:320
271311299833,6cyclictest2727289-21cat19:45:000
271311299832,3cyclictest0-21swapper/020:00:380
2713128998266,8cyclictest2980742-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:25:363
2713128998266,8cyclictest2980742-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:25:363
2713117998268,7cyclictest2729078-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
19:55:251
2713117998257,9cyclictest2885171-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:50:351
2713112998268,3cyclictest0-21swapper/021:00:320
2713112998261,3cyclictest0-21swapper/020:20:310
271311299821,5cyclictest2867467-21ssh22:35:280
2713132998167,7cyclictest2765252-21diskmemload-423:26:544
2713132998167,7cyclictest2765252-21diskmemload-423:26:534
2713128998167,7cyclictest2929109-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:37:233
2713123998170,5cyclictest2849916-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:35:112
2713123998167,7cyclictest2713707-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:31:502
2713112998152,13cyclictest0-21swapper/019:55:370
2713112998148,17cyclictest0-21swapper/019:49:540
2713112998146,15cyclictest0-21swapper/021:20:310
271311299811,4cyclictest0-21swapper/021:10:430
2713128998067,6cyclictest2865448-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:17:233
2713128998054,8cyclictest2814465-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:41:383
2713128998054,8cyclictest2814465-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:41:373
2713123998067,6cyclictest2760850-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:30:342
2713123998067,6cyclictest2760850-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:30:332
2713123998047,8cyclictest2980742-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:20:452
2713123998047,8cyclictest2980742-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:20:452
2713112998065,4cyclictest69050irq/528-eth0-Tx20:55:370
2713112998065,4cyclictest69050irq/528-eth0-Tx20:55:360
2713112998054,16cyclictest68950irq/527-eth0-Tx23:50:170
2713112998054,16cyclictest68950irq/527-eth0-Tx23:50:170
271311299801,53cyclictest2945609-21ssh23:38:210
2713117997965,6cyclictest2729078-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
19:53:281
2713117997965,6cyclictest2729078-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
19:53:271
2713117997950,7cyclictest2823126-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:33:461
2713117997950,7cyclictest2823126-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:33:451
2713112997949,15cyclictest0-21swapper/022:15:270
2713112997949,15cyclictest0-21swapper/022:15:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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