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2026-02-09 - 09:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Mon Feb 09, 2026 00:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1148943232573238,10sleep50-21swapper/519:05:405
1148943232573238,10sleep50-21swapper/519:05:395
11496449916384,44cyclictest1431584-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:23:380
11496449911380,21cyclictest69150irq/529-eth0-Tx00:30:360
11496449910962,18cyclictest0-21swapper/023:02:520
11496449910941,21cyclictest0-21swapper/023:07:400
11496449910866,16cyclictest0-21swapper/023:45:420
11496449910866,16cyclictest0-21swapper/023:45:420
1149644991061,81cyclictest0-21swapper/019:40:430
1149644991061,81cyclictest0-21swapper/019:40:420
11496479910484,7cyclictest1396123-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:05:341
11496649910396,3cyclictest0-21swapper/522:42:345
1149644991011,77cyclictest0-21swapper/020:12:090
1149644991011,77cyclictest0-21swapper/020:12:080
1149644991011,60cyclictest0-21swapper/020:35:410
1149647999077,6cyclictest1342556-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:12:561
1149644998767,6cyclictest1190402-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:25:520
1149644998757,7cyclictest1159609-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:50:360
114964499871,76cyclictest0-21swapper/020:20:190
114964499871,76cyclictest0-21swapper/020:00:190
13121062860,5sleep10-21swapper/122:41:271
1149664998681,2cyclictest0-21swapper/500:25:355
1149664998681,2cyclictest0-21swapper/500:25:345
1149656998674,6cyclictest1279302-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:27:343
1149656998674,6cyclictest1279302-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:27:333
114964499861,73cyclictest0-21swapper/022:30:170
114964499861,73cyclictest0-21swapper/021:35:350
12042732850,5sleep30-21swapper/321:15:413
12042732850,5sleep30-21swapper/321:15:413
114964499851,70cyclictest0-21swapper/021:59:570
114964499851,68cyclictest1428558-21/usr/sbin/munin00:15:230
1149644998512,37cyclictest0-21swapper/023:25:310
1149644998467,4cyclictest68950irq/527-eth0-Tx22:21:450
114964499841,71cyclictest0-21swapper/019:25:350
1149664998375,4cyclictest0-21swapper/521:32:025
1149652998366,8cyclictest1431584-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:23:362
1149644998362,7cyclictest1252335-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:06:390
1149644998359,15cyclictest68950irq/527-eth0-Tx21:41:570
114964499831,78cyclictest0-21swapper/020:40:350
114964499831,68cyclictest0-21swapper/019:35:350
114964499831,67cyclictest0-21swapper/019:45:280
1149664998276,3cyclictest0-21swapper/519:45:345
1149652998267,7cyclictest1194598-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:35:352
1149644998265,4cyclictest69050irq/528-eth0-Tx22:51:540
1149644998256,14cyclictest0-21swapper/000:36:030
114964499821,68cyclictest0-21swapper/020:55:370
1149664998174,3cyclictest0-21swapper/520:55:255
1149656998168,7cyclictest1423953-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:16:003
1149644998161,7cyclictest1190402-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:03:350
1149644998144,19cyclictest0-21swapper/020:05:340
114964499812,66cyclictest0-21swapper/022:12:150
114964499811,67cyclictest0-21swapper/023:41:400
114964499811,66cyclictest1330852-21taskset22:56:420
1149664998072,4cyclictest0-21swapper/523:11:015
1149656998067,7cyclictest1320796-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:20:493
1149647998056,8cyclictest1207807-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:27:191
114964499801,67cyclictest0-21swapper/022:47:420
1149664997972,3cyclictest0-21swapper/521:49:355
1149664997972,3cyclictest0-21swapper/519:20:385
1149661997960,14cyclictest1243880-21chrt21:47:144
1149647997966,7cyclictest1159609-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:12:561
1149647997966,7cyclictest1159609-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:12:561
1149644997960,4cyclictest68950irq/527-eth0-Tx23:31:480
1149644997955,15cyclictest69050irq/528-eth0-Tx21:50:060
1149644997955,15cyclictest69050irq/528-eth0-Tx21:20:230
1149644997955,15cyclictest69050irq/528-eth0-Tx21:20:230
1149644997924,38cyclictest0-21swapper/022:35:190
114964499791,65cyclictest0-21swapper/023:20:280
114964499791,56cyclictest0-21swapper/023:35:130
1149664997873,2cyclictest0-21swapper/521:52:255
114964499787,68cyclictest14250irq/98-imx_mu_c22:00:410
114964499787,68cyclictest14250irq/98-imx_mu_c22:00:400
114964499784,50cyclictest1208970-21latency_hist21:20:010
114964499784,50cyclictest1208970-21latency_hist21:20:010
114964499781,64cyclictest0-21swapper/022:26:550
114964499781,64cyclictest0-21swapper/022:26:550
114964499781,55cyclictest0-21swapper/023:50:090
114964499781,55cyclictest0-21swapper/023:50:080
1149664997772,2cyclictest0-21swapper/521:35:395
1149661997772,2cyclictest0-21swapper/420:48:294
1149644997755,14cyclictest69050irq/528-eth0-Tx21:32:210
114964499771,73cyclictest0-21swapper/023:55:360
114964499771,51cyclictest0-21swapper/019:55:360
114964499771,51cyclictest0-21swapper/019:55:360
1149664997670,3cyclictest0-21swapper/500:05:065
1149661997667,5cyclictest1368610-21ssh23:26:564
1149652997665,5cyclictest1149387-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:23:482
1149644997654,5cyclictest1201117-21ssh21:13:050
1149644997650,14cyclictest68950irq/527-eth0-Tx00:25:190
1149644997650,14cyclictest68950irq/527-eth0-Tx00:25:180
1149644997637,15cyclictest0-21swapper/000:03:490
114964499762,55cyclictest1418745-21ssh00:07:080
1149656997562,6cyclictest1155367-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
19:26:563
1149656997561,7cyclictest1252335-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:02:453
1149656997561,7cyclictest1252335-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:02:453
1149652997561,7cyclictest1396123-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:25:062
1149652997561,7cyclictest1396123-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:25:062
1149644997560,4cyclictest69050irq/528-eth0-Tx19:15:100
1149644997544,16cyclictest0-21swapper/020:25:020
114964499752,60cyclictest1166714-21ntpq19:50:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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