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2026-02-05 - 09:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Thu Feb 05, 2026 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4084426231613133,9sleep34079088-21kworker/3:3+events@
dbs_work_handler
19:05:253
40854002382357,15sleep40-21swapper/419:09:304
408560199154129,6cyclictest44357-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:35:580
408560199124111,6cyclictest4113708-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:20:320
40856019911869,42cyclictest107130-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:44:410
40856069910995,7cyclictest36618-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:45:581
40856019910859,29cyclictest25535-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:33:320
40856019910773,27cyclictest60041-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:54:390
40856019910555,31cyclictest4134233-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:11:350
40856189910490,7cyclictest4099604-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:29:343
40856189910490,7cyclictest4099604-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:29:343
4084254210486,7sleep14064307-21kworker/1:0+events@
dbs_work_handler
19:05:231
40856019910363,16cyclictest25535-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:24:380
4085601991033,60cyclictest36618-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:40:400
40856019910149,29cyclictest97116-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:29:340
40856019910127,57cyclictest4088637-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:19:030
40856019910127,57cyclictest4088637-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:19:020
40856069910086,7cyclictest44357-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:00:561
40856069910086,7cyclictest44357-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:00:551
40856019910064,13cyclictest4192311-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:02:440
40856019910064,13cyclictest4192311-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:02:430
4085618999985,7cyclictest4097541-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:40:223
4085601999985,7cyclictest4137644-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:30:580
4085601999959,33cyclictest87512-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:52:170
4085622999886,7cyclictest4174201-21ssh21:42:384
4085622999784,7cyclictest4137554-21diskmemload-400:06:244
4085622999784,7cyclictest4137554-21diskmemload-400:06:244
4085606999783,7cyclictest4117887-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:35:351
4085622999690,3cyclictest0-21swapper/400:17:034
4085601999684,6cyclictest154652-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:37:550
4085601999684,6cyclictest154652-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:37:540
4085601999682,7cyclictest44357-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:46:320
4085601999669,14cyclictest68950irq/527-eth0-Tx23:35:000
4085601999567,7cyclictest76114-21cat23:00:010
4085622999488,3cyclictest0-21swapper/421:01:344
4085601999481,6cyclictest4091319-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:33:350
4085601999468,14cyclictest69150irq/529-eth0-Tx22:15:010
4085627999388,2cyclictest0-21swapper/521:50:505
4085606999380,6cyclictest4166303-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:10:521
4085627999287,2cyclictest0-21swapper/521:29:355
4085627999287,2cyclictest0-21swapper/521:29:345
4085622999286,3cyclictest0-21swapper/423:26:014
408560199921,81cyclictest174118-21idleruntime-cro00:20:000
4085627999186,2cyclictest0-21swapper/523:38:015
4085627999186,2cyclictest0-21swapper/523:38:005
4085627999185,3cyclictest0-21swapper/521:15:415
408560199912,70cyclictest0-21swapper/000:07:130
408560199912,70cyclictest0-21swapper/000:07:120
4085627999083,3cyclictest0-21swapper/523:07:065
4085622999076,8cyclictest140882-21ssh23:51:544
4085601999076,7cyclictest107130-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:45:070
4085601999061,20cyclictest68950irq/527-eth0-Tx20:50:000
4085601999057,26cyclictest4132045-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:05:130
4085622998983,3cyclictest0-21swapper/423:14:344
4085606998976,7cyclictest4083273-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:20:141
4085601998979,7cyclictest4126453-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:36:440
4085601998960,7cyclictest97116-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:37:060
4085601998960,7cyclictest97116-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:37:050
4085601998937,44cyclictest4134233-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:24:280
4085601998937,44cyclictest4134233-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:24:270
744002880,5sleep44137554-21diskmemload-422:58:144
4085622998875,6cyclictest0-21swapper/421:34:264
4085611998874,7cyclictest4134233-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:20:422
4085611998874,7cyclictest4134233-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:20:422
4085601998874,7cyclictest44357-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:01:020
4085601998874,7cyclictest44357-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:01:010
4085601998868,4cyclictest69150irq/529-eth0-Tx21:25:360
4085601998868,4cyclictest69150irq/529-eth0-Tx21:25:360
4085627998782,2cyclictest0-21swapper/521:45:525
4085627998780,4cyclictest0-21swapper/520:50:005
4085606998773,7cyclictest4126453-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:05:391
4085601998775,6cyclictest4174716-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:49:000
4085606998663,8cyclictest25535-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:30:001
4085601998660,18cyclictest179009-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:30:530
4085601998660,18cyclictest179009-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:30:530
4085601998573,6cyclictest4108217-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
20:10:070
4085601998573,6cyclictest4108217-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
20:10:070
4085627998479,2cyclictest0-21swapper/500:30:535
4085627998479,2cyclictest0-21swapper/500:30:535
4085606998468,8cyclictest4166303-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:50:371
4085601998476,6cyclictest4174716-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:44:520
4085601998473,5cyclictest4081152-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:13:320
4085627998378,2cyclictest0-21swapper/523:40:585
4085622998377,3cyclictest0-21swapper/419:11:354
4085622998371,7cyclictest4150723-21ssh21:24:274
4085622998371,7cyclictest4150723-21ssh21:24:274
4085627998277,2cyclictest0-21swapper/523:52:405
4085627998275,3cyclictest0-21swapper/520:35:405
4085601998248,17cyclictest0-21swapper/022:25:390
4085627998176,2cyclictest0-21swapper/523:18:385
4085627998175,3cyclictest0-21swapper/523:46:145
4085622998175,3cyclictest0-21swapper/421:45:354
4085618998167,7cyclictest107130-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:38:253
4085618998167,7cyclictest107130-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:38:243
4085606998167,7cyclictest87512-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:31:341
4085606998145,8cyclictest4137644-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:28:231
4085606998145,8cyclictest4137644-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:28:231
4085601998173,6cyclictest4126453-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:03:350
4085601998167,7cyclictest4126453-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:15:410
4085622998067,7cyclictest4151587-21ssh21:25:044
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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