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2026-01-29 - 07:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack3slot4.osadl.org (updated Thu Jan 29, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3947529232463227,8sleep23944259-21kworker/2:2+events@
dbs_work_handler
19:05:342
3948523991434,70cyclictest4004944-21kworker/u12:3+rpciod@
rpc_async_schedule
21:45:200
39485239911930,52cyclictest69150irq/529-eth0-Tx00:35:360
404490721170,3sleep336-21rcuc/321:48:523
39485239911631,52cyclictest4134955-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:14:480
39485239911621,46cyclictest4004944-21kworker/u12:3+rpciod@
rpc_async_schedule
21:40:140
39485239911621,46cyclictest4004944-21kworker/u12:3+rpciod@
rpc_async_schedule
21:40:140
39485239910912,56cyclictest4075378-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:40:090
39485239910734,54cyclictest69050irq/528-eth0-Tx23:00:440
3948523991061,95cyclictest0-21swapper/000:20:340
3948523991051,89cyclictest0-21swapper/020:10:530
3948523991051,89cyclictest0-21swapper/020:10:530
3948523991032,82cyclictest0-21swapper/020:26:550
39485239910276,18cyclictest3988755-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:46:060
3948523991022,69cyclictest5198-21grep23:50:430
3948523991021,91cyclictest4084902-21memory22:20:250
3948523991001,87cyclictest0-21swapper/021:25:150
3948523991001,82cyclictest12325-21ssh23:56:440
3948523991001,78cyclictest0-21swapper/000:12:240
39485239910016,68cyclictest4129300-21ntpq22:55:410
3948544999891,3cyclictest0-21swapper/423:36:394
3948528999884,7cyclictest17936-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:28:351
394852399982,85cyclictest0-21swapper/020:01:560
394852399981,85cyclictest0-21swapper/019:33:310
394852399981,85cyclictest0-21swapper/019:33:310
394852399981,78cyclictest0-21swapper/020:55:200
3948523999817,57cyclictest4058211-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:14:470
3948523999817,57cyclictest4058211-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:14:470
3948523999765,23cyclictest68950irq/527-eth0-Tx20:50:340
394852399972,89cyclictest0-21swapper/019:55:250
3948523999664,22cyclictest68950irq/527-eth0-Tx00:01:220
394852399962,81cyclictest3997216-21diskmemload23:35:050
394852399962,78cyclictest0-21swapper/021:20:430
394852399962,76cyclictest4002058-21/usr/sbin/munin21:15:420
3948523999621,54cyclictest69250irq/530-eth0-Tx23:25:220
394852399961,90cyclictest0-21swapper/021:05:310
3948523999550,24cyclictest0-21swapper/021:30:350
394852399954,80cyclictest69250irq/530-eth0-Tx22:05:590
394852399954,80cyclictest69250irq/530-eth0-Tx22:05:590
394852399952,79cyclictest0-21swapper/020:07:230
394852399951,79cyclictest0-21swapper/021:35:310
394852399942,77cyclictest0-21swapper/019:35:220
394852399942,76cyclictest0-21swapper/019:13:400
394852399942,6cyclictest3999927-21ssh21:12:250
394852399942,6cyclictest3999927-21ssh21:12:240
394852399942,5cyclictest3963081-21aten2_r3power_c19:45:140
394852399941,81cyclictest0-21swapper/022:32:590
394852399941,77cyclictest0-21swapper/021:56:030
394852399941,74cyclictest0-21swapper/023:46:420
394852399933,58cyclictest4050067-21kworker/u12:0+rpciod@
rpc_async_schedule
22:45:080
394852399931,79cyclictest0-21swapper/020:30:120
3948523999231,39cyclictest4050067-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:37:220
394852399922,74cyclictest0-21swapper/023:41:240
394852399922,74cyclictest0-21swapper/023:41:240
394852399922,74cyclictest0-21swapper/019:21:130
394852399921,80cyclictest0-21swapper/019:19:260
394852399921,78cyclictest0-21swapper/021:00:330
394852399921,77cyclictest0-21swapper/022:16:050
394852399921,77cyclictest0-21swapper/022:16:050
394852399921,72cyclictest0-21swapper/020:35:310
394852399921,71cyclictest0-21swapper/023:30:310
394852399921,71cyclictest0-21swapper/023:30:310
394852399916,71cyclictest0-21swapper/000:30:460
3948523999167,16cyclictest3974813-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:16:020
394852399915,71cyclictest68950irq/527-eth0-Tx23:15:300
394852399911,79cyclictest0-21swapper/023:24:240
394852399911,64cyclictest0-21swapper/000:05:460
394852399911,4cyclictest0-21swapper/019:40:370
3948523999058,22cyclictest69150irq/529-eth0-Tx22:01:490
394852399902,83cyclictest0-21swapper/000:28:590
394852399901,68cyclictest0-21swapper/022:26:170
394852399901,41cyclictest0-21swapper/023:09:040
3948528998975,6cyclictest4134955-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:16:351
3948523998959,21cyclictest0-21swapper/020:42:500
394852399892,69cyclictest35369-21/usr/sbin/munin00:15:230
394852399892,69cyclictest35369-21/usr/sbin/munin00:15:220
3948528998873,7cyclictest4075378-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:47:351
3948539998773,7cyclictest4134955-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:35:033
3948528998672,7cyclictest4050067-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:36:271
394852399864,64cyclictest0-21swapper/021:50:270
394852399851,5cyclictest0-21swapper/019:50:260
3948523998511,58cyclictest0-21swapper/022:50:410
3948523998511,58cyclictest0-21swapper/022:50:410
394852399842,64cyclictest0-21swapper/019:25:150
39494172830,3sleep13949420-21head19:10:241
3948523998241,25cyclictest0-21swapper/020:21:330
40402302810,6sleep20-21swapper/221:45:132
3948528998168,7cyclictest3986164-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:26:111
3948528998049,10cyclictest4119889-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:08:211
3948544997966,7cyclictest4000636-21diskmemload-400:03:214
40953122780,6sleep50-21swapper/522:28:555
40783732780,3sleep40-21swapper/422:15:224
40783732780,3sleep40-21swapper/422:15:224
3948544997872,3cyclictest0-21swapper/421:10:434
3948544997872,3cyclictest0-21swapper/421:10:434
3948535997863,8cyclictest4050067-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:41:292
3948544997771,3cyclictest0-21swapper/422:27:334
3948535997765,6cyclictest4126685-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:21:352
3948544997670,3cyclictest0-21swapper/423:30:054
3948544997670,3cyclictest0-21swapper/423:30:054
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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