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2026-02-17 - 11:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Tue Feb 17, 2026 00:46:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3619170218961871,15sleep40-21swapper/419:09:284
36193709916994,40cyclictest3861861-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:13:010
361937999131117,7cyclictest3718843-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:52:392
361937999131117,7cyclictest3718843-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:52:382
361938799119112,3cyclictest0-21swapper/422:02:384
36193709911951,60cyclictest3668125-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:40:420
361939299117112,2cyclictest0-21swapper/522:02:395
36193849911097,7cyclictest3902362-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:18:023
36193799911096,7cyclictest3861861-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:08:002
36193799910795,6cyclictest3695447-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:57:372
36193799910794,7cyclictest3885293-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:23:012
36193799910794,7cyclictest3643353-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:27:272
36193709910631,36cyclictest3780877-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:04:350
36193799910390,6cyclictest3732162-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:57:482
36193849910265,9cyclictest3743195-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:12:433
37903302980,6sleep048-21rcuop/422:48:340
3619370999822,56cyclictest3918068-21/usr/sbin/munin00:30:220
37194912970,5sleep10-21swapper/121:51:361
37194912970,5sleep10-21swapper/121:51:351
3619379999682,7cyclictest3732162-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:06:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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