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2026-04-10 - 16:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Fri Apr 10, 2026 12:46:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10879349914065,47cyclictest1124489-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:50:510
108794799117103,7cyclictest1136006-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:10:123
10879349911647,17cyclictest1124489-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:25:340
10879349911485,21cyclictest1125100-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
08:40:290
10879479910995,8cyclictest1279979-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:20:383
10879349910862,39cyclictest1172318-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:00:290
10879479910792,8cyclictest1290623-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:35:393
10879349910757,42cyclictest1327562-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:40:160
108795299106101,3cyclictest0-21swapper/408:20:024
10879349910653,31cyclictest1209626-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:16:480
10879349910467,22cyclictest1172318-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:08:140
10879349910464,16cyclictest1138267-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:11:130
10879529910397,3cyclictest0-21swapper/409:05:104
10879349910354,26cyclictest1154399-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:28:480
10879349910269,19cyclictest1261399-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:09:340
10879349910241,45cyclictest69150irq/529-eth0-Tx08:25:200
10879349910235,43cyclictest1124489-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:45:230
10879479910086,7cyclictest1290623-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:23:353
10879479910086,7cyclictest1290623-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:23:343
1087938999987,6cyclictest1172318-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:41:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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