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2025-11-11 - 12:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Tue Nov 11, 2025 00:46:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1654173232713252,6sleep21646891-21kworker/2:3+events@
dbs_work_handler
19:05:272
1653810224152394,13sleep11653078-21kworker/1:3+events@
dbs_work_handler
19:05:211
16548122980970,5sleep50-21swapper/519:06:075
184586721550,3sleep21845868-21ssh23:09:502
165528099135121,7cyclictest1899060-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:58:522
165528099135121,7cyclictest1899060-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:58:522
165528099135121,7cyclictest1862139-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:29:042
165527299133109,21cyclictest1672912-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:58:000
165528099129116,6cyclictest1725608-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:53:272
16552729912397,19cyclictest1701344-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:38:260
165527999117103,7cyclictest1862139-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:34:061
165527999117103,7cyclictest1862139-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:34:051
191769721130,13sleep230-21ksoftirqd/200:08:362
1655272991131,95cyclictest0-21swapper/022:25:170
16552809911096,7cyclictest1702764-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork
21:13:172
16552809911096,7cyclictest1702764-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork
21:13:172
1655272991102,27cyclictest1725608-21kworker/u12:0+rpciod@
rpc_async_schedule
21:50:010
1655272991099,48cyclictest0-21swapper/022:15:320
1655272991099,48cyclictest0-21swapper/022:15:320
16552729910983,19cyclictest1862139-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:38:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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