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2026-03-03 - 12:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Tue Mar 03, 2026 00:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
398076499146109,29cyclictest65756-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:08:090
398076499144108,28cyclictest4032187-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:47:520
39807649913061,37cyclictest4138424-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:51:320
39807649913061,37cyclictest4138424-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:51:310
39807649912980,29cyclictest9451-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:45:340
39807649912980,29cyclictest9451-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:45:340
398078099122110,6cyclictest4138424-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:23:043
39807649911341,15cyclictest68950irq/527-eth0-Tx22:05:210
39807649911136,41cyclictest4151375-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:10:080
398079099109101,4cyclictest0-21swapper/500:08:095
39807649910936,42cyclictest13-21ksoftirqd/023:30:070
39807649910744,45cyclictest13-21ksoftirqd/023:44:430
398079099105100,2cyclictest0-21swapper/521:47:525
39807849910498,3cyclictest0-21swapper/419:17:294
39807649910478,19cyclictest41424-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:00:220
39807649910338,15cyclictest13-21ksoftirqd/000:30:280
39807649910320,59cyclictest4026932-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:00:380
39807649910276,18cyclictest3989260-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:32:310
39807649910140,39cyclictest65756-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:38:260
39807649910138,46cyclictest69050irq/528-eth0-Tx22:20:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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