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2026-09-14 - 02:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Mon Sep 14, 2026 00:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
354844399121115,3cyclictest0-21swapper/521:32:275
35484199911158,39cyclictest3594806-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:32:270
35484289910893,7cyclictest3594806-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:17:502
35484199910464,25cyclictest3833188-21cut00:10:000
35484199910128,13cyclictest67550irq/529-eth0-Tx00:30:330
35484199910117,24cyclictest0-21swapper/023:06:030
3548428999783,6cyclictest3772273-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:32:552
3548419999633,16cyclictest3728885-21missed_timers22:50:230
38057582950,10sleep337-21ksoftirqd/323:49:013
38057582950,10sleep337-21ksoftirqd/323:49:003
3548419999531,14cyclictest67550irq/529-eth0-Tx22:00:010
3548419999530,13cyclictest67650irq/530-eth0-Tx22:20:180
3548419999519,23cyclictest67450irq/528-eth0-Tx23:55:420
3548424999481,6cyclictest3579146-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:27:121
3548443999387,3cyclictest0-21swapper/522:02:355
3548419999326,51cyclictest0-21swapper/000:00:360
3548419999325,23cyclictest3834922-21ssh00:10:430
354841999923,75cyclictest3562710-21latency_hist19:45:010
35951892910,4sleep30-21swapper/321:05:013
3548428999177,7cyclictest3661858-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:22:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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