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2026-01-28 - 12:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Wed Jan 28, 2026 00:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1555395216021592,5sleep50-21swapper/519:08:175
15554862821807,6sleep11534759-21kworker/1:0+events@
dbs_work_handler
19:09:321
155568899138124,7cyclictest1780798-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:47:272
155568899128114,7cyclictest1850164-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:37:372
15556789911937,67cyclictest1536030-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:11:420
155568899118103,7cyclictest1605286-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:32:002
15556789911866,44cyclictest1780798-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:23:350
1555678991171,75cyclictest1676368-21kworker/u12:1+rpciod@
rpc_async_schedule
22:25:380
163676621150,3sleep40-21swapper/421:36:404
155568899115101,7cyclictest1568244-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:41:532
15556789911218,62cyclictest1560058-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:38:410
15556829911096,7cyclictest1780798-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:57:311
15556789911084,19cyclictest1620322-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:42:020
1555678991101,74cyclictest176487150kworker/u13:1+xprtiod@
xs_stream_data_receive_workfn
23:20:550
15556939910896,6cyclictest1647625-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:12:073
1555678991082,88cyclictest1669710-21ssh22:03:120
1555678991082,88cyclictest1669710-21ssh22:03:120
1555678991082,71cyclictest1722836-21wc22:45:250
15556939910793,7cyclictest1850164-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:32:373
15556789910770,30cyclictest1787892-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:37:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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