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2026-03-25 - 01:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Tue Mar 24, 2026 12:46:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1813471235133487,17sleep50-21swapper/507:05:365
18144739914367,40cyclictest1856480-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:00:310
18144739913657,64cyclictest2038054-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:50:330
181447899126111,7cyclictest1930512-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:20:221
18144739912682,23cyclictest2073322-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:55:410
18144739912172,33cyclictest2065420-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:20:470
18144739912172,33cyclictest2065420-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:20:460
1814473991214,39cyclictest0-21swapper/011:30:260
181449199120106,8cyclictest2026331-21ssh11:16:144
18144739911970,36cyclictest1937231-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:10:060
18144739911969,21cyclictest2073322-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:38:040
204140521180,12sleep123-21ksoftirqd/111:28:251
18144739911682,26cyclictest1894003-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:40:130
18144789911590,8cyclictest1916901-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:55:171
18144879911499,8cyclictest1869928-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:59:353
18144739911384,26cyclictest2082718-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
12:10:410
18144739911384,26cyclictest2082718-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
12:10:410
18144739911255,49cyclictest2024550-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:21:070
18144879911097,6cyclictest1853014-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:15:063
18144879911097,6cyclictest1853014-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:15:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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