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2025-11-18 - 14:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Wed Nov 12, 2025 12:47:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
865614223612346,6sleep3838609-21kworker/3:1+events@
dbs_work_handler
07:05:263
8663472517496,10sleep2864316-21kworker/2:0+events@
dbs_work_handler
07:06:382
866764991372,117cyclictest968718-21cron09:55:000
8667649913497,30cyclictest1017669-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:50:460
86676499133102,24cyclictest1088079-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:30:520
8667649913227,35cyclictest64250irq/527-eth0-Tx09:45:110
86678699128123,2cyclictest0-21swapper/509:20:285
8667649912892,27cyclictest902904-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
08:50:230
8667649912892,27cyclictest902904-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
08:50:220
8667649912473,41cyclictest64250irq/527-eth0-Tx11:55:210
8667649912473,41cyclictest64250irq/527-eth0-Tx11:55:210
8667649912290,24cyclictest1088079-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:35:540
8667649912290,24cyclictest1088079-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:35:540
8667649912167,25cyclictest946537-21sshd09:36:390
8667649912084,28cyclictest864749-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
07:20:060
866764991192,72cyclictest0-21swapper/008:30:010
8667649911786,24cyclictest1073371-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:20:490
8667649911684,24cyclictest1109203-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:50:550
8667649911684,24cyclictest1109203-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:50:550
866764991161,49cyclictest0-21swapper/009:35:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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