You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-18 - 13:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Wed Feb 18, 2026 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1814484226602636,16sleep21814399-21kworker/2:3+events@
dbs_work_handler
19:08:562
181474299126117,5cyclictest1883504-21ssh21:26:384
181474299122112,5cyclictest1902113-21ssh21:41:404
181474299120111,5cyclictest2121544-21ssh00:37:114
18147249912040,41cyclictest1924249-21/usr/sbin/munin22:00:460
181473399119106,6cyclictest1968373-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:36:512
181473799118105,6cyclictest1946109-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:26:513
181474299115105,5cyclictest0-21swapper/422:56:574
181473799114100,7cyclictest1961344-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:46:533
205688321120,6sleep12056886-21missed_timers23:45:261
205688321120,6sleep12056886-21missed_timers23:45:251
18147249911289,16cyclictest2035842-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:32:010
181474299110102,3cyclictest0-21swapper/423:01:554
18147249911074,16cyclictest1888159-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:46:420
18147339910795,6cyclictest1998789-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:06:572
18147339910795,6cyclictest1998789-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:06:562
18147339910693,7cyclictest1998789-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:16:572
18147339910693,7cyclictest1998789-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:16:572
18147429910599,3cyclictest0-21swapper/420:31:314
18147429910593,7cyclictest2015108-21ssh23:11:574
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional