You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-11 - 14:06
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Wed Mar 11, 2026 12:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3668421234133387,17sleep50-21swapper/507:05:365
3668965228692846,8sleep03666923-21kworker/0:3+events@
dbs_work_handler
07:06:380
36688172511492,9sleep23668451-21kworker/2:4+events@
dbs_work_handler
07:05:392
36693839914457,54cyclictest3779395-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:47:130
36693839913248,53cyclictest3910479-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:47:570
36693839913248,53cyclictest3910479-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:47:560
3669383991292,111cyclictest3867398-21ntpq11:05:380
3669383991292,111cyclictest3867398-21ntpq11:05:370
36693839912856,48cyclictest3709540-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:23:120
36693839912742,59cyclictest3755627-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:05:090
36693839912652,23cyclictest3727243-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:26:260
36693839912652,23cyclictest3727243-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:26:260
36693839912558,22cyclictest3786324-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:16:060
36693839912558,22cyclictest3786324-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:16:060
36693839912351,48cyclictest3931757-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:13:550
36693839912180,33cyclictest3931757-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:03:360
36693839912180,33cyclictest3931757-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:03:350
36693839911884,26cyclictest3985557-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:38:580
36693839911643,51cyclictest3680194-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
07:40:160
3669383991162,5cyclictest3681398-21sendmail-msp07:40:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional