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2026-01-11 - 10:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Sun Jan 11, 2026 00:46:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28483039915846,36cyclictest2995923-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:10:310
28483039915846,36cyclictest2995923-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:10:310
284831499153113,18cyclictest3101469-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:28:291
28483039914565,57cyclictest3011828-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:45:180
28483039914138,40cyclictest3073731-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:45:320
28483039914138,40cyclictest3073731-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:45:310
28483039913542,34cyclictest3109595-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:13:440
284832299134120,7cyclictest2988751-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:28:152
28483039913092,30cyclictest2880191-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:32:540
28483039913090,19cyclictest3016041-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork
22:58:180
28483039913090,19cyclictest3016041-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork
22:58:170
28483039912890,17cyclictest3004950-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:40:200
28483039912871,49cyclictest2957445-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:25:280
28483039912362,42cyclictest2897958-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:10:400
28483039911877,20cyclictest2854189-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:25:150
28483039911754,44cyclictest2858514-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:55:380
28483039911754,44cyclictest2858514-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:55:370
28483039911697,15cyclictest210-21kswapd021:30:270
28483039911680,15cyclictest3061469-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:03:260
28483039911680,15cyclictest3061469-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:03:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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