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2026-01-02 - 18:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Fri Jan 02, 2026 12:47:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3591854229312908,8sleep03591624-21kworker/0:1+events@
dbs_work_handler
07:07:250
3591460224102384,16sleep40-21swapper/407:05:394
3591871218593,1848sleep33591873-21sshd07:07:403
35907912929911,10sleep50-21swapper/507:05:225
359221199160125,27cyclictest3792464-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:40:020
359221199146108,18cyclictest3733753-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:39:490
359221199146108,18cyclictest3733753-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:39:480
359221199132105,23cyclictest210-21kswapd009:45:270
359221199132105,23cyclictest210-21kswapd009:45:270
359222199129115,7cyclictest3634468-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:29:332
35922119912964,29cyclictest3752793-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:48:390
35922119912964,29cyclictest3752793-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:48:380
359222899121105,7cyclictest3853970-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:25:113
359222199121106,8cyclictest3733753-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:34:482
359222199121106,8cyclictest3733753-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:34:472
35922119912179,25cyclictest3826475-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:15:190
35922119911797,15cyclictest210-21kswapd011:25:260
35922119911649,48cyclictest3702002-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:23:530
35922119911649,48cyclictest3702002-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:23:520
359222199115101,7cyclictest3792464-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:30:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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