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2026-01-07 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Wed Jan 07, 2026 12:46:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2833954234543428,16sleep40-21swapper/407:05:214
2833666211521133,10sleep50-21swapper/507:05:175
300379221480,3sleep40-21swapper/410:49:234
283534899146131,7cyclictest2973340-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:49:342
283534899145130,7cyclictest3049027-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:29:402
28353379913718,65cyclictest2877593-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:01:180
28353379913524,77cyclictest2855291-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:15:470
283534899132118,7cyclictest2923793-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:44:202
28353379913056,51cyclictest2923793-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:52:390
28353379913029,68cyclictest2835033-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:20:340
283534299129116,6cyclictest2940657-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:29:291
2835337991292,112cyclictest0-21swapper/012:10:210
2835337991292,112cyclictest0-21swapper/012:10:200
283534899128114,7cyclictest3041889-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:24:392
283534299127113,6cyclictest2909167-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:50:131
283534299125110,8cyclictest2923793-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:09:251
283535399121106,8cyclictest2973340-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:44:333
283535399121106,8cyclictest2973340-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:44:333
283534899121109,6cyclictest3072404-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:49:452
28353379912096,17cyclictest2942396-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork
10:04:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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