You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-14 - 12:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Wed Jan 14, 2026 00:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16534109917062,92cyclictest1693845-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:13:340
16534109916554,91cyclictest1752524-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:10:240
165341099161119,34cyclictest1849824-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:56:500
165341099161119,34cyclictest1849824-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:56:490
165341099153117,28cyclictest1849824-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:21:450
165341099153117,28cyclictest1849824-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:21:440
16534109915297,48cyclictest1769683-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:16:430
16534109915277,57cyclictest1665143-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:56:510
165341099136101,28cyclictest1687540-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:50:340
16534109913390,34cyclictest1806217-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:55:410
16534109913260,36cyclictest1727137-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:01:320
16534109913099,24cyclictest1769683-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:26:360
165342199129116,6cyclictest1910822-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:16:522
16534109912855,37cyclictest1707634-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:27:440
16534109912793,27cyclictest1674158-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:08:350
16534109912682,33cyclictest68950irq/527-eth0-Tx19:25:370
1653410991262,101cyclictest1699233-21ls21:00:400
16534109912569,49cyclictest1691444-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:40:030
16534109912565,53cyclictest1727137-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:05:140
16534109912565,53cyclictest1727137-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:05:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional