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2025-12-26 - 05:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Fri Dec 26, 2025 00:46:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26175689915760,51cyclictest2662479-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:27:030
2617568991354,118cyclictest0-21swapper/022:50:350
26175689913471,30cyclictest2854055-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:01:330
2617568991331,118cyclictest0-21swapper/023:20:210
26175689912953,54cyclictest13-21ksoftirqd/023:35:020
26175689912865,39cyclictest2739229-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:10:560
26175689912854,54cyclictest2611297-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:17:150
26175689912854,54cyclictest2611297-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:17:150
26175689912840,12cyclictest0-21swapper/022:00:400
26175689912651,61cyclictest0-21swapper/000:20:450
2617568991245,87cyclictest13-21ksoftirqd/022:35:020
26175689912389,27cyclictest2654451-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:41:350
26175689911967,33cyclictest2635230-21sort19:50:410
26175689911881,28cyclictest2619949-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:00:310
26175689911735,15cyclictest13-21ksoftirqd/021:52:450
26175689911731,29cyclictest2866692-21if_err_eth000:05:270
26175689911688,24cyclictest210-21kswapd021:20:270
2617568991166,50cyclictest13-21ksoftirqd/023:09:510
26175689911628,73cyclictest0-21swapper/023:53:260
26175689911628,73cyclictest0-21swapper/023:53:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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