You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-08-29 - 14:42
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Fri Aug 29, 2025 12:46:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1965166229342912,7sleep01964589-21kworker/0:2+events@
dbs_work_handler
07:05:400
1964632221072082,15sleep40-21swapper/407:05:334
1964313210351014,10sleep31960298-21kworker/3:4+events@
dbs_work_handler
07:05:263
19656919914895,44cyclictest2055016-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:50:270
196569199135107,20cyclictest2097230-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:40:440
19656919912042,68cyclictest0-21swapper/010:50:220
196571799118112,3cyclictest0-21swapper/510:40:435
19656919911664,43cyclictest64350irq/528-eth0-Tx11:07:100
19656979911097,6cyclictest1998044-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
08:30:221
19656979910793,7cyclictest2015768-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:20:291
19656919910779,20cyclictest1963463-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
07:15:070
19656919910779,20cyclictest1963463-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
07:15:060
196571799106100,3cyclictest0-21swapper/509:50:285
19657019910691,8cyclictest1979263-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
08:00:152
19657019910690,8cyclictest2015768-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:20:312
19656919910682,16cyclictest1983424-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:55:140
1965691991056,67cyclictest0-21swapper/009:20:210
1965691991055,88cyclictest0-21swapper/011:30:290
19657019910486,12cyclictest2005456-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
08:50:192
1965691991048,82cyclictest2007980-21aten2_r3power_c08:55:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional