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2026-01-01 - 05:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Thu Jan 01, 2026 00:47:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
407769914165,43cyclictest210-21kswapd022:30:070
407769914165,43cyclictest210-21kswapd022:30:060
4078799134120,7cyclictest263680-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:58:242
4078799134120,7cyclictest263680-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:58:242
407769913197,30cyclictest210-21kswapd000:35:260
407769913197,30cyclictest210-21kswapd000:35:260
4079699129120,5cyclictest188963-21ssh22:36:394
4079699129120,5cyclictest188963-21ssh22:36:384
4079199127113,7cyclictest312751-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:28:513
4079199127113,7cyclictest312751-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:28:513
4079699125120,2cyclictest0-21swapper/423:15:284
407769912494,14cyclictest210-21kswapd022:10:160
407769912494,14cyclictest210-21kswapd022:10:160
4078799122108,7cyclictest89263-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:16:232
4078799122108,7cyclictest89263-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:16:222
4079199120105,8cyclictest80915-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:31:263
4078799119106,6cyclictest54506-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:16:092
4078799119105,7cyclictest192203-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:01:432
407769911476,30cyclictest82928-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:05:230
407919911399,7cyclictest241995-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:35:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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