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2025-12-25 - 11:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Thu Dec 25, 2025 00:46:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25960499148141,3cyclictest0-21swapper/523:42:425
25960499148141,3cyclictest0-21swapper/523:42:425
25960499147141,3cyclictest0-21swapper/521:07:095
25959099143130,7cyclictest499253-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:38:562
25959099138123,7cyclictest350225-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:07:232
25957899137103,27cyclictest467168-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:37:410
25957899137103,27cyclictest467168-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:37:400
2595789913690,39cyclictest490528-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
00:28:440
25957899136102,17cyclictest210-21kswapd023:40:260
25957899136102,17cyclictest210-21kswapd023:40:260
25957899135107,18cyclictest293693-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:45:230
25957899135107,18cyclictest293693-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:45:220
25959099134106,15cyclictest305878-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:47:222
25959099134106,15cyclictest305878-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:47:222
25959099127114,6cyclictest401891-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:07:352
25959099127112,7cyclictest366653-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:02:222
25959499126114,6cyclictest265414-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:26:503
2595789912586,19cyclictest385932-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:55:230
25959099123113,4cyclictest319107-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:27:122
2595789912391,25cyclictest283516-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
20:17:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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