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2026-02-11 - 12:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Wed Feb 11, 2026 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17699239913148,45cyclictest1929395-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:45:450
17699239912967,54cyclictest1812199-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:20:170
17699239912760,59cyclictest1783973-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:10:120
17699239912290,23cyclictest1960575-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:11:290
17699239912290,23cyclictest1960575-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:11:290
17699239911969,28cyclictest1798313-21sort20:20:010
17699239911969,28cyclictest1798313-21sort20:20:000
1769923991182,35cyclictest0-21swapper/022:40:020
1769923991182,35cyclictest0-21swapper/022:40:020
17699239911784,24cyclictest1975915-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:55:240
17699239911774,35cyclictest1987089-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:36:520
17699239911774,35cyclictest1987089-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:36:520
17699239911767,34cyclictest1987089-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:34:170
17699239911766,15cyclictest1834107-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:45:340
17699239911584,22cyclictest1808039-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:46:120
17699309911297,7cyclictest1816324-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:21:171
17699309911297,7cyclictest1816324-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
21:21:161
17699239911179,24cyclictest1781871-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
19:40:320
17699309911096,6cyclictest1886123-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:20:351
17699239910961,22cyclictest1812199-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:02:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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