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2026-06-07 - 16:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Sun Jun 07, 2026 12:46:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269884399140100,20cyclictest2845992-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:35:040
269884399140100,20cyclictest2845992-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:35:040
269886299136126,5cyclictest2757826-21ssh09:19:484
269886299135129,3cyclictest0-21swapper/407:34:354
269884899132120,6cyclictest2747662-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:29:501
269885399129116,6cyclictest2993023-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:35:312
269885399129116,6cyclictest2993023-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:35:302
269885799128118,7cyclictest210-21kswapd012:25:273
269885399125112,7cyclictest2866388-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:50:062
26988439912348,60cyclictest2700519-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:19:230
269886299121110,6cyclictest2751486-21ssh09:14:474
269885399116102,7cyclictest2845992-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:30:022
26988439911669,26cyclictest2738350-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:36:440
26988539911298,7cyclictest2881451-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:00:092
26988539911197,7cyclictest2738350-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:09:462
26988439911078,24cyclictest2784841-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:40:350
26988439911050,41cyclictest2949477-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:21:120
26988439911035,52cyclictest13-21ksoftirqd/009:14:420
26988439910845,39cyclictest2747662-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:15:470
26988539910794,6cyclictest2866388-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:55:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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