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2026-03-10 - 14:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Tue Mar 10, 2026 12:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12256749915142,75cyclictest1391073-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:25:460
122567499151117,26cyclictest1481590-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
12:39:270
12256749915065,52cyclictest1498062-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:04:570
12256749913882,49cyclictest1391073-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:14:200
122567499136100,28cyclictest1230202-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:23:470
131249221340,5sleep41312491-21ssh09:40:224
12256749913360,36cyclictest1428819-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:11:250
12256749913169,54cyclictest1263666-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
08:45:240
12256749913160,36cyclictest1297017-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:44:580
12256749913093,28cyclictest1249835-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:18:510
12256749913093,28cyclictest1249835-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:18:510
12256749912961,31cyclictest1279538-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:03:130
12256749912867,54cyclictest1391073-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:45:360
12256749912861,57cyclictest1351861-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:25:010
12256749912861,57cyclictest1351861-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:25:010
12256749912854,40cyclictest1235654-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:02:330
12256749912854,40cyclictest1235654-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:02:330
12256749912761,58cyclictest1249835-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
08:23:510
12256749912591,27cyclictest1415182-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:24:220
12256749912565,53cyclictest1279538-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:37:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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