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2026-01-18 - 11:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Sun Jan 18, 2026 00:46:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2869781234323414,10sleep50-21swapper/519:05:385
2869546211791162,8sleep12869220-21kworker/1:2+events@
dbs_work_handler
19:05:281
28706939917734,97cyclictest2874475-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
19:40:320
287070699134120,7cyclictest3110384-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:53:062
296920021260,11sleep013-21ksoftirqd/021:51:400
287072599114109,2cyclictest0-21swapper/423:58:084
28706939911381,4cyclictest2995601-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:27:510
287072599111105,3cyclictest0-21swapper/422:52:574
287072599111105,3cyclictest0-21swapper/422:52:574
28706939911185,6cyclictest68950irq/527-eth0-Tx22:05:010
28706939911169,18cyclictest56-21rcuop/500:25:280
28706939911070,19cyclictest68950irq/527-eth0-Tx00:10:200
28706939910862,33cyclictest68950irq/527-eth0-Tx22:45:230
28707259910497,3cyclictest0-21swapper/419:42:144
28707069910489,7cyclictest3094312-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:34:332
28706939910471,9cyclictest2913016-1kworker/0:0H-kblockd22:50:280
28706939910471,9cyclictest2913016-1kworker/0:0H-kblockd22:50:280
2870725999994,2cyclictest0-21swapper/400:33:164
31616092970,4sleep10-21swapper/100:27:141
2870706999784,6cyclictest3087921-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:23:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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