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2026-10-25 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Sun Oct 25, 2026 00:46:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1356208227662741,15sleep40-21swapper/419:07:274
13566159912995,26cyclictest1592063-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:43:180
135661599129100,21cyclictest1464976-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:08:090
13566159912286,28cyclictest1455757-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:52:490
13566159912286,28cyclictest1455757-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:52:480
13566159912031,4cyclictest67550irq/529-eth0-Tx23:35:220
13566159911988,27cyclictest1464976-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:12:560
13566159911317,67cyclictest15-21rcuc/000:00:380
1356615991131,52cyclictest0-21swapper/021:55:440
1356615991131,52cyclictest0-21swapper/021:55:430
13566159911238,63cyclictest0-21swapper/000:10:300
146960321090,7chrt15-21rcuc/022:03:150
13566159910925,60cyclictest1391615-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:40:300
13566229910790,10cyclictest1407816-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:17:431
13566159910450,37cyclictest0-21swapper/019:55:370
13566159910430,70cyclictest13-21ksoftirqd/020:00:300
13566159910362,31cyclictest67350irq/527-eth0-Tx19:20:250
13566159910338,15cyclictest13-21ksoftirqd/022:35:460
13566159910338,15cyclictest13-21ksoftirqd/022:35:450
13566229910288,7cyclictest1561448-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:53:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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