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2026-01-05 - 07:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Mon Jan 05, 2026 00:47:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1089891230813066,6sleep21081740-21kworker/2:2+events@
dbs_work_handler
19:09:372
1088495213761346,12sleep01088327-21kworker/0:0+events@
dbs_work_handler
19:05:200
109009499140126,7cyclictest1138355-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:12:172
109009499140126,7cyclictest1138355-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:12:172
109009499140125,8cyclictest1267624-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:12:382
109009499139126,7cyclictest1295834-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:32:402
109009499132118,7cyclictest1201872-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:22:292
109009499132118,7cyclictest1201872-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:22:292
109009499131116,8cyclictest1070066-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:22:002
109008499131111,16cyclictest210-21kswapd022:45:270
10900849912958,7cyclictest1248552-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:05:460
109010499127121,3cyclictest0-21swapper/422:42:324
109010499127121,3cyclictest0-21swapper/422:42:324
135548021240,4sleep50-21swapper/500:20:365
109009499123109,7cyclictest1321779-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
23:57:402
10900849912295,19cyclictest1248552-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:50:140
10891622122102,9sleep11085020-21kworker/1:0+events@
dbs_work_handler
19:05:391
109009499121106,7cyclictest1236288-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:37:322
109009499121106,7cyclictest1236288-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:37:312
124499321160,3sleep00-21swapper/022:44:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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