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2026-06-07 - 04:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Sat Jun 06, 2026 00:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325410799134110,15cyclictest3266409-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:50:340
325410799134110,15cyclictest3266409-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:50:330
325412199132118,7cyclictest3276033-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:15:383
32541079912588,30cyclictest3300942-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:31:190
32541079912588,30cyclictest3300942-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
21:31:180
32541079912459,44cyclictest3298721-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:53:290
325411299121108,6cyclictest3467585-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:53:241
32541079912047,37cyclictest3511425-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
00:05:560
325412199119105,7cyclictest3348868-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork
21:51:033
32541079911468,39cyclictest3522142-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
00:01:000
32541079911443,33cyclictest3278252-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
20:15:210
32541129911098,6cyclictest3447247-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:36:221
325413299109104,2cyclictest0-21swapper/522:06:035
32541129910996,7cyclictest3286123-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
20:45:451
32541079910883,17cyclictest3298721-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:11:060
32541079910882,18cyclictest3324495-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:46:000
32541079910753,46cyclictest3536227-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:15:280
32541079910740,31cyclictest3276033-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:23:380
32541079910740,31cyclictest3276033-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:23:370
32541079910693,7cyclictest3298721-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:06:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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