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2026-01-07 - 11:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack3slot4.osadl.org (updated Wed Jan 07, 2026 00:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1631414212561229,17sleep50-21swapper/519:05:205
16328569919559,93cyclictest1767391-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:30:350
16328569919559,93cyclictest1767391-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:30:350
16328569913093,30cyclictest1864510-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:22:370
163286599124111,6cyclictest1700468-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:27:012
163286599124111,6cyclictest1700468-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:27:012
189843921210,4sleep20-21swapper/200:10:182
189843921210,4sleep20-21swapper/200:10:172
16328569911983,28cyclictest1733453-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
22:05:220
16328569911742,52cyclictest1715830-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
21:52:120
16328609911399,7cyclictest1752524-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:57:181
16328569911282,23cyclictest1767391-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:12:200
1632856991121,50cyclictest0-21swapper/000:35:190
16328569911182,24cyclictest210-21kswapd023:50:230
16328569911124,81cyclictest1832805-21ntpq23:15:370
16328569910978,24cyclictest1752524-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:47:160
16328569910978,24cyclictest1752524-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:47:160
16328569910927,7cyclictest1640673-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
19:47:150
16328569910827,44cyclictest13-21ksoftirqd/000:05:260
16328569910827,44cyclictest13-21ksoftirqd/000:05:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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