OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #3, slot #4

Click here to display the system's profile data or here to proceed to next system.

Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.
Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance

Characteristics of the 50 highest latencies:

System rack3slot4.osadl.org (updated Tue Jan 13, 2026 12:46:43)
Delayed (victim)					Switcher (culprit)			Timestamp	CPU
PID	Prio	Total latency (µs)	T^(,W^*) latency (µs)	Cmd	PID	Prio	Cmd	Timestamp	CPU
452398	2	3123	3098,16	sleep5	0	-21	swapper/5	07:05:18	5
453254	2	313	295,10	sleep2	431205	-21	kworker/2:2+events@ dbs_work_handler	07:05:39	2
454203	99	156	111,38	cyclictest	594428	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	10:39:53	0
454203	99	146	67,66	cyclictest	487112	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	08:42:41	0
454203	99	146	67,66	cyclictest	487112	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	08:42:40	0
454203	99	133	63,33	cyclictest	495207	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	09:41:59	0
454203	99	131	98,26	cyclictest	495207	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	09:53:34	0
454203	99	127	102,17	cyclictest	730981	-21	kworker/u12:4+events_unbound@ flush_memcg_stats_dwork	12:25:15	0
454203	99	123	45,40	cyclictest	635850	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	11:30:25	0
454203	99	123	27,14	cyclictest	0	-21	swapper/0	10:00:45	0
454207	99	121	107,7	cyclictest	500997	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	09:19:37	1
454207	99	121	107,7	cyclictest	495207	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	09:14:36	1
454203	99	121	90,23	cyclictest	551522	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	09:59:43	0
454203	99	117	73,36	cyclictest	674017	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	12:05:52	0
454203	99	117	73,30	cyclictest	674017	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	11:53:03	0
454203	99	116	59,38	cyclictest	586807	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	10:51:13	0
454207	99	115	101,7	cyclictest	617395	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	10:49:56	1
454207	99	114	98,8	cyclictest	586807	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	10:34:54	1
454203	99	113	55,50	cyclictest	650707	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	11:24:57	0
454203	99	112	61,43	cyclictest	560158	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	10:22:12	0
454203	99	112	61,43	cyclictest	560158	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	10:22:11	0
454203	99	112	51,39	cyclictest	460027	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	07:46:14	0
454203	99	110	70,32	cyclictest	635850	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	11:05:02	0
454203	99	109	77,24	cyclictest	560158	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	10:05:10	0
454203	99	109	77,24	cyclictest	560158	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	10:05:09	0
454203	99	109	51,34	cyclictest	690	50	irq/528-eth0-Tx	09:30:53	0
454203	99	109	51,34	cyclictest	690	50	irq/528-eth0-Tx	09:30:52	0
454203	99	108	73,26	cyclictest	457918	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	07:25:27	0
454203	99	108	49,50	cyclictest	635850	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	11:35:40	0
454203	99	106	74,24	cyclictest	635850	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	11:17:06	0
454203	99	106	74,24	cyclictest	635850	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	11:17:05	0
454203	99	106	55,43	cyclictest	594428	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	10:45:38	0
454207	99	103	89,7	cyclictest	560158	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	10:09:50	1
454207	99	103	89,7	cyclictest	560158	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	10:09:49	1
454216	99	102	88,7	cyclictest	680327	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	11:55:10	3
454216	99	102	88,7	cyclictest	680327	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	11:55:10	3
454203	99	101	67,14	cyclictest	479489	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	08:24:26	0
454207	99	100	87,6	cyclictest	586807	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	11:06:02	1
454203	99	100	74,16	cyclictest	594428	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	10:30:15	0
454203	99	100	65,15	cyclictest	607108	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	10:44:54	0
454203	99	100	64,15	cyclictest	479489	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	08:19:28	0
454203	99	99	72,20	cyclictest	692404	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	12:00:12	0
454203	99	99	69,23	cyclictest	453205	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	07:19:15	0
454203	99	98	66,17	cyclictest	680327	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	11:42:15	0
454203	99	98	65,16	cyclictest	540190	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	10:29:33	0
454203	99	98	64,15	cyclictest	741141	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	12:34:16	0
454216	99	97	83,7	cyclictest	586807	-21	kworker/u12:0+events_unbound@ flush_memcg_stats_dwork	10:29:51	3
454203	99	97	60,16	cyclictest	472193	-21	kworker/u12:2+events_unbound@ flush_memcg_stats_dwork	08:05:13	0
454203	99	97	60,15	cyclictest	692404	-21	kworker/u12:3+events_unbound@ flush_memcg_stats_dwork	12:11:35	0
454216	99	96	78,9	cyclictest	466016	-21	kworker/u12:1+events_unbound@ flush_memcg_stats_dwork	07:51:36	3
^Timer ^*Wakeup (latency=timer+wakeup+contextswitch)


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This page was last modified on 2019-05-28 - 00:17