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2025-07-10 - 04:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Thu Jul 10, 2025 00:46:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3764123223622337,8sleep03763218-21kworker/0:2+events@
dbs_work_handler
19:06:040
37641002808785,14sleep40-21swapper/419:05:504
3764570991381,107cyclictest3997516-21latency_hist23:45:020
3764570991171,70cyclictest3810414-21kworker/u12:1+rpciod@
rpc_async_schedule
21:20:120
3764570991161,75cyclictest3842889-21kworker/u12:1+rpciod@
rpc_async_schedule
21:42:010
376457999115102,6cyclictest3917091-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
22:51:362
37645849911494,8cyclictest3842889-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
21:46:233
37645709911327,55cyclictest64450irq/529-eth0-Tx22:20:320
37645709911327,55cyclictest64450irq/529-eth0-Tx22:20:310
37645709911327,55cyclictest64450irq/529-eth0-Tx22:20:310
3764570991131,95cyclictest0-21swapper/020:10:160
37645709911246,47cyclictest0-21swapper/022:29:030
37645709911246,47cyclictest0-21swapper/022:29:020
37645709911155,41cyclictest0-21swapper/020:05:510
37645709911155,41cyclictest0-21swapper/020:05:510
37645709911129,58cyclictest64350irq/528-eth0-Tx22:50:230
3764570991101,91cyclictest3919152-21ssh22:40:260
3764570991101,91cyclictest3919152-21ssh22:40:250
37645849910894,7cyclictest3786380-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:06:043
37645849910894,7cyclictest3786380-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
20:06:043
3764570991081,94cyclictest0-21swapper/020:40:120
37645849910793,7cyclictest4005742-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
23:57:433
3764570991071,73cyclictest0-21swapper/021:55:030
3764570991071,73cyclictest0-21swapper/021:55:030
37645709910712,79cyclictest64450irq/529-eth0-Tx23:15:170
3764570991062,80cyclictest0-21swapper/022:02:110
3764570991061,76cyclictest0-21swapper/021:10:210
3764570991061,3cyclictest0-21swapper/020:35:140
3764570991055,78cyclictest0-21swapper/022:38:290
3764570991051,91cyclictest0-21swapper/000:33:030
3764570991051,91cyclictest0-21swapper/000:33:030
3764570991051,90cyclictest0-21swapper/020:25:150
3764570991051,90cyclictest0-21swapper/020:25:150
3764570991051,89cyclictest0-21swapper/021:06:390
37645959910498,3cyclictest0-21swapper/523:06:425
37645799910491,6cyclictest3782187-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
19:51:032
3764570991049,72cyclictest64550irq/530-eth0-Tx00:25:210
37645709910480,16cyclictest3761147-21kworker/u12:4+events_unbound@
flush_memcg_stats_dwork
19:20:580
37645709910423,43cyclictest0-21swapper/022:46:330
37645709910423,43cyclictest0-21swapper/022:46:330
3764570991041,83cyclictest0-21swapper/021:45:330
37645709910410,79cyclictest64250irq/527-eth0-Tx22:34:430
3764570991032,87cyclictest0-21swapper/019:40:130
3764570991022,81cyclictest0-21swapper/019:39:130
3764570991021,66cyclictest0-21swapper/000:10:250
3764570991021,66cyclictest0-21swapper/000:10:250
3764570991021,64cyclictest0-21swapper/021:32:230
3764570991014,34cyclictest64450irq/529-eth0-Tx21:25:180
37645709910142,42cyclictest0-21swapper/019:15:510
3764570991012,30cyclictest4058546-21kworker/u12:4+rpciod@
rpc_async_schedule
00:37:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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