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2026-04-15 - 17:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Wed Apr 15, 2026 12:46:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
627080211951168,16sleep40-21swapper/407:05:154
6288849918357,43cyclictest661289-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
08:36:350
6288849915568,17cyclictest830881-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:25:350
6288849915568,17cyclictest830881-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
11:25:340
6288849914478,51cyclictest777853-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
10:28:560
6288849913557,49cyclictest764115-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:19:330
6288849913266,42cyclictest771216-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:16:340
6288849912575,42cyclictest777853-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:06:060
62888999124112,6cyclictest804293-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:58:591
62888999124112,6cyclictest729584-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:08:521
62888499123100,15cyclictest630718-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
08:03:370
62888499123100,15cyclictest630718-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
08:03:370
6288849911910,96cyclictest787949-21ntpq10:35:350
6288849911910,96cyclictest787949-21ntpq10:35:340
6288849911749,46cyclictest677970-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
09:14:200
6288849911491,15cyclictest669227-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:18:450
6288849911348,42cyclictest620590-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:12:220
6288849911348,42cyclictest620590-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
07:12:220
6288849911344,45cyclictest777853-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
11:13:310
6288849911288,16cyclictest669227-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
09:03:440
6288849911258,27cyclictest771216-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:21:050
628884991118,86cyclictest662198-21memory08:30:240
6288849911142,5cyclictest69250irq/530-eth0-Tx09:35:030
6288849911142,5cyclictest69250irq/530-eth0-Tx09:35:030
62890899110104,3cyclictest0-21swapper/508:03:375
62890899110104,3cyclictest0-21swapper/508:03:375
6288899911098,6cyclictest721817-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:13:531
628884991107,79cyclictest0-21swapper/007:35:310
6288849911064,38cyclictest796217-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:47:340
6288849911064,38cyclictest796217-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
10:47:340
628884991099,83cyclictest0-21swapper/007:45:010
6288849910966,40cyclictest920319-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
12:19:440
6288849910944,41cyclictest882826-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:11:130
6288849910944,41cyclictest882826-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
12:11:120
628884991077,84cyclictest0-21swapper/007:30:010
628884991077,84cyclictest0-21swapper/007:30:010
6288849910685,14cyclictest657124-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
08:28:400
6288899910592,6cyclictest721817-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:03:521
6288849910480,16cyclictest669227-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
08:50:250
628884991047,92cyclictest0-21swapper/008:05:200
6288999910382,7cyclictest804293-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:48:553
6288999910382,7cyclictest804293-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
10:48:543
6288899910364,7cyclictest906816-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:08:111
6288899910364,7cyclictest906816-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
12:08:101
6288849910369,25cyclictest69050irq/528-eth0-Tx07:30:180
6288849910341,38cyclictest210-21kswapd009:30:060
628884991027,59cyclictest0-21swapper/012:39:290
6289089910195,3cyclictest0-21swapper/511:29:015
6289089910195,3cyclictest0-21swapper/511:29:005
6288899910187,7cyclictest661289-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
08:35:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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