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2026-02-27 - 20:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Fri Feb 27, 2026 12:46:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3922925235373516,7sleep13922243-21kworker/1:2+events@
dbs_work_handler
07:05:201
3922925235373516,7sleep13922243-21kworker/1:2+events@
dbs_work_handler
07:05:191
3923422218741849,16sleep40-21swapper/407:05:344
3923422218741849,16sleep40-21swapper/407:05:344
392444999112103,5cyclictest4016147-21ssh09:44:014
392444999112103,5cyclictest4016147-21ssh09:44:014
39244309911095,7cyclictest4126380-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:12:220
39244349910590,8cyclictest3975149-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:54:031
39244349910590,8cyclictest3975149-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:54:021
39244309910436,43cyclictest3995974-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
10:12:210
39244309910432,6cyclictest4096842-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
11:02:500
39244309910278,6cyclictest3975149-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:45:340
39244309910278,6cyclictest3975149-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
09:45:330
39244309910226,55cyclictest3954554-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
08:31:590
3924430999724,49cyclictest3932755-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
07:32:500
40307742950,8sleep122-21rcuc/109:55:121
392443099921,79cyclictest0-21swapper/008:15:010
392443099921,5cyclictest69050irq/528-eth0-Tx11:25:410
3924449999184,3cyclictest0-21swapper/411:05:334
3924430999024,55cyclictest4124027-21threads11:05:420
3924449998983,3cyclictest0-21swapper/408:45:344
3924430998966,12cyclictest68950irq/527-eth0-Tx08:55:260
3924449998780,3cyclictest0-21swapper/407:43:364
3924440998773,7cyclictest3930352-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
07:33:352
3924430998729,49cyclictest0-21swapper/010:45:390
392443099871,78cyclictest0-21swapper/007:18:500
392443099871,71cyclictest0-21swapper/007:48:270
40990002860,15sleep123-21ksoftirqd/110:46:321
3924453998681,2cyclictest0-21swapper/510:03:365
392443099851,74cyclictest0-21swapper/008:07:280
392443099851,71cyclictest3973131-21diskmemload09:25:030
392443099851,3cyclictest0-21swapper/009:55:450
3924430998474,7cyclictest4160922-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:39:000
3924430998474,7cyclictest4160922-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
11:39:000
3924430998430,29cyclictest69150irq/529-eth0-Tx09:30:340
392443099841,69cyclictest0-21swapper/007:27:300
41798072830,18sleep123-21ksoftirqd/111:49:131
3924430998356,3cyclictest0-21swapper/010:03:350
392443099832,67cyclictest4174070-21ssh11:44:590
392443099831,72cyclictest0-21swapper/008:38:300
3924449998273,5cyclictest4084452-21ssh10:35:394
3924449998273,5cyclictest4084452-21ssh10:35:394
3924440998263,7cyclictest3995974-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:51:022
3924440998263,7cyclictest3995974-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork
09:51:022
392443099826,48cyclictest0-21swapper/011:21:340
392443099821,5cyclictest4070978-21ssh10:25:260
40056632810,5sleep30-21swapper/309:35:373
3924449998166,9cyclictest9020-21ssh12:06:134
3924430998119,40cyclictest3920217-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
07:11:560
392443099811,66cyclictest69250irq/530-eth0-Tx11:55:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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