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2025-08-22 - 00:11
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of system in rack #3, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Thu Aug 21, 2025 12:46:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
1848422677651,8sleep0181702-21kworker/0:3+events@
dbs_work_handler		07:08:210
18512099162126,29cyclictest257300-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		09:35:480
18512099146110,28cyclictest410835-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		12:16:390
1851209912590,16cyclictest421851-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		12:11:380
18512999124107,8cyclictest330105-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		10:46:232
1851209912385,18cyclictest364046-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		11:51:330
18513899115109,3cyclictest0-21swapper/410:21:234
18513899115109,3cyclictest0-21swapper/410:21:224
18512599114100,7cyclictest364046-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		11:56:341
1851209911447,41cyclictest257300-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		09:41:320
1851209911447,41cyclictest257300-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		09:41:310
1851259911298,7cyclictest212998-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		08:41:071
1851299911198,6cyclictest205843-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		08:11:002
1851389910996,7cyclictest259728-21ssh09:35:484
1851209910973,19cyclictest257300-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		09:55:520
1851259910794,7cyclictest445929-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		12:31:551
1851209910748,36cyclictest247270-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		10:45:530
18514399106101,2cyclictest0-21swapper/508:30:345
1851209910622,7cyclictest229247-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		09:27:150
1851259910592,7cyclictest316138-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		11:11:271
1851259910591,7cyclictest364046-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		11:46:501
1851209910548,23cyclictest0-21swapper/007:55:390
1851349910489,8cyclictest247270-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		10:15:533
1851209910446,45cyclictest64350irq/528-eth0-Tx11:00:270
1851349910389,7cyclictest445929-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork		12:36:553
1851209910371,18cyclictest0-21swapper/012:25:360
1851259910288,7cyclictest309664-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork		10:35:591
1851259910086,7cyclictest364046-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		12:01:511
1851209910039,48cyclictest0-21swapper/011:25:390
185125999986,6cyclictest247270-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		10:56:041
185120999962,25cyclictest0-21swapper/009:51:030
185120999865,24cyclictest197974-21needreboot07:40:270
185120999865,24cyclictest197974-21needreboot07:40:270
185120999865,23cyclictest64250irq/527-eth0-Tx10:40:180
185125999783,7cyclictest316138-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		11:16:061
185120999774,15cyclictest224811-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork		08:51:080
185120999763,25cyclictest0-21swapper/007:45:370
185120999663,13cyclictest0-21swapper/007:15:370
185120999641,42cyclictest64350irq/528-eth0-Tx10:35:140
185138999589,3cyclictest0-21swapper/408:21:024
185120999545,14cyclictest15-21rcuc/009:45:250
185120999545,14cyclictest15-21rcuc/009:45:240
185120999468,19cyclictest210762-21kworker/u12:1+events_unbound@
flush_memcg_stats_dwork		08:20:330
185120999462,21cyclictest64250irq/527-eth0-Tx08:55:300
185120999462,21cyclictest64250irq/527-eth0-Tx08:55:290
18512099931,46cyclictest410835-21kworker/u12:1+rpciod@
rpc_async_schedule		12:00:150
185120999247,31cyclictest0-21swapper/009:23:520
185138999180,6cyclictest235982-21diskmemload-411:24:564
185120999162,20cyclictest0-21swapper/008:15:210
185120999129,46cyclictest64450irq/529-eth0-Tx11:59:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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