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2026-07-15 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack3slot4.osadl.org (updated Wed Jul 15, 2026 00:46:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13943689915137,51cyclictest1654837-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
23:55:320
13943689912623,67cyclictest1654870-21sed23:50:440
13943689911812,68cyclictest1671856-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
00:25:430
139438699116109,3cyclictest0-21swapper/421:01:084
13943689910922,71cyclictest1548189-21irqstats22:30:230
13943769910692,7cyclictest1581845-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:16:452
13943769910692,7cyclictest1581845-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:16:452
1394368991061,81cyclictest0-21swapper/021:50:370
1394368991052,5cyclictest1426143-21cat20:25:430
1394368991041,65cyclictest0-21swapper/000:35:330
1394368991041,65cyclictest0-21swapper/000:35:330
13943769910389,7cyclictest1640894-21kworker/u12:0+events_unbound@
flush_memcg_stats_dwork
23:41:522
13943689910379,16cyclictest1197876-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
19:10:420
13943689910236,49cyclictest0-21swapper/021:25:560
13943689910171,12cyclictest67350irq/527-eth0-Tx21:35:550
13943689910171,12cyclictest67350irq/527-eth0-Tx21:35:550
13943689910167,24cyclictest67450irq/528-eth0-Tx00:33:450
13943689910167,24cyclictest67450irq/528-eth0-Tx00:33:450
1394368991011,4cyclictest1678917-21ssh00:09:430
13943689910066,22cyclictest67350irq/527-eth0-Tx19:30:130
1394368991002,5cyclictest1455596-21ssh21:20:290
1394368991001,83cyclictest1581789-21ntpq22:55:310
1394376999984,7cyclictest1540881-21kworker/u12:3+events_unbound@
flush_memcg_stats_dwork
22:41:382
1394368999965,25cyclictest0-21swapper/022:02:040
139436899991,80cyclictest1442968-21diskmemload22:13:470
139436899991,73cyclictest0-21swapper/022:40:370
1394368999865,14cyclictest67350irq/527-eth0-Tx23:10:040
1394368999865,14cyclictest67350irq/527-eth0-Tx23:10:040
139436899982,80cyclictest0-21swapper/021:45:130
139436899981,76cyclictest0-21swapper/021:10:120
1394386999791,3cyclictest0-21swapper/422:10:024
1394368999750,24cyclictest0-21swapper/019:25:350
1394368999747,29cyclictest0-21swapper/019:40:150
139436899972,6cyclictest1433964-21ntpq20:45:310
139436899971,82cyclictest0-21swapper/023:25:320
139436899971,80cyclictest0-21swapper/020:10:210
1394368999669,13cyclictest67650irq/530-eth0-Tx19:35:330
1394368999658,22cyclictest67450irq/528-eth0-Tx23:36:290
1394368999546,7cyclictest1576047-21ssh22:50:460
1394368999533,4cyclictest67450irq/528-eth0-Tx23:40:140
139436899951,79cyclictest1533751-21ssh22:19:590
139436899951,74cyclictest0-21swapper/021:05:310
1394376999482,6cyclictest1530756-21kworker/u12:2+events_unbound@
flush_memcg_stats_dwork
22:56:402
139436899945,75cyclictest0-21swapper/022:07:470
1394368999452,22cyclictest0-21swapper/023:45:110
1394368999429,53cyclictest67450irq/528-eth0-Tx21:15:530
139436899942,5cyclictest1417646-21ntpq20:05:270
139436899942,5cyclictest1417646-21ntpq20:05:270
139436899941,7cyclictest1587415-21awk23:00:100
139436899941,4cyclictest0-21swapper/020:56:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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