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2026-01-20 - 19:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Jan 20, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
206259912362,19cyclictest14-21ksoftirqd/007:40:130
206259911942,25cyclictest14-21ksoftirqd/012:25:140
206259911913,94cyclictest0-21swapper/009:50:140
206259911216,32cyclictest0-21swapper/010:25:120
206259911212,56cyclictest0-21swapper/011:05:160
206309911112,62cyclictest0-21swapper/110:10:131
206259911013,34cyclictest0-21swapper/009:45:240
206259910980,19cyclictest14-21ksoftirqd/007:50:140
206259910979,17cyclictest14-21ksoftirqd/008:55:150
206259910979,17cyclictest14-21ksoftirqd/008:55:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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