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2026-02-26 - 10:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Thu Feb 26, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
164342940,8chrt0-21swapper/122:25:171
11552999414,63cyclictest0-21swapper/021:00:130
1136629332,49sleep10-21swapper/119:09:281
102122895,73sleep010271-21irqstats19:05:220
1155299888,70cyclictest3138-21apt-get23:20:100
11552998726,54cyclictest31651-21cron00:39:590
11552998717,58cyclictest0-21swapper/022:15:130
11552998715,61cyclictest0-21swapper/021:15:110
11552998711,61cyclictest0-21swapper/020:55:230
11552998614,59cyclictest0-21swapper/021:35:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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