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2026-01-13 - 04:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Jan 13, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17244210119,38sleep00-21swapper/019:05:440
1782999955,60cyclictest0-21swapper/122:40:301
17829999141,34cyclictest26-21ksoftirqd/123:30:121
17824998915,60cyclictest0-21swapper/021:05:130
17824998817,58cyclictest0-21swapper/022:20:130
17824998816,60cyclictest0-21swapper/022:45:110
17824998716,62cyclictest0-21swapper/022:10:100
17824998716,58cyclictest0-21swapper/021:40:150
17824998715,58cyclictest0-21swapper/021:50:120
17824998616,57cyclictest0-21swapper/021:15:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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