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2026-01-13 - 00:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Mon Jan 12, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14110999853,26cyclictest26-21ksoftirqd/108:20:141
14110999653,23cyclictest26-21ksoftirqd/110:45:121
14110999254,21cyclictest26-21ksoftirqd/111:45:151
14100999263,17cyclictest0-21swapper/012:25:130
14110998854,19cyclictest26-21ksoftirqd/109:10:241
136592847,66sleep00-21swapper/007:07:280
1352828426,45sleep10-21swapper/107:06:031
14100998147,18cyclictest14-21ksoftirqd/011:50:240
14100998056,15cyclictest14-21ksoftirqd/011:45:120
14100997851,16cyclictest14-21ksoftirqd/008:30:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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