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2026-01-22 - 07:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Thu Jan 22, 2026 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16702213038,25sleep10-21swapper/119:05:291
17547998971,11cyclictest26-21ksoftirqd/121:50:111
17547998869,13cyclictest26-21ksoftirqd/122:25:131
17547998770,10cyclictest26-21ksoftirqd/119:30:121
1754599858,50cyclictest20564-21awk19:15:260
17545998541,22cyclictest14-21ksoftirqd/023:30:170
17547998264,12cyclictest26-21ksoftirqd/120:45:231
1579527936,26sleep00-21swapper/019:05:110
17545997839,14cyclictest14-21ksoftirqd/023:00:270
17545997837,15cyclictest14-21ksoftirqd/022:31:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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