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2026-02-13 - 17:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Fri Feb 13, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112429910183,11cyclictest14-21ksoftirqd/007:10:240
11242999881,10cyclictest14-21ksoftirqd/011:20:220
11242999877,11cyclictest14-21ksoftirqd/011:15:100
1061829726,25sleep10-21swapper/107:05:381
11250999551,24cyclictest26-21ksoftirqd/108:20:111
11242999363,17cyclictest14-21ksoftirqd/009:45:120
11242999166,17cyclictest14-21ksoftirqd/010:50:130
11242998659,18cyclictest14-21ksoftirqd/008:55:150
11242998458,17cyclictest14-21ksoftirqd/007:50:130
11242998355,19cyclictest14-21ksoftirqd/008:30:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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