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2026-01-16 - 17:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Fri Jan 16, 2026 12:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12736210132,23sleep10-21swapper/107:09:381
12904998857,17cyclictest14-21ksoftirqd/012:20:140
1290499877,67cyclictest29991-21apt-get07:55:130
12904998738,36cyclictest14-21ksoftirqd/010:50:130
12904998716,63cyclictest0-21swapper/009:25:140
12904998716,63cyclictest0-21swapper/009:25:140
12904998714,18cyclictest0-21swapper/007:15:350
12904998714,18cyclictest0-21swapper/007:15:340
12904998618,57cyclictest0-21swapper/010:00:130
12904998615,63cyclictest0-21swapper/009:50:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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