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2026-01-15 - 13:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Thu Jan 15, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29708998969,13cyclictest14-21ksoftirqd/023:55:130
29715998447,20cyclictest26-21ksoftirqd/123:35:111
2796928133,36sleep10-21swapper/119:05:121
29708997961,9cyclictest14-21ksoftirqd/022:55:130
29708997961,9cyclictest14-21ksoftirqd/022:55:120
29708997916,19cyclictest0-21swapper/022:45:140
284022780,8sleep00-21swapper/019:05:210
29708997414,54cyclictest0-21swapper/022:00:100
29708997353,11cyclictest14-21ksoftirqd/021:10:140
29715997241,17cyclictest500-21snmpd19:49:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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