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2026-02-14 - 17:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Sat Feb 14, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
992921190,8sleep1251rcuc/107:25:021
1317021060,6chrt13172-21sed12:05:451
3762210021,66sleep10-21swapper/107:08:031
4125999918,18cyclictest0-21swapper/007:10:130
4125999538,18cyclictest14-21ksoftirqd/012:25:160
4125999412,19cyclictest0-21swapper/011:30:140
412599936,20cyclictest24412-21apt-get08:05:120
4125999315,17cyclictest0-21swapper/012:00:140
4125999314,18cyclictest0-21swapper/011:35:140
4125999313,19cyclictest0-21swapper/011:10:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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