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2026-02-23 - 07:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Mon Feb 23, 2026 00:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1833921120,7chrt18335-21grep20:25:370
2138729032,47sleep10-21swapper/119:06:101
21920998936,16cyclictest0-21swapper/023:20:130
21920998530,50cyclictest488-21gdbus22:20:000
21920998514,56cyclictest0-21swapper/020:05:120
21920998462,9cyclictest14-21ksoftirqd/020:10:160
2192099842,75cyclictest19277-21taskset23:32:230
21920998415,55cyclictest0-21swapper/019:40:110
21920998414,56cyclictest0-21swapper/019:10:100
185832840,5sleep118585-21basename22:00:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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