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2026-02-01 - 05:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Sun Feb 01, 2026 00:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2730629019,27sleep00-21swapper/019:08:210
2764399882,79cyclictest12491-21apt-get00:35:120
27649998713,64cyclictest0-21swapper/121:15:131
27649998312,59cyclictest0-21swapper/121:45:131
27649998312,58cyclictest0-21swapper/121:00:111
2764999827,63cyclictest2800-21apt-get19:30:141
2764999826,60cyclictest9061-21apt-get22:50:141
27649998214,54cyclictest0-21swapper/119:45:131
27649998213,58cyclictest0-21swapper/120:10:161
27649998212,59cyclictest0-21swapper/121:40:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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