You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-05 - 13:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Thu Feb 05, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22560999715,18cyclictest0-21swapper/012:35:240
22560999511,77cyclictest0-21swapper/008:10:130
2256099949,38cyclictest500-21snmpd12:15:120
22560999420,18cyclictest0-21swapper/011:45:150
22560999320,16cyclictest0-21swapper/010:40:120
22560999315,16cyclictest0-21swapper/011:50:140
22560999315,16cyclictest0-21swapper/011:50:130
22560999219,17cyclictest0-21swapper/010:30:120
22560999215,18cyclictest0-21swapper/007:40:230
22560999214,19cyclictest0-21swapper/008:25:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional