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2025-05-09 - 05:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Fri May 09, 2025 00:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19568210418,39sleep00-21swapper/019:05:080
2074529929,24sleep10-21swapper/119:05:481
21339999516,17cyclictest0-21swapper/119:35:141
21339999515,18cyclictest0-21swapper/120:10:151
21339999418,18cyclictest0-21swapper/123:30:161
21339999415,17cyclictest0-21swapper/122:20:121
21339999314,17cyclictest0-21swapper/121:35:141
21339999133,21cyclictest420-21dbus-daemon00:39:001
21339999117,19cyclictest0-21swapper/120:30:131
21339999117,16cyclictest0-21swapper/123:00:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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