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2026-01-21 - 07:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Wed Jan 21, 2026 00:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18571215893,36sleep10-21swapper/119:05:171
19987999214,65cyclictest0-21swapper/121:05:131
19987999115,67cyclictest0-21swapper/119:20:161
19980999135,49cyclictest8240-21ntp_states23:05:280
19987998914,63cyclictest0-21swapper/121:00:161
19987998914,60cyclictest0-21swapper/120:10:121
19987998816,61cyclictest0-21swapper/122:50:141
19987998815,65cyclictest0-21swapper/122:25:141
19980998735,44cyclictest24292-21irqstats20:50:230
19980998733,47cyclictest2598-21/usr/sbin/munin00:20:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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