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2026-02-10 - 16:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Feb 10, 2026 12:45:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
266659911788,19cyclictest14-21ksoftirqd/010:35:150
266659911178,21cyclictest14-21ksoftirqd/009:25:120
266659911178,19cyclictest14-21ksoftirqd/011:35:120
266659911178,19cyclictest14-21ksoftirqd/011:35:110
266659911039,58cyclictest14-21ksoftirqd/007:35:120
266739910866,31cyclictest26-21ksoftirqd/111:20:121
266739910811,84cyclictest0-21swapper/110:00:121
266739910759,36cyclictest26-21ksoftirqd/108:50:221
26673991066,88cyclictest65-1kworker/1:1H07:40:131
266739910513,80cyclictest0-21swapper/108:15:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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