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2026-02-07 - 03:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Sat Feb 07, 2026 00:45:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236669911282,20cyclictest14-21ksoftirqd/022:10:120
236669910069,19cyclictest14-21ksoftirqd/023:25:130
236669910068,18cyclictest14-21ksoftirqd/023:20:210
23666999972,18cyclictest14-21ksoftirqd/021:05:110
23666999868,20cyclictest14-21ksoftirqd/019:30:110
23666999867,17cyclictest14-21ksoftirqd/022:25:150
23666999765,19cyclictest14-21ksoftirqd/022:05:120
23671999610,22cyclictest0-21swapper/121:35:221
23666999670,16cyclictest14-21ksoftirqd/021:20:110
23666999667,16cyclictest14-21ksoftirqd/000:35:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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