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2026-01-27 - 23:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Jan 27, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8239210538,19sleep10-21swapper/107:08:541
8548998972,11cyclictest26-21ksoftirqd/108:05:141
8548998453,18cyclictest26-21ksoftirqd/108:15:111
8548998355,17cyclictest26-21ksoftirqd/111:10:121
8548998154,17cyclictest26-21ksoftirqd/108:55:151
8543998023,11cyclictest0-21swapper/011:05:130
8548997952,16cyclictest26-21ksoftirqd/110:05:131
854899787,22cyclictest26-21ksoftirqd/109:40:011
8548997749,15cyclictest26-21ksoftirqd/107:15:151
854399764,62cyclictest6136-21apt-get11:35:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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