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2026-02-08 - 23:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Sun Feb 08, 2026 12:45:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1608399968,70cyclictest0-21swapper/010:30:150
1608399956,71cyclictest0-21swapper/008:35:130
16083999514,61cyclictest0-21swapper/007:30:220
1551229436,46sleep10-21swapper/107:05:571
1551229436,46sleep10-21swapper/107:05:571
16088999265,17cyclictest26-21ksoftirqd/107:35:151
16088999265,17cyclictest26-21ksoftirqd/107:35:141
16088999265,15cyclictest26-21ksoftirqd/111:55:121
16088999265,15cyclictest26-21ksoftirqd/109:50:131
16088999059,17cyclictest13850irq/14-ata_piix08:20:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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