You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-18 - 18:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Wed Feb 18, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1914829719,32sleep10-21swapper/107:05:101
20899998346,21cyclictest12294-21apt-get08:15:161
2053828020,51sleep00-21swapper/007:08:090
20899997949,15cyclictest7127-21apt-get12:35:121
20899997941,23cyclictest22301-21apt-get10:15:161
20899997941,23cyclictest22301-21apt-get10:15:161
20899997851,19cyclictest31602-21apt-get09:10:151
20899997847,15cyclictest29036-21apt-get12:05:121
20899997846,23cyclictest7027-21apt-get08:00:131
20899997841,23cyclictest1907-21apt-get12:20:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional