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2026-01-19 - 18:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Mon Jan 19, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2036529118,27sleep00-21swapper/007:05:480
2036529118,27sleep00-21swapper/007:05:470
291082900,6chrt29110-21swap12:00:350
48562860,5sleep14857-21basename10:55:141
20944998139,29cyclictest26-21ksoftirqd/111:35:141
20942997432,37cyclictest5520-21telnet09:25:170
20942997327,8cyclictest14-21ksoftirqd/010:09:010
20942997310,32cyclictest32369-21diskmemload09:10:130
1953027332,28sleep10-21swapper/107:05:191
1953027332,28sleep10-21swapper/107:05:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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