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2026-02-10 - 03:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Feb 10, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
844821270,9sleep0171rcuc/019:25:350
322902985,35sleep032397-21aten2.4_r3power19:05:160
186882920,9chrt0-21swapper/123:00:171
1598998560,12cyclictest26-21ksoftirqd/123:10:151
1598998157,20cyclictest26-21ksoftirqd/100:00:041
1598998053,13cyclictest26-21ksoftirqd/121:45:131
1598997644,17cyclictest26-21ksoftirqd/120:00:221
322132740,8chrt0-21swapper/120:35:021
1592997434,35cyclictest14-21ksoftirqd/023:35:270
1592997330,28cyclictest19310-21ntp_states23:00:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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