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2026-01-14 - 04:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Wed Jan 14, 2026 00:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64132988,77sleep06535-21df19:05:140
7959998664,15cyclictest0-21swapper/019:45:110
7959998664,15cyclictest0-21swapper/019:45:110
7959998146,23cyclictest4453-21apt-get20:30:120
7959998045,23cyclictest25879-21apt-get23:00:120
7965997842,25cyclictest26-21ksoftirqd/122:35:111
7959997847,14cyclictest973-21apt-get20:20:120
7959997746,15cyclictest13798-21apt-get19:25:130
7959997659,9cyclictest14-21ksoftirqd/021:20:130
7959997658,10cyclictest14-21ksoftirqd/022:25:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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