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2026-01-22 - 20:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Thu Jan 22, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1543721340,6chrt15440-21sed08:25:020
202999911688,17cyclictest26-21ksoftirqd/109:05:241
202999911684,21cyclictest26-21ksoftirqd/112:20:121
202999911684,21cyclictest26-21ksoftirqd/112:20:121
202969911612,89cyclictest0-21swapper/011:05:120
202999911587,18cyclictest26-21ksoftirqd/111:10:241
202999911185,17cyclictest26-21ksoftirqd/108:40:111
202999911180,20cyclictest26-21ksoftirqd/107:45:141
202999910979,19cyclictest26-21ksoftirqd/109:10:141
202999910880,19cyclictest26-21ksoftirqd/110:55:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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