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2026-01-13 - 23:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Jan 13, 2026 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1251929637,41sleep00-21swapper/007:05:230
1381599867,70cyclictest5422-21apt-get09:50:121
13815998310,65cyclictest0-21swapper/112:10:121
1380999826,20cyclictest27119-21apt-get07:45:120
13815998023,52cyclictest448-21dbus-daemon07:38:091
13815997823,50cyclictest448-21dbus-daemon09:40:001
13815997823,49cyclictest31817-21aten2.4_r3power11:05:171
13815997811,51cyclictest0-21swapper/107:40:151
1380999786,62cyclictest15678-21apt-get11:50:220
1381599777,55cyclictest1063-21apt-get11:10:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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