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2026-02-17 - 18:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Feb 17, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2497329318,28sleep00-21swapper/007:09:030
25202999162,16cyclictest0-21swapper/007:20:130
2505529130,49sleep10-21swapper/107:09:571
25202998858,16cyclictest0-21swapper/011:35:130
25202998762,11cyclictest14-21ksoftirqd/012:35:090
25202998459,13cyclictest14-21ksoftirqd/009:35:130
25202998459,13cyclictest14-21ksoftirqd/007:35:130
25202998154,13cyclictest14-21ksoftirqd/010:20:250
25202998064,9cyclictest14-21ksoftirqd/010:30:130
25202997955,12cyclictest14-21ksoftirqd/010:00:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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