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2026-07-09 - 15:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Thu Jul 09, 2026 12:45:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18652210733,25sleep10-21swapper/107:08:021
86862950,8sleep00-21swapper/008:10:160
19010999334,47cyclictest0-21swapper/011:55:120
19010999334,47cyclictest0-21swapper/011:55:120
19010998820,14cyclictest0-21swapper/011:15:120
19010998820,14cyclictest0-21swapper/011:15:120
184592846,16sleep00-21swapper/007:05:550
19010998126,15cyclictest3058-21sed09:20:370
1901099805,42cyclictest0-21swapper/008:38:120
19010998012,34cyclictest457-21dbus-daemon08:09:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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