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2026-02-21 - 19:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Sat Feb 21, 2026 12:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
75779912214,21cyclictest0-21swapper/109:20:261
194021160,5chrt1081-21/usr/sbin/munin11:20:431
375421140,6sleep10-21swapper/111:25:351
75729911081,16cyclictest14-21ksoftirqd/009:50:110
75729910371,18cyclictest14-21ksoftirqd/010:55:120
7572999464,19cyclictest14-21ksoftirqd/008:25:110
7572999463,21cyclictest14-21ksoftirqd/010:10:130
7572999262,20cyclictest14-21ksoftirqd/009:55:130
7572999161,19cyclictest14-21ksoftirqd/008:40:130
7572999110,66cyclictest0-21swapper/010:20:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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