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2026-08-17 - 19:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Mon Aug 17, 2026 12:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305299910141,52cyclictest13770-21runrttasks10:55:111
30529999516,68cyclictest0-21swapper/108:05:141
30529999413,73cyclictest0-21swapper/109:35:131
3011229422,26sleep00-21swapper/007:07:370
30529999316,69cyclictest0-21swapper/110:45:131
30529999312,72cyclictest0-21swapper/112:35:131
3007429329,19sleep10-21swapper/107:07:111
30529999226,23cyclictest457-21dbus-daemon10:55:011
30529999216,63cyclictest0-21swapper/109:50:111
30529999214,65cyclictest0-21swapper/111:20:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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