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2026-01-23 - 22:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Fri Jan 23, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2730821360,6chrt27305-21latency_hist12:40:000
1214529727,24sleep10-21swapper/107:06:171
1268699925,60cyclictest0-21swapper/108:50:321
12681998817,56cyclictest0-21swapper/010:05:130
12681998816,57cyclictest0-21swapper/007:45:140
1268199879,71cyclictest15903-21runrttasks12:05:110
12681998717,60cyclictest0-21swapper/010:10:130
12681998669,11cyclictest14-21ksoftirqd/012:25:210
1268199865,72cyclictest26312-21apt-get09:15:150
12681998618,57cyclictest0-21swapper/008:45:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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