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2026-02-24 - 08:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Feb 24, 2026 00:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
141159910760,27cyclictest14-21ksoftirqd/020:10:150
1411599917,66cyclictest0-21swapper/023:55:120
14115999147,24cyclictest14-21ksoftirqd/020:30:140
14115999147,24cyclictest14-21ksoftirqd/020:30:140
14117998354,20cyclictest26-21ksoftirqd/119:10:151
1411599826,58cyclictest0-21swapper/021:45:160
14115998225,43cyclictest0-21swapper/023:25:160
14117998157,14cyclictest26-21ksoftirqd/120:25:231
14115997915,50cyclictest14-21ksoftirqd/022:15:150
135632797,24sleep10-21swapper/119:06:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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