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2026-02-09 - 20:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Mon Feb 09, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51039911076,22cyclictest26-21ksoftirqd/111:10:131
5100991088,84cyclictest15902-21apache209:25:140
51009910712,82cyclictest0-21swapper/008:45:100
51009910666,26cyclictest14-21ksoftirqd/012:35:130
51009910310,81cyclictest0-21swapper/011:00:130
51039910257,33cyclictest26-21ksoftirqd/109:35:151
5100991018,78cyclictest9510-21runrttasks07:20:120
51009910153,39cyclictest14-21ksoftirqd/009:45:140
51009910057,31cyclictest14-21ksoftirqd/010:50:140
5103999828,57cyclictest27499-21sshd08:10:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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