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2026-02-22 - 19:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Sun Feb 22, 2026 12:45:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2795729118,27sleep00-21swapper/007:09:200
28150999042,16cyclictest0-21swapper/008:25:120
28150998917,57cyclictest0-21swapper/010:20:140
28150998917,57cyclictest0-21swapper/010:20:130
28150998914,63cyclictest0-21swapper/011:25:160
28150998914,62cyclictest0-21swapper/012:35:130
28156998718,43cyclictest0-21swapper/108:05:211
2815099877,64cyclictest17261-21apt-get09:40:110
28150998715,59cyclictest0-21swapper/011:40:130
28150998715,59cyclictest0-21swapper/008:35:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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