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2026-03-03 - 12:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Tue Mar 03, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2083129118,27sleep00-21swapper/019:08:080
2069329116,30sleep10-21swapper/119:06:411
84442850,17sleep0448-21dbus-daemon20:04:590
82582780,5sleep08256-21grep21:35:010
293832740,6sleep029386-21grep22:30:350
21189997457,12cyclictest14-21ksoftirqd/019:20:130
21189997451,15cyclictest0-21swapper/021:25:120
21189997415,17cyclictest0-21swapper/023:35:130
239552730,6sleep123957-21grep20:45:381
21189997236,26cyclictest5114-21apt-get19:55:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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