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2026-02-25 - 20:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Wed Feb 25, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14630210337,19sleep10-21swapper/107:08:581
137182946,78sleep013842-21awk07:05:230
14913998814,60cyclictest0-21swapper/009:40:130
14913998714,59cyclictest0-21swapper/012:20:150
1491399864,75cyclictest1108-21ls11:00:360
14913998620,51cyclictest0-21swapper/011:35:100
14913998515,59cyclictest0-21swapper/012:15:130
14913998515,59cyclictest0-21swapper/012:15:120
14913998515,58cyclictest0-21swapper/010:45:130
14913998514,57cyclictest0-21swapper/008:35:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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