You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-27 - 12:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack3slot6.osadl.org (updated Fri Feb 27, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53889910890,12cyclictest14-21ksoftirqd/021:25:130
5388999261,17cyclictest0-21swapper/022:05:120
5388998963,13cyclictest14-21ksoftirqd/000:35:120
5388998864,12cyclictest14-21ksoftirqd/000:05:120
5388998860,16cyclictest0-21swapper/000:10:150
5388998766,11cyclictest14-21ksoftirqd/022:30:130
5388998659,13cyclictest14-21ksoftirqd/019:15:130
5388998561,13cyclictest14-21ksoftirqd/021:35:120
5388998458,16cyclictest14-21ksoftirqd/023:25:150
5388998357,14cyclictest14-21ksoftirqd/000:30:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional