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2026-02-26 - 20:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Thu Feb 26, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
66582959,12sleep00-21swapper/007:06:330
7168998914,58cyclictest0-21swapper/111:25:101
716399876,73cyclictest0-21swapper/009:40:110
716899869,62cyclictest23734-21apt-get10:55:131
7168998620,56cyclictest32439-21seq08:20:091
7168998618,54cyclictest0-21swapper/108:15:131
7168998615,57cyclictest0-21swapper/108:10:161
716899856,20cyclictest23486-21apt-get12:25:131
7168998515,57cyclictest0-21swapper/109:45:231
7168998515,56cyclictest0-21swapper/112:35:131
7168998514,58cyclictest0-21swapper/111:40:101
716399857,63cyclictest0-21swapper/010:45:240
7163998519,59cyclictest548-21runrttasks09:25:140
685028522,17sleep10-21swapper/107:08:371
7168998414,54cyclictest0-21swapper/107:45:131
7168998413,60cyclictest0-21swapper/111:35:131
716399846,70cyclictest0-21swapper/008:00:110
716399846,67cyclictest0-21swapper/008:55:240
716899839,60cyclictest18416-21apt-get07:40:111
716899838,64cyclictest20256-21apt-get10:45:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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