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2026-01-29 - 09:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Thu Jan 29, 2026 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31967991059,76cyclictest0-21swapper/020:40:150
31967991048,77cyclictest0-21swapper/000:05:150
31967991048,77cyclictest0-21swapper/000:05:140
31967991048,72cyclictest0-21swapper/021:20:120
31967991039,73cyclictest0-21swapper/020:30:110
31967991027,87cyclictest0-21swapper/022:40:150
319739910140,16cyclictest0-21swapper/122:30:111
31967991008,72cyclictest0-21swapper/020:10:140
3196799997,73cyclictest0-21swapper/022:15:120
3196799997,72cyclictest0-21swapper/022:20:140
3196799995,66cyclictest0-21swapper/000:20:290
31973999838,14cyclictest0-21swapper/121:55:121
31973999814,19cyclictest0-21swapper/122:40:131
31973999813,21cyclictest0-21swapper/123:10:131
31973999810,36cyclictest462-21gmain00:00:141
3196799988,72cyclictest0-21swapper/000:25:120
3196799988,68cyclictest0-21swapper/023:05:120
3196799978,71cyclictest0-21swapper/000:35:110
31973999615,19cyclictest0-21swapper/100:05:121
31973999615,19cyclictest0-21swapper/100:05:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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