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2026-02-08 - 09:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sun Feb 08, 2026 00:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158219911785,21cyclictest26-21ksoftirqd/121:15:141
158219911481,22cyclictest26-21ksoftirqd/121:10:111
158079911180,19cyclictest14-21ksoftirqd/000:30:120
158079910978,19cyclictest14-21ksoftirqd/000:05:120
158079910978,19cyclictest14-21ksoftirqd/000:05:110
158219910768,28cyclictest26-21ksoftirqd/120:40:151
158079910612,80cyclictest0-21swapper/019:15:100
158079910575,17cyclictest14-21ksoftirqd/023:40:110
158219910464,31cyclictest26-21ksoftirqd/120:50:121
158079910212,77cyclictest0-21swapper/000:00:280
158219910159,31cyclictest26-21ksoftirqd/121:05:131
158219910155,37cyclictest26-21ksoftirqd/121:50:111
15604210137,19sleep10-21swapper/119:09:511
158079910071,17cyclictest14-21ksoftirqd/023:35:130
15807999912,30cyclictest0-21swapper/021:40:120
1580799989,60cyclictest0-21swapper/023:15:260
15821999540,41cyclictest26-21ksoftirqd/119:40:141
15821999511,68cyclictest0-21swapper/100:30:141
15807999561,23cyclictest0-21swapper/000:25:110
15821999446,28cyclictest26-21ksoftirqd/122:50:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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