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2026-02-19 - 17:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Thu Feb 19, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
873221250,5sleep10-21swapper/108:20:151
15619210330,25sleep10-21swapper/107:09:361
157899910173,13cyclictest14-21ksoftirqd/007:35:130
157899910075,14cyclictest14-21ksoftirqd/010:45:110
15789999971,18cyclictest14-21ksoftirqd/007:30:140
15789999872,15cyclictest14-21ksoftirqd/008:00:120
15789999668,17cyclictest14-21ksoftirqd/010:20:140
15789999663,19cyclictest0-21swapper/007:25:120
15789999366,16cyclictest14-21ksoftirqd/010:55:130
15789999362,17cyclictest0-21swapper/012:30:140
15789999362,17cyclictest0-21swapper/007:15:110
15789999266,14cyclictest14-21ksoftirqd/011:35:120
15789999167,13cyclictest14-21ksoftirqd/012:15:140
318592890,5chrt0-21swapper/110:55:271
15789998961,19cyclictest14-21ksoftirqd/008:20:130
15789998960,18cyclictest14-21ksoftirqd/011:55:150
15789998956,19cyclictest14-21ksoftirqd/009:50:120
15789998861,17cyclictest14-21ksoftirqd/012:35:150
15796998725,18cyclictest26791-31find07:40:281
15789998762,16cyclictest14-21ksoftirqd/011:20:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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