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2026-01-20 - 03:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Tue Jan 20, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1585221650,6sleep1251rcuc/119:10:011
1534029917,31sleep00-21swapper/019:06:330
15850999167,11cyclictest14-21ksoftirqd/000:30:130
15850998963,16cyclictest0-21swapper/000:25:130
15850998768,10cyclictest14-21ksoftirqd/019:15:150
15850998563,11cyclictest14-21ksoftirqd/023:00:120
15850998360,12cyclictest14-21ksoftirqd/023:50:120
15850998351,25cyclictest10638-21seq21:55:140
15850998160,12cyclictest14-21ksoftirqd/000:15:110
15850997955,14cyclictest14-21ksoftirqd/022:10:120
15850997951,15cyclictest14-21ksoftirqd/023:15:230
15850997850,18cyclictest14-21ksoftirqd/019:20:250
15850997748,18cyclictest14-21ksoftirqd/020:35:240
206992730,5sleep10-21swapper/120:50:291
15850997344,17cyclictest0-21swapper/000:05:140
15850997242,20cyclictest14-21ksoftirqd/022:40:130
15850997241,20cyclictest0-21swapper/023:25:120
15850997145,18cyclictest14-21ksoftirqd/022:05:140
15850997143,18cyclictest0-21swapper/000:20:250
15850997143,16cyclictest0-21swapper/020:05:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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