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2026-02-06 - 21:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Fri Feb 06, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1768921330,5chrt17688-21sshd11:27:091
225879911469,32cyclictest26-21ksoftirqd/110:25:111
225879911412,76cyclictest0-21swapper/108:45:111
225879911365,33cyclictest26-21ksoftirqd/107:25:131
225849911315,34cyclictest0-21swapper/009:40:100
225849911311,34cyclictest0-21swapper/007:35:140
225849911112,36cyclictest0-21swapper/009:50:120
225849911112,36cyclictest0-21swapper/009:50:110
225849911012,32cyclictest0-21swapper/007:40:130
225879910757,31cyclictest26-21ksoftirqd/109:35:121
225879910756,29cyclictest26-21ksoftirqd/111:35:141
225879910011,64cyclictest0-21swapper/112:30:131
22584999811,38cyclictest36-21kcompactd011:55:140
2258799978,64cyclictest1033-21diskmemload09:10:141
22587999711,60cyclictest0-21swapper/108:25:121
86892960,6chrt8684-21grep11:00:370
22587999612,60cyclictest0-21swapper/111:30:141
2258799957,24cyclictest0-21swapper/107:20:121
22587999510,61cyclictest0-21swapper/108:00:111
22587999413,56cyclictest0-21swapper/110:55:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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