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2026-05-28 - 16:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Thu May 28, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3108129028,51sleep10-21swapper/107:06:011
31643998969,12cyclictest26-21ksoftirqd/107:45:121
31643997952,14cyclictest26-21ksoftirqd/111:55:121
31643997948,15cyclictest26-21ksoftirqd/108:10:131
31643997746,19cyclictest26-21ksoftirqd/111:35:121
2989527728,37sleep00-21swapper/007:05:110
31643997445,19cyclictest26-21ksoftirqd/112:05:121
31643997445,19cyclictest26-21ksoftirqd/109:20:141
31643997240,18cyclictest0-21swapper/108:40:131
31643997125,11cyclictest26-21ksoftirqd/112:19:481
3163999718,6cyclictest151rcu_preempt09:00:220
31639997137,29cyclictest14-21ksoftirqd/011:30:360
31639997133,32cyclictest14-21ksoftirqd/010:20:120
31643997040,17cyclictest0-21swapper/107:30:111
31643997040,17cyclictest0-21swapper/107:30:111
31643997027,39cyclictest26-21ksoftirqd/107:51:441
31643997013,8cyclictest151rcu_preempt11:25:011
31639997035,20cyclictest14-21ksoftirqd/010:43:210
31643996940,16cyclictest26-21ksoftirqd/107:40:151
31643996940,15cyclictest0-21swapper/110:25:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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