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2026-02-09 - 13:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Mon Feb 09, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
84349910787,11cyclictest14-21ksoftirqd/022:50:160
84439910358,25cyclictest26-21ksoftirqd/100:25:161
8443999956,24cyclictest26-21ksoftirqd/123:05:131
8443999754,23cyclictest26-21ksoftirqd/121:40:231
8443999454,21cyclictest26-21ksoftirqd/121:55:141
8434999168,11cyclictest14-21ksoftirqd/023:35:110
8434998958,17cyclictest14-21ksoftirqd/021:35:130
8434998861,18cyclictest14-21ksoftirqd/019:20:120
8434998757,16cyclictest14-21ksoftirqd/000:10:130
8434998657,19cyclictest14-21ksoftirqd/021:40:260
8434998559,13cyclictest14-21ksoftirqd/020:10:150
823128527,47sleep10-21swapper/119:09:191
8434998459,14cyclictest14-21ksoftirqd/020:20:130
8434998457,18cyclictest14-21ksoftirqd/019:40:120
8434998454,19cyclictest14-21ksoftirqd/021:00:150
8434998355,17cyclictest14-21ksoftirqd/022:35:230
8434998253,16cyclictest14-21ksoftirqd/000:25:160
8434998161,12cyclictest14-21ksoftirqd/021:45:110
8434998152,20cyclictest14-21ksoftirqd/019:50:140
8434998054,16cyclictest14-21ksoftirqd/000:30:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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