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2026-01-26 - 06:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Mon Jan 26, 2026 00:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
175509911282,20cyclictest14-21ksoftirqd/022:45:140
175509911162,38cyclictest14-21ksoftirqd/023:50:210
175509910774,19cyclictest14-21ksoftirqd/021:35:210
175509910617,73cyclictest0-21swapper/023:10:120
17220210520,40sleep00-21swapper/019:08:250
175569910454,34cyclictest26-21ksoftirqd/122:35:151
175509910475,17cyclictest14-21ksoftirqd/000:25:250
175569910361,29cyclictest26-21ksoftirqd/121:00:121
175509910374,18cyclictest14-21ksoftirqd/019:50:150
175509910311,76cyclictest0-21swapper/019:20:170
175509910218,57cyclictest548-21runrttasks22:50:310
175569910153,33cyclictest26-21ksoftirqd/121:45:151
175509910151,37cyclictest14-21ksoftirqd/020:05:140
17550999864,20cyclictest0-21swapper/019:15:120
17550999765,21cyclictest14-21ksoftirqd/019:10:110
17556999613,26cyclictest0-21swapper/121:30:131
17556999412,65cyclictest0-21swapper/123:45:111
17556999412,62cyclictest0-21swapper/123:10:111
17550999451,29cyclictest14-21ksoftirqd/020:30:260
17556999312,27cyclictest0-21swapper/121:10:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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