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2026-04-24 - 06:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Fri Apr 24, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117159910814,81cyclictest0-21swapper/021:05:130
117159910563,30cyclictest14-21ksoftirqd/023:20:120
117159910513,27cyclictest0-21swapper/000:15:110
117199910433,57cyclictest0-21swapper/100:05:141
11715991049,82cyclictest0-21swapper/020:40:130
117159910467,25cyclictest0-21swapper/020:00:120
117159910466,26cyclictest14-21ksoftirqd/022:50:230
117159910366,24cyclictest0-21swapper/022:20:120
117159910366,23cyclictest0-21swapper/021:40:120
117159910363,29cyclictest14-21ksoftirqd/022:05:110
11258210229,24sleep10-21swapper/119:07:121
117159910112,77cyclictest0-21swapper/020:10:120
117159910060,27cyclictest0-21swapper/023:35:130
11715999853,34cyclictest14-21ksoftirqd/021:20:140
11719999452,30cyclictest26-21ksoftirqd/120:30:111
11719999450,33cyclictest26-21ksoftirqd/122:55:121
11719999346,35cyclictest26-21ksoftirqd/119:25:141
11715999314,62cyclictest0-21swapper/021:55:170
11715999214,66cyclictest0-21swapper/023:10:130
11715999211,66cyclictest0-21swapper/019:10:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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