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2025-11-29 - 23:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Sat Nov 29, 2025 12:45:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3098621360,6sleep0448-21dbus-daemon07:25:000
2463829623,27sleep00-21swapper/007:08:030
2478628527,46sleep10-21swapper/107:09:081
34552770,8sleep0171rcuc/012:10:010
25004997628,43cyclictest26-21ksoftirqd/111:53:191
25004997612,58cyclictest0-21swapper/111:05:121
25004997526,8cyclictest26-21ksoftirqd/109:30:491
40572690,6sleep04059-21grep07:40:010
25004996952,10cyclictest26-21ksoftirqd/107:40:131
25004996928,36cyclictest26-21ksoftirqd/109:10:271
25000996836,27cyclictest14-21ksoftirqd/010:52:190
2500099665,53cyclictest7632-21apt-get07:50:130
2500099665,52cyclictest18218-21apt-get11:20:240
25004996515,36cyclictest26-21ksoftirqd/107:15:241
25004996423,37cyclictest26-21ksoftirqd/110:35:321
25000996435,24cyclictest14-21ksoftirqd/010:15:200
25000996432,26cyclictest14-21ksoftirqd/009:10:210
25004996343,13cyclictest14971-21smartctl11:10:361
25004996343,13cyclictest14971-21smartctl11:10:351
25004996338,9cyclictest26-21ksoftirqd/109:23:341
2500099636,49cyclictest16438-21apt-get09:45:130
25004996234,8cyclictest26-21ksoftirqd/111:26:321
25000996237,19cyclictest14-21ksoftirqd/009:30:240
25000996233,24cyclictest14-21ksoftirqd/009:20:150
25000996222,24cyclictest14-21ksoftirqd/008:44:350
25004996138,8cyclictest26-21ksoftirqd/111:36:341
25004996138,8cyclictest26-21ksoftirqd/111:36:331
25004996137,9cyclictest26-21ksoftirqd/111:55:421
25004996137,9cyclictest26-21ksoftirqd/111:55:411
2500099615,16cyclictest25553-21apt-get11:40:170
25000996144,10cyclictest14-21ksoftirqd/008:50:240
25000996137,18cyclictest14-21ksoftirqd/010:29:210
25004996036,9cyclictest26-21ksoftirqd/107:23:521
25004996036,10cyclictest26-21ksoftirqd/110:10:581
25004996035,9cyclictest26-21ksoftirqd/109:37:421
2500499602,35cyclictest151rcu_preempt08:58:101
25000996037,17cyclictest14-21ksoftirqd/007:12:530
25000996036,18cyclictest14-21ksoftirqd/010:38:050
25004995936,8cyclictest26-21ksoftirqd/108:50:571
25004995936,8cyclictest26-21ksoftirqd/108:01:531
25004995935,9cyclictest26-21ksoftirqd/112:13:331
25004995935,8cyclictest26-21ksoftirqd/109:40:581
25004995934,9cyclictest26-21ksoftirqd/112:17:551
25000995936,18cyclictest14-21ksoftirqd/010:57:550
25000995936,18cyclictest14-21ksoftirqd/009:25:150
25000995935,18cyclictest14-21ksoftirqd/012:12:110
25000995935,18cyclictest14-21ksoftirqd/011:12:540
25000995935,18cyclictest14-21ksoftirqd/011:12:530
25004995836,8cyclictest26-21ksoftirqd/108:29:031
25004995835,9cyclictest26-21ksoftirqd/110:25:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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