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2026-04-24 - 05:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Fri Apr 24, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117159910814,81cyclictest0-21swapper/021:05:130
117159910563,30cyclictest14-21ksoftirqd/023:20:120
117159910513,27cyclictest0-21swapper/000:15:110
117199910433,57cyclictest0-21swapper/100:05:141
11715991049,82cyclictest0-21swapper/020:40:130
117159910467,25cyclictest0-21swapper/020:00:120
117159910466,26cyclictest14-21ksoftirqd/022:50:230
117159910366,24cyclictest0-21swapper/022:20:120
117159910366,23cyclictest0-21swapper/021:40:120
117159910363,29cyclictest14-21ksoftirqd/022:05:110
11258210229,24sleep10-21swapper/119:07:121
117159910112,77cyclictest0-21swapper/020:10:120
117159910060,27cyclictest0-21swapper/023:35:130
11715999853,34cyclictest14-21ksoftirqd/021:20:140
11719999452,30cyclictest26-21ksoftirqd/120:30:111
11719999450,33cyclictest26-21ksoftirqd/122:55:121
11719999346,35cyclictest26-21ksoftirqd/119:25:141
11715999314,62cyclictest0-21swapper/021:55:170
11715999214,66cyclictest0-21swapper/023:10:130
11715999211,66cyclictest0-21swapper/019:10:120
11719999114,64cyclictest0-21swapper/120:25:121
11719999114,63cyclictest0-21swapper/121:50:131
11715999114,61cyclictest0-21swapper/019:20:120
11719999010,66cyclictest0-21swapper/123:30:121
11715999044,28cyclictest14-21ksoftirqd/020:20:140
11715999011,66cyclictest0-21swapper/023:00:130
11719998947,29cyclictest26-21ksoftirqd/123:25:121
11719998938,34cyclictest26-21ksoftirqd/121:30:161
11719998912,64cyclictest0-21swapper/123:05:131
11719998912,64cyclictest0-21swapper/100:25:131
11719998911,66cyclictest0-21swapper/123:40:131
11719998911,66cyclictest0-21swapper/123:40:121
11719998911,64cyclictest0-21swapper/122:20:151
11715998940,34cyclictest14-21ksoftirqd/019:15:120
11715998939,41cyclictest14-21ksoftirqd/000:20:130
11715998935,43cyclictest14-21ksoftirqd/000:00:120
11715998914,62cyclictest0-21swapper/000:05:150
11715998912,61cyclictest0-21swapper/022:40:120
11715998912,61cyclictest0-21swapper/021:00:140
11715998912,61cyclictest0-21swapper/019:35:130
11715998911,62cyclictest0-21swapper/022:55:130
11715998911,62cyclictest0-21swapper/000:30:150
11715998911,58cyclictest0-21swapper/023:50:130
1171999888,61cyclictest30245-21chrt00:35:151
11719998812,63cyclictest0-21swapper/120:45:141
11719998810,64cyclictest0-21swapper/119:40:251
11719998810,62cyclictest0-21swapper/119:20:121
1171599888,62cyclictest22447-21diskmemload21:10:140
11715998811,23cyclictest0-21swapper/023:25:130
1171999877,62cyclictest562-21runrttasks23:45:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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