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2025-12-30 - 16:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Tue Dec 30, 2025 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178719911410,85cyclictest0-21swapper/110:30:121
178719911365,33cyclictest26-21ksoftirqd/107:55:141
178719911210,79cyclictest0-21swapper/111:10:131
178719910814,76cyclictest0-21swapper/108:10:131
178719910811,76cyclictest0-21swapper/110:50:151
178719910811,76cyclictest0-21swapper/110:20:131
178719910810,77cyclictest0-21swapper/111:40:151
17871991079,78cyclictest0-21swapper/111:55:131
17871991079,78cyclictest0-21swapper/111:55:121
178719910714,74cyclictest0-21swapper/107:15:141
178719910713,73cyclictest0-21swapper/110:15:101
178719910710,76cyclictest0-21swapper/108:55:131
178719910617,69cyclictest0-21swapper/111:50:271
178719910612,76cyclictest0-21swapper/110:25:151
178719910612,73cyclictest0-21swapper/112:30:141
178719910611,77cyclictest0-21swapper/107:35:131
178719910611,74cyclictest0-21swapper/108:30:131
17871991059,75cyclictest0-21swapper/109:05:131
17871991059,74cyclictest0-21swapper/109:20:141
178719910518,69cyclictest0-21swapper/111:05:151
178719910514,70cyclictest0-21swapper/107:10:141
178719910512,73cyclictest0-21swapper/112:20:131
178719910512,70cyclictest0-21swapper/109:55:111
178719910512,70cyclictest0-21swapper/109:45:131
178719910511,74cyclictest0-21swapper/112:15:131
178719910511,74cyclictest0-21swapper/110:45:251
178719910511,73cyclictest0-21swapper/111:30:151
178719910511,72cyclictest0-21swapper/108:05:181
178719910510,75cyclictest0-21swapper/111:00:151
178719910440,47cyclictest26-21ksoftirqd/112:35:121
178719910417,67cyclictest0-21swapper/108:25:151
178719910414,70cyclictest0-21swapper/108:40:241
178719910413,71cyclictest0-21swapper/112:25:131
178719910412,71cyclictest0-21swapper/110:00:161
178719910412,71cyclictest0-21swapper/110:00:151
178719910411,73cyclictest0-21swapper/109:50:161
178719910411,72cyclictest0-21swapper/107:45:141
178719910410,72cyclictest0-21swapper/108:15:171
178719910316,68cyclictest0-21swapper/110:35:151
178719910313,69cyclictest0-21swapper/108:50:161
178719910312,72cyclictest0-21swapper/109:30:171
178719910312,72cyclictest0-21swapper/107:30:151
178719910312,69cyclictest0-21swapper/107:25:111
178719910310,72cyclictest0-21swapper/112:10:171
178679910374,19cyclictest14-21ksoftirqd/010:35:120
17871991029,71cyclictest0-21swapper/108:45:141
17871991028,74cyclictest0-21swapper/108:20:121
178719910272,18cyclictest26-21ksoftirqd/109:25:151
178719910213,68cyclictest0-21swapper/111:35:151
178719910213,68cyclictest0-21swapper/111:35:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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