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2026-05-04 - 11:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Mon May 04, 2026 00:44:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2422621030,29chrt251rcuc/119:05:271
2334728130,39sleep00-21swapper/019:05:110
25098997929,45cyclictest26-21ksoftirqd/122:35:171
25098997732,26cyclictest26-21ksoftirqd/120:20:001
25098997533,36cyclictest26-21ksoftirqd/123:13:151
25098997330,38cyclictest26-21ksoftirqd/122:00:341
25098996749,12cyclictest26-21ksoftirqd/121:30:121
2277926723,24sleep00-21swapper/022:05:130
2509499667,22cyclictest2734-21apt-get00:10:130
2509499667,18cyclictest29198-21apt-get19:20:130
25094996610,51cyclictest0-21swapper/020:45:140
2509499659,51cyclictest0-21swapper/023:25:110
2509499658,52cyclictest0-21swapper/022:55:120
25094996530,29cyclictest14-21ksoftirqd/022:11:390
25094996436,12cyclictest14-21ksoftirqd/020:00:000
25098996319,8cyclictest26-21ksoftirqd/120:40:361
2509499638,13cyclictest0-21swapper/022:00:110
25094996328,12cyclictest14-21ksoftirqd/022:39:000
25098996225,13cyclictest26-21ksoftirqd/100:35:011
25098996223,13cyclictest26-21ksoftirqd/100:30:001
25098996223,13cyclictest26-21ksoftirqd/100:30:001
25098996221,14cyclictest26-21ksoftirqd/121:15:001
25098996123,14cyclictest26-21ksoftirqd/122:09:591
25098996117,13cyclictest26-21ksoftirqd/123:25:351
25094996137,19cyclictest32762-21df_inode21:00:200
2509499613,23cyclictest12349-21awk20:05:000
25098996036,18cyclictest26-21ksoftirqd/122:46:211
25098996022,14cyclictest26-21ksoftirqd/122:55:011
25094996036,18cyclictest14-21ksoftirqd/020:32:370
25094996025,20cyclictest14-21ksoftirqd/019:13:110
25094996024,12cyclictest14-21ksoftirqd/019:40:010
2509899599,7cyclictest151rcu_preempt21:15:331
25098995936,17cyclictest26-21ksoftirqd/123:56:431
25098995935,9cyclictest26-21ksoftirqd/123:54:521
25098995912,21cyclictest151rcu_preempt00:20:011
25094995935,8cyclictest14-21ksoftirqd/020:53:460
25094995934,18cyclictest14-21ksoftirqd/019:27:190
239722595,47sleep10-21swapper/120:35:221
25098995834,9cyclictest26-21ksoftirqd/120:21:151
25098995833,10cyclictest26-21ksoftirqd/122:11:111
25098995817,13cyclictest26-21ksoftirqd/123:40:051
25098995816,8cyclictest26-21ksoftirqd/122:20:461
2509499586,47cyclictest0-21swapper/020:10:340
25094995837,16cyclictest893-21needreboot19:30:270
25094995835,18cyclictest14-21ksoftirqd/021:25:160
25094995834,9cyclictest14-21ksoftirqd/023:53:510
25094995810,21cyclictest151rcu_preempt21:43:510
25098995735,9cyclictest26-21ksoftirqd/119:28:111
25098995735,17cyclictest26-21ksoftirqd/121:41:501
25098995735,17cyclictest26-21ksoftirqd/121:21:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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