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2026-01-31 - 02:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #3, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot6s.osadl.org (updated Sat Jan 31, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15693211895,18sleep00-21swapper/019:06:160
15890211594,16sleep30-21swapper/319:08:483
158022113102,6sleep20-21swapper/219:07:382
15654210083,11sleep10-21swapper/119:05:451
223082780,0sleep00-21swapper/022:07:540
269842690,0sleep00-21swapper/023:22:340
1601399280,2cyclictest0-21swapper/121:40:111
1601499222,15cyclictest0-21swapper/219:31:042
1601499220,20cyclictest0-21swapper/200:20:102
1601399221,19cyclictest0-21swapper/100:05:121
1601499210,19cyclictest0-21swapper/222:45:112
1601399211,2cyclictest0-21swapper/123:05:121
1601399211,2cyclictest0-21swapper/123:05:111
1601499200,2cyclictest0-21swapper/220:50:102
1601399200,2cyclictest0-21swapper/120:15:121
1601399200,18cyclictest0-21swapper/122:15:101
1601299200,2cyclictest0-21swapper/020:50:100
1601299200,19cyclictest0-21swapper/000:20:100
1601399191,2cyclictest0-21swapper/120:10:111
16014991815,2cyclictest17939-21kworker/u8:221:19:042
1601599171,3cyclictest0-21swapper/321:35:003
1601499172,2cyclictest0-21swapper/222:24:042
16014991714,2cyclictest3383-21kworker/u8:200:15:052
1601499171,14cyclictest0-21swapper/221:34:052
1601499170,2cyclictest0-21swapper/223:05:112
1601499170,2cyclictest0-21swapper/223:05:112
1601499170,14cyclictest0-21swapper/221:25:142
16013991711,3cyclictest0-21swapper/123:55:191
144922170,0sleep10-21swapper/122:00:021
16014991613,2cyclictest20293-21kworker/u8:119:22:042
1601499161,2cyclictest0-21swapper/223:19:052
1601499160,14cyclictest29169-21ssh22:15:142
1601599151,12cyclictest27371-21ssh23:23:123
16015991510,3cyclictest26071-21diskmemload22:46:053
1601599150,3cyclictest17436-21sort20:30:243
1601599150,13cyclictest0-21swapper/321:22:243
1601599150,13cyclictest0-21swapper/319:35:013
1601499151,2cyclictest0-21swapper/222:31:042
16014991512,2cyclictest12244-21kworker/u8:020:24:042
16014991511,2cyclictest17939-21kworker/u8:221:13:032
1601499151,12cyclictest0-21swapper/223:33:012
1601499150,2cyclictest0-21swapper/222:57:052
1601399151,3cyclictest7877-21rm23:36:171
1601399151,3cyclictest0-21swapper/122:34:531
1601399151,12cyclictest5400-21latency_hist23:00:001
1601399151,12cyclictest0-21swapper/123:41:111
16012991511,2cyclictest0-21swapper/021:35:550
16012991510,3cyclictest15420-21cat20:25:240
55492140,1sleep3381ktimersoftd/323:00:083
1601599149,3cyclictest19216-21ssh00:24:203
1601599149,3cyclictest0-21swapper/321:10:433
16015991411,2cyclictest0-21swapper/322:21:553
1601599140,12cyclictest14737-21ssh23:45:013
1601599140,12cyclictest14006-21ssh00:18:233
1601599140,12cyclictest0-21swapper/322:01:323
1601499149,3cyclictest0-21swapper/200:31:012
1601499142,7cyclictest0-21swapper/219:20:002
1601499141,7cyclictest0-21swapper/221:40:002
1601499141,3cyclictest17495-21ssh23:12:042
1601499141,2cyclictest610-21latency_hist22:55:002
16014991411,2cyclictest2688-21kworker/u8:321:56:052
16014991411,2cyclictest0-21swapper/223:53:152
1601499141,12cyclictest0-21swapper/223:36:052
16014991411,2cyclictest0-21swapper/222:40:342
16014991411,2cyclictest0-21swapper/221:49:342
16014991411,2cyclictest0-21swapper/200:12:452
1601499140,2cyclictest0-21swapper/223:49:052
1601499140,2cyclictest0-21swapper/221:23:542
1601499140,12cyclictest0-21swapper/222:10:002
16013991410,2cyclictest8825-21ssh23:02:591
1601399140,12cyclictest0-21swapper/122:14:181
16012991410,2cyclictest168122sleep023:45:470
16012991410,2cyclictest0-21swapper/023:30:350
1601299140,13cyclictest0-21swapper/021:12:190
1601299140,12cyclictest32148-21diskmemload23:57:150
1601299140,12cyclictest32148-21diskmemload23:35:430
1601299140,12cyclictest11277-21sed00:15:140
1601299140,12cyclictest0-21swapper/023:43:190
1601299140,12cyclictest0-21swapper/022:10:250
1601299140,12cyclictest0-21swapper/021:50:100
291332130,2sleep10-21swapper/100:35:071
1601599139,2cyclictest0-21swapper/321:35:103
1601599138,3cyclictest0-21swapper/321:45:003
16015991310,2cyclictest32148-21diskmemload21:16:523
16015991310,2cyclictest32148-21diskmemload00:36:243
16015991310,2cyclictest0-21swapper/323:35:103
16015991310,2cyclictest0-21swapper/323:25:543
16015991310,2cyclictest0-21swapper/322:57:123
16015991310,2cyclictest0-21swapper/322:37:113
16015991310,2cyclictest0-21swapper/322:13:513
16015991310,2cyclictest0-21swapper/321:53:213
16015991310,2cyclictest0-21swapper/321:47:343
16015991310,2cyclictest0-21swapper/321:25:233
16015991310,2cyclictest0-21swapper/320:35:123
1601599130,2cyclictest32148-21diskmemload22:26:523
1601599130,2cyclictest0-21swapper/323:32:503
1601599130,2cyclictest0-21swapper/323:05:013
1601599130,2cyclictest0-21swapper/323:05:013
1601599130,2cyclictest0-21swapper/320:25:143
1601599130,2cyclictest0-21swapper/300:09:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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