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2026-02-25 - 05:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #3, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot6s.osadl.org (updated Wed Feb 25, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22022211795,17sleep30-21swapper/319:06:543
22230211695,16sleep10-21swapper/119:09:361
22229211594,16sleep00-21swapper/019:09:350
22041210991,12sleep20-21swapper/219:07:092
196782740,1sleep00-21swapper/000:10:190
239402720,0sleep10-21swapper/123:40:531
133032700,0sleep10-21swapper/122:56:411
12302670,0sleep30-21swapper/323:51:053
2229299350,33cyclictest9457-21ssh22:20:101
216242300,1sleep3381ktimersoftd/321:59:183
271912250,1sleep2301ktimersoftd/223:45:122
2229399221,3cyclictest20558-21ssh23:05:102
2229299221,19cyclictest0-21swapper/121:25:111
2229299220,20cyclictest0-21swapper/119:55:111
2229399211,18cyclictest5549-21ssh00:30:132
2229399210,2cyclictest0-21swapper/223:55:122
104092210,0sleep10-21swapper/122:54:391
2229499200,2cyclictest0-21swapper/323:30:103
2229499200,2cyclictest0-21swapper/322:55:123
2229399200,18cyclictest0-21swapper/220:05:122
2229299200,2cyclictest0-21swapper/123:30:101
2229399170,15cyclictest3345-21rm22:46:252
2229399170,15cyclictest0-21swapper/221:17:002
22291991712,3cyclictest0-21swapper/023:40:000
76192160,0sleep10-21swapper/100:31:001
307422160,1sleep330747-21fschecks_time23:15:143
2229499161,3cyclictest5936-21diskmemload21:10:143
22294991611,3cyclictest5199-21latency22:15:163
2229399160,14cyclictest0-21swapper/221:00:202
2229399160,14cyclictest0-21swapper/219:25:332
22291991611,3cyclictest0-21swapper/000:05:140
22294991510,3cyclictest10550-21rm23:27:323
2229499150,13cyclictest0-21swapper/322:30:183
22293991510,4cyclictest0-21swapper/221:31:532
22293991510,4cyclictest0-21swapper/221:31:532
2229399150,4cyclictest0-21swapper/221:38:222
2229399150,4cyclictest0-21swapper/200:24:352
2229399150,4cyclictest0-21swapper/200:03:362
2229399150,3cyclictest0-21swapper/200:36:242
2229399150,14cyclictest0-21swapper/223:00:142
2229399150,14cyclictest0-21swapper/222:53:302
2229399150,14cyclictest0-21swapper/221:41:552
2229399150,14cyclictest0-21swapper/200:14:002
2229399150,14cyclictest0-21swapper/200:05:492
2229399150,13cyclictest6858-21nscd22:39:102
2229399150,13cyclictest0-21swapper/221:10:152
2229299159,4cyclictest30776-21rm22:41:051
22292991510,3cyclictest23-21ksoftirqd/100:15:111
2229299150,13cyclictest20937-21ssh00:11:281
2229199151,7cyclictest0-21swapper/022:45:000
2229199151,3cyclictest32282-21ssh21:35:410
2229199151,12cyclictest0-21swapper/022:55:140
2229499140,3cyclictest28223-21date00:20:013
2229499140,2cyclictest0-21swapper/300:28:473
2229499140,2cyclictest0-21swapper/300:28:463
2229499140,12cyclictest5936-21diskmemload21:16:113
2229499140,12cyclictest0-21swapper/322:45:543
2229499140,12cyclictest0-21swapper/322:05:363
2229499140,12cyclictest0-21swapper/320:00:133
2229399149,4cyclictest0-21swapper/223:42:372
2229399149,4cyclictest0-21swapper/221:59:362
2229399148,4cyclictest0-21swapper/223:10:072
2229399140,4cyclictest0-21swapper/222:25:212
2229399140,3cyclictest2089-21ssh23:52:262
2229399140,2cyclictest0-21swapper/223:26:292
2229399140,13cyclictest0-21swapper/223:32:282
2229399140,13cyclictest0-21swapper/223:22:002
2229399140,13cyclictest0-21swapper/222:40:592
2229399140,13cyclictest0-21swapper/222:15:482
2229399140,13cyclictest0-21swapper/221:29:052
2229399140,13cyclictest0-21swapper/221:22:012
2229399140,13cyclictest0-21swapper/200:18:422
2229399140,12cyclictest0-21swapper/223:18:132
2229399140,12cyclictest0-21swapper/222:20:382
2229299149,3cyclictest32411-21df22:10:121
2229299140,12cyclictest12081-21ssh21:49:261
2229299140,12cyclictest11566-21ssh23:29:081
2229299140,12cyclictest0-21swapper/123:39:581
2229199149,3cyclictest22482-21aten2.4_r3power22:00:120
2229199142,6cyclictest0-21swapper/021:20:000
2229199141,11cyclictest62132sleep021:43:040
2229199140,2cyclictest0-21swapper/022:35:200
2229199140,13cyclictest0-21swapper/023:27:500
2229199140,12cyclictest0-21swapper/023:40:190
2229199140,12cyclictest0-21swapper/000:35:140
20672140,2sleep30-21swapper/322:11:493
2229499138,3cyclictest32630-21sh22:44:013
2229499132,6cyclictest0-21swapper/319:49:593
22294991310,2cyclictest22759-21ssh23:06:243
22294991310,2cyclictest0-21swapper/323:48:313
22294991310,2cyclictest0-21swapper/323:42:163
22294991310,2cyclictest0-21swapper/323:20:013
22294991310,2cyclictest0-21swapper/323:12:133
22294991310,2cyclictest0-21swapper/321:42:243
22294991310,2cyclictest0-21swapper/321:29:443
22294991310,2cyclictest0-21swapper/300:02:013
2229499130,2cyclictest5936-21diskmemload23:36:253
2229499130,2cyclictest5936-21diskmemload21:48:543
2229499130,2cyclictest5936-21diskmemload21:20:123
2229499130,2cyclictest5936-21diskmemload00:32:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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