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2026-01-21 - 11:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #3, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack3slot6s.osadl.org (updated Wed Jan 21, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3772211994,18sleep00-21swapper/019:05:110
5262211696,14sleep30-21swapper/319:06:193
5241211694,16sleep20-21swapper/219:06:022
5260211495,14sleep10-21swapper/119:06:171
221702740,0sleep20-21swapper/222:20:202
324402720,0sleep10-21swapper/123:45:001
184172660,0sleep10-21swapper/100:05:121
303492350,1sleep20-21swapper/221:54:302
12072240,1sleep11206-21ssh21:21:341
557999230,2cyclictest0-21swapper/022:20:110
99702220,0sleep20-21swapper/221:30:332
558299210,5cyclictest0-21swapper/319:29:043
557999211,2cyclictest7458-21runrttasks19:25:090
558299201,4cyclictest0-21swapper/319:32:053
558099200,18cyclictest0-21swapper/122:50:111
557999200,15cyclictest0-21swapper/023:55:040
558299190,4cyclictest0-21swapper/321:36:053
557999190,2cyclictest0-21swapper/020:10:120
5582991816,1cyclictest0-21swapper/320:35:123
558299180,4cyclictest0-21swapper/322:22:053
558299180,4cyclictest0-21swapper/300:31:053
558299180,3cyclictest0-21swapper/321:04:043
558299180,3cyclictest0-21swapper/320:47:053
558299180,3cyclictest0-21swapper/320:08:053
558199180,4cyclictest0-21swapper/221:24:052
5582991715,1cyclictest0-21swapper/322:55:113
558299170,4cyclictest0-21swapper/323:51:043
558299170,4cyclictest0-21swapper/320:12:053
558299170,4cyclictest0-21swapper/300:25:053
558299170,3cyclictest0-21swapper/320:40:043
558299170,3cyclictest0-21swapper/300:19:043
5581991714,2cyclictest23452-21kworker/u8:021:47:052
5581991714,2cyclictest18481-21kworker/u8:122:55:042
5581991714,2cyclictest11572-21kworker/u8:120:56:052
5581991713,2cyclictest0-21swapper/219:15:102
558299162,2cyclictest0-21swapper/322:52:043
558199163,2cyclictest0-21swapper/200:26:052
558199162,2cyclictest0-21swapper/223:15:042
5581991613,2cyclictest5724-21kworker/u8:023:28:042
5581991613,2cyclictest30088-21kworker/u8:022:37:052
5581991613,2cyclictest30079-21kworker/u8:121:58:042
5581991613,2cyclictest25899-21kworker/u8:020:29:042
5581991613,2cyclictest25899-21kworker/u8:020:16:042
5581991613,2cyclictest25899-21kworker/u8:020:13:052
5581991613,2cyclictest17445-21kworker/u8:321:44:042
5581991613,2cyclictest14231-21kworker/u8:021:06:042
5581991613,2cyclictest11572-21kworker/u8:120:52:042
558199160,14cyclictest0-21swapper/223:43:032
557999160,2cyclictest0-21swapper/021:20:150
557999160,11cyclictest0-21swapper/023:45:040
5582991510,3cyclictest0-21swapper/322:05:443
5581991512,2cyclictest30181-21kworker/u8:100:06:042
5581991512,2cyclictest25899-21kworker/u8:020:41:042
5581991512,2cyclictest21059-21kworker/u8:000:13:052
5581991512,2cyclictest20471-21kworker/u8:019:34:052
5581991512,2cyclictest20102-21kworker/u8:019:51:042
5581991512,2cyclictest20102-21kworker/u8:019:49:052
5581991512,2cyclictest18481-21kworker/u8:122:54:042
5581991512,2cyclictest13819-21kworker/u8:119:43:052
5581991512,2cyclictest13745-21kworker/u8:122:16:042
5581991512,2cyclictest11572-21kworker/u8:121:13:052
5581991512,2cyclictest10108-21kworker/u8:219:21:042
5581991511,2cyclictest9495-21kworker/u8:023:59:052
558099152,8cyclictest0-21swapper/122:15:011
558099151,3cyclictest7256-21chrt23:51:581
558099151,12cyclictest10735-21irqstats20:40:161
558099151,12cyclictest0-21swapper/121:50:151
558099151,12cyclictest0-21swapper/121:29:151
5580991510,3cyclictest30311-21sh00:18:001
5580991510,3cyclictest18031-21users22:15:231
557999150,13cyclictest0-21swapper/023:11:320
558299141,1cyclictest0-21swapper/321:10:053
558299140,5cyclictest0-21swapper/319:48:053
558299140,12cyclictest0-21swapper/323:56:263
558299140,12cyclictest0-21swapper/323:05:463
5581991411,2cyclictest30181-21kworker/u8:123:52:042
5581991411,2cyclictest30181-21kworker/u8:100:01:042
5581991411,2cyclictest2927-21kworker/u8:200:33:032
5581991411,2cyclictest24586-21kworker/u8:122:27:032
5581991411,2cyclictest20471-21kworker/u8:019:13:052
5581991411,2cyclictest17587-21kworker/u8:219:37:042
5581991411,2cyclictest11572-21kworker/u8:121:35:042
5581991411,2cyclictest11572-21kworker/u8:120:45:052
5581991411,2cyclictest10108-21kworker/u8:219:26:042
558199141,11cyclictest3501-21ssh23:48:352
5581991410,2cyclictest24719-21apt-get23:00:112
558199140,3cyclictest0-21swapper/222:10:162
558199140,2cyclictest0-21swapper/222:32:052
558199140,2cyclictest0-21swapper/221:16:042
558099149,3cyclictest13648-21iostat21:35:151
558099149,3cyclictest0-21swapper/123:32:591
558099142,6cyclictest0-21swapper/119:25:011
558099140,3cyclictest27368-21munin-node1
558099140,3cyclictest0-21swapper/100:35:191
558099140,12cyclictest21911-21diskmemload21:47:431
558099140,12cyclictest0-21swapper/123:15:591
5579991411,2cyclictest0-21swapper/023:35:520
5579991410,2cyclictest0-21swapper/023:52:200
557999140,13cyclictest0-21swapper/021:19:050
557999140,13cyclictest0-21swapper/000:36:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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