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2026-02-28 - 12:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #3, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6s.osadl.org (updated Sat Feb 28, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21454211898,14sleep30-21swapper/319:06:153
216332115104,6sleep00-21swapper/019:08:320
21685211294,13sleep10-21swapper/119:09:131
21505210897,6sleep20-21swapper/219:06:542
86212840,1sleep00-21swapper/023:25:460
72172780,1sleep30-21swapper/322:50:543
293282770,1sleep00-21swapper/021:34:230
224202720,0sleep00-21swapper/021:26:060
251552690,0sleep30-21swapper/319:15:353
185102650,1sleep20-21swapper/221:22:362
2177599350,33cyclictest0-21swapper/121:10:121
2177599350,2cyclictest0-21swapper/121:50:101
2177699310,2cyclictest0-21swapper/220:40:102
45302260,1sleep00-21swapper/021:05:170
114912210,0sleep00-21swapper/021:49:220
2177799202,6cyclictest0-21swapper/321:52:583
2177599190,17cyclictest0-21swapper/123:40:111
2177799182,7cyclictest0-21swapper/321:29:583
2177799171,3cyclictest0-21swapper/322:10:143
2177799161,13cyclictest2926-21cron23:54:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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