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2026-01-29 - 16:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #3, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6s.osadl.org (updated Thu Jan 29, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24526211694,16sleep10-21swapper/107:05:571
24689211594,16sleep20-21swapper/207:08:022
24577211594,16sleep00-21swapper/007:06:360
2454329579,11sleep30-21swapper/307:06:113
93922650,1sleep02486899cyclictest12:05:110
194692550,0sleep00-21swapper/010:30:160
39872230,1sleep20-21swapper/212:35:012
255822230,0sleep30-21swapper/311:47:113
257742220,1sleep10-21swapper/111:47:301
2486899220,17cyclictest0-21swapper/009:56:050
2486899220,17cyclictest0-21swapper/009:19:050
2487099210,4cyclictest31-21ksoftirqd/212:20:052
2487099210,4cyclictest0-21swapper/212:17:032
2486899210,19cyclictest0-21swapper/007:25:120
2486899210,16cyclictest0-21swapper/010:36:050
174412210,1sleep20-21swapper/211:38:572
2487099200,3cyclictest0-21swapper/210:13:042
2486899203,2cyclictest0-21swapper/009:10:050
2486899200,2cyclictest0-21swapper/012:20:140
24871991916,2cyclictest23462-21kworker/u8:010:11:043
2487199190,14cyclictest0-21swapper/309:23:053
2487099190,5cyclictest0-21swapper/210:32:052
2486899190,14cyclictest0-21swapper/007:53:050
24871991815,2cyclictest8530-21kworker/u8:010:58:053
24871991815,2cyclictest18543-21kworker/u8:211:44:053
2487199180,17cyclictest0-21swapper/310:44:053
2487099183,2cyclictest0-21swapper/208:22:052
2487099183,2cyclictest0-21swapper/207:12:052
2487099182,2cyclictest0-21swapper/207:57:052
2487099180,3cyclictest0-21swapper/210:39:042
2486899181,2cyclictest0-21swapper/012:38:050
2486899180,2cyclictest0-21swapper/008:04:050
2486899180,17cyclictest0-21swapper/011:03:050
2486899180,16cyclictest0-21swapper/009:45:050
2486899180,16cyclictest0-21swapper/009:45:040
2486899180,14cyclictest0-21swapper/008:32:040
2486899180,13cyclictest0-21swapper/011:37:050
24871991714,2cyclictest6622-21kworker/u8:109:17:043
24871991714,2cyclictest30097-21kworker/u8:111:52:043
24871991714,2cyclictest18688-21kworker/u8:309:57:053
24871991714,2cyclictest15338-21kworker/u8:108:15:033
24871991714,2cyclictest13781-21kworker/u8:111:12:053
2486899171,14cyclictest4529-21ssh11:25:110
2486899170,16cyclictest0-21swapper/010:01:040
2486899170,15cyclictest0-21swapper/011:20:050
2486899170,12cyclictest0-21swapper/009:03:050
2486899170,11cyclictest0-21swapper/010:29:040
24871991613,2cyclictest8770-21kworker/u8:210:03:053
24871991613,2cyclictest2923-21kworker/u8:212:03:043
24871991613,2cyclictest25679-21kworker/u8:209:37:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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