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2026-01-26 - 19:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Mon Jan 26, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13078999415,17cyclictest0-21swapper/111:15:141
13078999314,18cyclictest0-21swapper/110:20:261
13078999314,18cyclictest0-21swapper/109:30:131
13078999117,19cyclictest0-21swapper/110:30:091
13078999114,18cyclictest0-21swapper/107:20:101
13078999114,17cyclictest0-21swapper/112:20:141
13078999114,16cyclictest0-21swapper/107:15:131
13078998916,18cyclictest0-21swapper/107:45:151
13078998914,17cyclictest0-21swapper/110:00:141
13078998914,17cyclictest0-21swapper/107:10:111
13078998819,15cyclictest0-21swapper/108:10:121
13078998817,16cyclictest0-21swapper/112:00:141
13078998816,19cyclictest0-21swapper/112:15:201
13078998814,16cyclictest0-21swapper/108:35:141
13078998813,16cyclictest0-21swapper/111:40:231
13078998715,18cyclictest0-21swapper/108:20:151
13078998715,17cyclictest0-21swapper/112:35:251
13078998715,17cyclictest0-21swapper/110:50:161
13078998714,19cyclictest0-21swapper/107:25:141
1307499876,20cyclictest17176-21apt-get07:20:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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