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2026-03-05 - 13:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Thu Mar 05, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
130019910671,26cyclictest26-21ksoftirqd/122:15:121
130019910671,26cyclictest26-21ksoftirqd/122:15:111
130019910657,31cyclictest26-21ksoftirqd/123:20:131
130019910523,68cyclictest0-21swapper/122:25:141
130019910323,71cyclictest12988-21cyclictest21:30:111
130019910318,70cyclictest0-21swapper/123:00:121
130019910313,74cyclictest0-21swapper/119:50:101
130019910213,76cyclictest0-21swapper/100:20:111
130019910213,73cyclictest0-21swapper/121:55:101
130019910212,74cyclictest0-21swapper/100:15:121
130019910212,71cyclictest0-21swapper/123:15:121
1182321020,6chrt11822-21sort23:40:010
130019910150,37cyclictest26-21ksoftirqd/122:00:131
130019910150,37cyclictest26-21ksoftirqd/122:00:131
130019910114,71cyclictest0-21swapper/100:05:121
130019910113,74cyclictest0-21swapper/120:50:231
130019910018,67cyclictest0-21swapper/120:40:101
130019910013,68cyclictest0-21swapper/123:25:131
130019910012,72cyclictest0-21swapper/119:35:131
130019910012,71cyclictest0-21swapper/121:25:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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