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2026-02-16 - 00:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sun Feb 15, 2026 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57939911813,91cyclictest0-21swapper/011:50:100
57939911813,91cyclictest0-21swapper/011:50:090
57939911712,91cyclictest0-21swapper/011:00:100
57939911211,58cyclictest0-21swapper/012:35:140
5793991114,85cyclictest31165-21sshd09:50:130
57939911115,81cyclictest0-21swapper/010:55:130
57939911113,85cyclictest0-21swapper/012:10:130
57939911015,82cyclictest0-21swapper/008:15:110
57939911013,81cyclictest0-21swapper/011:15:140
57939911012,81cyclictest0-21swapper/010:45:150
57939911012,76cyclictest0-21swapper/007:35:240
57939910913,78cyclictest0-21swapper/009:05:130
57939910912,81cyclictest0-21swapper/009:55:130
57939910912,80cyclictest0-21swapper/010:15:260
57939910861,36cyclictest0-21swapper/011:25:120
57939910834,25cyclictest151rcu_preempt11:05:140
57939910829,37cyclictest14-21ksoftirqd/008:55:120
57939910813,78cyclictest0-21swapper/007:30:140
57979910778,20cyclictest26-21ksoftirqd/108:25:131
57939910755,33cyclictest14-21ksoftirqd/012:00:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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