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2026-02-28 - 19:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sat Feb 28, 2026 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
263879911073,25cyclictest14-21ksoftirqd/011:35:130
263879910910,85cyclictest0-21swapper/009:00:110
263879910814,83cyclictest0-21swapper/009:55:130
263879910813,31cyclictest0-21swapper/011:55:130
263879910713,82cyclictest0-21swapper/009:45:110
263879910664,29cyclictest14-21ksoftirqd/007:35:140
263879910511,27cyclictest0-21swapper/007:10:120
263879910411,80cyclictest0-21swapper/010:55:130
263879910411,80cyclictest0-21swapper/010:55:130
263879910261,29cyclictest14-21ksoftirqd/010:15:140
263879910259,32cyclictest14-21ksoftirqd/009:20:140
263879910259,31cyclictest14-21ksoftirqd/012:25:240
26387999838,47cyclictest14-21ksoftirqd/009:35:130
26394999643,42cyclictest26-21ksoftirqd/110:10:141
26387999634,50cyclictest14-21ksoftirqd/012:05:110
2466529540,39sleep00-21swapper/007:05:310
2466529540,39sleep00-21swapper/007:05:300
26387999447,34cyclictest14-21ksoftirqd/010:30:120
26387999343,37cyclictest14-21ksoftirqd/008:00:160
26387999313,65cyclictest0-21swapper/011:30:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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