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2026-03-02 - 13:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Mon Mar 02, 2026 00:45:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
267579911477,26cyclictest26-21ksoftirqd/100:25:131
267579911172,29cyclictest26-21ksoftirqd/119:40:131
267579910965,31cyclictest26-21ksoftirqd/123:05:151
267579910965,31cyclictest26-21ksoftirqd/123:05:151
267579910870,26cyclictest26-21ksoftirqd/122:30:131
267579910767,30cyclictest26-21ksoftirqd/100:15:141
267579910052,33cyclictest26-21ksoftirqd/119:50:121
267579910051,35cyclictest26-21ksoftirqd/123:55:141
2675799978,70cyclictest548-21runrttasks19:25:111
2675799977,71cyclictest5014-21diskmemload21:10:091
26757999613,65cyclictest0-21swapper/122:45:241
26757999515,63cyclictest0-21swapper/120:30:131
26757999514,65cyclictest0-21swapper/100:20:121
26757999512,62cyclictest0-21swapper/120:25:251
2675799949,64cyclictest0-21swapper/119:35:091
26757999443,32cyclictest26-21ksoftirqd/122:00:131
26757999443,32cyclictest26-21ksoftirqd/122:00:121
26757999434,44cyclictest26-21ksoftirqd/120:05:141
26757999412,70cyclictest0-21swapper/122:40:111
26757999412,62cyclictest0-21swapper/122:55:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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