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2026-02-07 - 18:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sat Feb 07, 2026 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19797991197,88cyclictest0-21swapper/010:20:140
19797991089,30cyclictest0-21swapper/011:35:130
19797991088,27cyclictest0-21swapper/007:10:130
197979910711,26cyclictest0-21swapper/012:25:120
197979910710,25cyclictest0-21swapper/009:35:150
19797991058,25cyclictest0-21swapper/010:30:100
19797991049,27cyclictest0-21swapper/008:15:140
19797991048,25cyclictest0-21swapper/011:55:120
19797991038,24cyclictest0-21swapper/009:45:140
19797991037,24cyclictest0-21swapper/012:30:130
19797991037,22cyclictest0-21swapper/012:10:140
197979910316,24cyclictest0-21swapper/008:55:120
197979910312,25cyclictest0-21swapper/009:30:230
197979910311,23cyclictest0-21swapper/007:20:110
197979910311,23cyclictest0-21swapper/007:20:110
197979910216,25cyclictest0-21swapper/008:25:260
197979910210,21cyclictest0-21swapper/009:10:150
198009910172,18cyclictest26-21ksoftirqd/108:45:121
198009910172,16cyclictest26-21ksoftirqd/111:20:131
198009910171,19cyclictest26-21ksoftirqd/108:30:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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