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2026-02-20 - 20:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Fri Feb 20, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5775210016,32sleep10-21swapper/107:07:561
229542870,8chrt0-21swapper/107:55:151
615999837,66cyclictest16901-21apt-get10:40:141
560928322,50sleep00-21swapper/007:06:080
615999826,66cyclictest10429-21apt-get08:50:111
6156998037,35cyclictest8688-21apt-get08:45:140
615999796,64cyclictest1654-21apt-get08:25:121
615999796,63cyclictest28290-21apt-get09:40:121
6159997926,47cyclictest448-21dbus-daemon11:00:001
6159997912,56cyclictest0-21swapper/110:10:121
6159997911,53cyclictest0-21swapper/109:50:131
615999787,59cyclictest18644-21apt-get10:45:121
6159997813,50cyclictest0-21swapper/111:50:141
6159997813,50cyclictest0-21swapper/109:55:111
6159997812,54cyclictest0-21swapper/108:35:111
6159997812,52cyclictest0-21swapper/112:15:121
615999777,57cyclictest12801-21apt-get12:00:121
615999772,68cyclictest14235-21cat10:30:351
6159997714,55cyclictest0-21swapper/107:30:111
6159997712,50cyclictest0-21swapper/108:45:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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