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2026-03-01 - 11:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sun Mar 01, 2026 00:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17807991206,92cyclictest0-21swapper/023:50:120
178079911613,27cyclictest0-21swapper/000:10:120
178079911611,28cyclictest0-21swapper/022:50:120
17807991117,80cyclictest0-21swapper/022:45:150
178079911011,30cyclictest0-21swapper/021:15:110
17807991099,23cyclictest0-21swapper/022:10:250
178079910212,24cyclictest0-21swapper/022:25:110
178129910170,19cyclictest26-21ksoftirqd/121:20:131
1780799967,24cyclictest0-21swapper/019:30:130
1750429536,47sleep10-21swapper/119:08:411
17807999420,33cyclictest14-21ksoftirqd/019:15:130
17812999063,18cyclictest26-21ksoftirqd/121:35:131
17812998955,21cyclictest26-21ksoftirqd/120:30:231
17812998656,20cyclictest26-21ksoftirqd/123:10:151
17812998549,24cyclictest26-21ksoftirqd/123:15:241
17812998250,22cyclictest26-21ksoftirqd/100:15:131
17807998233,28cyclictest0-21swapper/000:15:140
17807998233,27cyclictest0-21swapper/019:45:130
1780799818,51cyclictest0-21swapper/000:00:130
17807998033,30cyclictest0-21swapper/020:00:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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