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2026-02-22 - 09:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sun Feb 22, 2026 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
42529912693,19cyclictest14-21ksoftirqd/023:40:120
42559912087,20cyclictest26-21ksoftirqd/121:30:141
42529911812,94cyclictest0-21swapper/023:35:120
42529911612,92cyclictest0-21swapper/023:55:120
42559911483,18cyclictest26-21ksoftirqd/122:30:141
42559911382,21cyclictest26-21ksoftirqd/119:35:121
42559911281,20cyclictest26-21ksoftirqd/123:30:121
42529911115,31cyclictest0-21swapper/021:20:120
42529911113,25cyclictest0-21swapper/020:10:110
42559911081,18cyclictest26-21ksoftirqd/122:45:141
42529911012,31cyclictest0-21swapper/022:35:120
42529910914,27cyclictest0-21swapper/020:00:120
42529910912,27cyclictest0-21swapper/023:45:150
42529910912,27cyclictest0-21swapper/020:40:160
42559910880,19cyclictest26-21ksoftirqd/119:55:131
42529910813,27cyclictest0-21swapper/020:30:120
42529910811,28cyclictest0-21swapper/020:20:100
42529910714,30cyclictest0-21swapper/021:45:120
42529910712,26cyclictest0-21swapper/023:15:120
42559910673,20cyclictest26-21ksoftirqd/123:20:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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