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2026-01-31 - 00:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Fri Jan 30, 2026 12:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1086421100,6sleep10-21swapper/112:20:271
279419910542,15cyclictest14-21ksoftirqd/011:00:140
1895621020,7chrt18943-21cron11:14:591
279419910113,18cyclictest0-21swapper/009:45:120
27941999616,19cyclictest0-21swapper/007:40:140
27941999535,21cyclictest26196-21cron10:05:000
27941999516,19cyclictest0-21swapper/008:55:130
27941999515,18cyclictest0-21swapper/009:20:130
27941999315,71cyclictest0-21swapper/008:15:140
27941999315,15cyclictest0-21swapper/012:20:110
27941999314,18cyclictest0-21swapper/011:50:240
27941999312,17cyclictest0-21swapper/012:05:130
27941999216,17cyclictest0-21swapper/007:45:110
27941999215,18cyclictest0-21swapper/011:30:140
27941999214,18cyclictest0-21swapper/010:45:150
27941999214,18cyclictest0-21swapper/010:25:120
27941999117,17cyclictest0-21swapper/011:45:120
27941999114,68cyclictest0-21swapper/010:15:170
27941999114,20cyclictest0-21swapper/007:35:130
27941998921,14cyclictest0-21swapper/012:00:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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