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2026-08-23 - 01:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sat Aug 22, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
273619911711,93cyclictest0-21swapper/007:55:120
273619911312,86cyclictest0-21swapper/010:00:130
273619911311,86cyclictest0-21swapper/007:35:230
273619911211,84cyclictest0-21swapper/011:45:140
273619911064,34cyclictest0-21swapper/008:15:150
273619910911,23cyclictest0-21swapper/011:25:170
273619910910,82cyclictest0-21swapper/010:25:160
273619910760,33cyclictest14-21ksoftirqd/011:30:140
273619910660,35cyclictest14-21ksoftirqd/007:45:120
27361991048,76cyclictest0-21swapper/012:15:120
273619910456,33cyclictest0-21swapper/008:30:140
273619910253,32cyclictest14-21ksoftirqd/012:20:120
273619910253,30cyclictest14-21ksoftirqd/009:05:150
273619910253,29cyclictest14-21ksoftirqd/012:10:160
27072210015,39sleep00-21swapper/007:08:540
27361999718,58cyclictest0-21swapper/010:50:130
27361999715,60cyclictest0-21swapper/007:40:260
27361999712,61cyclictest0-21swapper/010:30:140
27361999512,63cyclictest0-21swapper/007:15:130
27361999411,62cyclictest0-21swapper/009:55:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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