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2026-02-03 - 18:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Tue Feb 03, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
976099916,72cyclictest21451-21apt-get12:15:110
9760999016,60cyclictest0-21swapper/010:30:230
976099899,57cyclictest19629-21apt-get09:10:150
9760998916,65cyclictest0-21swapper/010:40:120
9760998915,60cyclictest0-21swapper/011:40:110
9760998914,60cyclictest0-21swapper/009:00:130
9760998914,60cyclictest0-21swapper/009:00:120
9760998842,41cyclictest0-21swapper/010:25:220
976099877,66cyclictest26694-21apt-get12:30:120
9760998720,60cyclictest250-21systemd-journal08:43:390
9760998715,59cyclictest0-21swapper/007:45:230
9760998713,60cyclictest0-21swapper/012:25:120
9769998650,20cyclictest26-21ksoftirqd/108:35:131
976099867,66cyclictest23217-21apt-get12:20:130
976099866,67cyclictest24805-21apt-get07:50:140
976099866,67cyclictest19070-21apt-get07:35:130
9760998616,59cyclictest0-21swapper/011:05:140
9760998616,58cyclictest0-21swapper/007:20:110
9760998615,58cyclictest0-21swapper/009:20:130
9760998615,57cyclictest0-21swapper/010:50:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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