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2026-02-04 - 19:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Wed Feb 04, 2026 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2890129521,27sleep00-21swapper/007:08:170
2890129521,27sleep00-21swapper/007:08:160
2875028948,30sleep10-21swapper/107:06:391
2875028948,30sleep10-21swapper/107:06:391
29246998557,13cyclictest14-21ksoftirqd/009:40:130
29246998164,10cyclictest14-21ksoftirqd/011:15:220
29246998159,12cyclictest14-21ksoftirqd/009:55:140
29246998155,15cyclictest0-21swapper/007:50:140
29246998155,14cyclictest14-21ksoftirqd/009:25:100
29246998053,14cyclictest14-21ksoftirqd/012:00:140
29246997752,14cyclictest14-21ksoftirqd/007:25:150
29246997547,15cyclictest14-21ksoftirqd/011:45:090
29251997450,15cyclictest10585-21apt-get12:20:141
29251997340,18cyclictest26-21ksoftirqd/109:10:141
29246997348,14cyclictest14-21ksoftirqd/010:15:150
29246997142,18cyclictest14-21ksoftirqd/007:40:110
29246997141,18cyclictest0-21swapper/008:50:160
29246997140,18cyclictest0-21swapper/011:30:120
29246997139,26cyclictest1049-21telnet07:20:170
29246997128,37cyclictest0-21swapper/009:15:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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