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2026-01-21 - 19:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Wed Jan 21, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1675029714,37sleep00-21swapper/007:09:340
16927999246,33cyclictest500-21snmpd11:03:410
1641529133,46sleep10-21swapper/107:06:301
16927998152,23cyclictest24537-21telnet10:30:260
323582800,6sleep0171rcuc/010:50:340
303632800,9sleep014-21ksoftirqd/012:15:170
16927998039,35cyclictest14-21ksoftirqd/009:10:460
16927997950,16cyclictest500-21snmpd07:45:300
16927997839,22cyclictest14-21ksoftirqd/010:27:010
233872770,7sleep1251rcuc/108:55:311
201092770,10sleep126-21ksoftirqd/107:15:331
16927997740,23cyclictest14-21ksoftirqd/008:06:450
134562760,5sleep126-21ksoftirqd/110:00:001
16927997245,15cyclictest14-21ksoftirqd/008:45:150
16927997241,15cyclictest14-21ksoftirqd/007:50:110
16927997236,31cyclictest8389-21sshd08:14:280
16927997140,15cyclictest14-21ksoftirqd/009:39:330
16927997139,15cyclictest761-21/usr/sbin/munin10:55:230
16927997138,14cyclictest14-21ksoftirqd/008:25:160
16927997043,15cyclictest14-21ksoftirqd/011:15:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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