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2026-02-03 - 03:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Tue Feb 03, 2026 00:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13704210316,38sleep00-21swapper/019:06:280
13704210316,38sleep00-21swapper/019:06:280
14216998970,9cyclictest14-21ksoftirqd/000:20:130
14216998872,10cyclictest14-21ksoftirqd/021:35:140
14216998661,13cyclictest14-21ksoftirqd/021:55:130
14216998452,19cyclictest0-21swapper/021:20:110
14216998155,15cyclictest0-21swapper/022:35:140
1362927919,47sleep10-21swapper/119:05:391
1362927919,47sleep10-21swapper/119:05:391
14216997748,19cyclictest14-21ksoftirqd/019:30:150
14216997715,25cyclictest20536-21cron00:00:000
1421699769,21cyclictest0-21swapper/019:40:300
14216997647,18cyclictest14-21ksoftirqd/022:45:140
14216997545,19cyclictest14-21ksoftirqd/000:05:120
14216997245,18cyclictest14-21ksoftirqd/021:30:230
14216997215,18cyclictest0-21swapper/020:45:140
14216997116,30cyclictest500-21snmpd20:20:140
14221996910,38cyclictest20642-21latency_hist00:00:011
14216996929,35cyclictest250-21systemd-journal00:37:130
14216996917,19cyclictest15569-21munin-run22:15:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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