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2026-01-18 - 17:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sun Jan 18, 2026 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
245699911614,81cyclictest0-21swapper/009:30:140
245699911610,91cyclictest0-21swapper/008:55:080
245699911610,91cyclictest0-21swapper/008:55:070
245699911414,84cyclictest0-21swapper/009:00:140
245749911313,33cyclictest0-21swapper/109:15:231
245699911312,84cyclictest0-21swapper/011:05:130
245699911311,88cyclictest0-21swapper/007:40:210
245699911310,86cyclictest0-21swapper/012:25:140
245699911213,86cyclictest0-21swapper/011:50:110
245699911114,85cyclictest0-21swapper/008:40:120
245699911068,31cyclictest14-21ksoftirqd/011:10:150
245749910913,34cyclictest0-21swapper/108:15:221
245699910810,25cyclictest0-21swapper/011:20:130
245699910810,25cyclictest0-21swapper/011:20:120
24574991079,53cyclictest36-21kcompactd009:25:221
245699910668,28cyclictest14-21ksoftirqd/007:15:110
245699910668,28cyclictest14-21ksoftirqd/007:15:100
245699910457,34cyclictest14-21ksoftirqd/011:40:260
245699910360,32cyclictest0-21swapper/010:40:120
245699910258,32cyclictest0-21swapper/012:10:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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