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2026-03-12 - 20:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Thu Mar 12, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1152999315,17cyclictest0-21swapper/012:35:120
1152999314,17cyclictest0-21swapper/009:50:120
1152999313,17cyclictest0-21swapper/007:45:130
81629219,28sleep00-21swapper/007:08:450
1152999215,17cyclictest0-21swapper/009:35:120
1152999115,18cyclictest0-21swapper/008:45:140
1152999115,16cyclictest0-21swapper/011:50:120
1152999114,17cyclictest0-21swapper/011:05:130
1152999114,17cyclictest0-21swapper/011:05:120
1152999114,16cyclictest0-21swapper/011:45:110
1152999114,16cyclictest0-21swapper/010:45:120
1152999113,16cyclictest0-21swapper/009:55:130
1152999014,19cyclictest0-21swapper/012:20:130
1152999014,16cyclictest0-21swapper/009:20:140
1152999014,16cyclictest0-21swapper/007:15:120
1152999013,18cyclictest0-21swapper/012:15:110
1152999013,17cyclictest0-21swapper/010:10:120
1152999013,15cyclictest0-21swapper/012:10:130
1152999013,14cyclictest0-21swapper/007:35:120
1152999012,17cyclictest0-21swapper/010:00:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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