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2026-02-21 - 09:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Sat Feb 21, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9979999673,9cyclictest14-21ksoftirqd/020:45:130
9979999472,10cyclictest14-21ksoftirqd/021:40:120
9979999469,11cyclictest14-21ksoftirqd/022:05:110
9979999370,12cyclictest14-21ksoftirqd/020:05:130
9979999366,15cyclictest14-21ksoftirqd/021:20:140
9979999063,14cyclictest14-21ksoftirqd/000:15:130
9979998966,12cyclictest14-21ksoftirqd/022:00:120
9979998866,12cyclictest14-21ksoftirqd/023:20:100
9979998759,15cyclictest14-21ksoftirqd/000:25:110
9979998563,12cyclictest14-21ksoftirqd/023:05:110
9979998458,15cyclictest14-21ksoftirqd/020:20:120
9979998358,14cyclictest14-21ksoftirqd/000:10:230
9979998356,17cyclictest14-21ksoftirqd/021:10:240
9979998354,17cyclictest14-21ksoftirqd/020:30:140
9979998353,19cyclictest14-21ksoftirqd/020:25:150
9979998319,19cyclictest0-21swapper/000:00:120
9979998256,17cyclictest0-21swapper/020:40:120
9979998252,17cyclictest14-21ksoftirqd/023:30:150
9979998054,18cyclictest14-21ksoftirqd/023:00:140
9979998051,16cyclictest14-21ksoftirqd/022:45:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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