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2026-02-20 - 02:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack3slot6.osadl.org (updated Fri Feb 20, 2026 00:45:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
102609911114,30cyclictest0-21swapper/123:20:131
10260991108,53cyclictest36-21kcompactd023:25:231
10254991098,38cyclictest20935-21diskmemload21:10:140
102609910815,34cyclictest10246-21cyclictest22:59:561
102549910868,27cyclictest14-21ksoftirqd/019:40:130
102549910868,27cyclictest0-21swapper/019:20:130
102549910810,83cyclictest0-21swapper/022:50:140
102609910712,32cyclictest0-21swapper/123:40:111
102549910712,82cyclictest0-21swapper/022:00:130
102609910614,33cyclictest0-21swapper/122:35:131
102549910619,75cyclictest0-21swapper/019:30:110
102549910613,82cyclictest0-21swapper/023:45:160
102549910613,80cyclictest0-21swapper/021:35:130
102549910611,28cyclictest0-21swapper/023:55:110
102549910513,78cyclictest0-21swapper/000:35:120
102549910424,30cyclictest0-21swapper/020:45:130
102549910412,29cyclictest0-21swapper/022:40:120
102549910412,29cyclictest0-21swapper/022:40:110
102609910012,27cyclictest0-21swapper/123:05:121
10254999953,32cyclictest14-21ksoftirqd/019:10:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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