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2025-10-18 - 20:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Sat Oct 18, 2025 12:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199299911211,21cyclictest0-21swapper/009:30:150
199329911080,16cyclictest26-21ksoftirqd/110:20:171
199299911061,36cyclictest14-21ksoftirqd/010:35:150
199299910914,25cyclictest0-21swapper/011:55:140
199299910912,51cyclictest0-21swapper/012:00:140
199299910652,36cyclictest14-21ksoftirqd/011:10:160
199329910574,21cyclictest26-21ksoftirqd/111:25:151
199299910514,26cyclictest0-21swapper/007:25:140
199329910473,19cyclictest26-21ksoftirqd/109:30:131
199299910412,26cyclictest0-21swapper/007:45:140
199299910410,25cyclictest0-21swapper/010:05:140
199329910373,19cyclictest26-21ksoftirqd/111:45:241
199299910313,29cyclictest0-21swapper/011:35:190
199299910313,26cyclictest0-21swapper/007:20:160
199299910313,24cyclictest0-21swapper/010:25:160
199299910313,24cyclictest0-21swapper/010:25:150
199299910313,21cyclictest0-21swapper/012:05:180
199299910312,32cyclictest0-21swapper/009:00:160
199299910312,32cyclictest0-21swapper/007:55:130
199299910311,25cyclictest0-21swapper/007:10:140
19929991029,25cyclictest0-21swapper/009:25:140
199299910213,24cyclictest0-21swapper/008:00:130
199299910212,29cyclictest0-21swapper/010:00:130
199299910211,23cyclictest0-21swapper/012:10:150
199299910210,28cyclictest0-21swapper/009:35:130
199299910210,28cyclictest0-21swapper/009:35:120
199299910210,23cyclictest0-21swapper/009:40:140
199329910169,20cyclictest26-21ksoftirqd/112:15:151
199299910111,30cyclictest0-21swapper/008:35:140
199299910111,29cyclictest0-21swapper/012:35:240
199299910111,27cyclictest0-21swapper/011:20:150
199299910111,24cyclictest0-21swapper/010:10:130
199299910110,22cyclictest0-21swapper/007:30:140
199299910013,29cyclictest0-21swapper/011:15:160
199299910012,30cyclictest0-21swapper/010:20:150
199299910012,23cyclictest0-21swapper/008:30:190
199299910011,26cyclictest0-21swapper/008:50:140
199299910011,22cyclictest0-21swapper/008:05:180
199299910010,24cyclictest0-21swapper/012:30:140
19929999912,26cyclictest0-21swapper/009:45:140
19929999912,25cyclictest0-21swapper/007:40:170
19929999910,28cyclictest0-21swapper/010:55:160
19929999814,27cyclictest0-21swapper/012:20:130
19929999813,29cyclictest0-21swapper/011:40:140
19929999812,26cyclictest0-21swapper/012:25:150
19929999812,26cyclictest0-21swapper/008:25:150
19929999811,25cyclictest0-21swapper/010:40:160
19929999810,25cyclictest0-21swapper/010:30:180
19929999713,26cyclictest0-21swapper/008:10:270
19929999712,24cyclictest0-21swapper/011:00:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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