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2026-07-12 - 21:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Sun Jul 12, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2523629431,51sleep10-21swapper/107:06:531
25714998158,9cyclictest22429-21aten2.4_r3power10:00:260
75282780,10sleep1251rcuc/110:45:371
25715997825,47cyclictest26-21ksoftirqd/108:25:001
2397627527,37sleep00-21swapper/007:05:150
25714997250,15cyclictest9531-21apt-get09:25:150
25714997236,17cyclictest14-21ksoftirqd/011:04:210
25715997119,46cyclictest26-21ksoftirqd/107:35:161
25714997032,20cyclictest14-21ksoftirqd/011:34:270
25714996844,9cyclictest14-21ksoftirqd/008:30:490
25714996837,25cyclictest14-21ksoftirqd/007:38:130
25714996830,14cyclictest14-21ksoftirqd/009:05:000
25715996724,8cyclictest26-21ksoftirqd/108:40:011
25714996730,14cyclictest14-21ksoftirqd/008:00:000
25714996730,14cyclictest14-21ksoftirqd/008:00:000
25714996730,14cyclictest14-21ksoftirqd/007:20:010
25714996725,14cyclictest14-21ksoftirqd/011:30:010
25714996631,15cyclictest14-21ksoftirqd/011:39:000
25714996621,13cyclictest14-21ksoftirqd/008:30:010
25714996532,16cyclictest30127-21head10:20:270
25714996531,13cyclictest14-21ksoftirqd/010:10:050
25714996530,14cyclictest14-21ksoftirqd/011:20:010
25714996529,15cyclictest14-21ksoftirqd/008:15:000
25715996421,38cyclictest26-21ksoftirqd/111:00:121
25714996430,14cyclictest14-21ksoftirqd/011:50:000
25714996429,14cyclictest14-21ksoftirqd/009:45:050
25714996429,14cyclictest14-21ksoftirqd/009:25:000
25714996429,13cyclictest14-21ksoftirqd/012:00:010
25714996428,14cyclictest14-21ksoftirqd/012:25:000
25714996428,14cyclictest14-21ksoftirqd/012:24:590
2571599632,36cyclictest151rcu_preempt08:10:211
25715996320,38cyclictest26-21ksoftirqd/110:10:421
25714996328,14cyclictest14-21ksoftirqd/011:15:010
25714996326,14cyclictest14-21ksoftirqd/007:55:000
25714996325,16cyclictest14-21ksoftirqd/009:39:000
25714996325,15cyclictest14-21ksoftirqd/012:10:000
25714996325,15cyclictest14-21ksoftirqd/007:25:240
25715996237,9cyclictest26-21ksoftirqd/112:04:301
25715996215,22cyclictest151rcu_preempt10:30:371
25714996229,14cyclictest14-21ksoftirqd/007:25:000
25714996227,14cyclictest14-21ksoftirqd/009:15:010
25714996226,15cyclictest14-21ksoftirqd/008:20:010
25714996225,14cyclictest14-21ksoftirqd/008:40:250
25714996224,16cyclictest14-21ksoftirqd/010:55:010
25714996224,14cyclictest14-21ksoftirqd/011:55:000
25715996137,9cyclictest26-21ksoftirqd/109:50:161
25715996125,13cyclictest26-21ksoftirqd/109:30:161
25715996118,8cyclictest26-21ksoftirqd/110:00:211
25715996116,40cyclictest0-21swapper/108:30:361
25715996115,41cyclictest26-21ksoftirqd/107:20:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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