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2026-03-31 - 07:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Tue Mar 31, 2026 00:45:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1709991279,79cyclictest0-21swapper/019:45:160
1709991198,86cyclictest0-21swapper/023:45:130
1709991179,82cyclictest0-21swapper/019:25:130
1709991169,88cyclictest0-21swapper/020:35:140
1709991169,83cyclictest0-21swapper/023:35:130
1709991167,89cyclictest0-21swapper/000:05:180
1709991149,83cyclictest0-21swapper/022:20:120
1709991148,83cyclictest0-21swapper/023:25:140
1709991148,83cyclictest0-21swapper/023:25:130
1709991148,83cyclictest0-21swapper/019:15:140
1709991139,82cyclictest0-21swapper/021:15:130
1709991139,81cyclictest0-21swapper/020:45:120
1709991139,81cyclictest0-21swapper/020:45:110
1709991119,76cyclictest0-21swapper/019:20:120
17099911116,72cyclictest0-21swapper/021:45:120
1709991109,77cyclictest0-21swapper/022:15:130
1709991108,80cyclictest0-21swapper/020:30:130
1709991099,78cyclictest0-21swapper/020:55:140
1709991098,83cyclictest0-21swapper/000:00:120
1709991098,83cyclictest0-21swapper/000:00:110
1709991098,80cyclictest0-21swapper/022:10:170
1709991098,80cyclictest0-21swapper/022:10:170
1709991089,79cyclictest0-21swapper/023:00:130
1709991088,78cyclictest0-21swapper/023:10:140
1709991087,79cyclictest0-21swapper/023:20:110
1709991087,78cyclictest0-21swapper/023:15:110
1709991079,71cyclictest0-21swapper/022:35:130
1709991078,78cyclictest0-21swapper/000:20:130
17099910710,76cyclictest0-21swapper/000:30:130
17099910710,76cyclictest0-21swapper/000:10:140
17119910613,33cyclictest0-21swapper/122:00:111
1709991068,76cyclictest0-21swapper/022:00:150
1709991068,76cyclictest0-21swapper/021:25:110
1709991058,75cyclictest0-21swapper/022:40:110
17119910418,27cyclictest0-21swapper/122:05:131
1709991048,76cyclictest0-21swapper/023:40:120
1709991039,70cyclictest0-21swapper/022:50:130
1709991037,77cyclictest0-21swapper/022:30:140
17099910310,71cyclictest0-21swapper/020:40:130
17119910216,30cyclictest0-21swapper/122:10:151
17119910216,30cyclictest0-21swapper/122:10:141
17099910211,68cyclictest0-21swapper/020:10:120
17119910117,29cyclictest0-21swapper/123:05:131
17119910117,29cyclictest0-21swapper/123:05:121
1709991017,74cyclictest0-21swapper/021:55:150
17119910016,26cyclictest0-21swapper/123:40:161
1709991009,70cyclictest0-21swapper/020:15:150
1709991009,70cyclictest0-21swapper/019:40:110
1709991007,75cyclictest0-21swapper/023:55:160
17099910010,67cyclictest0-21swapper/021:35:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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