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2025-11-26 - 16:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Wed Nov 26, 2025 12:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
209599912010,86cyclictest0-21swapper/009:00:110
209629911715,31cyclictest0-21swapper/108:55:131
209629911511,51cyclictest0-21swapper/111:55:141
209629911511,51cyclictest0-21swapper/111:55:131
209629911420,25cyclictest0-21swapper/111:15:131
209629911418,28cyclictest0-21swapper/108:05:151
209629911214,29cyclictest0-21swapper/111:10:141
209629911013,30cyclictest0-21swapper/110:30:131
209629911013,30cyclictest0-21swapper/109:20:151
209629910612,29cyclictest0-21swapper/110:40:251
209629910612,29cyclictest0-21swapper/110:40:241
209629910414,30cyclictest0-21swapper/111:30:111
20959991036,76cyclictest0-21swapper/010:35:130
20962991028,49cyclictest31477-21diskmemload09:10:141
209629910273,20cyclictest26-21ksoftirqd/112:20:111
20959991028,69cyclictest0-21swapper/007:20:170
20959991026,75cyclictest0-21swapper/011:20:150
20959991026,74cyclictest0-21swapper/010:50:140
20962999912,37cyclictest14139-21users11:20:401
20962999910,39cyclictest1-21systemd07:30:151
2095999997,69cyclictest0-21swapper/008:00:130
2095999986,17cyclictest0-21swapper/009:50:130
20959999815,61cyclictest0-21swapper/007:40:120
20959999814,62cyclictest0-21swapper/008:30:130
20959999813,62cyclictest0-21swapper/009:20:110
2095999979,67cyclictest0-21swapper/011:35:130
2095999979,67cyclictest0-21swapper/011:35:120
2095999977,67cyclictest0-21swapper/010:15:130
2095999967,68cyclictest0-21swapper/007:45:130
20959999527,49cyclictest14-21ksoftirqd/008:05:140
2095999947,67cyclictest0-21swapper/008:45:130
2095999947,65cyclictest0-21swapper/010:20:130
2095999946,67cyclictest0-21swapper/009:25:160
20962999320,25cyclictest0-21swapper/111:45:121
2095999926,66cyclictest0-21swapper/010:30:160
20959999212,58cyclictest0-21swapper/009:35:130
20962999160,19cyclictest26-21ksoftirqd/110:45:121
2095999917,65cyclictest0-21swapper/012:00:150
2095999917,63cyclictest0-21swapper/009:55:130
20959999113,58cyclictest0-21swapper/007:15:150
2050929124,16sleep10-21swapper/107:07:131
2095999907,64cyclictest0-21swapper/012:35:240
2095999907,63cyclictest0-21swapper/008:35:130
2095999906,64cyclictest0-21swapper/012:05:140
2095999898,61cyclictest0-21swapper/012:15:130
2095999898,61cyclictest0-21swapper/012:15:120
2095999897,64cyclictest0-21swapper/007:25:200
2095999897,63cyclictest0-21swapper/010:55:140
2095999897,62cyclictest0-21swapper/011:05:130
2095999896,65cyclictest0-21swapper/009:45:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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