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2026-03-31 - 14:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Tue Mar 31, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30344210338,49sleep00-21swapper/007:05:200
1102621030,7chrt11028-21sh10:45:011
1102621030,7chrt11028-21sh10:45:001
31743999817,20cyclictest0-21swapper/011:30:110
31743999815,19cyclictest0-21swapper/011:10:130
31743999415,19cyclictest0-21swapper/011:20:120
31743999413,17cyclictest0-21swapper/011:45:130
31743999316,16cyclictest0-21swapper/008:05:120
31743999315,20cyclictest0-21swapper/010:00:140
31743999315,17cyclictest0-21swapper/011:50:120
31743999314,19cyclictest0-21swapper/009:15:130
31743999313,17cyclictest0-21swapper/008:30:130
31743999226,61cyclictest250-21systemd-journal09:49:050
31743999218,16cyclictest0-21swapper/011:40:140
31743999217,19cyclictest0-21swapper/009:30:110
31743999215,17cyclictest0-21swapper/012:10:150
31743999214,15cyclictest0-21swapper/010:35:120
31743999213,18cyclictest0-21swapper/012:00:140
31743999114,17cyclictest0-21swapper/010:45:130
31743999113,19cyclictest0-21swapper/008:25:160
31743999113,16cyclictest0-21swapper/009:55:130
31743999113,16cyclictest0-21swapper/009:00:110
31743999019,15cyclictest0-21swapper/008:00:110
31743999016,18cyclictest0-21swapper/011:55:150
31743999016,17cyclictest0-21swapper/008:15:130
31743999016,15cyclictest0-21swapper/011:25:130
31743999015,18cyclictest0-21swapper/010:05:140
31743999015,14cyclictest0-21swapper/007:45:130
31743999014,16cyclictest0-21swapper/008:10:140
31743999013,17cyclictest0-21swapper/010:20:120
31743999013,15cyclictest0-21swapper/009:40:140
31743998918,15cyclictest0-21swapper/010:50:120
31743998916,16cyclictest0-21swapper/011:05:240
31743998915,17cyclictest0-21swapper/007:40:140
31743998914,16cyclictest0-21swapper/012:15:120
31743998913,16cyclictest0-21swapper/008:20:240
31743998912,18cyclictest0-21swapper/007:10:120
31743998912,15cyclictest0-21swapper/011:00:150
31743998817,18cyclictest0-21swapper/007:25:140
31743998815,18cyclictest0-21swapper/011:35:160
31743998815,18cyclictest0-21swapper/011:35:150
31743998815,17cyclictest0-21swapper/007:15:150
31743998815,15cyclictest0-21swapper/008:40:120
31743998815,15cyclictest0-21swapper/008:35:120
31743998815,14cyclictest0-21swapper/012:20:120
31743998811,16cyclictest0-21swapper/007:20:120
31743998810,24cyclictest500-21snmpd10:40:140
31743998810,24cyclictest500-21snmpd10:40:130
31743998724,18cyclictest14-21ksoftirqd/009:20:130
31743998716,15cyclictest0-21swapper/009:35:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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