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2026-05-17 - 13:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack3slot6.osadl.org (updated Sun May 17, 2026 00:45:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
59419912583,28cyclictest0-21swapper/021:30:140
59419912112,96cyclictest0-21swapper/021:00:120
59449911512,54cyclictest0-21swapper/122:55:231
59419911511,84cyclictest0-21swapper/020:05:260
59449911412,56cyclictest0-21swapper/119:45:221
59419911412,87cyclictest0-21swapper/000:10:110
59419911410,89cyclictest0-21swapper/023:30:130
59449911386,18cyclictest26-21ksoftirqd/122:25:161
59449911386,18cyclictest26-21ksoftirqd/122:25:161
59419911311,59cyclictest0-21swapper/022:35:140
59419911311,28cyclictest0-21swapper/020:45:120
59419911212,28cyclictest0-21swapper/019:40:120
59419911212,28cyclictest0-21swapper/019:40:120
59419910948,49cyclictest14-21ksoftirqd/020:40:240
59419910910,80cyclictest0-21swapper/000:05:120
5941991078,17cyclictest0-21swapper/019:10:140
5941991078,17cyclictest0-21swapper/019:10:140
59419910639,51cyclictest14-21ksoftirqd/022:20:120
59419910614,72cyclictest0-21swapper/023:40:130
59419910613,70cyclictest0-21swapper/000:20:110
59419910455,33cyclictest14-21ksoftirqd/019:50:120
59419910412,70cyclictest0-21swapper/020:25:110
59419910312,67cyclictest0-21swapper/022:05:120
59419910211,68cyclictest0-21swapper/000:30:250
59419910211,67cyclictest0-21swapper/023:05:120
59419910211,67cyclictest0-21swapper/000:15:150
59419910115,65cyclictest0-21swapper/022:30:140
59419910113,66cyclictest0-21swapper/020:10:100
59419910112,64cyclictest0-21swapper/022:40:120
59419910111,23cyclictest0-21swapper/022:55:250
59419910013,67cyclictest0-21swapper/021:10:250
59419910012,65cyclictest0-21swapper/021:15:260
59419910012,65cyclictest0-21swapper/020:50:120
59419910010,66cyclictest0-21swapper/022:15:250
5941999956,27cyclictest14-21ksoftirqd/023:00:140
5941999915,63cyclictest0-21swapper/020:15:110
5941999913,63cyclictest0-21swapper/023:25:130
5941999912,64cyclictest0-21swapper/023:45:140
5941999912,64cyclictest0-21swapper/021:55:150
5941999912,64cyclictest0-21swapper/021:40:150
5941999910,67cyclictest0-21swapper/019:35:120
215152990,6chrt20342-21/usr/sbin/munin21:15:511
5941999816,61cyclictest0-21swapper/021:05:140
5941999812,66cyclictest0-21swapper/023:50:260
5941999712,66cyclictest0-21swapper/019:30:250
5941999712,62cyclictest0-21swapper/000:35:150
5944999663,20cyclictest26-21ksoftirqd/123:40:161
5941999614,62cyclictest0-21swapper/023:55:140
5941999614,62cyclictest0-21swapper/023:55:140
5941999613,62cyclictest0-21swapper/019:55:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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