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2022-05-20 - 05:31

x86 Intel Xeon E3-1220L V2 @2300 MHz, Linux 4.19.8-rt6 (Profile)

Latency plot of system in rack #4, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack4slot0.osadl.org (updated Fri May 20, 2022 00:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134002780,0sleep20-21swapper/223:24:072
271382750,1sleep0111rcuc/021:34:340
129602740,0sleep10-21swapper/121:51:061
61472680,0sleep20-21swapper/223:29:212
206052680,0sleep10-21swapper/122:05:491
234912670,0sleep20-21swapper/222:46:092
170732650,0sleep30-21swapper/320:25:173
1747925923,29sleep30-21swapper/319:09:493
1716425526,9sleep10-21swapper/119:06:371
272582490,3sleep21766499cyclictest19:30:182
1742624530,9sleep20-21swapper/219:09:082
1721624427,10sleep00-21swapper/019:06:560
240722410,1sleep2311rcuc/223:32:582
159082320,2sleep21766499cyclictest22:05:012
124212290,0sleep20-21swapper/221:50:592
321242230,0sleep20-21swapper/222:21:282
91752220,1sleep09177-21bash23:23:140
243852220,0sleep00-21swapper/022:00:070
92802210,0sleep10-21swapper/121:11:181
29122210,1sleep12908-21sshd21:29:421
1766599213,1cyclictest0-21swapper/321:38:533
1766399210,1cyclictest0-21swapper/120:28:191
27452200,0sleep30-21swapper/321:29:393
1766599202,1cyclictest0-21swapper/319:17:113
1766599200,3cyclictest0-21swapper/322:25:083
1766599200,3cyclictest0-21swapper/300:29:223
1766499203,1cyclictest0-21swapper/222:00:252
1766499202,3cyclictest13678-21lspci22:44:182
1766499202,1cyclictest0-21swapper/222:32:152
1766399200,3cyclictest0-21swapper/119:53:151
1766399200,3cyclictest0-21swapper/119:29:511
1766299202,1cyclictest0-21swapper/000:02:380
1766299200,3cyclictest0-21swapper/020:53:060
1766599192,2cyclictest0-21swapper/320:11:193
1766599192,1cyclictest0-21swapper/321:45:223
1766599191,1cyclictest0-21swapper/323:20:133
1766599191,1cyclictest0-21swapper/323:06:473
1766599191,1cyclictest0-21swapper/323:01:393
1766599191,1cyclictest0-21swapper/320:50:443
1766599190,4cyclictest13225-21sshd23:17:233
1766599190,2cyclictest0-21swapper/319:36:333
1766599190,2cyclictest0-21swapper/300:35:283
1766599190,1cyclictest0-21swapper/300:01:273
1766499190,2cyclictest0-21swapper/220:15:022
1766499190,1cyclictest0-21swapper/219:50:152
1766499190,1cyclictest0-21swapper/219:38:092
1766399195,2cyclictest0-21swapper/123:15:521
1766399192,3cyclictest0-21swapper/122:40:151
1766399191,3cyclictest0-21swapper/123:34:341
1766399191,1cyclictest25-21ksoftirqd/100:05:351
1766399190,4cyclictest32525-21bash21:22:301
1766399190,3cyclictest458-21lspci22:21:381
1766399190,2cyclictest0-21swapper/123:46:351
1766399190,2cyclictest0-21swapper/122:01:251
1766399190,2cyclictest0-21swapper/100:27:331
1766399190,1cyclictest23159-21bash22:52:521
1766299193,11cyclictest8983-21sshd00:10:560
1766299190,2cyclictest0-21swapper/023:38:570
1766599181,1cyclictest0-21swapper/323:50:503
1766599180,3cyclictest0-21swapper/323:10:203
1766599180,2cyclictest0-21swapper/300:17:333
1766599180,1cyclictest30848-21lspci00:23:373
1766599180,1cyclictest0-21swapper/323:33:173
1766599180,1cyclictest0-21swapper/322:54:553
1766599180,1cyclictest0-21swapper/322:12:573
1766599180,1cyclictest0-21swapper/321:43:113
1766599180,1cyclictest0-21swapper/321:31:573
1766599180,1cyclictest0-21swapper/321:23:493
1766599180,1cyclictest0-21swapper/320:22:203
1766499180,1cyclictest0-21swapper/223:56:062
1766499180,1cyclictest0-21swapper/222:50:132
1766499180,1cyclictest0-21swapper/221:33:102
1766499180,1cyclictest0-21swapper/200:27:242
1766499180,1cyclictest0-21swapper/200:05:292
1766399185,3cyclictest25-21ksoftirqd/119:49:591
1766399180,3cyclictest0-21swapper/121:04:021
1766399180,3cyclictest0-21swapper/120:01:111
1766399180,2cyclictest0-21swapper/123:37:171
1766399180,1cyclictest13754-21kworker/1:222:16:261
1766399180,1cyclictest0-21swapper/121:45:171
1766399180,1cyclictest0-21swapper/120:41:381
1766399180,1cyclictest0-21swapper/119:23:371
1766299182,3cyclictest19179-21sshd22:18:550
1766299182,11cyclictest9-21ksoftirqd/021:23:460
1766299181,10cyclictest9-21ksoftirqd/023:40:260
1766299181,10cyclictest9-21ksoftirqd/023:40:250
1766299180,6cyclictest9-21ksoftirqd/021:10:120
1766299180,3cyclictest4652-21sshd21:30:010
1766299180,3cyclictest0-21swapper/022:50:510
1766299180,1cyclictest0-21swapper/022:09:450
1766299180,1cyclictest0-21swapper/021:40:590
1766299180,1cyclictest0-21swapper/019:35:580
1766299180,1cyclictest0-21swapper/019:23:240
1766299180,1cyclictest0-21swapper/000:24:390
179982170,0sleep00-21swapper/023:45:050
1766599172,1cyclictest0-21swapper/300:09:433
1766599170,1cyclictest0-21swapper/323:47:093
1766599170,1cyclictest0-21swapper/321:19:073
1766599170,1cyclictest0-21swapper/320:38:563
1766599170,0cyclictest0-21swapper/319:42:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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