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2026-01-13 - 08:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Tue Jan 13, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
539421500,3sleep121-21ksoftirqd/122:34:301
539421500,3sleep121-21ksoftirqd/122:34:301
1568121220,3chrt0-21swapper/200:23:022
1568121220,3chrt0-21swapper/200:23:022
110032920,7sleep211004-21cron22:40:262
110032920,7sleep211004-21cron22:40:262
110032920,7sleep211004-21cron22:40:262
143842880,4sleep10-21swapper/120:55:441
143842880,4sleep10-21swapper/120:55:441
40902860,8sleep333-21ksoftirqd/321:27:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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