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2026-02-15 - 01:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Sun Feb 15, 2026 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1521221670,2sleep20-21swapper/221:17:582
1521221670,2sleep20-21swapper/221:17:582
1521221670,2sleep20-21swapper/221:17:582
1016521280,3sleep30-21swapper/321:13:133
1016521280,3sleep30-21swapper/321:13:133
605921160,3chrt6053-21/usr/sbin/munin19:41:091
2734121150,2sleep10-21swapper/122:01:221
2734121150,2sleep10-21swapper/122:01:221
1996221110,3sleep20-21swapper/200:35:362
1996221110,3sleep20-21swapper/200:35:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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