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2026-01-21 - 13:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Wed Jan 21, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
885521340,2sleep20-21swapper/210:09:112
885521340,2sleep20-21swapper/210:09:112
30021320,2sleep30-21swapper/312:10:543
30021320,2sleep30-21swapper/312:10:543
438321270,9sleep333-21ksoftirqd/307:10:503
133782900,3chrt13374-21unixbench_multi11:50:570
133782900,3chrt13374-21unixbench_multi11:50:570
198552880,2sleep30-21swapper/310:20:343
198552880,2sleep30-21swapper/310:20:343
210572870,2sleep20-21swapper/210:54:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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