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2026-01-28 - 17:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Wed Jan 28, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2830121440,3sleep10-21swapper/109:24:091
2830121440,3sleep10-21swapper/109:24:091
611521160,5sleep10-21swapper/107:16:021
611521160,5sleep10-21swapper/107:16:021
935121020,3sleep10-21swapper/112:20:401
935121020,3sleep10-21swapper/112:20:401
2910621000,3sleep0151rcuc/008:20:550
169692850,3sleep00-21swapper/011:55:440
169692850,3sleep00-21swapper/011:55:440
301742820,4sleep030178-21fschecks_count10:30:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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