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2026-01-26 - 17:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Mon Jan 26, 2026 12:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1672621600,3sleep00-21swapper/010:23:160
1672621600,3sleep00-21swapper/010:23:160
944221090,1sleep30-21swapper/310:48:233
2716621090,2sleep30-21swapper/311:38:063
2716621090,2sleep30-21swapper/311:38:063
2716621090,2sleep30-21swapper/311:38:063
3067821030,3sleep30-21swapper/311:09:573
3067821030,3sleep30-21swapper/311:09:573
2641521010,2chrt0-21swapper/109:27:351
2641521010,2chrt0-21swapper/109:27:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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