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2026-01-27 - 07:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Tue Jan 27, 2026 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2397921640,2sleep0151rcuc/023:41:030
2397921640,2sleep0151rcuc/023:41:030
1577721130,2sleep115779-21sh00:06:001
34002820,3sleep30-21swapper/321:43:393
34002820,3sleep30-21swapper/321:43:393
297082780,3chrt0-21swapper/119:26:011
297082780,3chrt0-21swapper/119:26:011
281312780,3sleep227-21ksoftirqd/222:08:012
281312780,3sleep227-21ksoftirqd/222:08:012
179882770,2chrt0-21swapper/200:08:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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