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2026-03-06 - 05:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Thu Mar 05, 2026 19:41:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2092322050,6sleep30-21swapper/319:11:443
228532920,5sleep122852-21grep19:16:411
228532920,5sleep122852-21grep19:16:411
213592800,3sleep20-21swapper/219:12:562
199602530,2sleep019746-21ls19:11:290
274632350,1sleep127492-21latency_hist19:31:241
274632350,1sleep127492-21latency_hist19:31:241
269332280,3sleep30-21swapper/319:26:553
269332280,3sleep30-21swapper/319:26:553
2127499271,9cyclictest26625-21find19:26:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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