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2026-01-29 - 06:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Thu Jan 29, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
650521270,4sleep227-21ksoftirqd/200:17:272
650521270,4sleep227-21ksoftirqd/200:17:272
650521270,4sleep227-21ksoftirqd/200:17:272
2322521260,3sleep10-21swapper/100:01:101
2386221220,4sleep20-21swapper/222:56:372
2386221220,4sleep20-21swapper/222:56:372
3199721120,2sleep20-21swapper/223:05:532
3199721120,2sleep20-21swapper/223:05:532
3045921060,4sleep20-21swapper/200:09:312
85542920,3sleep10-21swapper/121:36:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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