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2026-01-23 - 00:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Thu Jan 22, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3136521320,2sleep30-21swapper/309:55:573
3136521320,2sleep30-21swapper/309:55:573
1728221250,4sleep30-21swapper/312:05:133
1728221250,4sleep30-21swapper/312:05:133
1528421150,3sleep00-21swapper/012:02:290
1528421150,3sleep00-21swapper/012:02:290
1061621090,4sleep00-21swapper/008:30:540
1061621090,4sleep00-21swapper/008:30:540
3026921020,2sleep30-21swapper/309:15:503
3026921020,2sleep30-21swapper/309:15:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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