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2026-02-14 - 00:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Fri Feb 13, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2939521540,4sleep00-21swapper/011:11:280
2939521540,4sleep00-21swapper/011:11:280
2640821060,3sleep20-21swapper/207:16:162
2640821060,3sleep20-21swapper/207:16:162
3016721030,3chrt30169-21grep07:26:161
3016721030,3chrt30169-21grep07:26:161
84542980,3sleep10-21swapper/112:26:451
84542980,3sleep10-21swapper/112:26:451
161322870,3chrt0-21swapper/112:02:421
175072860,3sleep20-21swapper/210:28:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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