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2026-02-04 - 00:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Tue Feb 03, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
106321530,3sleep00-21swapper/010:11:560
2363921450,3sleep30-21swapper/310:35:133
2363921450,3sleep30-21swapper/310:35:133
1642321330,3chrt0-21swapper/310:27:263
1642321330,3chrt0-21swapper/310:27:263
2915421240,2chrt0-21swapper/309:35:583
2915421240,2chrt0-21swapper/309:35:583
649521170,4sleep333-21ksoftirqd/307:46:033
649521170,4sleep333-21ksoftirqd/307:46:033
29232990,2chrt0-21swapper/209:41:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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