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2026-01-22 - 02:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Thu Jan 22, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2003621330,4sleep0151rcuc/023:04:330
2003621330,4sleep0151rcuc/023:04:330
2479521290,1chrt0-21swapper/223:41:082
2479521290,1chrt0-21swapper/223:41:082
3164621270,3chrt0-21swapper/122:43:121
3164621270,3chrt0-21swapper/122:43:121
2290021270,3sleep00-21swapper/020:30:500
2675621240,3sleep00-21swapper/023:10:520
2222221230,3sleep30-21swapper/320:30:373
2222221230,3sleep30-21swapper/320:30:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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