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2026-01-27 - 17:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Tue Jan 27, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1218521510,3sleep00-21swapper/010:06:010
1218521510,3sleep00-21swapper/010:06:010
668121490,2sleep30-21swapper/309:28:183
668121490,2sleep30-21swapper/309:28:183
1905821460,3sleep10-21swapper/111:50:351
1905821460,3sleep10-21swapper/111:50:351
51721220,3sleep20-21swapper/209:55:022
51721220,3sleep20-21swapper/209:55:022
1702721210,3sleep20-21swapper/207:30:512
1702721210,3sleep20-21swapper/207:30:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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