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2026-02-09 - 20:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Mon Feb 09, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2416221170,3chrt0-21swapper/012:10:540
2416221170,3chrt0-21swapper/012:10:540
2991521100,3chrt0-21swapper/312:16:083
2991521100,3chrt0-21swapper/312:16:083
2040521040,3sleep00-21swapper/009:58:480
2040521040,3sleep00-21swapper/009:58:480
839421030,3chrt7703-21/usr/sbin/munin07:51:112
839421030,3chrt7703-21/usr/sbin/munin07:51:112
3259621020,2sleep30-21swapper/311:15:193
3259621020,2sleep30-21swapper/311:15:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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