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2026-01-25 - 02:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Sun Jan 25, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
842921510,2sleep30-21swapper/321:25:453
842921510,2sleep30-21swapper/321:25:453
2398621430,3sleep30-21swapper/321:05:483
2398621430,3sleep30-21swapper/321:05:483
3038121280,3sleep30-21swapper/300:29:313
3038121280,3sleep30-21swapper/300:29:313
1444421280,2sleep30-21swapper/323:08:133
1390321280,2sleep30-21swapper/320:35:583
1390321280,2sleep30-21swapper/320:35:583
2419621130,3sleep10-21swapper/123:17:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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