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2026-01-16 - 08:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Fri Jan 16, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
463521570,4sleep30-21swapper/300:13:503
463521570,4sleep30-21swapper/300:13:503
1574121330,2sleep115743-21ssh22:46:151
1574121330,2sleep115743-21ssh22:46:151
2104521250,6sleep121-21ksoftirqd/122:51:381
2104521250,6sleep121-21ksoftirqd/122:51:381
1305621200,4sleep0482-21snmpd23:16:080
1305621200,4sleep0482-21snmpd23:16:080
2069421170,4sleep00-21swapper/000:30:190
2069421170,4sleep00-21swapper/000:30:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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