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2026-02-02 - 19:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Mon Feb 02, 2026 12:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3107221200,4sleep10-21swapper/109:20:581
3107221200,4sleep10-21swapper/109:20:581
1184921160,3sleep30-21swapper/311:11:153
2705421030,3chrt0-21swapper/312:31:093
2705421030,3chrt0-21swapper/312:31:093
269522980,3sleep10-21swapper/110:21:061
269522980,3sleep10-21swapper/110:21:061
29092970,3chrt0-21swapper/311:35:473
29092970,3chrt0-21swapper/311:35:473
212032940,3sleep30-21swapper/311:21:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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