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2026-01-14 - 12:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Wed Jan 14, 2026 00:45:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2342821420,2sleep10-21swapper/100:06:391
2342821420,2sleep10-21swapper/100:06:391
95621390,3chrt0-21swapper/219:10:512
95621390,3chrt0-21swapper/219:10:512
1231121190,4chrt0-21swapper/219:45:312
1231121190,4chrt0-21swapper/219:45:312
2592121160,1sleep2131rcu_preempt20:20:472
935621050,3chrt0-21swapper/222:14:202
935621050,3chrt0-21swapper/222:14:202
2388621030,3sleep20-21swapper/223:35:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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