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2026-03-05 - 05:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Wed Mar 04, 2026 22:01:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2993321590,2sleep30-21swapper/321:47:333
2739321260,2sleep30-21swapper/319:51:373
2398721070,3chrt0-21swapper/121:41:311
2398721070,3chrt0-21swapper/121:41:311
2360321000,2sleep123598-21find21:06:381
2360321000,2sleep123598-21find21:06:381
312252970,2sleep131220-21find20:01:401
206682750,7sleep121-21ksoftirqd/121:38:141
206682750,7sleep121-21ksoftirqd/121:38:141
206682750,7sleep121-21ksoftirqd/121:38:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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