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2026-01-26 - 05:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot1.osadl.org (updated Mon Jan 26, 2026 00:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2460321310,4sleep30-21swapper/322:52:513
2460321310,4sleep30-21swapper/322:52:513
2036221300,2sleep30-21swapper/300:26:033
2036221300,2sleep30-21swapper/300:26:033
3139421090,3sleep30-21swapper/321:55:403
3139421090,3sleep30-21swapper/321:55:403
860821060,2sleep10-21swapper/119:11:021
860821060,2sleep10-21swapper/119:11:021
1333621010,3sleep30-21swapper/322:09:513
1333621010,3sleep30-21swapper/322:09:513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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