You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-01 - 06:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack4slot1.osadl.org (updated Sat Feb 28, 2026 19:46:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35882550,3sleep00-21swapper/019:16:390
35882550,3sleep00-21swapper/019:16:390
34412350,3sleep30-21swapper/319:16:383
34412350,3sleep30-21swapper/319:16:383
16622311,24sleep30-21swapper/319:11:413
16622311,24sleep30-21swapper/319:11:413
16202316,15sleep00-21swapper/019:11:220
16202316,15sleep00-21swapper/019:11:220
16682265,14sleep20-21swapper/219:11:442
16682265,14sleep20-21swapper/219:11:442
171699228,11cyclictest2450-21fschecks_count19:16:262
171699228,11cyclictest2450-21fschecks_count19:16:262
171499201,14cyclictest6103-21ls19:31:280
171499201,14cyclictest6103-21ls19:31:280
16602204,10sleep11425-21ls19:11:391
16602204,10sleep11425-21ls19:11:391
171699198,9cyclictest5485-21cat19:31:172
171699198,9cyclictest5485-21cat19:31:172
171699191,10cyclictest695-21runrttasks19:33:022
171699191,10cyclictest695-21runrttasks19:33:022
1714991912,5cyclictest0-21swapper/019:25:410
1714991912,5cyclictest0-21swapper/019:25:410
171699171,9cyclictest695-21runrttasks19:36:382
171699171,9cyclictest695-21runrttasks19:36:382
1716991711,4cyclictest8581-21idleruntime-cro19:46:122
171599179,5cyclictest2916-21uname19:16:311
171599179,5cyclictest2916-21uname19:16:311
171599170,5cyclictest80482cat19:41:171
171599170,5cyclictest80482cat19:41:171
171499171,7cyclictest5550-21ls19:31:200
171499171,7cyclictest5550-21ls19:31:200
171499171,5cyclictest0-21swapper/019:46:140
171699161,7cyclictest4696-21cron19:26:112
171699161,7cyclictest4696-21cron19:26:112
171599161,14cyclictest0-21swapper/119:43:141
171599161,12cyclictest6714-21sed19:31:361
171599161,12cyclictest6714-21sed19:31:361
171499161,5cyclictest7903-21latency_hist19:41:120
171499161,5cyclictest7903-21latency_hist19:41:120
171799151,11cyclictest8049-21taskset19:41:183
171799151,11cyclictest8049-21taskset19:41:183
171599151,12cyclictest695-21runrttasks19:26:141
171599151,12cyclictest695-21runrttasks19:26:141
171599151,11cyclictest5563-21latency_hist19:31:201
171599151,11cyclictest5563-21latency_hist19:31:201
171799141,10cyclictest5210-21chrt19:29:363
171799141,10cyclictest5210-21chrt19:29:363
171799133,7cyclictest0-21swapper/319:36:183
171799133,7cyclictest0-21swapper/319:36:183
171799127,3cyclictest82182chrt19:42:103
171799110,9cyclictest4433-21chrt19:23:133
171799110,9cyclictest4433-21chrt19:23:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional