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2026-03-09 - 14:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot1.osadl.org (updated Mon Mar 09, 2026 07:16:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76982580,2sleep27775-21/usr/sbin/munin07:11:452
76982580,2sleep27775-21/usr/sbin/munin07:11:452
67402540,3sleep06498-21ls07:11:310
67402540,3sleep06498-21ls07:11:310
72312257,9sleep10-21swapper/107:11:361
72312257,9sleep10-21swapper/107:11:361
80032221,15sleep30-21swapper/307:11:553
80032221,15sleep30-21swapper/307:11:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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