You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-22 - 14:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack4slot2.osadl.org (updated Sun Feb 22, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501960,0irq/46-4a1000001698-21runrttasks07:07:180
17729913143,0cyclictest0-21swapper11:08:030
17729912939,0cyclictest0-21swapper08:37:460
17729912841,0cyclictest0-21swapper12:24:450
17729912641,0cyclictest0-21swapper11:53:170
17729912641,0cyclictest0-21swapper07:58:220
17729912640,0cyclictest0-21swapper11:42:400
17729912640,0cyclictest0-21swapper10:32:320
17729912541,0cyclictest0-21swapper11:38:200
17729912439,0cyclictest0-21swapper12:33:190
17729912341,0cyclictest0-21swapper12:13:580
17729912341,0cyclictest0-21swapper09:48:020
17729912341,0cyclictest0-21swapper08:57:400
17729912339,0cyclictest0-21swapper08:18:310
17729912235,0cyclictest0-21swapper10:12:330
17729912139,0cyclictest0-21swapper10:53:170
17729911135,0cyclictest0-21swapper07:28:250
1772999372,0cyclictest0-21swapper10:02:420
1772999260,0cyclictest0-21swapper11:57:520
1772999159,0cyclictest0-21swapper10:18:230
1772999156,0cyclictest0-21swapper10:37:470
1772999057,0cyclictest0-21swapper08:03:050
1772999057,0cyclictest0-21swapper07:22:580
1772998958,0cyclictest0-21swapper09:53:200
1772998958,0cyclictest0-21swapper09:12:410
1772998955,0cyclictest0-21swapper07:48:080
1772998856,0cyclictest0-21swapper08:52:410
1772998855,0cyclictest0-21swapper09:38:180
1772998855,0cyclictest0-21swapper09:08:100
1772998855,0cyclictest0-21swapper08:47:410
1772998854,0cyclictest0-21swapper11:48:150
1772998854,0cyclictest0-21swapper07:53:200
1772998666,0cyclictest0-21swapper10:33:290
1772998664,0cyclictest0-21swapper10:42:400
1772998657,0cyclictest0-21swapper08:13:200
1772998653,0cyclictest0-21swapper07:38:220
1772998555,0cyclictest0-21swapper11:13:160
1772998553,0cyclictest0-21swapper12:18:290
1772998552,0cyclictest0-21swapper11:23:130
1772998552,0cyclictest0-21swapper08:43:190
1772998453,0cyclictest0-21swapper07:18:000
1772998451,0cyclictest0-21swapper07:13:370
1772998352,0cyclictest0-21swapper07:32:480
1772998350,0cyclictest0-21swapper09:28:260
1772998250,0cyclictest0-21swapper09:03:190
1772998150,0cyclictest0-21swapper08:08:040
1772998148,0cyclictest0-21swapper07:43:050
7350800,0irq/45-4a10000013344-21memory10:48:160
1772997948,0cyclictest0-21swapper10:57:560
1772997946,0cyclictest0-21swapper11:33:060
7350780,0irq/45-4a10000024449-21runrttasks09:46:400
7350780,0irq/45-4a10000021217-21latency_hist09:37:330
7350770,0irq/45-4a100000500-21kworker/0:312:04:360
7350770,0irq/45-4a10000028975-21/usr/sbin/munin08:23:230
7350770,0irq/45-4a10000028010-21wc11:32:310
1772997745,0cyclictest0-21swapper11:18:210
7350760,0irq/45-4a1000005188-21cat10:23:270
7350760,0irq/45-4a10000032600-1kworker/u3:007:07:470
7350760,0irq/45-4a10000019172-1kworker/u3:208:33:170
7350760,0irq/45-4a10000018372-21interrupts11:03:030
7350760,0irq/45-4a10000017227-21chrt09:23:290
1772997643,0cyclictest0-21swapper12:08:270
7350750,0irq/45-4a10000028717-21meminfo09:58:100
7350750,0irq/45-4a10000012-21ksoftirqd/008:31:470
7450740,0irq/46-4a10000015335-21grep09:18:240
7350740,0irq/45-4a10000015308-21mailstats12:28:250
5472730,0sleep0448-1kworker/u3:010:11:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional