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2026-02-27 - 20:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack4slot2.osadl.org (updated Fri Feb 27, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73502460,0irq/45-4a10000018703-21kworker/0:407:06:440
243109912749,0cyclictest0-21swapper07:08:080
243109912657,0cyclictest0-21swapper09:52:560
243109912646,0cyclictest0-21swapper09:57:520
243109910856,0cyclictest0-21swapper08:57:590
243109910348,0cyclictest0-21swapper07:48:120
24310999949,0cyclictest0-21swapper11:47:420
24310999674,0cyclictest0-21swapper12:22:560
24310999259,0cyclictest0-21swapper07:18:020
24310999159,0cyclictest0-21swapper07:22:370
24310999157,0cyclictest0-21swapper11:43:080
24310999067,0cyclictest0-21swapper11:33:030
24310999059,0cyclictest0-21swapper11:13:090
24310999058,0cyclictest0-21swapper09:28:100
24310999058,0cyclictest0-21swapper08:22:330
24310999058,0cyclictest0-21swapper08:02:560
24310998966,0cyclictest0-21swapper10:37:510
24310998958,0cyclictest0-21swapper08:08:080
24310998954,0cyclictest0-21swapper10:57:580
24310998951,0cyclictest0-21swapper07:38:020
24310998867,0cyclictest0-21swapper12:03:160
24310998857,0cyclictest0-21swapper12:17:590
24310998856,0cyclictest0-21swapper11:53:140
24310998856,0cyclictest0-21swapper08:53:050
24310998856,0cyclictest0-21swapper08:32:570
24310998856,0cyclictest0-21swapper07:57:520
24310998855,0cyclictest0-21swapper08:48:100
1258328818,0sleep012625-21sed11:17:570
7350870,0irq/45-4a1000007573-21ntpq11:03:030
24310998757,0cyclictest0-21swapper10:32:520
24310998756,0cyclictest0-21swapper10:17:510
24310998756,0cyclictest0-21swapper10:08:120
24310998756,0cyclictest0-21swapper09:22:520
24310998756,0cyclictest0-21swapper08:47:180
24310998753,0cyclictest0-21swapper11:57:320
24310998753,0cyclictest0-21swapper08:28:130
24310998654,0cyclictest0-21swapper12:13:150
24310998654,0cyclictest0-21swapper10:22:420
24310998654,0cyclictest0-21swapper09:48:030
24310998555,0cyclictest0-21swapper07:33:380
24310998554,0cyclictest0-21swapper09:03:070
7350840,0irq/45-4a1000004090-21meminfo10:52:570
24310998454,0cyclictest0-21swapper12:07:380
24310998453,0cyclictest0-21swapper08:13:050
7450830,0irq/46-4a100000460-21snmpd08:19:180
7350830,0irq/45-4a10000016816-21seq11:30:400
24310998352,0cyclictest0-21swapper10:28:160
7350820,0irq/45-4a1000003957-21fw_forwarded_lo12:27:480
7350820,0irq/45-4a10000022730-21fw_conntrack08:37:480
7350820,0irq/45-4a10000022487-21df10:12:350
24310998251,0cyclictest0-21swapper09:12:420
24310998249,0cyclictest0-21swapper09:32:430
24310998148,0cyclictest0-21swapper11:37:290
7350800,0irq/45-4a1000006789-21modprobe12:37:180
24310998049,0cyclictest0-21swapper07:27:500
24310998048,0cyclictest0-21swapper09:43:000
24310998048,0cyclictest0-21swapper09:38:050
7450790,0irq/46-4a1000001629-21chrt10:47:090
7350790,0irq/45-4a100000440-21grep09:07:440
7350790,0irq/45-4a1000002856-21sendmail-mta10:48:220
24310997948,0cyclictest0-21swapper07:43:080
7350780,0irq/45-4a1000004525-21sed09:18:160
24310997847,0cyclictest0-21swapper07:53:140
7450770,0irq/46-4a10000019704-21which10:03:100
261702770,0chrt25560-1kworker/u3:207:12:240
7350760,0irq/45-4a1000008904-21sed11:07:360
7450740,0irq/46-4a10000014027-1kworker/u3:011:22:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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