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2026-01-26 - 04:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Mon Jan 26, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501970,0irq/46-4a1000005862-21runrttasks19:04:520
7450940,0irq/46-4a1000008986-21sed20:48:500
7450940,0irq/46-4a10000014509-21memory21:04:180
7450930,0irq/46-4a10000030862-21runrttasks23:28:330
7450930,0irq/46-4a10000018110-21rt-features21:14:260
7450930,0irq/46-4a10000014490-21meminfo19:29:150
7450930,0irq/46-4a10000012716-21irqstats20:59:090
7450920,0irq/46-4a1000007955-21sensors23:54:280
7450920,0irq/46-4a1000002800-21basename23:39:260
7450920,0irq/46-4a10000022635-21df19:53:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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