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2026-02-28 - 12:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Sat Feb 28, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502770,0irq/46-4a1000006804-1kworker/u3:119:06:260
72669913141,0cyclictest10281-21/usr/sbin/munin20:47:590
72669912535,0cyclictest27423-21awk21:38:050
72669912533,0cyclictest21932-21df_abs22:57:360
72669912531,0cyclictest8823-21runrttasks19:11:220
72669912444,0cyclictest4768-21/usr/sbin/munin23:42:330
72669912439,0cyclictest28814-21fschecks_count21:42:410
72669912339,0cyclictest20105-21/usr/sbin/munin22:52:320
72669912335,0cyclictest29015-21irqstats23:17:550
72669912334,0cyclictest15743-21runrttasks19:28:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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