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2026-01-24 - 08:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Sat Jan 24, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73501990,0irq/45-4a10000029468-21kworker/0:019:03:470
7350940,0irq/45-4a1000009331-21fschecks_time00:19:030
58172930,0sleep01889-1kworker/u3:122:34:000
7350890,0irq/45-4a10000016262-21chrt21:29:140
49012890,0sleep01366-1kworker/u3:220:54:530
7450880,0irq/46-4a10000030501-21seq22:09:400
7450870,0irq/46-4a10000026380-21fschecks_count21:59:030
7450860,0irq/46-4a1000005124-1kworker/u3:021:04:170
7450860,0irq/46-4a1000005102-21seq22:31:310
7450860,0irq/46-4a10000020995-21wget21:43:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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