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2026-01-31 - 12:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Sat Jan 31, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73502120,0irq/45-4a10000014703-21kworker/0:219:03:370
166539911577,0cyclictest4292-21idleruntime-cro20:08:220
166539911175,0cyclictest28191-21cron21:18:210
166539910978,0cyclictest4707-21df_inode20:08:420
166539910887,0cyclictest25602-21ntpdc19:34:090
166539910778,0cyclictest28348-21/usr/sbin/munin19:43:310
166539910687,0cyclictest13144-21/usr/sbin/munin23:43:350
166539910685,0cyclictest16696-21df_inode22:18:420
166539910677,0cyclictest13247-21df_inode22:08:390
166539910676,0cyclictest32063-21/usr/sbin/munin23:03:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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