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2026-02-23 - 07:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Mon Feb 23, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73502010,0irq/45-4a10000018386-21kworker/0:319:03:210
7450970,0irq/46-4a10000010445-21ps20:13:200
7450960,0irq/46-4a10000011998-21chrt23:28:080
7450950,0irq/46-4a10000029106-21runrttasks22:43:100
7450950,0irq/46-4a10000024137-21chrt00:03:180
7450950,0irq/46-4a10000022459-21zcat20:48:220
7450950,0irq/46-4a10000022419-21proc_pri23:58:200
7450950,0irq/46-4a10000021026-21users22:18:300
7450950,0irq/46-4a10000013001-21munin-run20:22:280
7450940,0irq/46-4a1000006935-21nfs_client21:38:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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