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2026-02-25 - 09:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Wed Feb 25, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501940,0irq/46-4a10000014838-21runrttasks19:03:520
7450920,0irq/46-4a10000026395-21wget19:37:370
7350880,0irq/45-4a1000004609-21/usr/sbin/munin21:43:010
265622880,0sleep025885-1kworker/u3:022:47:440
7450870,0irq/46-4a10000025885-21runrttasks21:10:270
17532860,0sleep031110-1kworker/u3:119:58:340
7450850,0irq/46-4a1000008096-21runrttasks23:28:060
7350850,0irq/45-4a1000005808-21aten_r4power_en21:47:340
7350850,0irq/45-4a10000016339-21runrttasks23:52:460
156282850,0chrt15089-1kworker/u3:119:07:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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