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2026-01-28 - 19:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Wed Jan 28, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74509020,0irq/46-4a10000010962-1kworker/u3:107:07:000
7350930,0irq/45-4a10000029248-1kworker/u3:109:38:310
11922999258,0cyclictest0-21swapper11:49:210
11922999258,0cyclictest0-21swapper07:49:260
38422917,0sleep03906-21ps09:54:180
11922999158,0cyclictest0-21swapper10:03:390
11922999157,0cyclictest0-21swapper08:14:020
11922999155,0cyclictest0-21swapper12:09:020
11922999057,0cyclictest0-21swapper11:39:200
11922999057,0cyclictest0-21swapper07:54:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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