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2026-02-24 - 08:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Tue Feb 24, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501880,0irq/46-4a10000020865-21/usr/sbin/munin19:03:090
256392897,0sleep025641-21cron20:52:250
7450860,0irq/46-4a100000460-21snmpd23:00:060
7450850,0irq/46-4a1000008001-21unixbench_singl23:08:230
938628414,0sleep021666-21cyclictest23:13:140
7450840,0irq/46-4a10000016389-21seq23:33:160
7450840,0irq/46-4a10000011132-21ntp_states23:18:150
7450830,0irq/46-4a1000009028-21seq21:37:490
7450830,0irq/46-4a1000005188-21munin-run00:37:260
7450830,0irq/46-4a10000022947-21runrttasks19:09:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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