You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-27 - 18:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Tue Jan 27, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501910,0irq/46-4a10000031173-21runrttasks07:07:250
31356999656,0cyclictest0-21swapper10:59:200
7450940,0irq/46-4a10000021158-21users08:09:300
31356999360,0cyclictest0-21swapper08:04:170
31356999260,0cyclictest0-21swapper12:24:070
31356999169,0cyclictest0-21swapper10:24:140
31356999159,0cyclictest0-21swapper07:19:220
31356999157,0cyclictest0-21swapper08:33:450
31356999157,0cyclictest0-21swapper08:14:240
31356998959,0cyclictest0-21swapper07:34:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional