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2026-01-25 - 08:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Sun Jan 25, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73502080,0irq/45-4a1000002631-21kworker/0:119:03:390
8082999975,0cyclictest3455-21runrttasks22:02:590
8082999676,0cyclictest12673-21/usr/sbin/munin20:54:100
8082999573,0cyclictest5699-21seq23:43:560
8082999471,0cyclictest19502-21runrttasks19:39:070
8082999469,0cyclictest18033-21ntpdc22:44:210
8082999376,0cyclictest17825-21perl00:19:070
8082999373,0cyclictest21963-21runrttasks21:20:340
8082999371,0cyclictest16622-21unixbench_singl19:29:320
8082999370,0cyclictest11892-21runrttasks19:17:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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