You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-22 - 18:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Sun Feb 22, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501960,0irq/46-4a1000001698-21runrttasks07:07:180
17729913143,0cyclictest0-21swapper11:08:030
17729912939,0cyclictest0-21swapper08:37:460
17729912841,0cyclictest0-21swapper12:24:450
17729912641,0cyclictest0-21swapper11:53:170
17729912641,0cyclictest0-21swapper07:58:220
17729912640,0cyclictest0-21swapper11:42:400
17729912640,0cyclictest0-21swapper10:32:320
17729912541,0cyclictest0-21swapper11:38:200
17729912439,0cyclictest0-21swapper12:33:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional