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2026-01-19 - 17:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Mon Jan 19, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73504830,0irq/45-4a1000008486-21kworker/0:207:03:590
105399910984,0cyclictest9243-21/usr/sbin/munin08:39:350
105399910783,0cyclictest2255-21irqstats11:29:250
105399910584,0cyclictest19250-21fw_conntrack09:09:180
105399910581,0cyclictest24477-21irqstats10:59:270
105399910484,0cyclictest22876-21/usr/sbin/munin12:29:340
105399910484,0cyclictest20724-21df10:49:050
105399910484,0cyclictest12629-21munin-node07:14:050
105399910481,0cyclictest27351-21/usr/sbin/munin09:34:440
105399910476,0cyclictest22522-21df_inode10:54:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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