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2026-02-08 - 16:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Sun Feb 08, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502570,0irq/46-4a10000016612-1kworker/u3:107:07:090
7450960,0irq/46-4a1000002804-21latency11:08:410
7450950,0irq/46-4a10000018526-21swap08:43:570
16910999561,0cyclictest0-21swapper07:14:100
7450940,0irq/46-4a1000004643-21ntpq09:38:490
7450940,0irq/46-4a10000027160-21wc10:43:580
7450940,0irq/46-4a10000014419-21df_abs10:08:210
7450930,0irq/46-4a1000009551-21if_err_eth009:53:350
7450930,0irq/46-4a100000561-21aten_r4power_en09:28:100
7450930,0irq/46-4a100000460-21snmpd12:26:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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