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2026-02-04 - 13:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Wed Feb 04, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502410,0irq/46-4a10000021062-1kworker/u3:219:05:260
7450970,0irq/46-4a1000005226-21seq21:23:560
7450950,0irq/46-4a10000013839-21ntp_kernel_pll_23:23:580
7450940,0irq/46-4a10000024588-21ls19:13:190
7450930,0irq/46-4a1000003727-21wc22:54:070
7450930,0irq/46-4a10000026823-21/usr/sbin/munin22:29:030
7450930,0irq/46-4a10000025578-21fschecks_time23:58:420
7350930,0irq/45-4a10000015088-21sed23:28:300
7450920,0irq/46-4a10000030551-21chrt00:13:330
7450920,0irq/46-4a10000022990-21chrt23:50:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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