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2026-02-03 - 12:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Tue Feb 03, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
745010420,0irq/46-4a10000028045-1kworker/u3:019:03:290
301129912628,0cyclictest1648-1kworker/u3:120:58:260
301129912336,0cyclictest19554-21/usr/sbin/munin23:19:000
301129912332,0cyclictest3944-21chrt19:23:460
301129912235,0cyclictest17360-21/usr/sbin/munin20:03:310
301129912233,0cyclictest2233-21/usr/sbin/munin20:53:490
301129912135,0cyclictest32483-21seq20:48:180
301129912134,0cyclictest5793-21/usr/sbin/munin19:28:570
301129912132,0cyclictest8830-21/usr/sbin/munin00:23:310
301129912039,0cyclictest26128-21fschecks_time22:03:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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