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2026-01-26 - 16:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Mon Jan 26, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73502760,0irq/45-4a100000215192sleep007:05:270
219359910373,0cyclictest3407-21runrttasks07:46:040
219359910278,0cyclictest17829-21forks08:28:570
219359910277,0cyclictest733-21diskstats09:13:570
219359910277,0cyclictest32406-1kworker/u3:210:46:390
219359910277,0cyclictest31712-21irqstats07:34:100
219359910276,0cyclictest10316-1kworker/u3:211:19:450
219359910179,0cyclictest18824-21sshd10:06:240
219359910177,0cyclictest31429-21df12:18:510
219359910176,0cyclictest15586-1kworker/u3:108:26:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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