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2026-01-22 - 16:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Thu Jan 22, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501980,0irq/46-4a1000001554-21runrttasks07:08:040
16829913453,0cyclictest0-21swapper10:03:540
16829913151,0cyclictest0-21swapper10:46:220
1682999869,0cyclictest0-21swapper07:59:070
1682999269,0cyclictest0-21swapper09:34:380
1682999258,0cyclictest0-21swapper10:59:260
1682999159,0cyclictest0-21swapper11:59:400
1682999158,0cyclictest0-21swapper07:19:260
1682999157,0cyclictest0-21swapper08:44:340
1682999058,0cyclictest0-21swapper09:53:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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