You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-28 - 07:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Wed Jan 28, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74501940,0irq/46-4a1000003834-21runrttasks19:06:530
7450960,0irq/46-4a1000004668-21runrttasks23:53:290
7450940,0irq/46-4a10000027889-21runrttasks23:24:220
7350940,0irq/45-4a10000011834-21df22:38:440
7450930,0irq/46-4a10000027570-21/usr/sbin/munin20:14:080
7450930,0irq/46-4a10000024035-21seq21:38:590
7450930,0irq/46-4a10000015233-21seq21:13:470
205832930,0sleep018314-1kworker/u3:223:03:570
7450920,0irq/46-4a1000006710-21chrt20:48:460
7450920,0irq/46-4a10000032637-21/usr/sbin/munin23:39:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional