You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-30 - 12:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Fri Jan 30, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502760,0irq/46-4a100000229982sleep019:04:380
7450990,0irq/46-4a10000014421-21/usr/sbin/munin23:23:540
29482970,0sleep01768-1kworker/u3:021:14:230
7450960,0irq/46-4a1000007504-21fschecks_time21:28:520
7450960,0irq/46-4a10000032109-21users19:29:270
7450960,0irq/46-4a10000026394-21/usr/sbin/munin23:58:540
7450960,0irq/46-4a10000021245-21runrttasks20:33:580
7450950,0irq/46-4a10000029615-21df19:23:410
7450950,0irq/46-4a10000025706-1kworker/u3:122:29:080
191252950,0sleep018539-1kworker/u3:122:03:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional