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2026-02-18 - 18:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Wed Feb 18, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502740,0irq/46-4a1000007376-1kworker/u3:007:06:140
83439913237,0cyclictest4034-21/usr/sbin/munin08:27:510
83439913142,0cyclictest0-21swapper07:57:330
83439912938,0cyclictest0-21swapper11:27:090
83439912936,0cyclictest4997-21/usr/sbin/munin11:38:350
83439912936,0cyclictest0-21swapper12:24:350
83439912745,0cyclictest0-21swapper07:13:310
83439912743,0cyclictest0-21swapper09:40:550
83439912737,0cyclictest0-21swapper07:27:350
83439912641,0cyclictest0-21swapper11:08:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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