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2026-01-23 - 17:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Fri Jan 23, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
745013150,0irq/46-4a1000006827-1kworker/u3:207:08:150
71259913057,0cyclictest7350irq/45-4a10000010:55:390
71259912741,0cyclictest0-21swapper07:10:590
71259912652,0cyclictest7350irq/45-4a10000008:00:430
71259912546,0cyclictest31198-21fschecks_time08:19:070
71259912544,0cyclictest7411-21irqstats10:19:160
71259912537,0cyclictest0-21swapper08:44:400
71259912451,0cyclictest7350irq/45-4a10000009:44:070
71259912444,0cyclictest25625-21/usr/sbin/munin11:29:280
71259912440,0cyclictest17493-21fschecks_time09:14:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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