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2026-02-07 - 15:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Sat Feb 07, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74509890,0irq/46-4a10000025681-1kworker/u3:107:05:480
7450970,0irq/46-4a10000030009-21cstates08:53:200
7450960,0irq/46-4a1000002507-21aten_r4power_en09:08:150
7450950,0irq/46-4a1000006104-21df07:43:230
7450940,0irq/46-4a10000014411-21/usr/sbin/munin08:09:050
7450940,0irq/46-4a10000011618-21missed_timers09:33:490
26617999471,0cyclictest0-21swapper09:39:020
7450930,0irq/46-4a1000006351-21fw_forwarded_lo09:18:350
7450930,0irq/46-4a10000031391-21latency_hist10:33:040
7450930,0irq/46-4a10000028566-21fw_conntrack10:23:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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