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2026-01-25 - 21:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Sun Jan 25, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502530,0irq/46-4a10000019087-1kworker/u3:207:07:480
7450960,0irq/46-4a1000002726-21ntpdc11:04:190
7450960,0irq/46-4a10000024145-21cron10:33:350
7450960,0irq/46-4a10000022570-21/usr/sbin/munin07:18:440
7450960,0irq/46-4a1000001944-21latency_hist11:03:350
7350960,0irq/45-4a10000024989-21ntp_states07:24:240
7450950,0irq/46-4a10000019359-21chrt11:53:520
7450950,0irq/46-4a10000016268-21irqstats11:44:120
7450950,0irq/46-4a10000015502-21sshd08:32:590
7350950,0irq/45-4a10000022564-21/usr/sbin/munin08:53:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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