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2026-02-23 - 14:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot2.osadl.org (updated Mon Feb 23, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502070,0irq/46-4a1000003060-21/usr/sbin/munin07:02:370
7450960,0irq/46-4a10000024739-21meminfo11:13:080
7450940,0irq/46-4a1000003555-21cut10:12:300
7450940,0irq/46-4a10000011742-21chrt08:59:560
7450930,0irq/46-4a10000025838-21/usr/sbin/munin08:08:140
7450930,0irq/46-4a10000016217-21meminfo12:23:070
7350930,0irq/45-4a10000029024-1kworker/u3:208:30:310
7350930,0irq/45-4a1000001997-21aten_r4power_en11:42:380
4640999370,0cyclictest0-21swapper08:43:120
7450920,0irq/46-4a100000460-21snmpd07:22:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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