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2026-01-20 - 16:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot2.osadl.org (updated Tue Jan 20, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74504540,0irq/46-4a10000014513-1kworker/u3:207:08:330
14861999359,0cyclictest0-21swapper09:54:380
14861999357,0cyclictest0-21swapper10:39:330
14861999257,0cyclictest0-21swapper09:18:590
14861999159,0cyclictest0-21swapper10:09:270
14861999159,0cyclictest0-21swapper08:59:350
14861999158,0cyclictest0-21swapper07:34:120
14861999058,0cyclictest0-21swapper09:09:400
14861998956,0cyclictest0-21swapper10:49:410
14861998953,0cyclictest0-21swapper08:44:350
14861998953,0cyclictest0-21swapper08:39:480
14861998855,0cyclictest0-21swapper11:14:240
14861998855,0cyclictest0-21swapper10:04:240
14861998855,0cyclictest0-21swapper08:04:340
14861998766,0cyclictest0-21swapper12:04:360
14861998755,0cyclictest0-21swapper07:54:020
14861998755,0cyclictest0-21swapper07:49:220
14861998754,0cyclictest0-21swapper10:29:210
14861998752,0cyclictest0-21swapper07:44:350
14861998664,0cyclictest0-21swapper10:54:390
14861998655,0cyclictest0-21swapper11:44:180
14861998655,0cyclictest0-21swapper09:59:380
14861998654,0cyclictest0-21swapper07:09:440
14861998653,0cyclictest0-21swapper11:19:340
14861998556,0cyclictest0-21swapper08:54:420
14861998556,0cyclictest0-21swapper07:59:520
14861998551,0cyclictest0-21swapper10:59:010
14861998551,0cyclictest0-21swapper07:15:060
14861998453,0cyclictest0-21swapper11:09:250
14861998453,0cyclictest0-21swapper08:34:270
14861998452,0cyclictest0-21swapper12:19:500
14861998451,0cyclictest0-21swapper11:29:390
14861998451,0cyclictest0-21swapper09:04:200
14861998451,0cyclictest0-21swapper08:14:210
14861998349,0cyclictest0-21swapper08:24:270
14861998252,0cyclictest0-21swapper12:24:350
14861998249,0cyclictest0-21swapper10:14:430
14861998248,0cyclictest0-21swapper09:24:160
14861998159,0cyclictest0-21swapper08:49:400
14861998158,0cyclictest0-21swapper11:49:190
14861998051,0cyclictest0-21swapper10:34:390
14861998049,0cyclictest0-21swapper07:38:560
14861998047,0cyclictest0-21swapper07:19:330
14861997849,0cyclictest0-21swapper11:04:370
14861997848,0cyclictest0-21swapper07:29:190
14861997757,0cyclictest0-21swapper11:59:420
14861997747,0cyclictest0-21swapper08:09:410
14861997745,0cyclictest0-21swapper11:24:210
14861997649,0cyclictest0-21swapper08:29:000
14861997648,0cyclictest0-21swapper09:34:440
14861997641,0cyclictest0-21swapper10:26:200
14861997554,0cyclictest0-21swapper12:34:230
14861997544,0cyclictest0-21swapper12:14:460
14861997541,0cyclictest0-21swapper11:39:230
14861997453,0cyclictest21967-21runrttasks07:26:190
14861997444,0cyclictest0-21swapper08:19:420
14861997441,0cyclictest0-21swapper10:44:430
14861997440,0cyclictest0-21swapper09:49:130
14861997353,0cyclictest0-21swapper12:29:090
14861997346,0cyclictest0-21swapper11:33:560
14861997341,0cyclictest0-21swapper09:14:220
14861997258,0cyclictest3109-21runrttasks09:40:470
14861997251,0cyclictest4740-21runrttasks09:45:090
14861997246,0cyclictest0-21swapper12:09:190
14861997246,0cyclictest0-21swapper11:58:110
14861997149,0cyclictest0-21swapper09:28:560
14861997046,0cyclictest10920-21kworker/0:210:20:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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