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2026-01-30 - 16:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack4slot2.osadl.org (updated Fri Jan 30, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73502770,0irq/45-4a10000022676-21kworker/0:407:03:560
306189910857,0cyclictest0-21swapper11:59:250
30618999257,0cyclictest0-21swapper08:23:460
30618999156,0cyclictest0-21swapper07:19:420
30618999057,0cyclictest0-21swapper10:08:560
30618999057,0cyclictest0-21swapper07:08:590
30618998957,0cyclictest0-21swapper08:14:200
30618998955,0cyclictest0-21swapper08:49:090
30618998954,0cyclictest0-21swapper07:34:150
30618998857,0cyclictest0-21swapper09:09:200
30618998855,0cyclictest0-21swapper08:09:080
30618998854,0cyclictest0-21swapper12:04:020
30618998854,0cyclictest0-21swapper09:04:190
30618998852,0cyclictest0-21swapper07:48:380
30618998754,0cyclictest0-21swapper09:59:090
30618998752,0cyclictest0-21swapper11:43:380
30618998656,0cyclictest0-21swapper07:59:000
30618998654,0cyclictest0-21swapper07:43:570
30618998652,0cyclictest0-21swapper12:24:100
7350850,0irq/45-4a10000010347-1kworker/u3:007:42:000
30618998562,0cyclictest0-21swapper08:38:460
30618998552,0cyclictest0-21swapper11:04:110
30618998550,0cyclictest0-21swapper08:59:030
30618998464,0cyclictest0-21swapper09:48:550
30618998462,0cyclictest0-21swapper10:24:030
30618998452,0cyclictest0-21swapper08:34:200
30618998451,0cyclictest0-21swapper10:13:520
30618998451,0cyclictest0-21swapper09:13:340
30618998451,0cyclictest0-21swapper08:54:080
30618998449,0cyclictest0-21swapper08:29:040
7350830,0irq/45-4a10000023233-21fw_conntrack08:18:530
7350830,0irq/45-4a10000016352-21tune2fs09:33:490
30618998351,0cyclictest0-21swapper11:53:460
7350820,0irq/45-4a1000005511-21chrt07:28:020
30618998251,0cyclictest0-21swapper11:24:200
30618998251,0cyclictest0-21swapper10:19:170
7350810,0irq/45-4a10000023992-1kworker/u3:011:32:400
7350810,0irq/45-4a10000018462-21ps08:04:160
30618998155,0cyclictest0-21swapper12:13:310
30618998150,0cyclictest0-21swapper12:28:580
7450800,0irq/46-4a10000015843-21seq07:58:250
7450800,0irq/46-4a10000012404-21awk10:58:240
30618998050,0cyclictest0-21swapper11:14:080
30618998048,0cyclictest0-21swapper09:19:180
7450790,0irq/46-4a10000017773-21wget09:38:350
7350790,0irq/45-4a10000031858-1kworker/u3:007:13:390
7350790,0irq/45-4a10000012337-1kworker/u3:012:37:490
276102790,0chrt27444-1kworker/u3:011:42:010
7450780,0irq/46-4a10000025195-21ntp_states11:34:120
7350780,0irq/45-4a10000026231-21aten_r4power_cu10:03:330
7350780,0irq/45-4a1000002104-1kworker/u3:010:28:530
30618997847,0cyclictest0-21swapper10:48:460
7450770,0irq/46-4a1000006707-21grep10:39:190
7450770,0irq/46-4a10000019339-21latency_hist11:18:270
7450770,0irq/46-4a10000012765-21chrt09:23:420
7350770,0irq/45-4a1000008571-21runrttasks10:44:580
7350770,0irq/45-4a1000007827-21cut12:18:490
7350770,0irq/45-4a1000005704-21aten_r4power_cu07:28:340
7350770,0irq/45-4a1000004004-21aten_r4power_cu10:33:330
7350770,0irq/45-4a10000029640-21grep11:48:330
7350770,0irq/45-4a10000017545-21latency_hist11:13:240
7350770,0irq/45-4a10000014237-21/usr/sbin/munin09:29:240
30618997741,0cyclictest0-21swapper09:54:080
7450760,0irq/46-4a1000004260-21grep12:08:410
7450760,0irq/46-4a10000032066-21open_inodes08:44:120
7450760,0irq/46-4a10000019708-21grep09:43:470
7450760,0irq/46-4a10000013227-21ntp_offset10:59:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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