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2026-05-11 - 19:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Mon May 11, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
745010380,0irq/46-4a1000009345-1kworker/u3:007:01:020
7450970,0irq/46-4a10000028198-21aten_r4power_cu07:54:400
7450950,0irq/46-4a10000019528-21awk12:14:300
7450950,0irq/46-4a10000011767-21ntp_kernel_pll_08:40:170
7450940,0irq/46-4a100000804-21cat09:44:330
7450940,0irq/46-4a1000004918-21/usr/sbin/munin09:55:150
7450940,0irq/46-4a100000460-21snmpd11:17:100
7450940,0irq/46-4a10000028180-21/usr/sbin/munin09:30:300
7450940,0irq/46-4a10000025716-21/usr/sbin/munin12:30:260
7450940,0irq/46-4a10000014990-21idleruntime12:00:030
7350940,0irq/45-4a10000023059-21/usr/sbin/munin10:50:340
7450930,0irq/46-4a1000009834-21fw_forwarded_lo10:10:010
7450930,0irq/46-4a1000008125-21fw_conntrack10:05:000
7450930,0irq/46-4a1000006164-21cstates09:59:440
7450930,0irq/46-4a1000006005-21aten_r4power_en08:24:410
7450930,0irq/46-4a1000003553-21chrt11:25:280
7450930,0irq/46-4a1000003085-21irqstats08:15:050
7450930,0irq/46-4a10000027302-21cat07:50:220
7450930,0irq/46-4a10000025662-21/usr/sbin/munin09:20:240
7450930,0irq/46-4a10000023592-21chrt09:15:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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