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2026-03-04 - 00:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Tue Mar 03, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
745012890,0irq/46-4a1000005617-1kworker/u3:107:04:370
276002977,0sleep027601-21irqstats07:57:460
7350950,0irq/45-4a1000008081-1kworker/u3:008:36:500
7350940,0irq/45-4a10000025368-21aten_r4power_cu09:27:190
9280999374,0cyclictest0-21swapper10:48:010
9280999260,0cyclictest0-21swapper07:28:070
9280999258,0cyclictest0-21swapper10:12:540
7450920,0irq/46-4a1000003765-21memory11:32:510
7450920,0irq/46-4a10000022404-21fw_forwarded_lo10:52:400
7450920,0irq/46-4a10000018999-21sshd12:17:390
1125129210,0sleep011266-21users07:12:240
9280999157,0cyclictest0-21swapper08:48:090
9280999157,0cyclictest0-21swapper08:02:210
9280999156,0cyclictest0-21swapper12:13:040
7450910,0irq/46-4a10000021972-21aten_r4power_cu12:27:180
7450910,0irq/46-4a10000021532-1kworker/u3:307:41:320
7450910,0irq/46-4a1000001326-21sh11:27:090
7350910,0irq/45-4a1000007132-21ls10:07:460
9280999059,0cyclictest0-21swapper09:37:420
9280999059,0cyclictest0-21swapper08:12:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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