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2026-05-30 - 22:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Sat May 30, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73502340,0irq/45-4a10000011138-21kworker/0:306:58:560
7450970,0irq/46-4a10000025680-21runrttasks09:08:440
7450960,0irq/46-4a1000009417-21ntp_states08:19:310
7450960,0irq/46-4a1000009409-21runrttasks11:29:320
7450960,0irq/46-4a10000029319-21aten_r4power_vo12:28:560
7450960,0irq/46-4a10000019274-21df_inode11:59:040
7450960,0irq/46-4a10000018368-21runrttasks07:10:050
7350960,0irq/45-4a10000027705-21seq12:23:580
7350960,0irq/45-4a10000026412-21modprobe07:34:260
7450950,0irq/46-4a1000007891-21sensors09:49:400
7450950,0irq/46-4a10000025894-21aten_r4power_vo10:43:570
7450950,0irq/46-4a10000016631-21uptime10:14:440
286062950,0sleep027302-1kworker/u3:010:49:520
7450940,0irq/46-4a1000007860-21runrttasks11:24:370
7450940,0irq/46-4a1000006368-21/usr/sbin/munin11:19:410
7450940,0irq/46-4a10000023001-21missed_timers08:59:290
7450940,0irq/46-4a10000019504-21sshd07:14:210
7450940,0irq/46-4a10000017757-21seq08:44:200
14841999459,0cyclictest0-21swapper08:29:230
14841999458,0cyclictest0-21swapper07:29:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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