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2026-02-21 - 23:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Sat Feb 21, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73501970,0irq/45-4a10000032556-21kworker/0:207:04:040
7450960,0irq/46-4a100000460-21snmpd12:00:190
7450960,0irq/46-4a1000003272-21interrupts08:38:090
7450950,0irq/46-4a1000005091-21missed_timers10:18:150
7450950,0irq/46-4a1000004641-21cstates08:42:460
7450940,0irq/46-4a10000030533-21fw_forwarded_lo11:33:020
7450930,0irq/46-4a1000006065-21ntp_states07:12:540
7450930,0irq/46-4a10000032356-21latency08:28:110
7450930,0irq/46-4a10000029948-21munin-run09:57:320
7450930,0irq/46-4a10000025019-21wget08:07:430
7450930,0irq/46-4a10000023455-21df_abs08:02:490
7450930,0irq/46-4a10000010586-21timerwakeupswit07:23:350
7450930,0irq/46-4a10000010569-21timerwakeupswit12:08:290
7350930,0irq/45-4a1000001677-21runrttasks08:33:170
3738999371,0cyclictest0-21swapper09:13:240
7450920,0irq/46-4a1000003064-21cut10:12:540
7450920,0irq/46-4a10000030296-21seq09:57:500
7450920,0irq/46-4a10000021047-21runrttasks07:54:500
7450920,0irq/46-4a10000011156-21cron09:02:310
3738999259,0cyclictest0-21swapper09:47:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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