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2026-02-24 - 23:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Tue Feb 24, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73506220,0irq/45-4a10000032035-21kworker/0:307:03:380
52679912841,0cyclictest16856-21/usr/sbin/munin12:23:070
52679912742,0cyclictest23707-21/usr/sbin/munin07:58:090
52679912736,0cyclictest19950-21diskstats09:22:470
52679912642,0cyclictest0-21swapper08:02:580
52679912638,0cyclictest0-21swapper10:47:490
52679912532,0cyclictest26355-21idleruntime-cro09:42:240
52679912444,0cyclictest11554-21fw_forwarded_lo08:57:570
52679912443,0cyclictest0-21swapper07:18:180
52679912441,0cyclictest0-21swapper10:29:340
52679912441,0cyclictest0-21swapper08:22:520
52679912440,0cyclictest0-21swapper07:32:420
52679912351,0cyclictest7350irq/45-4a10000012:02:570
52679912342,0cyclictest0-21swapper07:53:070
52679912339,0cyclictest0-21swapper11:04:400
52679912336,0cyclictest0-21swapper11:41:470
52679912241,0cyclictest0-21swapper10:52:440
52679912240,0cyclictest0-21swapper07:10:480
52679912239,0cyclictest0-21swapper07:48:560
52679912152,0cyclictest0-21swapper12:21:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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