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2026-07-28 - 02:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Tue Jul 28, 2026 00:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
745013060,0irq/46-4a1000008468-1kworker/u3:019:04:370
8971998861,0cyclictest0-21swapper21:51:570
8971998658,0cyclictest0-21swapper20:20:450
8971998258,0cyclictest0-21swapper22:03:350
8971998256,0cyclictest0-21swapper00:14:310
8971998165,0cyclictest19166-21/usr/sbin/munin19:34:230
8971998062,0cyclictest20514-21/usr/sbin/munin21:14:040
8971998061,0cyclictest17103-21meminfo21:04:020
8971998044,0cyclictest25089-21aten_r4power_po23:03:330
8971997961,0cyclictest19343-21runrttasks00:19:540
8971997854,0cyclictest10127-21fw_forwarded_lo20:43:530
8971997764,0cyclictest7350irq/45-4a10000021:19:130
8971997758,0cyclictest20561-21missed_timers19:39:150
8971997755,0cyclictest29597-21runrttasks23:15:040
8971997754,0cyclictest27327-21meminfo23:09:030
8971997753,0cyclictest0-21swapper22:44:260
8971997741,0cyclictest15331-21irqstats20:59:050
8971997658,0cyclictest8796-21fgrep20:39:230
8971997654,0cyclictest12665-21runrttasks00:01:110
8971997652,0cyclictest13791-21/usr/sbin/munin22:29:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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