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2026-01-19 - 05:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Mon Jan 19, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73502680,0irq/45-4a100000284082sleep019:06:020
28790999875,0cyclictest0-21swapper21:59:000
28790999173,0cyclictest31676-21fw_conntrack19:14:390
28790999069,0cyclictest30393-21runrttasks19:13:180
28790998970,0cyclictest7165-21munin-run22:48:500
28790998873,0cyclictest20290-21users20:14:490
28790998871,0cyclictest1079-21memory00:04:340
28790998870,0cyclictest1636-21chrt22:30:420
28790998770,0cyclictest4777-21wc21:04:440
28790998468,0cyclictest21412-21fw_forwarded_lo20:19:220
28790998466,0cyclictest5997-21grep19:34:190
28790998368,0cyclictest9971-21timerwakeupswit19:44:460
28790998259,0cyclictest0-21swapper20:39:040
28790998066,0cyclictest17963-21fw_conntrack20:09:190
28790997965,0cyclictest4947-21users22:39:510
28790997865,0cyclictest19540-21diskstats21:49:140
28790997864,0cyclictest3147-21timerwakeupswit22:34:480
28790997862,0cyclictest22315-21runrttasks21:57:190
28790997763,0cyclictest23847-21modprobe23:35:440
28790997662,0cyclictest7278-1kworker/u3:221:19:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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