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2026-02-16 - 08:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot2.osadl.org (updated Mon Feb 16, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74509910,0irq/46-4a1000005578-1kworker/u3:019:05:590
65109912749,0cyclictest7350irq/45-4a10000000:28:180
65109912533,0cyclictest8311-21chown19:12:480
65109912334,0cyclictest9132-21df_abs20:48:000
65109912331,0cyclictest21369-21chrt00:33:140
65109912241,0cyclictest26813-21/usr/sbin/munin20:03:350
65109912232,0cyclictest916-21irqstats20:23:200
65109912138,0cyclictest19178-21aten_r4power_cu22:52:530
65109912135,0cyclictest9339-21grep19:13:320
65109912131,0cyclictest25520-21seq19:59:500
65109912035,0cyclictest11985-21runrttasks20:56:040
65109912034,0cyclictest3443-21runrttasks23:40:540
65109912032,0cyclictest17079-21runrttasks19:35:470
65109911942,0cyclictest0-21swapper23:55:400
65109911941,0cyclictest25851-21seq23:12:420
65109911938,0cyclictest24728-21fschecks_time21:33:120
65109911932,0cyclictest8901-21wc23:57:480
65109911930,0cyclictest2840-21pure-ftpd20:28:360
65109911837,0cyclictest13999-21latency_hist22:37:480
65109911836,0cyclictest2088-21/usr/sbin/munin22:03:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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