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2026-02-11 - 18:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of all highest latencies:
System rack4slot2.osadl.org (updated Wed Feb 11, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502460,0irq/46-4a10000010532-1kworker/u3:007:03:530
124849912853,0cyclictest0-21swapper10:13:110
124849912852,0cyclictest0-21swapper08:18:170
124849912640,0cyclictest0-21swapper11:38:300
124849912542,0cyclictest0-21swapper12:23:100
124849912542,0cyclictest0-21swapper09:03:430
124849912541,0cyclictest0-21swapper12:28:280
124849912540,0cyclictest0-21swapper08:38:050
124849912540,0cyclictest0-21swapper08:23:270
124849912442,0cyclictest0-21swapper08:53:170
124849912442,0cyclictest0-21swapper08:52:150
124849912441,0cyclictest0-21swapper11:28:040
124849912441,0cyclictest0-21swapper11:01:200
124849912441,0cyclictest0-21swapper10:33:320
124849912341,0cyclictest0-21swapper07:18:390
124849912338,0cyclictest0-21swapper09:11:400
124849912337,0cyclictest0-21swapper10:20:010
124849912240,0cyclictest0-21swapper12:18:420
124849912240,0cyclictest0-21swapper10:43:070
124849912238,0cyclictest0-21swapper08:33:460
124849912140,0cyclictest0-21swapper10:28:100
124849912140,0cyclictest0-21swapper07:38:220
124849912041,0cyclictest0-21swapper07:08:550
124849911739,0cyclictest0-21swapper08:13:140
124849911649,0cyclictest0-21swapper08:58:570
124849911560,0cyclictest0-21swapper09:28:370
124849911338,0cyclictest0-21swapper11:47:380
124849910552,0cyclictest0-21swapper08:08:230
124849910249,0cyclictest0-21swapper08:43:560
12484999843,0cyclictest0-21swapper10:38:490
12484999358,0cyclictest0-21swapper07:23:340
12484999260,0cyclictest0-21swapper08:03:340
12484999058,0cyclictest0-21swapper12:33:330
12484999058,0cyclictest0-21swapper09:18:320
12484998858,0cyclictest0-21swapper07:13:250
12484998857,0cyclictest0-21swapper11:58:080
12484998857,0cyclictest0-21swapper07:58:290
12484998854,0cyclictest0-21swapper10:08:100
12484998765,0cyclictest0-21swapper10:48:310
12484998756,0cyclictest0-21swapper11:13:320
12484998753,0cyclictest0-21swapper08:28:440
12484998664,0cyclictest0-21swapper11:53:160
12484998652,0cyclictest0-21swapper07:53:510
12484998553,0cyclictest0-21swapper11:48:090
12484998553,0cyclictest0-21swapper10:53:440
12484998447,0cyclictest0-21swapper09:53:440
12484998352,0cyclictest0-21swapper09:42:550
12484998352,0cyclictest0-21swapper07:33:500
12484998350,0cyclictest0-21swapper09:58:270
12484998262,0cyclictest0-21swapper12:13:370
12484998260,0cyclictest0-21swapper11:08:350
12484998252,0cyclictest0-21swapper09:13:450
7350800,0irq/45-4a10000031134-21cut09:33:470
12484998057,0cyclictest0-21swapper10:23:090
12484997959,0cyclictest0-21swapper09:48:410
12484997947,0cyclictest0-21swapper07:48:390
7450780,0irq/46-4a1000007918-21cron11:37:540
12484997855,0cyclictest0-21swapper11:18:430
12484997756,0cyclictest0-21swapper11:23:060
12484997746,0cyclictest0-21swapper09:23:060
7350760,0irq/45-4a1000009075-21grep10:03:530
12484997644,0cyclictest0-21swapper07:43:270
12484997643,0cyclictest0-21swapper09:43:290
7450750,0irq/46-4a10000018847-21irqstats12:08:290
7350750,0irq/45-4a10000029620-21unixbench_singl11:03:510
7350750,0irq/45-4a10000020402-21grep07:28:220
7450730,0irq/46-4a10000016473-1kworker/u3:012:04:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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