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2026-02-18 - 14:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of all highest latencies:
System rack4slot2.osadl.org (updated Wed Feb 18, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
74502740,0irq/46-4a1000007376-1kworker/u3:007:06:140
83439913237,0cyclictest4034-21/usr/sbin/munin08:27:510
83439913142,0cyclictest0-21swapper07:57:330
83439912938,0cyclictest0-21swapper11:27:090
83439912936,0cyclictest4997-21/usr/sbin/munin11:38:350
83439912936,0cyclictest0-21swapper12:24:350
83439912745,0cyclictest0-21swapper07:13:310
83439912743,0cyclictest0-21swapper09:40:550
83439912737,0cyclictest0-21swapper07:27:350
83439912641,0cyclictest0-21swapper11:08:140
83439912640,0cyclictest0-21swapper07:58:060
83439912637,0cyclictest18705-21sshd12:18:440
83439912636,0cyclictest21973-21timerandwakeup07:43:360
83439912540,0cyclictest0-21swapper09:53:390
83439912540,0cyclictest0-21swapper08:07:540
83439912538,0cyclictest0-21swapper08:18:070
83439912537,0cyclictest0-21swapper10:05:020
83439912441,0cyclictest0-21swapper08:57:510
83439912441,0cyclictest0-21swapper08:03:100
83439912440,0cyclictest18807-21runrttasks10:44:410
83439912438,0cyclictest0-21swapper09:25:100
83439912438,0cyclictest0-21swapper07:27:540
83439912438,0cyclictest0-21swapper07:07:590
83439912427,0cyclictest25880-21runrttasks11:06:400
83439912338,0cyclictest0-21swapper12:27:520
83439912338,0cyclictest0-21swapper11:31:250
83439912338,0cyclictest0-21swapper10:37:140
83439912338,0cyclictest0-21swapper10:17:510
83439912338,0cyclictest0-21swapper09:07:540
83439912337,0cyclictest0-21swapper09:36:240
83439912336,0cyclictest0-21swapper12:13:320
83439912336,0cyclictest0-21swapper09:14:350
83439912335,0cyclictest0-21swapper12:35:050
83439912247,0cyclictest7350irq/45-4a10000011:43:100
83439912240,0cyclictest0-21swapper07:37:350
83439912239,0cyclictest0-21swapper11:58:370
83439912239,0cyclictest0-21swapper10:48:250
83439912239,0cyclictest0-21swapper08:52:390
83439912239,0cyclictest0-21swapper08:22:490
83439912239,0cyclictest0-21swapper07:49:330
83439912238,0cyclictest0-21swapper08:37:500
83439912236,0cyclictest0-21swapper08:43:320
83439912143,0cyclictest7350irq/45-4a10000010:23:010
83439912143,0cyclictest0-21swapper08:15:400
83439912141,0cyclictest0-21swapper11:50:500
83439912139,0cyclictest0-21swapper09:18:260
83439912138,0cyclictest0-21swapper09:04:090
83439912137,0cyclictest0-21swapper11:18:110
83439912136,0cyclictest16593-21sh10:38:250
83439912136,0cyclictest0-21swapper09:48:060
83439912136,0cyclictest0-21swapper09:43:160
83439912136,0cyclictest0-21swapper08:35:420
83439912135,0cyclictest0-21swapper12:10:390
83439912045,0cyclictest0-21swapper11:33:100
83439912037,0cyclictest0-21swapper10:53:460
83439912037,0cyclictest0-21swapper10:13:070
83439912035,0cyclictest0-21swapper10:11:550
83439912035,0cyclictest0-21swapper09:58:180
83439912031,0cyclictest0-21swapper08:52:540
83439911936,0cyclictest0-21swapper07:18:240
83439911931,0cyclictest0-21swapper12:04:200
83439911930,0cyclictest10496-21runrttasks11:56:380
83439911832,0cyclictest0-21swapper10:58:200
83439911737,0cyclictest0-21swapper07:38:360
83439911733,0cyclictest0-21swapper11:16:200
83439911733,0cyclictest0-21swapper10:32:030
83439911129,0cyclictest0-21swapper09:32:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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