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2026-01-31 - 17:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of all highest latencies:
System rack4slot2.osadl.org (updated Sat Jan 31, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
745012970,0irq/46-4a10000029317-1kworker/u3:007:06:350
299739912740,0cyclictest0-21swapper07:40:350
299739912435,0cyclictest26178-21/usr/sbin/munin11:39:020
299739912342,0cyclictest0-21swapper08:54:010
299739912335,0cyclictest2247-21memory10:29:050
299739912335,0cyclictest0-21swapper07:15:040
299739912249,0cyclictest7350irq/45-4a10000010:09:000
299739912241,0cyclictest0-21swapper08:08:580
299739912142,0cyclictest17622-21/usr/sbin/munin09:39:010
299739912141,0cyclictest0-21swapper08:58:340
299739912138,0cyclictest0-21swapper12:28:010
299739912136,0cyclictest31153-21/usr/sbin/munin08:43:540
299739912041,0cyclictest9357-21sensors10:49:150
299739912041,0cyclictest0-21swapper11:19:120
299739912040,0cyclictest15201-21latency_hist09:33:230
299739912039,0cyclictest0-21swapper11:28:030
299739912039,0cyclictest0-21swapper08:42:000
299739912038,0cyclictest30199-21sshd11:50:280
299739912038,0cyclictest0-21swapper11:29:060
299739912036,0cyclictest15897-21/usr/sbin/munin11:08:590
299739911941,0cyclictest0-21swapper10:13:390
299739911941,0cyclictest0-21swapper09:24:000
299739911941,0cyclictest0-21swapper07:53:470
299739911940,0cyclictest0-21swapper08:33:580
299739911939,0cyclictest0-21swapper09:08:350
299739911938,0cyclictest0-21swapper09:53:330
299739911938,0cyclictest0-21swapper09:48:420
299739911937,0cyclictest0-21swapper08:03:440
299739911933,0cyclictest25724-21grep10:03:350
299739911851,0cyclictest0-21swapper09:20:060
299739911841,0cyclictest0-21swapper12:29:070
299739911840,0cyclictest0-21swapper08:14:050
299739911840,0cyclictest0-21swapper07:59:330
299739911840,0cyclictest0-21swapper07:50:260
299739911839,0cyclictest0-21swapper08:26:430
299739911838,0cyclictest0-21swapper12:19:370
299739911837,0cyclictest0-21swapper08:29:130
299739911829,0cyclictest4706-21runrttasks10:36:380
299739911825,0cyclictest367-21perl08:48:510
299739911821,0cyclictest24156-21df_inode09:58:410
299739911810,0cyclictest23599-21sshd08:22:290
299739911741,0cyclictest0-21swapper11:13:550
299739911740,0cyclictest0-21swapper07:34:210
299739911739,0cyclictest0-21swapper07:24:210
299739911738,0cyclictest0-21swapper11:33:460
299739911738,0cyclictest0-21swapper09:04:130
299739911737,0cyclictest12001-21aten_r4power_vo10:58:330
299739911737,0cyclictest10167-21latency_hist07:43:260
299739911737,0cyclictest0-21swapper12:33:410
299739911734,0cyclictest19026-21df_inode09:43:420
299739911732,0cyclictest0-21swapper07:20:150
299739911731,0cyclictest6179-21runrttasks07:29:410
299739911644,0cyclictest12-21ksoftirqd/012:08:440
299739911639,0cyclictest0-21swapper10:48:210
299739911638,0cyclictest0-21swapper11:43:440
299739911636,0cyclictest13703-21aten_r4power_vo11:03:320
299739911540,0cyclictest0-21swapper09:13:320
299739911538,0cyclictest0-21swapper12:03:380
299739911535,0cyclictest0-21swapper11:59:220
299739911535,0cyclictest0-21swapper10:22:260
299739911535,0cyclictest0-21swapper09:37:090
299739911534,0cyclictest0-21swapper10:54:060
299739911531,0cyclictest30088-21/usr/sbin/munin07:08:460
299739911516,0cyclictest460-21snmpd10:25:330
299739911441,0cyclictest0-21swapper10:39:130
299739911436,0cyclictest0-21swapper12:14:140
299739911226,0cyclictest30788-21runrttasks11:53:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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