You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-20 - 09:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Fri Feb 20, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1422227760,4sleep014224-21latency_hist19:11:240
142869915415,128cyclictest15487-21munin-node00:12:030
142869915314,39cyclictest13600-21munin-node20:47:100
142869915314,101cyclictest5744-21munin-node20:22:230
142869915115,97cyclictest3241-21sh20:16:400
142869915014,126cyclictest17022-21missed_timers00:17:020
142869914815,123cyclictest31793-21munin-node23:22:160
142869914714,123cyclictest12203-21munin-node00:02:030
142869914714,122cyclictest14026-21munin-node00:07:140
142869914614,123cyclictest23263-21seq21:17:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional