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2026-02-05 - 08:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Thu Feb 05, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36119913514,110cyclictest13973-21munin-node21:23:380
36119913014,106cyclictest14574-21munin-node23:04:010
36119912815,103cyclictest11987-21diskstats19:38:330
36119912714,103cyclictest25357-21idleruntime21:58:430
36119912614,102cyclictest3695-21runrttasks22:38:260
36119912614,101cyclictest13624-21munin-node19:43:340
36119912515,99cyclictest17990-21sshd19:56:460
36119912515,100cyclictest31058-21uptime23:54:110
36119912514,101cyclictest32142-21open_files22:18:570
36119912415,98cyclictest17217-21munin-node21:33:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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