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2026-01-22 - 00:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Wed Jan 21, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1849525240,4sleep018494-21grep07:07:460
195729911432,72cyclictest25168-21proc_pri07:28:020
195729911330,74cyclictest10392-21if_err_eth008:22:420
195729911229,73cyclictest4063-21ls09:42:410
195729911132,70cyclictest2762-21date07:58:120
195729911131,71cyclictest31429-21aten_r4power_po11:07:290
195729911042,57cyclictest20556-21munin-node12:12:440
195729911030,70cyclictest18782-21fschecks_count12:07:360
195729910737,60cyclictest19777-21munin-node08:52:260
195729910732,66cyclictest3695-21runrttasks10:27:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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