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2026-02-11 - 14:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Wed Feb 11, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1462221180,4sleep014623-21netstat10:06:090
8266211413,88sleep07701-21munin-node11:26:070
20251211316,23sleep020327-21df07:05:440
32372210514,16sleep032384-21munin-node07:41:210
27727210314,76sleep027747-21timerandwakeup09:06:240
8882990,4sleep0889-21latency_hist09:25:320
2615229914,15sleep03250-21snmpd07:22:010
21792999815,73cyclictest24221-21munin-node10:36:000
1988629814,16sleep03250-21snmpd08:42:370
21792999715,72cyclictest17759-21munin-node08:36:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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