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2026-02-09 - 11:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Mon Feb 09, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21759915415,129cyclictest6079-21munin-node21:00:430
21759915314,128cyclictest28187-21seq22:08:520
21759915214,128cyclictest9366-21awk22:50:370
21759915114,99cyclictest6841-21find00:21:050
21759914914,125cyclictest32429-21processes22:21:000
21759914815,123cyclictest18695-21chrt20:00:280
21759914814,125cyclictest21024-21proc_pri21:45:590
21759914614,122cyclictest5006-21grep00:15:530
21759914614,122cyclictest26664-21munin-node20:25:370
21759914614,122cyclictest26233-21munin-node22:01:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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