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2026-02-15 - 13:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Sun Feb 15, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
221829914814,124cyclictest19505-21munin-node22:21:080
221829914614,121cyclictest11484-21tune2fs21:56:150
221829914613,123cyclictest13861-21munin-node23:41:470
221829914416,118cyclictest25641-21cut21:01:040
221829914415,49cyclictest14481-21wget22:06:050
221829914315,118cyclictest3250-21snmpd20:37:360
221829914315,118cyclictest24002-21munin-node20:56:030
221829914314,120cyclictest3568-21runrttasks22:56:420
221829914314,118cyclictest14671-21munin-node20:26:210
221829914115,116cyclictest3568-21runrttasks00:33:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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