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2026-02-16 - 03:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Mon Feb 16, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
217999914715,66cyclictest7777-21fschecks_count21:46:190
217999914414,67cyclictest22676-21fschecks_time00:11:210
217999914315,64cyclictest20156-21runrttasks00:02:110
217999914114,69cyclictest25136-21idleruntime-cro21:00:580
217999914114,63cyclictest8451-21seq20:07:310
217999914114,61cyclictest25246-21munin-node21:01:310
217999914014,64cyclictest27537-21fschecks_time00:26:210
217999913914,37cyclictest9007-21runrttasks23:29:110
217999913913,66cyclictest12594-21munin-node23:41:240
217999913815,64cyclictest3568-21runrttasks19:46:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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