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2026-03-09 - 14:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Mon Mar 09, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40099915714,133cyclictest25689-21chrt11:38:400
40099915414,42cyclictest12858-21ntpq09:18:530
40099915314,129cyclictest28955-21munin-node08:28:500
40099915314,129cyclictest11281-21awk10:53:520
40099914913,45cyclictest21412-21munin-node11:24:100
40099914315,118cyclictest23274-21runrttasks08:12:260
40099914315,118cyclictest19314-21munin-node07:58:560
40099914214,33cyclictest7957-21seq07:23:580
40099914214,118cyclictest5975-21fschecks_count08:58:330
40099914115,116cyclictest6910-21munin-node12:19:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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