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2026-01-20 - 23:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Tue Jan 20, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
145899915314,71cyclictest3589-21munin-node09:57:230
145899914515,71cyclictest3489-21latency_hist09:57:140
145899914515,120cyclictest22653-21sshd12:33:150
145899914314,63cyclictest11539-21aten_r4power_cu08:42:250
145899914214,58cyclictest18134-21munin-node07:22:320
145899914114,61cyclictest16791-21munin-node10:37:310
145899914113,66cyclictest17640-21timerandwakeup12:18:080
145899914014,66cyclictest10396-21fschecks_time10:17:340
145899913814,62cyclictest23093-21cut10:57:230
145899913714,37cyclictest29790-21sh11:17:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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