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2026-01-26 - 14:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Mon Jan 26, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15940212018,80sleep015963-21munin-node07:08:120
779621100,4sleep07797-21wc08:23:140
1872021080,4sleep018721-21grep10:37:370
25782210114,16sleep025780-21ntp_states09:18:200
2366629814,15sleep023667-21sshd10:52:400
1591329814,16sleep015924-21df_inode12:07:530
1862729714,16sleep018652-21wget08:57:470
16815999715,73cyclictest14609-21load12:03:100
2709629614,16sleep03377-21snmpd07:43:100
16815999615,71cyclictest358-21runrttasks08:01:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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