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2026-02-17 - 07:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Tue Feb 17, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299549915815,132cyclictest18661-21seq21:54:460
299549915315,127cyclictest32384-21ntpq20:56:410
299549914814,124cyclictest17096-21latency_hist20:11:060
299549914714,123cyclictest9788-21munin-node23:06:320
299549914514,121cyclictest10880-21aten_r4power_po21:31:180
299549914215,117cyclictest16313-21munin-node21:46:440
299549914214,119cyclictest27941-21pluginstate00:01:510
299549914115,52cyclictest27954-21munin-node22:21:590
299549914016,50cyclictest26973-21wget20:41:170
299549914014,117cyclictest21581-21vmstat22:02:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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