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2026-01-31 - 17:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Sat Jan 31, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
236319912740,77cyclictest17947-21munin-node11:53:180
22074211817,21sleep022150-21cpu07:08:170
236319911315,89cyclictest10291-21munin-node11:28:440
236319911129,73cyclictest3644-21unixbench_singl07:48:540
236319910830,68cyclictest14317-21aten_r4power_en10:03:070
236319910631,66cyclictest7101-21sendmail_mailqu11:18:450
236319910145,46cyclictest24582-21munin-node12:13:190
236319910139,52cyclictest30155-21munin-node07:33:340
236319910042,48cyclictest27371-21wget10:43:070
23631999941,49cyclictest18556-21munin-node10:13:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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