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2026-02-21 - 10:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Sat Feb 21, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17518210115,16sleep017519-21irqstats23:57:000
29874210014,15sleep029900-21munin-node19:36:510
2857529914,16sleep028577-21sh19:32:110
2682529914,16sleep03303-21ntpd19:27:040
2149829913,16sleep021535-21wc20:51:310
2817429814,16sleep028180-21munin-run22:51:300
2392529814,16sleep023928-21memory22:37:040
2096129814,16sleep020984-21cat22:27:210
21409999615,72cyclictest28479-21aten_r4power_cu00:31:420
21409999614,72cyclictest31856-21open_inodes19:42:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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