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2026-01-25 - 02:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Sun Jan 25, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1507327820,4sleep015070-21ntpq19:07:570
12295210414,26sleep012335-21rt-features22:18:200
13242210315,21sleep013278-21fschecks_count20:42:500
19701210215,17sleep019707-21hddtemp_smartct19:22:530
22856210114,16sleep022882-21ls22:52:310
31755210014,15sleep031790-21proc_pri23:18:160
21201210014,15sleep021255-21aten_r4power_vo21:07:420
512729915,16sleep05180-21grep20:17:520
2013429914,16sleep020140-21iostat_ios22:42:590
1390529913,15sleep013907-21memory00:03:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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