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2026-01-30 - 16:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Fri Jan 30, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16008212018,24sleep016079-21aten_r4power_vo07:08:030
176269910127,65cyclictest31315-21fschecks_time11:13:120
17626999824,65cyclictest10516-21wc08:28:430
17626999715,72cyclictest30879-21aten_r4power_en09:33:050
17626999715,71cyclictest29724-21munin-node11:08:120
36272960,4sleep03625-21uname08:08:240
17626999526,60cyclictest26607-21munin-node09:18:320
17626999523,63cyclictest6632-21munin-node09:58:300
17626999515,16cyclictest3377-21snmpd11:30:500
17626999511,74cyclictest1544-21cut08:03:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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