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2026-02-24 - 10:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Tue Feb 24, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
67009915314,68cyclictest4396-21munin-node22:22:250
67009915114,72cyclictest29943-21aten_r4power_vo23:42:010
67009914814,67cyclictest31803-21grep23:47:110
67009914714,70cyclictest8247-21runrttasks22:34:030
67009914414,69cyclictest28265-21munin-node23:36:590
67009914314,68cyclictest3568-21runrttasks22:37:370
67009914314,62cyclictest699-21munin-node23:52:000
67009914215,65cyclictest9201-21fschecks_time00:17:130
67009914214,66cyclictest20472-21if_eth023:12:140
67009914214,63cyclictest26294-21munin-plugin-st21:51:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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