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2026-02-13 - 23:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Fri Feb 13, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57989915315,70cyclictest24323-21irqstats09:46:130
222321150,4sleep02225-21sort11:56:350
10959210814,82sleep011020-21cpu09:05:560
1950210414,16sleep01974-21munin-node10:16:300
15253210314,15sleep03250-21snmpd07:39:030
29363210014,15sleep029369-21munin-node11:41:100
15079210015,16sleep015099-21sensors10:56:310
942829914,72sleep09449-21aten_r4power_cu10:40:540
456929817,56sleep04583-21iostat07:06:030
5798999715,73cyclictest6421-21aten_r4power_po12:10:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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