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2026-03-03 - 16:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Tue Mar 03, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1822528070,4sleep018222-21mailstats07:08:100
190819916223,68cyclictest6247-21crond11:32:350
27605210214,16sleep027631-21fw_packets09:17:570
5025210116,16sleep05049-21kernelversion08:08:050
491210114,16sleep0551-21date09:33:260
4480210015,15sleep04514-21latency_hist08:07:350
984229814,71sleep09525-21munin-node10:02:570
2269129814,15sleep022740-21df12:22:480
196442980,4sleep019645-21cat07:13:150
2941829713,15sleep029419-21irqstats11:03:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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