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2026-02-11 - 01:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Tue Feb 10, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11984211717,23sleep011985-21sshd07:08:370
13875210714,81sleep012871-21munin-node12:11:240
13799210714,80sleep013801-21sshd08:53:380
7702210314,16sleep07777-21wc10:15:250
3928210114,15sleep03929-21users10:01:230
25338210119,16sleep025371-21aten_r4power_en07:50:340
17425210114,74sleep017211-21munin-node07:25:430
3149210014,15sleep03150-21iostat_ios08:20:530
22488210014,15sleep022528-21munin-node09:20:460
764429914,16sleep03250-21snmpd11:53:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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