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2026-02-10 - 12:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot3.osadl.org (updated Tue Feb 10, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
628921270,4sleep06288-21uname19:05:460
747499978,79cyclictest19554-21cat21:25:540
747499957,78cyclictest15156-21sendmail_mailqu22:51:070
7474999534,51cyclictest233522chrt21:36:180
7474999515,71cyclictest13590-21switchtime22:46:120
7474999514,71cyclictest8206-21processes19:11:080
7474999417,67cyclictest31501-21switchtime23:41:120
7474999415,69cyclictest17525-21seq00:38:380
747499938,75cyclictest9681-21sort20:55:460
747499938,74cyclictest21351-21munin-node21:31:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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