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2026-02-12 - 07:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Thu Feb 12, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
255929915315,128cyclictest27659-21fschecks_count20:55:530
255929914515,64cyclictest11846-21munin-node21:46:080
255929914214,64cyclictest19147-21runrttasks20:30:260
255929914115,62cyclictest827-21sensors_temp22:51:230
255929914015,115cyclictest26155-21df_abs22:30:490
255929914014,64cyclictest27080-21runrttasks19:15:120
255929914014,116cyclictest4122-21timerwakeupswit21:21:280
255929913915,114cyclictest31481-21munin-node21:06:240
255929913914,32cyclictest5449-21munin-node19:46:220
255929913815,63cyclictest15418-21switchtime21:56:310
255929913814,64cyclictest17979-21cpu22:05:470
255929913715,64cyclictest16495-21aten_r4power_vo23:40:460
255929913714,59cyclictest3940-21needreboot23:01:100
255929913514,56cyclictest26183-21aten_r4power_cu00:10:470
255929913514,112cyclictest19468-21df_abs20:30:490
255929913415,61cyclictest3568-21runrttasks00:38:000
255929913415,55cyclictest11511-21munin-node23:26:250
255929913414,59cyclictest14466-21latency_hist21:55:350
255929913315,57cyclictest481-21ntp_states21:11:180
255929913314,60cyclictest27848-21fschecks_count22:35:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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