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2026-02-18 - 22:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Wed Feb 18, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19439914015,115cyclictest1990-21munin-node07:11:240
478213718,27sleep0482-21diskstats07:06:290
19439913615,110cyclictest11034-21munin-node09:16:590
19439913315,107cyclictest27028-21munin-node11:46:320
19439913314,109cyclictest18305-21munin-node08:02:040
19439913114,107cyclictest31459-21latency_hist10:21:160
19439913114,106cyclictest26703-21munin-node10:06:260
19439912815,103cyclictest5483-21munin-node09:01:250
19439912714,104cyclictest3568-21runrttasks12:21:340
19439912614,102cyclictest20645-21munin-node08:06:590
19439912415,99cyclictest26023-21seq10:02:120
19439912415,100cyclictest22222-21fschecks_time11:31:360
19439912414,101cyclictest19313-21munin-node09:42:040
19439912414,100cyclictest13180-21chrt09:23:350
19439912315,98cyclictest28877-21ntpdc10:11:530
19439912315,72cyclictest12976-21smart_hda11:02:020
19439912315,71cyclictest31405-21aten_r4power_vo08:41:240
19439912314,99cyclictest18942-21runrttasks11:21:350
19439912215,96cyclictest30275-21df_inode11:56:320
19439912214,99cyclictest515-21munin-node08:46:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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