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2026-02-24 - 14:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Tue Feb 24, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
113949913515,110cyclictest739-21ntpdc08:17:300
113949913414,110cyclictest20545-21grep10:57:280
113949913015,77cyclictest7323-21munin-node08:37:280
113949913015,106cyclictest7889-21munin-node11:57:400
113949913015,104cyclictest3250-21snmpd10:33:120
113949913014,106cyclictest21616-21aten_r4power_po11:02:050
113949912915,105cyclictest13732-21runrttasks10:37:130
113949912915,104cyclictest20335-21forks12:37:120
113949912614,102cyclictest11576-21seq12:09:300
113949912515,100cyclictest15260-21runrttasks12:22:040
113949912514,102cyclictest13015-21runrttasks08:56:070
113949912514,101cyclictest4471-21ntpq11:47:320
113949912514,101cyclictest17179-21wc07:27:470
113949912415,97cyclictest5088-21munin-node08:32:490
113949912414,101cyclictest3568-21runrttasks08:03:260
113949912414,100cyclictest12237-21smart_hda07:12:510
113949912314,99cyclictest3568-21runrttasks11:45:330
113949912314,99cyclictest20193-21ntpq07:37:330
113949912314,72cyclictest26954-21timerandwakeup07:57:460
9795212218,23sleep09861-21aten_r4power_vo07:07:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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