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2026-02-26 - 20:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Thu Feb 26, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23946211716,22sleep03250-21snmpd07:07:050
1062210113,23sleep01082-21switchtime12:32:560
2873210014,30sleep02898-21unixbench_singl12:38:030
15533210014,17sleep015534-21munin-node09:58:000
340529914,16sleep03250-21snmpd07:42:290
25644999814,75cyclictest14203-21munin-node11:33:030
2013629714,16sleep020177-21sed08:32:570
862829614,16sleep08636-21memory09:37:370
3157229614,18sleep031597-21ps10:47:490
25644999614,73cyclictest12271-21date09:47:580
2510129615,16sleep025144-21gzip10:27:520
224029514,19sleep02289-21munin-node09:17:490
3272829414,15sleep032711-21missed_timers07:32:440
25644999415,69cyclictest3573-21df11:02:190
25644999414,70cyclictest30379-21seq07:26:430
1198129414,16sleep011982-21iostat_ios11:27:330
376529314,16sleep03789-21missed_timers09:22:400
674929214,16sleep06812-21cpu11:12:170
25644999215,68cyclictest2432-21ps10:57:480
25644999215,68cyclictest21626-21fschecks_time11:57:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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