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2026-01-14 - 12:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Wed Jan 14, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301879914915,34cyclictest9515-21munin-node21:26:580
301879914715,122cyclictest3695-21runrttasks22:57:270
301879914614,122cyclictest1990-21grep19:22:410
301879914614,122cyclictest17709-21munin-node21:52:000
301879914415,119cyclictest30369-21munin-node19:11:570
301879914314,32cyclictest3740-21munin-node22:47:260
301879914314,120cyclictest27585-21wget00:01:590
301879914314,119cyclictest5306-21grep21:12:340
301879914215,116cyclictest6382-21munin-node21:17:060
301879914214,38cyclictest29331-21runrttasks00:07:020
301879914115,35cyclictest3695-21runrttasks19:42:340
301879914114,117cyclictest9672-21munin-node23:06:580
301879914014,116cyclictest3695-21runrttasks23:39:130
301879914014,116cyclictest26704-21munin-node22:17:460
301879913914,35cyclictest14644-21cpu23:21:590
301879913816,111cyclictest13022-21memory19:57:270
301879913814,114cyclictest3097-21interrupts19:27:130
301879913814,113cyclictest20736-21munin-node20:21:590
301879913715,35cyclictest23001-21cat22:07:240
301879913714,114cyclictest412-21open_inodes22:37:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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