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2026-01-26 - 01:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sun Jan 25, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
145879915814,78cyclictest19354-21seq10:44:320
145879915114,67cyclictest6799-21ls10:07:340
145879914914,71cyclictest12196-21open_files08:43:180
145879914715,66cyclictest26505-21munin-node07:48:060
145879914714,69cyclictest18065-21munin-node09:02:450
145879914513,69cyclictest17736-21unixbench_singl12:18:300
145879914314,73cyclictest30885-21cut08:02:460
145879914114,69cyclictest23634-21idleruntime12:37:580
30591210314,15sleep03377-21snmpd09:39:480
287429713,15sleep02878-21smart_hda11:33:250
14587999613,73cyclictest29378-21chrt11:16:430
2193829414,15sleep021936-21ntp_states09:13:160
14587999415,70cyclictest32659-21df08:07:460
14587999415,70cyclictest1116-21processes11:28:190
14587999414,43cyclictest5898-21memory11:43:070
1177429413,15sleep011825-21date12:02:340
14587999315,69cyclictest12336-21munin-node10:23:100
14587999315,68cyclictest11408-21sh08:42:310
2327429214,65sleep023296-21munin-node09:17:580
1982829214,15sleep019832-21hddtemp_smartct07:27:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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