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2026-02-14 - 11:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sat Feb 14, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9753210218,16sleep09809-21ls19:06:160
109349910223,69cyclictest12010-21timerandwakeup20:51:390
109349910123,68cyclictest17641-21runrttasks21:10:550
109349910024,66cyclictest28862-21munin-node20:05:580
1623229814,18sleep016256-21fschecks_count21:06:070
10934999814,74cyclictest31783-21munin-node23:31:420
10934999714,73cyclictest6681-21basename23:56:010
10934999714,73cyclictest29924-21timerwakeupswit21:46:400
10934999625,62cyclictest9263-21vmstat00:01:460
10934999625,62cyclictest23460-21runrttasks19:47:350
10934999624,63cyclictest27619-21if_eth020:01:120
10934999621,66cyclictest9361-21runrttasks22:24:030
10934999615,72cyclictest11836-21munin-node22:31:210
10934999524,62cyclictest13994-21timerandwakeup00:16:390
10934999521,65cyclictest14711-21latency19:21:180
10934999514,72cyclictest20498-21threads00:36:410
1912729413,15sleep019181-21aten_r4power_vo19:35:560
1843929414,16sleep018457-21ntp_states22:51:260
10934999422,62cyclictest5262-21tune2fs23:51:080
10934999418,67cyclictest27702-21fschecks_time21:41:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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