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2026-01-18 - 17:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sun Jan 18, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78039913314,109cyclictest26905-21grep11:37:290
78039913114,107cyclictest2358-21grep10:22:250
78039912914,80cyclictest5603-21munin-node12:12:150
78039912914,105cyclictest17469-21munin-plugin-st07:42:030
78039912914,105cyclictest13786-21uniq10:57:250
78039912914,104cyclictest12097-21munin-node09:12:270
78039912913,106cyclictest10111-21munin-node09:07:150
78039912814,104cyclictest17690-21aten_r4power_vo07:42:160
78039912714,103cyclictest26470-21aten_r4power_vo09:57:170
78039912615,101cyclictest16883-21aten_r4power_po11:07:160
78039912614,103cyclictest13160-21runrttasks12:33:160
78039912514,101cyclictest3882-21aten_r4power_vo10:27:170
78039912314,99cyclictest19244-21munin-node09:33:020
78039912215,97cyclictest16540-21chrt11:05:500
78039912214,98cyclictest28761-21munin-node08:22:400
78039912214,97cyclictest19935-21basename07:52:110
78039912214,71cyclictest21500-21munin-node09:42:550
78039912115,95cyclictest14331-21munin-node07:32:540
78039912114,97cyclictest21614-21latency_hist11:22:060
78039912114,96cyclictest22226-21munin-node08:02:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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