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2026-02-06 - 14:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Fri Feb 06, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2998828450,5sleep029984-21tune2fs07:08:450
313479917315,148cyclictest25704-21sshd07:19:070
313479917017,144cyclictest25704-21sshd08:21:110
313479916915,143cyclictest25704-21sshd11:00:250
313479916816,142cyclictest25704-21sshd07:40:530
313479916815,142cyclictest25704-21sshd09:17:550
313479916517,139cyclictest25704-21sshd08:08:160
313479916316,137cyclictest25704-21sshd07:56:270
313479916215,112cyclictest25704-21sshd11:40:570
313479916119,131cyclictest25704-21sshd11:26:080
313479915916,113cyclictest25704-21sshd11:36:000
313479915915,112cyclictest25704-21sshd10:47:030
313479915914,135cyclictest25704-21sshd11:44:160
313479915717,130cyclictest25704-21sshd09:11:220
313479915717,128cyclictest25704-21sshd09:02:310
313479915714,131cyclictest25704-21sshd11:30:240
313479915617,129cyclictest25704-21sshd07:44:020
313479915616,130cyclictest25704-21sshd09:35:500
313479915616,107cyclictest25704-21sshd07:13:270
313479915615,131cyclictest25704-21sshd10:03:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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