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2026-01-17 - 15:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sat Jan 17, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
129659915215,128cyclictest31731-21seq09:47:490
129659914915,64cyclictest20687-21vmstat09:13:010
129659914914,66cyclictest28245-21munin-node07:57:400
129659914914,64cyclictest12094-21munin-node10:27:280
129659914515,61cyclictest21465-21munin-node07:37:240
129659914415,61cyclictest30173-21ls08:02:550
129659914415,119cyclictest11397-21seq10:25:270
129659914314,60cyclictest32727-21munin-node08:12:210
129659914214,65cyclictest32192-21runrttasks08:10:290
129659914014,116cyclictest15836-21runrttasks07:19:420
129659913916,59cyclictest2406-21smartctl11:37:250
129659913916,55cyclictest192302chrt07:30:520
129659913914,65cyclictest31290-21aten_r4power_po11:27:140
129659913914,60cyclictest29520-21aten_r4power_vo09:42:130
129659913914,37cyclictest28176-21cat09:37:270
129659913914,34cyclictest16735-21fschecks_time09:02:240
129659913715,59cyclictest5045-21runrttasks11:45:140
129659913714,63cyclictest19561-21latency_hist09:12:010
129659913714,62cyclictest13480-21cpu10:32:130
129659913714,58cyclictest24542-21munin-node09:27:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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