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2026-02-23 - 13:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Mon Feb 23, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3539915815,72cyclictest7384-21hostname22:51:530
3539915015,43cyclictest15176-21wget19:56:540
32743210218,17sleep032733-21ls19:11:440
2379421020,4sleep023795-21basename22:02:070
6232210114,21sleep06240-21memory22:47:170
1088421010,3sleep010885-21cat19:42:210
878529714,15sleep08814-21df_inode19:36:570
811029614,16sleep03321-21lldpd19:33:280
65422960,4sleep06541-21cat00:27:230
353999615,71cyclictest2758-21chrt20:57:170
1934729614,15sleep019352-21smart_hda21:47:310
353999515,71cyclictest9660-21proc_pri22:57:280
353999515,71cyclictest5461-21seq19:26:540
353999415,70cyclictest22034-21seq21:57:030
353999415,69cyclictest3568-21runrttasks20:46:080
353999414,71cyclictest30123-21aten_r4power_cu00:01:530
2885729414,16sleep028897-21if_eth023:57:080
250629414,16sleep02507-21irqstats19:17:200
119129413,15sleep01194-21iostat_ios22:32:110
959029314,16sleep09593-21iostat_ios00:37:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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