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2026-02-16 - 18:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Mon Feb 16, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243869911030,69cyclictest15325-21munin-node11:41:150
243869910927,72cyclictest31654-21munin-node10:51:260
243869910925,73cyclictest8734-21munin-node09:41:230
243869910424,69cyclictest19893-21munin-node08:36:160
243869910320,73cyclictest21530-21aten_r4power_cu10:21:120
243869910119,72cyclictest13615-21aten_r4power_en11:36:130
243869910115,16cyclictest5884-21irqstats11:11:300
243869910015,76cyclictest26518-21latency07:16:350
24386999917,73cyclictest18718-21munin-node10:11:330
24386999827,62cyclictest5293-21munin-node07:51:220
24386999818,71cyclictest17094-21cut11:46:210
24386999815,74cyclictest16885-21sh08:26:280
24386999725,62cyclictest2686-21ls11:01:370
24386999721,66cyclictest15236-21munin-node10:01:230
24386999720,67cyclictest24064-21seq08:47:400
24386999715,73cyclictest2544-21sendmail_mailtr07:41:510
24386999714,74cyclictest30386-21grep12:26:360
24386999521,64cyclictest23880-21cat12:06:360
24386999516,70cyclictest22029-21proc_pri08:41:460
24386999514,72cyclictest1130-21switchtime09:16:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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