You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-27 - 16:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Tue Jan 27, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2293421190,4sleep022932-21users07:08:220
235829910212,80cyclictest22116-21chrt12:05:020
235829910114,78cyclictest16683-21munin-node11:48:200
23582999912,78cyclictest25669-21chrt12:17:300
23582999814,74cyclictest15345-21chrt10:04:280
23582999812,76cyclictest4901-21uname09:33:110
23582999715,73cyclictest10861-21runrttasks08:12:520
23582999712,75cyclictest25857-21munin-node08:58:110
23582999612,75cyclictest13911-21crond08:22:390
23582999513,72cyclictest1384-21runrttasks09:23:030
23582999415,70cyclictest23604-21munin-node07:13:010
23582999415,41cyclictest25612-21munin-node10:38:290
23582999315,69cyclictest19298-21sh10:17:550
23582999314,69cyclictest27159-21wget09:02:550
23582999313,71cyclictest20719-21df_abs08:42:550
23582999312,72cyclictest28822-21cpu09:07:540
23582999312,72cyclictest27259-21aten_r4power_cu10:42:520
23582999312,72cyclictest14079-21aten_r4power_en08:22:510
23582999312,71cyclictest30231-21cpu07:32:520
23582999311,73cyclictest26983-21cpu07:22:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional