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2026-03-05 - 14:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Thu Mar 05, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18204210613,32sleep018213-21smart_hda09:48:370
318359910121,70cyclictest3701-21runrttasks10:43:370
16599210115,16sleep016626-21switchtime09:43:390
9205210014,21sleep09230-21latency_hist09:22:480
314729914,16sleep03151-21kernelversion07:23:170
2715629914,17sleep027211-21munin-node10:17:590
31835999814,75cyclictest20629-21runrttasks11:37:480
31835999715,73cyclictest3568-21runrttasks10:47:590
31835999714,73cyclictest2436-21seq09:01:030
31835999714,47cyclictest16404-21proc_pri08:03:320
3257829614,16sleep032576-21ntp_states08:53:310
31835999615,71cyclictest6532-21kernelversion09:13:190
31835999614,73cyclictest30270-21latency_hist10:27:480
31835999614,72cyclictest14260-21aten_r4power_cu11:17:580
2254529615,16sleep022550-21hddtemp_smartct08:23:100
31835999514,72cyclictest13236-21munin-node09:33:330
362429414,16sleep03627-21ntp_states12:23:300
31835999415,69cyclictest5213-21munin-node12:28:260
31835999315,69cyclictest7030-21timerandwakeup10:53:410
31835999315,69cyclictest27672-21munin-node08:38:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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