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2026-02-03 - 06:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Tue Feb 03, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
268019915515,67cyclictest22484-21munin-node20:38:320
268019915214,67cyclictest19239-21munin-node22:08:230
268019915114,127cyclictest11154-21iostat20:03:340
268019914714,68cyclictest26251-21missed_timers00:08:410
268019914714,64cyclictest3695-21runrttasks21:53:150
268019914614,70cyclictest3695-21runrttasks21:10:270
268019914614,35cyclictest9275-21munin-node19:58:220
268019914515,34cyclictest4634-21fschecks_count21:23:260
268019914514,65cyclictest2919-21if_err_eth019:38:310
268019914215,31cyclictest30766-21munin-node00:23:200
268019914214,33cyclictest2349-21chrt19:37:390
268019914014,65cyclictest3695-21runrttasks23:40:410
268019914014,65cyclictest12531-21runrttasks23:27:340
268019913914,63cyclictest3695-21runrttasks21:41:100
268019913827,47cyclictest3081-21dbus-daemon19:48:020
268019913615,64cyclictest3077-21munin-node22:58:210
268019913614,38cyclictest2297-21ls00:33:590
268019913415,56cyclictest7997-21memory19:53:400
268019913414,67cyclictest17413-21munin-node22:03:430
268019913314,62cyclictest22291-21munin-node22:18:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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