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2026-01-21 - 02:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Wed Jan 21, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168489913814,90cyclictest26703-21sa121:22:140
168489913215,80cyclictest20877-21munin-node21:02:520
168489913116,105cyclictest7556-21sa123:42:140
168489913115,106cyclictest2946-21if_eth021:47:390
168489913015,105cyclictest30941-21cat21:33:070
168489912915,103cyclictest24366-21sensors_volt21:13:030
168489912914,105cyclictest18907-21munin-node19:17:390
168489912914,104cyclictest27236-21munin-node21:22:400
168489912814,103cyclictest11701-21munin-node23:53:070
168489912725,92cyclictest0-21swapper23:05:030
168489912715,74cyclictest1844-21munin-node21:43:110
168489912714,103cyclictest4515-21fschecks_time21:52:360
168489912514,102cyclictest3695-21runrttasks22:54:530
168489912414,100cyclictest18020-21munin-node22:33:020
168489912315,99cyclictest3695-21runrttasks00:01:430
168489912314,98cyclictest28067-21runrttasks19:46:410
168489912215,97cyclictest30870-21awk23:12:520
168489912214,99cyclictest20895-21if_eth022:42:400
168489912115,95cyclictest22090-21smartctl19:27:360
168489912114,98cyclictest25377-21munin-node22:58:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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