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2026-02-28 - 20:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sat Feb 28, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32505211917,24sleep032506-21sshd07:11:470
326809910229,64cyclictest24742-21munin-node08:28:080
32680999920,69cyclictest17184-21if_eth009:42:410
2375729914,16sleep023813-21tune2fs11:42:380
32680999715,72cyclictest12132-21munin-node11:07:270
32680999714,74cyclictest3568-21runrttasks12:38:110
32680999714,74cyclictest27376-21vmstat08:33:120
2544429714,19sleep025445-21memory10:07:520
32680999626,61cyclictest1050-21sensors_temp07:13:050
32680999615,72cyclictest29723-21ls10:22:180
32680999614,73cyclictest9288-21uname10:57:480
32680999524,62cyclictest2379-21fschecks_time08:57:370
32680999515,70cyclictest15904-21date11:17:530
1888429514,16sleep018885-21ntp_states08:07:590
1374929515,17sleep013750-21diskstats09:32:350
32680999422,63cyclictest26743-21df_abs10:12:310
32680999415,69cyclictest26731-21aten_r4power_cu11:52:280
32680999414,71cyclictest7669-21swap07:33:080
3124329414,15sleep031283-21aten_r4power_en08:47:280
782029314,16sleep07823-21iostat_ios12:32:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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