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2026-02-01 - 17:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sun Feb 01, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
203089913415,81cyclictest23749-21df_abs07:23:140
203089913214,108cyclictest21543-21ntp_states12:13:420
203089913214,108cyclictest17639-21munin-node12:03:110
203089913214,108cyclictest1297-21munin-node07:53:250
203089912915,104cyclictest2971-21munin-node07:58:240
203089912913,106cyclictest29179-21perl10:58:210
203089912814,105cyclictest19107-21runrttasks10:28:140
203089912814,104cyclictest32509-21munin-node07:48:480
203089912615,102cyclictest3695-21runrttasks10:52:030
203089912514,102cyclictest3695-21runrttasks11:31:440
203089912514,101cyclictest4479-21munin-node09:43:130
203089912514,101cyclictest2958-21diskstats09:38:160
203089912514,101cyclictest25224-21aten_r4power_cu07:28:110
203089912514,101cyclictest22621-21aten_r4power_vo12:18:130
203089912415,99cyclictest30520-21wget11:03:120
203089912414,100cyclictest12947-21if_err_eth010:08:260
203089912314,100cyclictest3695-21runrttasks08:33:450
203089912313,100cyclictest19785-21munin-node12:08:350
203089912215,97cyclictest1333-21fschecks_count09:33:220
203089912215,96cyclictest21275-21munin-node07:13:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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