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2026-02-19 - 11:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Thu Feb 19, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
407828320,4sleep04076-21munin-node19:06:530
49429911230,72cyclictest4358-21munin-node00:06:460
49429910725,72cyclictest2226-21munin-node22:21:350
49429910624,73cyclictest17268-21seq19:47:100
49429910523,73cyclictest6973-21munin-node22:36:300
49429910424,70cyclictest24678-21munin-node21:51:270
49429910421,73cyclictest16872-21fschecks_time21:26:410
49429910327,66cyclictest15671-21munin-node23:01:530
49429910321,73cyclictest853-21latency22:16:490
49429910217,75cyclictest3229-21automount19:26:540
49429910127,65cyclictest32428-21runrttasks23:52:280
49429910123,68cyclictest31721-21missed_timers22:11:520
49429910121,70cyclictest5271-21latency_hist22:31:180
49429910121,43cyclictest30026-21cut23:46:380
49429910120,72cyclictest12279-21iostat22:51:440
49429910120,72cyclictest11484-21aten_r4power_cu19:31:270
49429910023,67cyclictest10601-21munin-node00:26:320
4942999824,64cyclictest3568-21runrttasks21:56:260
4942999823,65cyclictest9397-21sed21:02:270
4942999821,66cyclictest28073-21cpu22:01:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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