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2026-02-06 - 07:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Fri Feb 06, 2026 00:43:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1708216400,5sleep025704-21sshd19:08:330
32029917415,149cyclictest25704-21sshd21:28:390
32029917316,148cyclictest25704-21sshd23:12:190
32029917115,118cyclictest25704-21sshd19:38:430
32029916617,140cyclictest25704-21sshd22:34:030
32029916615,142cyclictest25704-21sshd00:13:240
32029916417,113cyclictest8-21rcu_preempt19:29:510
32029916316,112cyclictest25704-21sshd21:09:410
32029916315,138cyclictest25704-21sshd19:58:390
32029916218,135cyclictest25704-21sshd21:02:490
32029916216,115cyclictest25704-21sshd23:38:060
32029916215,138cyclictest25704-21sshd21:56:130
32029916019,132cyclictest25704-21sshd19:35:240
32029916016,135cyclictest25704-21sshd21:51:010
32029916016,134cyclictest25704-21sshd19:54:350
32029916015,136cyclictest25704-21sshd21:39:340
32029915816,133cyclictest25704-21sshd22:43:530
32029915816,110cyclictest25704-21sshd20:33:010
32029915715,110cyclictest25704-21sshd23:46:480
32029915715,107cyclictest25704-21sshd23:41:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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