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2026-02-08 - 20:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sun Feb 08, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3119915314,129cyclictest13729-21chrt09:30:220
3119915214,127cyclictest9213-21tune2fs10:55:340
3119914914,125cyclictest2210-21diskstats07:15:310
3119914815,96cyclictest993-21fschecks_time10:30:330
3119914714,123cyclictest3874-21munin-node09:00:230
3119914615,122cyclictest2431-21cut08:55:310
3119914614,122cyclictest26774-21cat11:50:130
3119914414,120cyclictest1521-21grep08:51:090
3119914314,119cyclictest25141-21wc10:05:240
3119914314,118cyclictest31746-21munin-node10:25:310
3119914313,120cyclictest20561-21munin-node09:50:390
3119914214,119cyclictest7533-21if_eth009:10:370
3119914214,118cyclictest23616-21munin-node10:00:320
3119914214,118cyclictest11718-21munin-run07:45:110
3119914214,117cyclictest932-21munin-node12:10:240
3119914115,117cyclictest23241-21chrt08:20:210
3119914114,117cyclictest3857-21df07:20:240
3119914113,118cyclictest5165-21munin-node12:21:090
3119914016,114cyclictest18009-21sshd08:03:260
3119914015,115cyclictest8998-21munin-node07:35:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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