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2026-02-04 - 05:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Wed Feb 04, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19445211014,31sleep019475-21cpu23:43:230
8577210814,38sleep08609-21unixbench_singl19:49:090
3137210413,18sleep03182-21munin-node19:33:410
27051210317,67sleep027101-21sh19:08:220
5136210214,16sleep05151-21iostat22:58:380
27326210214,16sleep027380-21munin-node22:28:210
8221210114,20sleep08227-21munin-node21:28:380
29752210114,19sleep029754-21munin-node22:34:020
13300210114,16sleep013319-21ntp_states21:43:500
1419229914,16sleep02887-21syslogd23:26:430
1093829914,16sleep03377-21snmpd23:16:410
986829815,16sleep09886-21ntpq19:53:490
658329815,16sleep06637-21cut23:03:310
3083429815,20sleep030835-21irqstats20:58:450
1946329714,16sleep019504-21cut22:03:320
422529614,16sleep04239-21unixbench_singl00:34:080
28570999614,73cyclictest7996-21aten_r4power_cu23:08:210
2794029614,16sleep027943-21sshd00:08:430
697829514,16sleep06980-21smart_hda21:24:000
55929514,17sleep0574-21ntp_states00:23:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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