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2026-01-24 - 14:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sat Jan 24, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134619915214,40cyclictest3695-21runrttasks12:13:050
134619914915,69cyclictest842-21latency_hist11:32:300
134619914914,65cyclictest13646-21munin-node07:12:420
134619914514,69cyclictest15026-21sshd10:34:510
134619914415,66cyclictest18863-21cpu10:47:410
134619914414,70cyclictest20933-21sendmail_mailqu09:13:150
134619914314,65cyclictest30475-21processes08:03:160
134619914115,65cyclictest3695-21runrttasks12:21:340
134619914115,64cyclictest12952-21munin-node10:28:150
134619914115,63cyclictest1429-21chrt09:53:140
134619914015,36cyclictest14000-21munin-node08:52:500
134619913915,65cyclictest4391-21munin-node10:02:500
134619913914,65cyclictest21967-21munin-node10:57:540
134619913814,66cyclictest13306-21runrttasks08:50:340
134619913414,38cyclictest7735-21fschecks_count11:52:480
750929914,15sleep07537-21if_eth008:32:540
1303729614,69sleep013043-21open_files12:08:140
13461999516,69cyclictest20787-21fschecks_count12:32:470
1626129414,15sleep016267-21smart_hda10:38:210
13461999414,71cyclictest19025-21latency09:08:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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