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2026-02-04 - 22:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Wed Feb 04, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2993124130,5sleep029929-21munin-node07:08:240
2922211114,37sleep02927-21munin-node09:03:370
28415210115,16sleep028418-21memory12:03:490
736029814,16sleep07363-21iostat_ios12:38:410
493729814,16sleep04962-21proc_pri09:08:580
1752029814,16sleep017521-21irqstats08:08:420
218829714,21sleep02189-21entropy12:23:320
1273329714,16sleep012737-21hddtemp_smartct09:33:370
3143129614,15sleep031483-21cut12:13:350
3008329617,18sleep029520-21munin-node12:08:490
1981329617,16sleep019829-21sendmail_mailqu11:33:590
565529514,16sleep05659-21hddtemp_smartct12:33:350
31528999514,72cyclictest3695-21runrttasks07:33:400
2851429514,16sleep028551-21aten_r4power_vo08:43:250
1896129514,16sleep019004-21latency_hist11:33:140
927929414,16sleep09295-21hddtemp_smartct07:43:330
31528999414,71cyclictest3695-21runrttasks08:06:340
2690829415,16sleep026906-21ntp_states11:58:530
2419829414,16sleep024199-21iostat_ios10:08:420
2085929414,16sleep020888-21df_inode11:38:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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