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2026-03-04 - 13:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Wed Mar 04, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2545210414,25sleep02596-21uptime09:18:370
16814210414,16sleep016252-21munin-node10:03:190
31608210115,16sleep031633-21munin-node10:48:280
21943210115,16sleep021965-21sendmail_mailst11:58:290
19847210114,16sleep019848-21iostat_ios08:33:090
9506210014,16sleep03250-21snmpd11:20:500
616210014,16sleep0638-21sendmail_mailst07:33:270
31213210014,16sleep031249-21ls09:08:130
2949929913,15sleep029146-21munin-node09:03:050
1576329914,16sleep03250-21snmpd08:20:140
2912629814,17sleep029198-21latency_hist10:42:430
2649529815,16sleep026498-21iostat_ios12:13:100
25814999815,74cyclictest3568-21runrttasks08:23:000
2327829714,16sleep022736-21munin-node10:23:170
194229715,16sleep01945-21df_inode12:37:570
25814999615,71cyclictest4537-21seq07:46:150
25814999615,71cyclictest18160-21chrt11:47:570
2155329514,15sleep021554-21iostat_ios10:18:120
25814999415,70cyclictest7113-21netstat09:33:170
2471029414,16sleep024714-21hddtemp_smartct10:28:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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