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2026-03-01 - 16:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Sun Mar 01, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
66359911331,72cyclictest7575-21ls07:13:150
66359911129,71cyclictest10092-21munin-node07:22:370
66359911027,73cyclictest15112-21munin-node10:57:360
66359910929,71cyclictest12188-21munin-node07:28:060
66359910825,73cyclictest3079-21seq08:40:140
66359910723,74cyclictest10440-21uniq12:22:430
66359910526,69cyclictest7196-21fschecks_count12:12:410
66359910523,72cyclictest3560-21crond12:02:230
66359910519,75cyclictest10750-21munin-node09:03:090
66359910425,69cyclictest27734-21chrt08:17:300
66359910326,67cyclictest24349-21chrt08:07:060
66359910223,69cyclictest18488-21if_eth009:27:470
66359910217,76cyclictest32468-21runrttasks10:11:260
66359910129,62cyclictest5645-21runrttasks10:27:500
66359910019,71cyclictest32679-21aten_r4power_po08:32:330
663599999,80cyclictest6824-21runrttasks12:12:230
6635999936,53cyclictest3250-21snmpd12:05:450
6635999921,68cyclictest29154-21runrttasks10:00:530
6635999822,67cyclictest30235-21timerandwakeup08:23:140
6635999722,38cyclictest9343-21sendmail_mailtr12:18:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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