You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-03 - 19:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Tue Feb 03, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2772524120,5sleep027723-21munin-node07:08:260
290159914915,124cyclictest9569-21seq11:13:400
290159914714,123cyclictest9429-21sshd09:33:410
290159914615,93cyclictest4775-21ps09:18:560
290159914615,93cyclictest1103-21aten_r4power_en12:28:190
290159914615,121cyclictest28530-21tune2fs08:53:290
290159914414,91cyclictest30903-21chrt12:18:480
290159914414,121cyclictest3695-21runrttasks11:49:370
290159914414,120cyclictest14176-21hddtemp_smartct09:48:320
290159914414,120cyclictest10747-21munin-node11:18:190
290159914314,120cyclictest3695-21runrttasks08:47:350
290159914314,120cyclictest2221-21seq10:51:290
290159914314,119cyclictest28977-21munin-node10:33:430
290159914314,119cyclictest26186-21smart_hda12:03:590
290159914314,119cyclictest15058-21seq11:29:250
290159914313,120cyclictest26642-21chrt10:27:330
290159914214,118cyclictest3695-21runrttasks12:26:560
290159914114,118cyclictest6025-21cpu11:03:210
290159914114,117cyclictest19392-21munin-node11:43:420
290159914114,117cyclictest15631-21aten_r4power_cu11:33:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional