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2026-03-02 - 05:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot3.osadl.org (updated Mon Mar 02, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
643428670,4sleep06430-21iostat19:07:470
76399914715,59cyclictest10308-21munin-node00:18:140
76399914615,121cyclictest16616-21munin-node00:38:040
76399914614,37cyclictest30609-21sed22:02:400
76399914415,119cyclictest19075-21basename19:47:370
76399914315,118cyclictest11710-21needreboot00:23:030
76399914314,120cyclictest3568-21runrttasks21:01:130
76399914214,38cyclictest25724-21runrttasks21:47:380
76399914214,118cyclictest17989-21missed_timers21:23:000
76399914214,118cyclictest14663-21grep00:32:460
76399914115,116cyclictest5002-21munin-node00:02:510
76399914114,30cyclictest28348-21chrt23:33:540
76399914114,118cyclictest12893-21if_err_eth019:27:510
76399914114,117cyclictest9813-21missed_timers19:18:000
76399914014,117cyclictest16932-21vmstat22:58:240
76399914013,118cyclictest16443-21proc_pri19:38:080
76399913914,116cyclictest3568-21runrttasks23:38:540
76399913914,115cyclictest16344-21cat21:17:570
76399913815,113cyclictest30607-21munin-node20:22:440
76399913814,115cyclictest7817-21munin-node22:32:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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