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2026-03-05 - 19:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Thu Mar 05, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71470rcu_preempt0-21swapper/211:25:482
71470rcu_preempt0-21swapper/211:25:482
71460rcu_preempt6085-21copy11:41:450
71460rcu_preempt6085-21copy11:41:450
71460rcu_preempt6085-21copy11:41:450
46050460irq/122-QManpo28809-2110:48:550
46050460irq/122-QManpo28809-2110:48:550
71450rcu_preempt0-21swapper/007:10:380
71450rcu_preempt0-21swapper/007:10:380
46050430irq/122-QManpo8887-2110:48:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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