You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-08 - 22:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Sun Feb 08, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71450rcu_preempt16864-21taskset11:47:380
71450rcu_preempt16864-21taskset11:47:380
71450rcu_preempt16864-21taskset11:47:380
2298999442cyclictest30261-21memory12:11:293
2298999442cyclictest30261-21memory12:11:293
1599440migration/022560-21/usr/sbin/munin07:06:340
1599440migration/022560-21/usr/sbin/munin07:06:340
2298999434cyclictest0-21swapper/311:06:083
2298999434cyclictest0-21swapper/311:06:083
2298999433cyclictest0-21swapper/309:45:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional