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2026-02-20 - 17:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Fri Feb 20, 2026 12:44:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71690rcu_preempt0-21swapper/109:46:281
71690rcu_preempt0-21swapper/109:46:281
71610rcu_preempt0-21swapper/107:36:281
71610rcu_preempt0-21swapper/107:36:281
71610rcu_preempt0-21swapper/107:36:281
71550rcu_preempt0-21swapper/311:28:273
71550rcu_preempt0-21swapper/311:28:273
71460rcu_preempt0-21swapper/209:36:132
71460rcu_preempt0-21swapper/209:36:132
71450rcu_preempt0-21swapper/209:29:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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