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2026-02-23 - 19:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Mon Feb 23, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
781299511cyclictest20014-21apt-get12:21:351
781299511cyclictest20014-21apt-get12:21:351
7811995139cyclictest13434-21apt-get07:31:330
7811995139cyclictest13434-21apt-get07:31:330
7811994936cyclictest20290-21apt-get09:31:350
7811994936cyclictest20290-21apt-get09:31:350
7811994936cyclictest20290-21apt-get09:31:350
46050470irq/122-QManpo7735-2110:48:550
46050470irq/122-QManpo7735-2110:48:550
781299462cyclictest19261-21df10:26:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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