You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-02 - 19:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Mon Mar 02, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71810rcu_preempt3341-21copy09:31:411
71810rcu_preempt3341-21copy09:31:411
2337999523cyclictest0-21swapper/011:03:340
2337999523cyclictest0-21swapper/011:03:340
2337999522cyclictest11385-21diskstats12:36:470
2337999522cyclictest11385-21diskstats12:36:470
2337999522cyclictest11385-21diskstats12:36:470
2337999513cyclictest0-21swapper/010:51:410
2337999513cyclictest0-21swapper/010:51:410
2337999513cyclictest0-21swapper/010:51:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional