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2026-01-14 - 12:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Wed Jan 14, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71460rcu_preempt0-21swapper/122:53:041
71460rcu_preempt0-21swapper/122:53:041
71460rcu_preempt0-21swapper/122:53:041
71450rcu_preempt0-21swapper/019:41:080
71450rcu_preempt0-21swapper/019:41:080
46050440irq/122-QManpo19013-2110:48:550
46050440irq/122-QManpo19013-2110:48:550
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
1599440migration/019447-21taskset19:07:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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