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2026-02-04 - 19:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Wed Feb 04, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71530rcu_preempt0-21swapper/012:28:360
71530rcu_preempt0-21swapper/012:28:360
71460rcu_preempt20465-21kworker/2:209:41:072
71460rcu_preempt20465-21kworker/2:209:41:072
71460rcu_preempt20465-21kworker/2:209:41:072
71450rcu_preempt0-21swapper/009:56:240
71450rcu_preempt0-21swapper/009:56:240
450599428cyclictest0-21swapper/010:11:170
450599428cyclictest0-21swapper/010:11:170
4505994119cyclictest22398-21fw_packets12:31:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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