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2026-01-28 - 13:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Wed Jan 28, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301362494sleep030191-21diskstats19:06:080
301362494sleep030191-21diskstats19:06:080
71430rcu_preempt0-21swapper/000:29:490
71430rcu_preempt0-21swapper/000:29:490
46250430irq/120-QManpo30461-2110:48:551
46250430irq/120-QManpo30461-2110:48:551
71420rcu_preempt0-21swapper/319:26:123
71420rcu_preempt0-21swapper/319:26:123
71420rcu_preempt0-21swapper/119:26:141
71420rcu_preempt0-21swapper/119:26:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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