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2026-02-15 - 03:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Sun Feb 15, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71670rcu_preempt0-21swapper/023:45:010
71670rcu_preempt0-21swapper/023:45:010
71670rcu_preempt0-21swapper/023:45:010
71660rcu_preempt30357-21diskstats21:01:320
71660rcu_preempt30357-21diskstats21:01:320
71600rcu_preempt0-21swapper/000:17:370
71600rcu_preempt0-21swapper/000:17:370
71600rcu_preempt0-21swapper/000:17:370
71510rcu_preempt0-21swapper/019:51:360
71510rcu_preempt0-21swapper/019:51:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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