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2026-02-09 - 11:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Mon Feb 09, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71710rcu_preempt0-21swapper/022:13:140
71710rcu_preempt0-21swapper/022:13:140
71710rcu_preempt0-21swapper/022:13:140
71630rcu_preempt0-21swapper/022:19:560
71630rcu_preempt0-21swapper/022:19:560
1599520migration/02202-21/usr/sbin/munin19:06:270
1599520migration/02202-21/usr/sbin/munin19:06:270
71490rcu_preempt0-21swapper/219:11:202
71490rcu_preempt0-21swapper/219:11:202
71480rcu_preempt0-21swapper/222:26:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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