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2026-02-07 - 20:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot4.osadl.org (updated Sat Feb 07, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2573999543cyclictest0-21swapper/010:46:200
2573999543cyclictest0-21swapper/010:46:200
2573999543cyclictest0-21swapper/010:46:200
2573999532cyclictest1959-21runrttasks08:04:150
2573999532cyclictest1959-21runrttasks08:04:150
2573999525cyclictest8762-21wget08:06:180
2573999525cyclictest8762-21wget08:06:180
2573999522cyclictest7755-21ssh10:31:150
2573999522cyclictest7755-21ssh10:31:150
2573999522cyclictest31786-21meminfo07:31:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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