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2026-04-23 - 17:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Apr 23, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71650rcu_preempt0-21swapper/112:33:291
71650rcu_preempt0-21swapper/112:33:291
71640rcu_preempt0-21swapper/211:29:082
71640rcu_preempt0-21swapper/211:29:082
71640rcu_preempt0-21swapper/211:29:082
97682500chrt46450irq/118-QMan10:48:552
97682500chrt46450irq/118-QMan10:48:552
71500rcu_preempt0-21swapper/110:44:391
71500rcu_preempt0-21swapper/110:44:391
71500rcu_preempt0-21swapper/110:44:391
71500rcu_preempt0-21swapper/110:44:391
294099494cyclictest0-21swapper/309:02:563
294099494cyclictest0-21swapper/309:02:563
294099494cyclictest0-21swapper/309:02:563
20662485sleep22081-21ntp_states07:07:502
20662485sleep22081-21ntp_states07:07:502
71470rcu_preempt0-21swapper/110:07:421
71470rcu_preempt0-21swapper/110:07:421
71470rcu_preempt0-21swapper/110:07:421
71460rcu_preempt16109-1sh12:29:571
71460rcu_preempt16109-1sh12:29:571
71460rcu_preempt16109-1sh12:29:571
71450rcu_preempt1558-21taskset07:07:383
71450rcu_preempt1558-21taskset07:07:383
294099453cyclictest5813-21diskstats11:12:453
294099453cyclictest5813-21diskstats11:12:453
294099452cyclictest14625-21ntp_states07:52:513
294099452cyclictest14625-21ntp_states07:52:513
294099452cyclictest14625-21ntp_states07:52:513
2940994413cyclictest28200-21df08:42:423
2940994413cyclictest28200-21df08:42:423
71430rcu_preempt3785-21grep07:12:571
71430rcu_preempt3785-21grep07:12:571
71430rcu_preempt2815-21crond07:12:280
71430rcu_preempt2815-21crond07:12:280
294099434cyclictest0-21swapper/312:17:173
294099434cyclictest0-21swapper/312:17:173
294099434cyclictest0-21swapper/310:07:263
294099434cyclictest0-21swapper/310:07:263
294099433cyclictest29467-21meminfo09:57:503
294099433cyclictest29467-21meminfo09:57:503
294099433cyclictest0-21swapper/311:57:223
294099433cyclictest0-21swapper/311:57:223
294099433cyclictest0-21swapper/311:57:223
2940994317cyclictest0-21swapper/312:07:063
2940994317cyclictest0-21swapper/312:07:063
2940994317cyclictest0-21swapper/312:07:063
2940994312cyclictest0-21swapper/308:17:433
2940994312cyclictest0-21swapper/308:17:433
293599438cyclictest0-21swapper/211:53:132
293599438cyclictest0-21swapper/211:53:132
293599438cyclictest0-21swapper/211:53:132
71420rcu_preempt0-21swapper/110:53:561
71420rcu_preempt0-21swapper/110:53:561
71420rcu_preempt0-21swapper/107:12:301
71420rcu_preempt0-21swapper/107:12:301
294099424cyclictest0-21swapper/310:31:093
294099424cyclictest0-21swapper/310:31:093
294099424cyclictest0-21swapper/310:31:093
294099424cyclictest0-21swapper/309:34:073
294099424cyclictest0-21swapper/309:34:073
294099423cyclictest0-21swapper/312:41:283
294099423cyclictest0-21swapper/312:41:283
294099423cyclictest0-21swapper/312:41:283
294099423cyclictest0-21swapper/309:54:453
294099423cyclictest0-21swapper/309:54:453
294099423cyclictest0-21swapper/309:49:063
294099423cyclictest0-21swapper/309:49:063
294099423cyclictest0-21swapper/309:49:063
294099422cyclictest0-21swapper/310:37:423
294099422cyclictest0-21swapper/310:37:423
294099422cyclictest0-21swapper/310:37:423
2940994218cyclictest12054-21ssh09:26:443
2940994218cyclictest12054-21ssh09:26:443
2940994218cyclictest12054-21ssh09:26:443
71410rcu_preempt12955-21ssh09:27:541
71410rcu_preempt12955-21ssh09:27:541
71410rcu_preempt12955-21ssh09:27:541
71410rcu_preempt11850-21ntp_states11:22:540
71410rcu_preempt11850-21ntp_states11:22:540
71410rcu_preempt0-21swapper/209:26:552
71410rcu_preempt0-21swapper/209:26:552
71410rcu_preempt0-21swapper/209:26:552
71410rcu_preempt0-21swapper/110:05:301
71410rcu_preempt0-21swapper/110:05:301
71410rcu_preempt0-21swapper/012:10:180
71410rcu_preempt0-21swapper/012:10:180
71410rcu_preempt0-21swapper/012:10:180
71410rcu_preempt0-21swapper/012:06:450
71410rcu_preempt0-21swapper/012:06:450
71410rcu_preempt0-21swapper/012:06:450
71410rcu_preempt0-21swapper/007:22:310
71410rcu_preempt0-21swapper/007:22:310
71410rcu_preempt0-21swapper/007:22:310
294099413cyclictest0-21swapper/312:07:413
294099413cyclictest0-21swapper/312:07:413
294099413cyclictest0-21swapper/312:07:413
294099413cyclictest0-21swapper/308:32:463
294099413cyclictest0-21swapper/308:32:463
2940994117cyclictest18333-21ssh12:33:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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