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2026-08-28 - 12:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Aug 28, 2026 00:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243712720chrt46050irq/122-QMan10:48:550
243712720chrt46050irq/122-QMan10:48:550
71680rcu_preempt0-21swapper/322:25:193
71680rcu_preempt0-21swapper/322:25:193
71670rcu_preempt0-21swapper/200:01:592
71670rcu_preempt0-21swapper/200:01:592
71580rcu_preempt0-21swapper/000:25:350
71580rcu_preempt0-21swapper/000:25:350
2755799542cyclictest26088-21/usr/sbin/munin23:04:590
2755799542cyclictest26088-21/usr/sbin/munin23:04:590
2755799514cyclictest0-21swapper/021:55:000
2755799514cyclictest0-21swapper/021:55:000
2755799513cyclictest0-21swapper/021:10:090
2755799513cyclictest0-21swapper/021:10:090
27557995118cyclictest0-21swapper/022:45:180
27557995118cyclictest0-21swapper/022:45:180
27557995118cyclictest0-21swapper/022:45:180
2755799503cyclictest0-21swapper/023:29:410
2755799503cyclictest0-21swapper/023:29:410
2755799503cyclictest0-21swapper/022:59:280
2755799503cyclictest0-21swapper/022:59:280
2755799493cyclictest0-21swapper/021:47:530
2755799493cyclictest0-21swapper/021:47:530
2755799483cyclictest0-21swapper/019:44:400
2755799483cyclictest0-21swapper/019:44:400
71460rcu_preempt0-21swapper/021:15:290
71460rcu_preempt0-21swapper/021:15:290
71460rcu_preempt0-21swapper/021:15:290
2755799431cyclictest0-21swapper/019:54:520
2755799431cyclictest0-21swapper/019:54:520
100650430irq/38-i2c-mpc0-21swapper/023:22:450
100650430irq/38-i2c-mpc0-21swapper/023:22:450
71420rcu_preempt0-21swapper/319:19:523
71420rcu_preempt0-21swapper/319:19:523
71420rcu_preempt0-21swapper/020:39:490
71420rcu_preempt0-21swapper/020:39:490
71410rcu_preempt0-21swapper/321:31:343
71410rcu_preempt0-21swapper/321:31:343
71410rcu_preempt0-21swapper/000:40:360
71410rcu_preempt0-21swapper/000:40:360
71410rcu_preempt0-21swapper/000:40:360
71400rcu_preempt0-21swapper/321:52:503
71400rcu_preempt0-21swapper/321:52:503
71400rcu_preempt0-21swapper/121:24:541
71400rcu_preempt0-21swapper/121:24:541
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
71390rcu_preempt27091-1kworker/1:2H23:25:011
71390rcu_preempt27091-1kworker/1:2H23:25:011
71390rcu_preempt0-21swapper/023:03:190
71390rcu_preempt0-21swapper/023:03:190
71390rcu_preempt0-21swapper/023:03:190
71390rcu_preempt0-21swapper/020:49:590
71390rcu_preempt0-21swapper/020:49:590
100650390irq/38-i2c-mpc0-21swapper/123:38:061
100650390irq/38-i2c-mpc0-21swapper/123:38:061
100650390irq/38-i2c-mpc0-21swapper/123:38:061
100650390irq/38-i2c-mpc0-21swapper/021:32:200
100650390irq/38-i2c-mpc0-21swapper/021:32:200
71380rcu_preempt32402-21processes23:15:060
71380rcu_preempt32402-21processes23:15:060
71380rcu_preempt0-21swapper/222:54:432
71380rcu_preempt0-21swapper/222:54:432
71380rcu_preempt0-21swapper/221:45:342
71380rcu_preempt0-21swapper/221:45:342
71380rcu_preempt0-21swapper/123:44:451
71380rcu_preempt0-21swapper/123:44:451
71380rcu_preempt0-21swapper/123:44:451
46050380irq/122-QManpo30061-2110:48:550
46050380irq/122-QManpo30061-2110:48:550
71370rcu_preempt30242-21taskset23:11:100
71370rcu_preempt30242-21taskset23:11:100
71370rcu_preempt1460-21copy21:24:440
71370rcu_preempt1460-21copy21:24:440
71370rcu_preempt1460-21copy21:24:440
71370rcu_preempt0-21swapper/222:26:562
71370rcu_preempt0-21swapper/222:26:562
71370rcu_preempt0-21swapper/200:39:532
71370rcu_preempt0-21swapper/200:39:532
71370rcu_preempt0-21swapper/200:39:532
71370rcu_preempt0-21swapper/200:39:432
71370rcu_preempt0-21swapper/200:39:432
71370rcu_preempt0-21swapper/121:46:301
71370rcu_preempt0-21swapper/121:46:301
71370rcu_preempt0-21swapper/121:18:051
71370rcu_preempt0-21swapper/121:18:051
71370rcu_preempt0-21swapper/121:18:051
71370rcu_preempt0-21swapper/022:51:310
71370rcu_preempt0-21swapper/022:51:310
71370rcu_preempt0-21swapper/020:54:560
71370rcu_preempt0-21swapper/020:54:560
71370rcu_preempt0-21swapper/020:19:490
71370rcu_preempt0-21swapper/020:19:490
71370rcu_preempt0-21swapper/020:19:490
46450370irq/118-QManpo27255-2110:48:552
46450370irq/118-QManpo27255-2110:48:552
71360rcu_preempt32263-21sh21:20:412
71360rcu_preempt32263-21sh21:20:412
71360rcu_preempt32263-21sh21:20:412
71360rcu_preempt19995-21ssh23:50:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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