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2025-11-28 - 11:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Nov 28, 2025 00:54:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71700rcu_preempt0-21swapper/000:29:530
71700rcu_preempt0-21swapper/000:29:530
71620rcu_preempt0-21swapper/322:17:223
71620rcu_preempt0-21swapper/322:17:223
71540rcu_preempt0-21swapper/321:39:353
71540rcu_preempt0-21swapper/321:39:353
71540rcu_preempt0-21swapper/100:54:391
71540rcu_preempt0-21swapper/100:54:391
744899474cyclictest0-21swapper/222:28:082
744899474cyclictest0-21swapper/222:28:082
46050470irq/122-QManpo0-210
46050470irq/122-QManpo0-210
46050470irq/122-QManpo0-210
744899464cyclictest0-21swapper/220:57:412
744899464cyclictest0-21swapper/220:57:412
744899464cyclictest0-21swapper/200:27:412
744899464cyclictest0-21swapper/200:27:412
744899464cyclictest0-21swapper/200:27:412
46050460irq/122-QManpo0-210
46050460irq/122-QManpo0-210
744899453cyclictest27519-21ntp_states22:13:072
744899453cyclictest27519-21ntp_states22:13:072
744899453cyclictest0-21swapper/222:00:052
744899453cyclictest0-21swapper/222:00:052
744899453cyclictest0-21swapper/222:00:052
744899444cyclictest0-21swapper/223:03:002
744899444cyclictest0-21swapper/223:03:002
744899444cyclictest0-21swapper/222:35:112
744899444cyclictest0-21swapper/222:35:112
744899444cyclictest0-21swapper/221:38:142
744899444cyclictest0-21swapper/221:38:142
744899443cyclictest0-21swapper/223:22:132
744899443cyclictest0-21swapper/223:22:132
744899443cyclictest0-21swapper/223:22:132
744899443cyclictest0-21swapper/221:18:032
744899443cyclictest0-21swapper/221:18:032
744899442cyclictest17801-21load23:53:032
744899442cyclictest17801-21load23:53:032
744899442cyclictest17801-21load23:53:032
71440rcu_preempt0-21swapper/220:18:022
71440rcu_preempt0-21swapper/220:18:022
744899434cyclictest0-21swapper/222:25:502
744899434cyclictest0-21swapper/222:25:502
744899434cyclictest0-21swapper/222:08:082
744899434cyclictest0-21swapper/222:08:082
744899434cyclictest0-21swapper/221:47:412
744899434cyclictest0-21swapper/221:47:412
744899434cyclictest0-21swapper/221:47:412
744899434cyclictest0-21swapper/200:06:562
744899434cyclictest0-21swapper/200:06:562
744899433cyclictest0-21swapper/223:59:572
744899433cyclictest0-21swapper/223:59:572
744899433cyclictest0-21swapper/200:53:082
744899433cyclictest0-21swapper/200:53:082
744899433cyclictest0-21swapper/200:13:072
744899433cyclictest0-21swapper/200:13:072
7448994310cyclictest3974-21/usr/sbin/munin00:28:062
7448994310cyclictest3974-21/usr/sbin/munin00:28:062
744899424cyclictest0-21swapper/221:57:452
744899424cyclictest0-21swapper/221:57:452
744899423cyclictest0-21swapper/223:48:032
744899423cyclictest0-21swapper/223:48:032
744899423cyclictest0-21swapper/223:31:122
744899423cyclictest0-21swapper/223:31:122
744899423cyclictest0-21swapper/223:31:122
744899423cyclictest0-21swapper/222:04:522
744899423cyclictest0-21swapper/222:04:522
744899423cyclictest0-21swapper/201:02:422
744899423cyclictest0-21swapper/201:02:422
744899423cyclictest0-21swapper/201:02:422
744899423cyclictest0-21swapper/200:08:022
744899423cyclictest0-21swapper/200:08:022
744899414cyclictest0-21swapper/221:28:092
744899414cyclictest0-21swapper/221:28:092
744899413cyclictest0-21swapper/223:12:392
744899413cyclictest0-21swapper/223:12:392
744899413cyclictest0-21swapper/223:02:442
744899413cyclictest0-21swapper/223:02:442
744899413cyclictest0-21swapper/222:48:432
744899413cyclictest0-21swapper/222:48:432
744899413cyclictest0-21swapper/222:48:432
744899413cyclictest0-21swapper/222:18:092
744899413cyclictest0-21swapper/222:18:092
744899413cyclictest0-21swapper/220:22:592
744899413cyclictest0-21swapper/220:22:592
744899413cyclictest0-21swapper/201:08:062
744899413cyclictest0-21swapper/201:08:062
744899413cyclictest0-21swapper/200:35:422
744899413cyclictest0-21swapper/200:35:422
744899413cyclictest0-21swapper/200:35:422
71410rcu_preempt0-21swapper/323:17:553
71410rcu_preempt0-21swapper/323:17:553
71410rcu_preempt0-21swapper/323:17:553
71410rcu_preempt0-21swapper/022:28:090
71410rcu_preempt0-21swapper/022:28:090
744899403cyclictest0-21swapper/223:17:172
744899403cyclictest0-21swapper/223:17:172
744899403cyclictest0-21swapper/223:17:172
744899403cyclictest0-21swapper/222:53:072
744899403cyclictest0-21swapper/222:53:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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