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2026-06-12 - 05:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Jun 12, 2026 00:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
408299483cyclictest0-21swapper/123:11:291
408299483cyclictest0-21swapper/123:11:291
408299483cyclictest0-21swapper/123:11:291
46050460irq/122-QManpo0-210
46050460irq/122-QManpo0-210
408299464cyclictest0-21swapper/122:22:411
408299464cyclictest0-21swapper/122:22:411
408299463cyclictest0-21swapper/100:26:461
408299463cyclictest0-21swapper/100:26:461
408299463cyclictest0-21swapper/100:26:461
71450rcu_preempt0-21swapper/122:17:101
71450rcu_preempt0-21swapper/122:17:101
46450450irq/118-QManpo3942-2110:48:552
46450450irq/118-QManpo3942-2110:48:552
408299453cyclictest0-21swapper/120:13:321
408299453cyclictest0-21swapper/120:13:321
408299453cyclictest0-21swapper/100:33:481
408299453cyclictest0-21swapper/100:33:481
408299453cyclictest0-21swapper/100:33:481
408299451cyclictest26513-21/usr/sbin/munin23:58:331
408299451cyclictest26513-21/usr/sbin/munin23:58:331
408299451cyclictest26513-21/usr/sbin/munin23:58:331
71440rcu_preempt15916-21kworker/0:121:33:220
71440rcu_preempt15916-21kworker/0:121:33:220
71440rcu_preempt15916-21kworker/0:121:33:220
408299444cyclictest0-21swapper/123:24:361
408299444cyclictest0-21swapper/123:24:361
408299444cyclictest0-21swapper/121:58:531
408299444cyclictest0-21swapper/121:58:531
408299443cyclictest29645-21ntp_states20:43:481
408299443cyclictest29645-21ntp_states20:43:481
408299443cyclictest29645-21ntp_states20:43:481
408299443cyclictest0-21swapper/123:18:521
408299443cyclictest0-21swapper/123:18:521
408299443cyclictest0-21swapper/122:48:501
408299443cyclictest0-21swapper/122:48:501
408299443cyclictest0-21swapper/122:23:511
408299443cyclictest0-21swapper/122:23:511
408299443cyclictest0-21swapper/122:23:511
408299443cyclictest0-21swapper/122:12:321
408299443cyclictest0-21swapper/122:12:321
408299441cyclictest4087-21/usr/sbin/munin19:13:351
408299441cyclictest4087-21/usr/sbin/munin19:13:351
46050430irq/122-QManpo8233-10
46050430irq/122-QManpo8233-10
46050430irq/122-QManpo8233-10
408299434cyclictest0-21swapper/121:49:311
408299434cyclictest0-21swapper/121:49:311
408299434cyclictest0-21swapper/121:49:311
408299434cyclictest0-21swapper/100:08:371
408299434cyclictest0-21swapper/100:08:371
408299434cyclictest0-21swapper/100:08:371
408299433cyclictest0-21swapper/123:55:011
408299433cyclictest0-21swapper/123:55:011
408299433cyclictest0-21swapper/123:55:011
408299433cyclictest0-21swapper/123:13:471
408299433cyclictest0-21swapper/123:13:471
408299433cyclictest0-21swapper/123:13:471
408299433cyclictest0-21swapper/123:06:051
408299433cyclictest0-21swapper/123:06:051
408299433cyclictest0-21swapper/123:06:051
408299433cyclictest0-21swapper/122:46:241
408299433cyclictest0-21swapper/122:46:241
408299433cyclictest0-21swapper/122:46:241
408299433cyclictest0-21swapper/121:53:471
408299433cyclictest0-21swapper/121:53:471
408299433cyclictest0-21swapper/121:53:471
408299433cyclictest0-21swapper/121:38:521
408299433cyclictest0-21swapper/121:38:521
408299433cyclictest0-21swapper/121:31:351
408299433cyclictest0-21swapper/121:31:351
408299433cyclictest0-21swapper/121:31:351
408299433cyclictest0-21swapper/120:22:471
408299433cyclictest0-21swapper/120:22:471
408299433cyclictest0-21swapper/100:19:451
408299433cyclictest0-21swapper/100:19:451
4082994317cyclictest10754-21meminfo21:23:441
4082994317cyclictest10754-21meminfo21:23:441
4082994317cyclictest10754-21meminfo21:23:441
4082994316cyclictest15291-21memory00:38:441
4082994316cyclictest15291-21memory00:38:441
4082994316cyclictest15291-21memory00:38:441
71420rcu_preempt0-21swapper/223:48:262
71420rcu_preempt0-21swapper/223:48:262
71420rcu_preempt0-21swapper/223:48:262
408299423cyclictest0-21swapper/123:49:211
408299423cyclictest0-21swapper/123:49:211
408299423cyclictest0-21swapper/123:49:211
408299423cyclictest0-21swapper/123:38:211
408299423cyclictest0-21swapper/123:38:211
408299423cyclictest0-21swapper/123:38:211
408299423cyclictest0-21swapper/123:33:271
408299423cyclictest0-21swapper/123:33:271
408299423cyclictest0-21swapper/123:00:391
408299423cyclictest0-21swapper/123:00:391
408299423cyclictest0-21swapper/123:00:391
408299423cyclictest0-21swapper/122:56:011
408299423cyclictest0-21swapper/122:56:011
408299423cyclictest0-21swapper/122:56:011
408299423cyclictest0-21swapper/122:43:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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