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2026-04-24 - 16:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Apr 24, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121022910sleep246450irq/118-QMan10:48:552
121022910sleep246450irq/118-QMan10:48:552
121022910sleep246450irq/118-QMan10:48:552
71650rcu_preempt0-21swapper/309:17:273
71650rcu_preempt0-21swapper/309:17:273
71620rcu_preempt0-21swapper/209:15:422
71620rcu_preempt0-21swapper/209:15:422
46050500irq/122-QManpo32681-2110:48:550
46050500irq/122-QManpo32681-2110:48:550
71480rcu_preempt0-21swapper/011:04:290
71480rcu_preempt0-21swapper/011:04:290
71480rcu_preempt0-21swapper/011:04:290
71470rcu_preempt0-21swapper/211:17:262
71470rcu_preempt0-21swapper/211:17:262
71460rcu_preempt0-21swapper/011:27:410
71460rcu_preempt0-21swapper/011:27:410
71460rcu_preempt0-21swapper/011:27:410
141299453cyclictest0-21swapper/209:17:542
141299453cyclictest0-21swapper/209:17:542
141299451cyclictest17575-21/usr/sbin/munin10:37:562
141299451cyclictest17575-21/usr/sbin/munin10:37:562
141299451cyclictest17575-21/usr/sbin/munin10:37:562
71440rcu_preempt0-21swapper/210:03:142
71440rcu_preempt0-21swapper/210:03:142
141299444cyclictest0-21swapper/211:37:572
141299444cyclictest0-21swapper/211:37:572
141299443cyclictest0-21swapper/210:30:582
141299443cyclictest0-21swapper/210:30:582
141299443cyclictest0-21swapper/210:30:582
141299443cyclictest0-21swapper/209:28:002
141299443cyclictest0-21swapper/209:28:002
141299443cyclictest0-21swapper/209:28:002
141299443cyclictest0-21swapper/208:27:572
141299443cyclictest0-21swapper/208:27:572
141299443cyclictest0-21swapper/208:02:542
141299443cyclictest0-21swapper/208:02:542
141299443cyclictest0-21swapper/208:02:542
71430rcu_preempt0-21swapper/109:13:491
71430rcu_preempt0-21swapper/109:13:491
71430rcu_preempt0-21swapper/010:32:490
71430rcu_preempt0-21swapper/010:32:490
71430rcu_preempt0-21swapper/008:30:070
71430rcu_preempt0-21swapper/008:30:070
46650430irq/116-QManpo9678-2110:48:553
46650430irq/116-QManpo9678-2110:48:553
46650430irq/116-QManpo9678-2110:48:553
141299434cyclictest0-21swapper/212:11:212
141299434cyclictest0-21swapper/212:11:212
141299434cyclictest0-21swapper/212:11:212
141299434cyclictest0-21swapper/211:18:262
141299434cyclictest0-21swapper/211:18:262
141299434cyclictest0-21swapper/210:42:572
141299434cyclictest0-21swapper/210:42:572
141299434cyclictest0-21swapper/210:42:572
141299434cyclictest0-21swapper/210:27:042
141299434cyclictest0-21swapper/210:27:042
141299434cyclictest0-21swapper/210:27:042
141299433cyclictest22336-21meminfo09:47:512
141299433cyclictest22336-21meminfo09:47:512
141299433cyclictest22336-21meminfo09:47:512
141299433cyclictest0-21swapper/212:05:482
141299433cyclictest0-21swapper/212:05:482
141299433cyclictest0-21swapper/211:22:542
141299433cyclictest0-21swapper/211:22:542
141299433cyclictest0-21swapper/211:22:542
141299433cyclictest0-21swapper/210:55:132
141299433cyclictest0-21swapper/210:55:132
141299433cyclictest0-21swapper/210:55:132
141299432cyclictest26972-21ntp_states08:42:542
141299432cyclictest26972-21ntp_states08:42:542
141299432cyclictest26324-21munin-run08:42:302
141299432cyclictest26324-21munin-run08:42:302
141299432cyclictest2314-21users07:12:572
141299432cyclictest2314-21users07:12:572
141299432cyclictest20188-21users09:42:592
141299432cyclictest20188-21users09:42:592
141299432cyclictest15296-21ntp_states11:32:542
141299432cyclictest15296-21ntp_states11:32:542
141299431cyclictest0-21swapper/207:27:522
141299431cyclictest0-21swapper/207:27:522
71420rcu_preempt0-21swapper/110:26:521
71420rcu_preempt0-21swapper/110:26:521
71420rcu_preempt0-21swapper/110:26:521
71420rcu_preempt0-21swapper/109:26:441
71420rcu_preempt0-21swapper/109:26:441
71420rcu_preempt0-21swapper/109:26:441
46050420irq/122-QManpo2833-210
46050420irq/122-QManpo2833-210
141299424cyclictest0-21swapper/207:22:532
141299424cyclictest0-21swapper/207:22:532
141299423cyclictest0-21swapper/212:25:112
141299423cyclictest0-21swapper/212:25:112
141299423cyclictest0-21swapper/210:49:032
141299423cyclictest0-21swapper/210:49:032
141299423cyclictest0-21swapper/210:49:032
141299423cyclictest0-21swapper/209:58:162
141299423cyclictest0-21swapper/209:58:162
141299423cyclictest0-21swapper/209:33:392
141299423cyclictest0-21swapper/209:33:392
141299423cyclictest0-21swapper/209:27:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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