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2025-12-10 - 05:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Dec 10, 2025 00:53:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8481994815cyclictest25581-21/usr/sbin/munin20:43:120
8481994815cyclictest25581-21/usr/sbin/munin20:43:120
71480rcu_preempt0-21swapper/023:53:030
71480rcu_preempt0-21swapper/023:53:030
71480rcu_preempt0-21swapper/023:53:030
71470rcu_preempt0-21swapper/223:03:532
71470rcu_preempt0-21swapper/223:03:532
71460rcu_preempt0-21swapper/100:12:481
71460rcu_preempt0-21swapper/100:12:481
71460rcu_preempt0-21swapper/100:12:481
71450rcu_preempt0-21swapper/323:53:113
71450rcu_preempt0-21swapper/323:53:113
71450rcu_preempt0-21swapper/323:53:113
71450rcu_preempt0-21swapper/220:03:202
71450rcu_preempt0-21swapper/220:03:202
71450rcu_preempt0-21swapper/023:27:110
71450rcu_preempt0-21swapper/023:27:110
71450rcu_preempt0-21swapper/023:27:110
71430rcu_preempt0-21swapper/021:08:160
71430rcu_preempt0-21swapper/021:08:160
71430rcu_preempt0-21swapper/021:08:160
8481994211cyclictest0-21swapper/000:03:330
8481994211cyclictest0-21swapper/000:03:330
71420rcu_preempt23320-21/usr/sbin/munin00:58:153
71420rcu_preempt23320-21/usr/sbin/munin00:58:153
71420rcu_preempt0-21swapper/023:51:160
71420rcu_preempt0-21swapper/023:51:160
8481994112cyclictest8352-21diskmemload22:08:340
8481994112cyclictest8352-21diskmemload22:08:340
71410rcu_preempt0-21swapper/322:33:523
71410rcu_preempt0-21swapper/322:33:523
71410rcu_preempt0-21swapper/022:30:430
71410rcu_preempt0-21swapper/022:30:430
71400rcu_preempt0-21swapper/322:57:573
71400rcu_preempt0-21swapper/322:57:573
71400rcu_preempt0-21swapper/322:04:503
71400rcu_preempt0-21swapper/322:04:503
71400rcu_preempt0-21swapper/322:04:503
71400rcu_preempt0-21swapper/121:08:131
71400rcu_preempt0-21swapper/121:08:131
71400rcu_preempt0-21swapper/121:08:131
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
848199398cyclictest0-21swapper/022:15:320
848199398cyclictest0-21swapper/022:15:320
8481993924cyclictest0-21swapper/023:30:050
8481993924cyclictest0-21swapper/023:30:050
71390rcu_preempt16740-21vmstat20:08:233
71390rcu_preempt16740-21vmstat20:08:233
71390rcu_preempt0-21swapper/223:22:502
71390rcu_preempt0-21swapper/223:22:502
71390rcu_preempt0-21swapper/221:08:012
71390rcu_preempt0-21swapper/221:08:012
71390rcu_preempt0-21swapper/221:01:352
71390rcu_preempt0-21swapper/221:01:352
71390rcu_preempt0-21swapper/021:43:240
71390rcu_preempt0-21swapper/021:43:240
8481993820cyclictest31131-21apt-get21:03:060
8481993820cyclictest31131-21apt-get21:03:060
8481993818cyclictest12595-21df22:43:080
8481993818cyclictest12595-21df22:43:080
8481993811cyclictest214101ntp_states22:58:220
8481993811cyclictest214101ntp_states22:58:220
71380rcu_preempt29130-21latency_hist23:13:012
71380rcu_preempt0-21swapper/322:12:583
71380rcu_preempt0-21swapper/322:12:583
71380rcu_preempt0-21swapper/300:34:373
71380rcu_preempt0-21swapper/300:34:373
71380rcu_preempt0-21swapper/222:58:002
71380rcu_preempt0-21swapper/222:58:002
71380rcu_preempt0-21swapper/200:48:062
71380rcu_preempt0-21swapper/200:48:062
71380rcu_preempt0-21swapper/200:48:062
71380rcu_preempt0-21swapper/022:38:220
71380rcu_preempt0-21swapper/022:38:220
71380rcu_preempt0-21swapper/022:03:480
71380rcu_preempt0-21swapper/022:03:480
71380rcu_preempt0-21swapper/022:03:480
71380rcu_preempt0-21swapper/021:03:000
71380rcu_preempt0-21swapper/020:53:400
71380rcu_preempt0-21swapper/020:53:400
71380rcu_preempt0-21swapper/000:00:300
71380rcu_preempt0-21swapper/000:00:300
848199379cyclictest13329-21chrt00:39:160
848199379cyclictest13329-21chrt00:39:160
8481993722cyclictest0-21swapper/000:17:240
8481993722cyclictest0-21swapper/000:17:240
8481993722cyclictest0-21swapper/000:17:240
8481993716cyclictest3189-21/usr/sbin/munin21:18:150
8481993716cyclictest3189-21/usr/sbin/munin21:18:150
8481993715cyclictest29343-21df23:13:080
8481993715cyclictest29343-21df23:13:080
8481993714cyclictest15229-21/usr/sbin/munin22:48:160
8481993714cyclictest15229-21/usr/sbin/munin22:48:160
8481993714cyclictest0-21swapper/000:12:560
8481993714cyclictest0-21swapper/000:12:560
8481993714cyclictest0-21swapper/000:12:560
71370rcu_preempt19578-21cat23:53:162
71370rcu_preempt19578-21cat23:53:162
71370rcu_preempt19578-21cat23:53:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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