You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-27 - 14:27
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Dec 27, 2025 12:43:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71680rcu_preempt3056-21copy11:15:320
71680rcu_preempt3056-21copy11:15:320
71520rcu_preempt17329-21apt-get11:40:421
71520rcu_preempt17329-21apt-get11:40:421
71520rcu_preempt17329-21apt-get11:40:421
71470rcu_preempt0-21swapper/310:40:223
71470rcu_preempt0-21swapper/310:40:223
71460rcu_preempt17298-21sh11:40:170
71460rcu_preempt17298-21sh11:40:170
71460rcu_preempt17298-21sh11:40:170
2757299452cyclictest23798-21ssh10:54:571
2757299452cyclictest23798-21ssh10:54:571
2757299452cyclictest23798-21ssh10:54:571
71440rcu_preempt0-21swapper/209:25:222
71440rcu_preempt0-21swapper/209:25:222
27574994419cyclictest5505-21ntp_states09:25:463
27574994419cyclictest5505-21ntp_states09:25:463
2757299445cyclictest0-21swapper/109:50:381
2757299445cyclictest0-21swapper/109:50:381
2757299444cyclictest0-21swapper/112:24:191
2757299444cyclictest0-21swapper/112:24:191
2757499434cyclictest0-21swapper/310:16:343
2757499434cyclictest0-21swapper/310:16:343
2757499434cyclictest0-21swapper/310:16:343
2757499434cyclictest0-21swapper/308:15:423
2757499434cyclictest0-21swapper/308:15:423
2757499434cyclictest0-21swapper/308:15:423
2757499433cyclictest0-21swapper/309:35:293
2757499433cyclictest0-21swapper/309:35:293
27574994319cyclictest29861-21ssh11:05:293
27574994319cyclictest29861-21ssh11:05:293
27574994317cyclictest27263-21diskstats11:00:363
27574994317cyclictest27263-21diskstats11:00:363
27574994317cyclictest27263-21diskstats11:00:363
27574994316cyclictest8344-21df_inode12:20:373
27574994316cyclictest8344-21df_inode12:20:373
2757299433cyclictest0-21swapper/112:15:391
2757299433cyclictest0-21swapper/112:15:391
2757299433cyclictest0-21swapper/112:15:391
2757299433cyclictest0-21swapper/109:26:471
2757299433cyclictest0-21swapper/109:26:471
2757299433cyclictest0-21swapper/108:10:451
2757299433cyclictest0-21swapper/108:10:451
71420rcu_preempt22494-21ssh11:48:540
71420rcu_preempt22494-21ssh11:48:540
71420rcu_preempt0-21swapper/210:45:282
71420rcu_preempt0-21swapper/210:45:282
71420rcu_preempt0-21swapper/110:16:061
71420rcu_preempt0-21swapper/110:16:061
71420rcu_preempt0-21swapper/110:16:061
71420rcu_preempt0-21swapper/011:15:220
71420rcu_preempt0-21swapper/011:15:220
46650420irq/116-QManpo27162-2110:48:553
46650420irq/116-QManpo27162-2110:48:553
46650420irq/116-QManpo27162-2110:48:553
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
2757499424cyclictest0-21swapper/312:40:183
2757499424cyclictest0-21swapper/312:40:183
2757499424cyclictest0-21swapper/311:25:383
2757499424cyclictest0-21swapper/311:25:383
2757499423cyclictest25351-21irqstats10:00:393
2757499423cyclictest25351-21irqstats10:00:393
2757499423cyclictest0-21swapper/311:53:243
2757499423cyclictest0-21swapper/311:53:243
2757499423cyclictest0-21swapper/309:53:383
2757499423cyclictest0-21swapper/309:53:383
2757499422cyclictest18099-21ntp_states11:40:483
2757499422cyclictest18099-21ntp_states11:40:483
2757499422cyclictest18099-21ntp_states11:40:483
27574994217cyclictest29654-21/usr/sbin/munin12:00:463
27574994217cyclictest29654-21/usr/sbin/munin12:00:463
27574994216cyclictest0-21swapper/309:15:333
27574994216cyclictest0-21swapper/309:15:333
27574994216cyclictest0-21swapper/309:15:333
2757299424cyclictest0-21swapper/111:26:321
2757299424cyclictest0-21swapper/111:26:321
27572994217cyclictest7458-21ssh11:21:581
27572994217cyclictest7458-21ssh11:21:581
71410rcu_preempt4726-21sh09:25:170
71410rcu_preempt4726-21sh09:25:170
71410rcu_preempt0-21swapper/008:00:390
71410rcu_preempt0-21swapper/008:00:390
46050410irq/122-QManpo833-2110:48:550
46050410irq/122-QManpo833-2110:48:550
2757499413cyclictest0-21swapper/312:05:483
2757499413cyclictest0-21swapper/312:05:483
2757499413cyclictest0-21swapper/310:30:333
2757499413cyclictest0-21swapper/310:30:333
2757499413cyclictest0-21swapper/310:25:563
2757499413cyclictest0-21swapper/310:25:563
2757499413cyclictest0-21swapper/310:25:563
2757499413cyclictest0-21swapper/310:10:343
2757499413cyclictest0-21swapper/310:10:343
2757499413cyclictest0-21swapper/308:50:323
2757499413cyclictest0-21swapper/308:50:323
2757499412cyclictest6527-21meminfo11:20:423
2757499412cyclictest6527-21meminfo11:20:423
2757499412cyclictest16488-21users10:40:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional