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2026-06-03 - 11:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Jun 03, 2026 00:44:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71610rcu_preempt0-21swapper/223:10:002
71610rcu_preempt0-21swapper/223:10:002
71510rcu_preempt0-21swapper/222:03:422
71510rcu_preempt0-21swapper/222:03:422
46050510irq/122-QManpo32438-210
46050510irq/122-QManpo32438-210
71490rcu_preempt0-21swapper/222:30:402
71490rcu_preempt0-21swapper/222:30:402
71490rcu_preempt0-21swapper/222:30:402
71470rcu_preempt0-21swapper/219:13:162
71470rcu_preempt0-21swapper/219:13:162
46650440irq/116-QManpo1284-2110:48:553
46650440irq/116-QManpo1284-2110:48:553
141499444cyclictest0-21swapper/100:21:281
141499444cyclictest0-21swapper/100:21:281
141499444cyclictest0-21swapper/100:21:281
141499443cyclictest0-21swapper/122:48:281
141499443cyclictest0-21swapper/122:48:281
141499443cyclictest0-21swapper/122:48:281
141499443cyclictest0-21swapper/121:08:351
141499443cyclictest0-21swapper/121:08:351
141499443cyclictest0-21swapper/121:08:351
71430rcu_preempt4791-21kworker/0:419:48:220
71430rcu_preempt4791-21kworker/0:419:48:220
141499433cyclictest0-21swapper/123:38:311
141499433cyclictest0-21swapper/123:38:311
141499433cyclictest0-21swapper/123:38:311
141499433cyclictest0-21swapper/123:13:431
141499433cyclictest0-21swapper/123:13:431
141499433cyclictest0-21swapper/123:13:431
141499432cyclictest18246-21ssh23:51:071
141499432cyclictest18246-21ssh23:51:071
141499432cyclictest18246-21ssh23:51:071
141499431cyclictest9101-21ssh21:29:231
141499431cyclictest9101-21ssh21:29:231
141499431cyclictest9101-21ssh21:29:231
141499431cyclictest24809-1kworker/1:0H23:08:341
141499431cyclictest24809-1kworker/1:0H23:08:341
1414994319cyclictest0-21swapper/122:38:421
1414994319cyclictest0-21swapper/122:38:421
1414994319cyclictest0-21swapper/122:38:421
71420rcu_preempt0-21swapper/021:28:040
71420rcu_preempt0-21swapper/021:28:040
71420rcu_preempt0-21swapper/021:28:040
46050420irq/122-QManpo13553-2110:48:550
46050420irq/122-QManpo13553-2110:48:550
46050420irq/122-QManpo13553-2110:48:550
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
141499424cyclictest0-21swapper/121:45:451
141499424cyclictest0-21swapper/121:45:451
141499424cyclictest0-21swapper/121:45:451
141499424cyclictest0-21swapper/100:23:271
141499424cyclictest0-21swapper/100:23:271
141499424cyclictest0-21swapper/100:23:271
141499423cyclictest0-21swapper/123:45:441
141499423cyclictest0-21swapper/123:45:441
141499423cyclictest0-21swapper/123:45:441
141499423cyclictest0-21swapper/122:09:461
141499423cyclictest0-21swapper/122:09:461
141499423cyclictest0-21swapper/122:09:461
141499423cyclictest0-21swapper/122:03:441
141499423cyclictest0-21swapper/122:03:441
141499423cyclictest0-21swapper/121:58:371
141499423cyclictest0-21swapper/121:58:371
141499423cyclictest0-21swapper/121:58:371
141499423cyclictest0-21swapper/121:37:261
141499423cyclictest0-21swapper/121:37:261
141499423cyclictest0-21swapper/121:19:241
141499423cyclictest0-21swapper/121:19:241
141499423cyclictest0-21swapper/119:51:031
141499423cyclictest0-21swapper/119:51:031
141499423cyclictest0-21swapper/100:03:441
141499423cyclictest0-21swapper/100:03:441
141499423cyclictest0-21swapper/100:03:441
141499422cyclictest9197-21meminfo23:33:351
141499422cyclictest9197-21meminfo23:33:351
141499422cyclictest9197-21meminfo23:33:351
141499422cyclictest22772-21df_inode22:58:311
141499422cyclictest22772-21df_inode22:58:311
141499422cyclictest22772-21df_inode22:58:311
141499422cyclictest18771-21cat20:23:311
141499422cyclictest18771-21cat20:23:311
141499422cyclictest18771-21cat20:23:311
141499422cyclictest18310-21cat20:23:141
141499422cyclictest18310-21cat20:23:141
141499422cyclictest15003-21diskstats22:43:281
141499422cyclictest15003-21diskstats22:43:281
1414994213cyclictest5533-21ssh23:26:491
1414994213cyclictest5533-21ssh23:26:491
1414994213cyclictest5533-21ssh23:26:491
71410rcu_preempt0-21swapper/121:42:131
71410rcu_preempt0-21swapper/121:42:131
71410rcu_preempt0-21swapper/121:42:131
46050410irq/122-QManpo28647-2110:48:550
46050410irq/122-QManpo28647-2110:48:550
141499413cyclictest0-21swapper/122:32:511
141499413cyclictest0-21swapper/122:32:511
141499413cyclictest0-21swapper/122:32:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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