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2026-06-13 - 06:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Jun 13, 2026 00:44:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71680rcu_preempt0-21swapper/200:35:342
71680rcu_preempt0-21swapper/200:35:342
71680rcu_preempt0-21swapper/200:35:342
71570rcu_preempt0-21swapper/321:49:053
71570rcu_preempt0-21swapper/321:49:053
71540rcu_preempt0-21swapper/100:30:451
71540rcu_preempt0-21swapper/100:30:451
71540rcu_preempt0-21swapper/100:30:451
46050510irq/122-QManpo1011-2110:48:550
46050510irq/122-QManpo1011-2110:48:550
46050510irq/122-QManpo1011-2110:48:550
46050510irq/122-QManpo1011-2110:48:550
71470rcu_preempt4554-1kworker/0:1H21:03:390
71470rcu_preempt4554-1kworker/0:1H21:03:390
71470rcu_preempt4201-21wc19:09:532
71470rcu_preempt4201-21wc19:09:532
71470rcu_preempt4201-21wc19:09:532
71470rcu_preempt4201-21wc19:09:532
71450rcu_preempt2711-21sh00:10:112
71450rcu_preempt2711-21sh00:10:112
71450rcu_preempt2711-21sh00:10:112
46650450irq/116-QManpo506-213
46650450irq/116-QManpo506-213
46650450irq/116-QManpo506-213
46650450irq/116-QManpo506-213
71440rcu_preempt0-21swapper/323:03:343
71430rcu_preempt7461-21runrttasks00:18:552
71430rcu_preempt7461-21runrttasks00:18:552
71430rcu_preempt1444-21od19:08:451
71430rcu_preempt1444-21od19:08:451
71430rcu_preempt1444-21od19:08:451
71430rcu_preempt1444-21od19:08:451
71430rcu_preempt0-21swapper/223:02:442
71430rcu_preempt0-21swapper/223:02:442
71430rcu_preempt0-21swapper/223:02:442
71430rcu_preempt0-21swapper/223:02:442
71430rcu_preempt0-21swapper/222:52:552
71430rcu_preempt0-21swapper/222:52:552
71430rcu_preempt0-21swapper/222:52:552
71430rcu_preempt0-21swapper/222:36:232
71430rcu_preempt0-21swapper/222:36:232
71430rcu_preempt0-21swapper/222:27:322
71430rcu_preempt0-21swapper/222:27:322
71420rcu_preempt0-21swapper/323:06:043
71420rcu_preempt0-21swapper/323:06:043
71420rcu_preempt0-21swapper/323:06:043
71420rcu_preempt0-21swapper/323:06:043
71420rcu_preempt0-21swapper/222:29:212
71420rcu_preempt0-21swapper/222:29:212
71420rcu_preempt0-21swapper/222:29:212
71420rcu_preempt0-21swapper/022:44:480
71420rcu_preempt0-21swapper/022:44:480
71420rcu_preempt0-21swapper/022:44:480
71420rcu_preempt0-21swapper/022:44:480
71410rcu_preempt4292-21copy21:03:381
71410rcu_preempt4292-21copy21:03:381
71410rcu_preempt21316-21copy20:08:270
71410rcu_preempt21316-21copy20:08:270
71410rcu_preempt0-21swapper/300:26:213
71410rcu_preempt0-21swapper/300:26:213
71410rcu_preempt0-21swapper/300:26:213
71410rcu_preempt0-21swapper/223:56:552
71410rcu_preempt0-21swapper/223:56:552
71410rcu_preempt0-21swapper/223:56:552
71410rcu_preempt0-21swapper/223:23:542
71410rcu_preempt0-21swapper/223:23:542
71410rcu_preempt0-21swapper/221:47:172
71410rcu_preempt0-21swapper/221:47:172
71410rcu_preempt0-21swapper/221:47:172
71410rcu_preempt0-21swapper/221:22:292
71410rcu_preempt0-21swapper/221:22:292
71410rcu_preempt0-21swapper/221:22:292
71410rcu_preempt0-21swapper/221:22:292
71410rcu_preempt0-21swapper/020:33:250
71410rcu_preempt0-21swapper/020:33:250
46250410irq/120-QManpo13934-2110:48:551
46250410irq/120-QManpo13934-2110:48:551
46250410irq/120-QManpo13934-2110:48:551
46050410irq/122-QManpo14453-2110:48:550
46050410irq/122-QManpo14453-2110:48:550
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
71400rcu_preempt8088-1kworker/2:2H23:37:212
71400rcu_preempt8088-1kworker/2:2H23:37:212
71400rcu_preempt8088-1kworker/2:2H23:37:212
71400rcu_preempt5088-21kworker/2:122:12:172
71400rcu_preempt5088-21kworker/2:122:12:172
71400rcu_preempt5088-21kworker/2:122:12:172
71400rcu_preempt21619-21sendmail-msp22:47:163
71400rcu_preempt21619-21sendmail-msp22:47:163
71400rcu_preempt21619-21sendmail-msp22:47:163
71400rcu_preempt21619-21sendmail-msp22:47:163
71400rcu_preempt0-21swapper/321:35:403
71400rcu_preempt0-21swapper/321:35:403
71400rcu_preempt0-21swapper/321:35:403
71400rcu_preempt0-21swapper/300:09:433
71400rcu_preempt0-21swapper/300:09:433
71400rcu_preempt0-21swapper/300:09:433
71400rcu_preempt0-21swapper/223:39:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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