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2026-05-06 - 21:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed May 06, 2026 12:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
171912680chrt46250irq/120-QMan10:48:551
171912680chrt46250irq/120-QMan10:48:551
171912680chrt46250irq/120-QMan10:48:551
71460rcu_preempt19941-1kworker/0:2H10:23:040
71460rcu_preempt19941-1kworker/0:2H10:23:040
71460rcu_preempt19941-1kworker/0:2H10:23:040
71460rcu_preempt0-21swapper/107:09:081
71460rcu_preempt0-21swapper/107:09:081
71460rcu_preempt0-21swapper/107:09:081
71460rcu_preempt0-21swapper/011:53:350
71460rcu_preempt0-21swapper/011:53:350
71440rcu_preempt0-21swapper/110:13:471
71440rcu_preempt0-21swapper/110:13:471
46050440irq/122-QManpo12141-2110:48:550
46050440irq/122-QManpo12141-2110:48:550
46050440irq/122-QManpo12141-2110:48:550
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
71430rcu_preempt0-21swapper/009:48:360
71430rcu_preempt0-21swapper/009:48:360
71430rcu_preempt0-21swapper/009:48:360
46050430irq/122-QManpo29298-2110:48:550
46050430irq/122-QManpo29298-2110:48:550
71420rcu_preempt0-21swapper/112:27:511
71420rcu_preempt0-21swapper/112:27:511
71420rcu_preempt0-21swapper/112:27:511
71420rcu_preempt0-21swapper/009:24:160
71420rcu_preempt0-21swapper/009:24:160
71420rcu_preempt0-21swapper/009:24:160
46050420irq/122-QManpo19623-2110:48:550
46050420irq/122-QManpo19623-2110:48:550
46050420irq/122-QManpo19623-2110:48:550
71410rcu_preempt0-21swapper/112:30:181
71410rcu_preempt0-21swapper/112:30:181
71410rcu_preempt0-21swapper/112:30:181
46650410irq/116-QManpo9273-2110:48:553
46650410irq/116-QManpo9273-2110:48:553
46650410irq/116-QManpo9273-2110:48:553
46450410irq/118-QManpo13267-2110:48:552
46450410irq/118-QManpo13267-2110:48:552
46450410irq/118-QManpo13267-2110:48:552
13392994136cyclictest12614-21grep11:08:110
13392994136cyclictest12614-21grep11:08:110
13392994136cyclictest12614-21grep11:08:110
71400rcu_preempt22160-21sh12:27:280
71400rcu_preempt22160-21sh12:27:280
71400rcu_preempt22160-21sh12:27:280
71400rcu_preempt0-21swapper/310:43:123
71400rcu_preempt0-21swapper/310:43:123
71400rcu_preempt0-21swapper/310:43:123
71400rcu_preempt0-21swapper/111:57:421
71400rcu_preempt0-21swapper/111:57:421
71400rcu_preempt0-21swapper/109:44:501
71400rcu_preempt0-21swapper/109:44:501
71400rcu_preempt0-21swapper/109:44:501
71390rcu_preempt25939-21/usr/sbin/munin07:57:563
71390rcu_preempt25939-21/usr/sbin/munin07:57:563
71390rcu_preempt10353-1kworker/1:3H12:18:471
71390rcu_preempt10353-1kworker/1:3H12:18:471
71390rcu_preempt0-21swapper/312:05:563
71390rcu_preempt0-21swapper/312:05:563
71390rcu_preempt0-21swapper/312:05:563
71390rcu_preempt0-21swapper/310:15:483
71390rcu_preempt0-21swapper/310:15:483
71390rcu_preempt0-21swapper/210:32:382
71390rcu_preempt0-21swapper/210:32:382
71390rcu_preempt0-21swapper/110:27:421
71390rcu_preempt0-21swapper/110:27:421
71390rcu_preempt0-21swapper/110:27:421
71390rcu_preempt0-21swapper/010:48:330
71390rcu_preempt0-21swapper/010:48:330
71390rcu_preempt0-21swapper/010:48:330
46050390irq/122-QManpo6942-10
46050390irq/122-QManpo6942-10
71380rcu_preempt8848-21sendmail-msp12:08:093
71380rcu_preempt8848-21sendmail-msp12:08:093
71380rcu_preempt8848-21sendmail-msp12:08:093
71380rcu_preempt19902-21sh11:22:541
71380rcu_preempt19902-21sh11:22:541
71380rcu_preempt19902-21sh11:22:541
71380rcu_preempt0-21swapper/311:15:383
71380rcu_preempt0-21swapper/311:15:383
71380rcu_preempt0-21swapper/212:33:312
71380rcu_preempt0-21swapper/212:33:312
71380rcu_preempt0-21swapper/212:33:312
71380rcu_preempt0-21swapper/111:07:551
71380rcu_preempt0-21swapper/111:07:551
71380rcu_preempt0-21swapper/111:07:551
71380rcu_preempt0-21swapper/107:57:531
71380rcu_preempt0-21swapper/107:57:531
71380rcu_preempt0-21swapper/012:18:060
71380rcu_preempt0-21swapper/012:18:060
71380rcu_preempt0-21swapper/011:33:260
71380rcu_preempt0-21swapper/011:33:260
71380rcu_preempt0-21swapper/011:33:260
71380rcu_preempt0-21swapper/009:45:000
71380rcu_preempt0-21swapper/009:45:000
71380rcu_preempt0-21swapper/009:45:000
71380rcu_preempt0-21swapper/009:31:460
71380rcu_preempt0-21swapper/009:31:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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