You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-28 - 20:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Jan 28, 2026 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71600rcu_preempt0-21swapper/109:52:051
71600rcu_preempt0-21swapper/109:52:051
1574699563cyclictest0-21swapper/010:01:020
1574699563cyclictest0-21swapper/010:01:020
1574699553cyclictest0-21swapper/011:18:110
1574699553cyclictest0-21swapper/011:18:110
1574699553cyclictest0-21swapper/011:18:110
1574699533cyclictest5192-21ntp_states12:36:170
1574699533cyclictest5192-21ntp_states12:36:170
1574699533cyclictest5192-21ntp_states12:36:170
71520rcu_preempt0-21swapper/307:51:133
71520rcu_preempt0-21swapper/307:51:133
71520rcu_preempt0-21swapper/307:51:133
1574699523cyclictest0-21swapper/010:47:010
1574699523cyclictest0-21swapper/010:47:010
1574699513cyclictest0-21swapper/008:06:060
1574699513cyclictest0-21swapper/008:06:060
1574699512cyclictest26475-21/usr/sbin/munin11:21:210
1574699512cyclictest26475-21/usr/sbin/munin11:21:210
1574699511cyclictest15919-21/usr/sbin/munin10:06:240
1574699511cyclictest15919-21/usr/sbin/munin10:06:240
1574699511cyclictest15919-21/usr/sbin/munin10:06:240
1574699511cyclictest0-21swapper/010:51:260
1574699511cyclictest0-21swapper/010:51:260
1574699504cyclictest0-21swapper/010:56:050
1574699504cyclictest0-21swapper/010:56:050
1574699504cyclictest0-21swapper/010:56:050
1574699504cyclictest0-21swapper/007:46:080
1574699504cyclictest0-21swapper/007:46:080
1574699503cyclictest0-21swapper/012:01:480
1574699503cyclictest0-21swapper/012:01:480
1574699503cyclictest0-21swapper/012:01:480
1574699503cyclictest0-21swapper/010:25:540
1574699503cyclictest0-21swapper/010:25:540
1574699503cyclictest0-21swapper/007:30:550
1574699503cyclictest0-21swapper/007:30:550
1574699501cyclictest16789-21/usr/sbin/munin09:11:200
1574699501cyclictest16789-21/usr/sbin/munin09:11:200
1574999492cyclictest24401-21sendmail-msp10:21:423
1574999492cyclictest24401-21sendmail-msp10:21:423
1574699494cyclictest0-21swapper/011:01:440
1574699494cyclictest0-21swapper/011:01:440
1574699494cyclictest0-21swapper/011:01:440
1574699494cyclictest0-21swapper/008:40:540
1574699494cyclictest0-21swapper/008:40:540
1574699493cyclictest0-21swapper/012:31:180
1574699493cyclictest0-21swapper/012:31:180
1574699493cyclictest0-21swapper/012:10:030
1574699493cyclictest0-21swapper/012:10:030
1574699493cyclictest0-21swapper/012:10:030
1574699493cyclictest0-21swapper/010:16:130
1574699493cyclictest0-21swapper/010:16:130
1574699493cyclictest0-21swapper/010:16:130
1574699493cyclictest0-21swapper/009:31:130
1574699493cyclictest0-21swapper/009:31:130
1574699492cyclictest8958-21ntp_states08:41:190
1574699492cyclictest8958-21ntp_states08:41:190
1574699492cyclictest25415-21/usr/sbin/munin09:26:120
1574699492cyclictest25415-21/usr/sbin/munin09:26:120
1574699492cyclictest13112-21/usr/sbin/munin10:01:060
1574699492cyclictest13112-21/usr/sbin/munin10:01:060
15746994918cyclictest2999-21ssh09:42:320
15746994918cyclictest2999-21ssh09:42:320
15746994918cyclictest2999-21ssh09:42:320
1574699489cyclictest26368-1kworker/0:2H11:36:370
1574699489cyclictest26368-1kworker/0:2H11:36:370
1574699489cyclictest26368-1kworker/0:2H11:36:370
1574699484cyclictest0-21swapper/011:42:020
1574699484cyclictest0-21swapper/011:42:020
1574699483cyclictest0-21swapper/011:47:240
1574699483cyclictest0-21swapper/011:47:240
1574699483cyclictest0-21swapper/009:56:090
1574699483cyclictest0-21swapper/009:16:140
1574699483cyclictest0-21swapper/009:16:140
1574699483cyclictest0-21swapper/009:16:140
1574699483cyclictest0-21swapper/008:56:450
1574699483cyclictest0-21swapper/008:56:450
1574699483cyclictest0-21swapper/008:46:220
1574699483cyclictest0-21swapper/008:46:220
1574699483cyclictest0-21swapper/008:11:480
1574699483cyclictest0-21swapper/008:11:480
1574699481cyclictest32641-21sed11:31:170
1574699481cyclictest32641-21sed11:31:170
1574699481cyclictest3137-21/usr/sbin/munin08:21:090
1574699481cyclictest3137-21/usr/sbin/munin08:21:090
15746994818cyclictest0-21swapper/010:40:440
15746994818cyclictest0-21swapper/010:40:440
15746994818cyclictest0-21swapper/010:40:440
71470rcu_preempt0-21swapper/108:41:401
71470rcu_preempt0-21swapper/108:41:401
46050470irq/122-QManpo15702-2110:48:550
46050470irq/122-QManpo15702-2110:48:550
1574699473cyclictest0-21swapper/012:28:400
1574699473cyclictest0-21swapper/012:28:400
1574699473cyclictest0-21swapper/011:56:090
1574699473cyclictest0-21swapper/011:56:090
1574699472cyclictest24047-21grep07:40:550
1574699472cyclictest24047-21grep07:40:550
1574699472cyclictest24047-21grep07:40:550
1574699471cyclictest4284-21/usr/sbin/munin08:26:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional