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2026-07-15 - 20:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Jul 15, 2026 12:44:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71520rcu_preempt5364-21kworker/3:208:09:083
71520rcu_preempt0-21swapper/211:49:102
71520rcu_preempt0-21swapper/211:49:102
71520rcu_preempt0-21swapper/211:49:102
46050510irq/122-QManpo22786-2110:48:550
46050510irq/122-QManpo22786-2110:48:550
71500rcu_preempt0-21swapper/210:09:162
71500rcu_preempt0-21swapper/210:09:162
71490rcu_preempt0-21swapper/112:01:551
71490rcu_preempt0-21swapper/112:01:551
2304799479cyclictest8888-21sh10:51:063
2304799479cyclictest8888-21sh10:51:063
71460rcu_preempt0-21swapper/009:55:350
71460rcu_preempt0-21swapper/009:55:350
2304799461cyclictest20720-21/usr/sbin/munin09:04:153
2304799461cyclictest20720-21/usr/sbin/munin09:04:153
2304799461cyclictest20720-21/usr/sbin/munin09:04:153
71450rcu_preempt4631-1unixbench_multi09:39:262
71450rcu_preempt4631-1unixbench_multi09:39:262
71450rcu_preempt4631-1unixbench_multi09:39:262
2304799453cyclictest0-21swapper/308:59:133
2304799453cyclictest0-21swapper/308:59:133
2304799446cyclictest0-21swapper/310:07:043
2304799446cyclictest0-21swapper/310:07:043
2304799446cyclictest0-21swapper/310:07:043
2304799443cyclictest0-21swapper/310:59:233
2304799443cyclictest0-21swapper/310:59:233
1599440migration/023313-21taskset10:16:510
1599440migration/023313-21taskset10:16:510
1599440migration/023313-21taskset10:16:510
1599440migration/023313-21taskset10:16:510
71430rcu_preempt0-21swapper/208:09:002
71430rcu_preempt0-21swapper/208:09:002
71430rcu_preempt0-21swapper/208:09:002
71430rcu_preempt0-21swapper/208:09:002
46050430irq/122-QManpo12393-210
46050430irq/122-QManpo12393-210
46050430irq/122-QManpo12393-210
2304799437cyclictest12851-21ssh09:55:593
2304799437cyclictest12851-21ssh09:55:593
2304799434cyclictest0-21swapper/310:39:123
2304799434cyclictest0-21swapper/310:39:123
2304799433cyclictest19231-21ntp_states12:14:283
2304799433cyclictest19231-21ntp_states12:14:283
2304799433cyclictest19231-21ntp_states12:14:283
2304799433cyclictest19231-21ntp_states12:14:283
2304799433cyclictest15691-21ntp_states08:44:203
2304799433cyclictest15691-21ntp_states08:44:203
2304799433cyclictest0-21swapper/310:26:203
2304799433cyclictest0-21swapper/310:26:203
2304799433cyclictest0-21swapper/310:26:203
2304799432cyclictest21191-21df12:19:103
2304799432cyclictest21191-21df12:19:103
2304799432cyclictest21191-21df12:19:103
2304799432cyclictest21191-21df12:19:103
2304799431cyclictest25201-21sendmail-msp07:27:333
2304799431cyclictest25201-21sendmail-msp07:27:333
2304799431cyclictest25201-21sendmail-msp07:27:333
71420rcu_preempt24386-21grep09:14:251
71420rcu_preempt24386-21grep09:14:251
71420rcu_preempt24386-21grep09:14:251
2304799424cyclictest0-21swapper/311:45:093
2304799424cyclictest0-21swapper/311:45:093
2304799424cyclictest0-21swapper/311:45:093
2304799423cyclictest0-21swapper/312:41:113
2304799423cyclictest0-21swapper/312:41:113
2304799423cyclictest0-21swapper/312:41:113
2304799423cyclictest0-21swapper/312:14:003
2304799423cyclictest0-21swapper/312:14:003
2304799423cyclictest0-21swapper/312:14:003
2304799423cyclictest0-21swapper/312:14:003
2304799423cyclictest0-21swapper/311:53:523
2304799423cyclictest0-21swapper/311:53:523
2304799423cyclictest0-21swapper/311:53:523
2304799423cyclictest0-21swapper/310:31:453
2304799423cyclictest0-21swapper/310:31:453
2304799423cyclictest0-21swapper/309:09:223
2304799423cyclictest0-21swapper/309:09:223
2304799423cyclictest0-21swapper/309:09:223
2304799423cyclictest0-21swapper/309:09:223
2304799422cyclictest11180-21df08:29:093
2304799422cyclictest11180-21df08:29:093
2304799421cyclictest6157-21sendmail-msp10:21:413
2304799421cyclictest6157-21sendmail-msp10:21:413
2304799421cyclictest6157-21sendmail-msp10:21:413
2304799421cyclictest5197-21ssh10:44:193
2304799421cyclictest5197-21ssh10:44:193
2304799421cyclictest5197-21ssh10:44:193
71410rcu_preempt0-21swapper/111:20:581
71410rcu_preempt0-21swapper/111:20:581
71410rcu_preempt0-21swapper/111:20:581
71410rcu_preempt0-21swapper/011:46:380
71410rcu_preempt0-21swapper/011:46:380
71410rcu_preempt0-21swapper/011:46:380
71410rcu_preempt0-21swapper/011:17:140
71410rcu_preempt0-21swapper/011:17:140
71410rcu_preempt0-21swapper/009:28:210
71410rcu_preempt0-21swapper/009:28:210
2304799413cyclictest0-21swapper/312:06:393
2304799413cyclictest0-21swapper/312:06:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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