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2026-09-17 - 08:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Sep 17, 2026 00:44:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
535499582cyclictest25815-21sh22:46:060
535499582cyclictest25815-21sh22:46:060
535499572cyclictest0-21swapper/000:01:540
535499572cyclictest0-21swapper/000:01:540
535499572cyclictest0-21swapper/000:01:540
535499563cyclictest0-21swapper/023:51:100
535499563cyclictest0-21swapper/023:51:100
535499544cyclictest0-21swapper/022:55:270
535499544cyclictest0-21swapper/022:55:270
535499544cyclictest0-21swapper/022:55:270
535499544cyclictest0-21swapper/021:25:250
535499544cyclictest0-21swapper/021:25:250
535499544cyclictest0-21swapper/019:40:270
535499544cyclictest0-21swapper/019:40:270
535499543cyclictest20897-21irqstats23:35:190
535499543cyclictest20897-21irqstats23:35:190
71530rcu_preempt0-21swapper/319:20:293
71530rcu_preempt0-21swapper/319:20:293
535499533cyclictest13731-21memory19:45:220
535499531cyclictest0-21swapper/020:40:170
535499531cyclictest0-21swapper/020:40:170
535499524cyclictest0-21swapper/022:15:350
535499524cyclictest0-21swapper/022:15:350
535499524cyclictest0-21swapper/022:09:280
535499524cyclictest0-21swapper/022:09:280
535499524cyclictest0-21swapper/022:09:280
535499523cyclictest0-21swapper/023:30:080
535499523cyclictest0-21swapper/023:30:080
535499514cyclictest0-21swapper/021:42:570
535499514cyclictest0-21swapper/021:42:570
535499514cyclictest0-21swapper/021:42:570
535499514cyclictest0-21swapper/000:10:240
535499514cyclictest0-21swapper/000:10:240
535499513cyclictest0-21swapper/023:45:010
535499513cyclictest0-21swapper/023:45:010
535499513cyclictest0-21swapper/023:45:010
535499513cyclictest0-21swapper/023:25:200
535499513cyclictest0-21swapper/023:25:200
535499513cyclictest0-21swapper/021:20:320
535499513cyclictest0-21swapper/021:20:320
535499513cyclictest0-21swapper/000:20:180
535499513cyclictest0-21swapper/000:20:180
535499513cyclictest0-21swapper/000:20:180
535499512cyclictest1690-21users23:00:320
535499512cyclictest1690-21users23:00:320
535499512cyclictest1690-21users23:00:320
535499505cyclictest10533-21aten_r4power_cu22:20:180
535499505cyclictest10533-21aten_r4power_cu22:20:180
535499504cyclictest0-21swapper/022:14:390
535499504cyclictest0-21swapper/022:14:390
535499504cyclictest0-21swapper/000:44:270
535499504cyclictest0-21swapper/000:44:270
535499503cyclictest0-21swapper/022:50:260
535499503cyclictest0-21swapper/022:50:260
535499503cyclictest0-21swapper/022:41:350
535499503cyclictest0-21swapper/022:41:350
535499503cyclictest0-21swapper/021:58:540
535499503cyclictest0-21swapper/021:58:540
535499503cyclictest0-21swapper/021:36:030
535499503cyclictest0-21swapper/021:36:030
535499503cyclictest0-21swapper/020:30:150
535499503cyclictest0-21swapper/020:30:150
535499503cyclictest0-21swapper/019:18:540
535499503cyclictest0-21swapper/019:18:540
535499503cyclictest0-21swapper/000:35:060
535499503cyclictest0-21swapper/000:35:060
535499502cyclictest5518-21diskstats00:05:180
535499502cyclictest5518-21diskstats00:05:180
535499502cyclictest5518-21diskstats00:05:180
535499502cyclictest3789-21df23:05:150
535499502cyclictest3789-21df23:05:150
535499502cyclictest23512-21memory21:45:270
535499502cyclictest23512-21memory21:45:270
535499502cyclictest12196-21ssh23:20:160
535499502cyclictest12196-21ssh23:20:160
535499502cyclictest12196-21ssh23:20:160
535499501cyclictest9687-21meminfo23:15:250
535499501cyclictest9687-21meminfo23:15:250
535499501cyclictest9687-21meminfo23:15:250
535499501cyclictest17683-21df_abs20:00:160
535499501cyclictest17683-21df_abs20:00:160
535499493cyclictest0-21swapper/023:59:440
535499493cyclictest0-21swapper/023:59:440
535499493cyclictest0-21swapper/023:59:440
535499493cyclictest0-21swapper/023:46:350
535499493cyclictest0-21swapper/023:46:350
535499493cyclictest0-21swapper/023:14:150
535499493cyclictest0-21swapper/023:14:150
535499493cyclictest0-21swapper/022:25:260
535499493cyclictest0-21swapper/022:25:260
535499493cyclictest0-21swapper/019:55:230
535499493cyclictest0-21swapper/019:55:230
535499493cyclictest0-21swapper/019:50:250
535499493cyclictest0-21swapper/019:50:250
535499493cyclictest0-21swapper/019:20:190
535499493cyclictest0-21swapper/019:20:190
535499493cyclictest0-21swapper/000:37:280
535499493cyclictest0-21swapper/000:37:280
535499492cyclictest32079-21ntp_states22:00:250
535499492cyclictest32079-21ntp_states22:00:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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