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2026-02-02 - 12:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Feb 02, 2026 00:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71680rcu_preempt0-21swapper/122:01:451
71680rcu_preempt0-21swapper/122:01:451
71680rcu_preempt0-21swapper/122:01:451
71610rcu_preempt0-21swapper/200:22:242
71610rcu_preempt0-21swapper/200:22:242
71560rcu_preempt0-21swapper/219:41:032
71560rcu_preempt0-21swapper/219:41:032
71560rcu_preempt0-21swapper/219:41:032
71530rcu_preempt0-21swapper/121:41:071
71530rcu_preempt0-21swapper/121:41:071
71500rcu_preempt0-21swapper/221:41:302
71500rcu_preempt0-21swapper/221:41:302
71490rcu_preempt0-21swapper/123:46:091
71490rcu_preempt0-21swapper/123:46:091
71480rcu_preempt0-21swapper/120:13:191
71480rcu_preempt0-21swapper/120:13:191
71460rcu_preempt0-21swapper/221:40:292
71460rcu_preempt0-21swapper/221:40:292
71460rcu_preempt0-21swapper/221:40:292
71460rcu_preempt0-21swapper/122:41:591
71460rcu_preempt0-21swapper/122:41:591
71460rcu_preempt0-21swapper/100:21:151
71460rcu_preempt0-21swapper/100:21:151
71450rcu_preempt0-21swapper/223:48:442
71450rcu_preempt0-21swapper/223:48:442
71450rcu_preempt0-21swapper/019:07:010
71450rcu_preempt0-21swapper/019:07:010
46050450irq/122-QManpo29257-210
46050450irq/122-QManpo29257-210
46050450irq/122-QManpo29257-210
71440rcu_preempt32147-21apt-get23:01:112
71440rcu_preempt32147-21apt-get23:01:112
71440rcu_preempt10103-1kworker/1:1H19:41:141
71440rcu_preempt10103-1kworker/1:1H19:41:141
71440rcu_preempt0-21swapper/322:23:353
71440rcu_preempt0-21swapper/322:23:353
71440rcu_preempt0-21swapper/021:36:360
71440rcu_preempt0-21swapper/021:36:360
71440rcu_preempt0-21swapper/021:36:360
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
213399442cyclictest819-21diskstats22:06:173
213399442cyclictest819-21diskstats22:06:173
213399442cyclictest819-21diskstats22:06:173
213399442cyclictest12186-21irqstats21:26:213
213399442cyclictest12186-21irqstats21:26:213
213399442cyclictest12186-21irqstats21:26:213
213399441cyclictest8093-21ssh22:18:293
213399441cyclictest8093-21ssh22:18:293
71430rcu_preempt10454-21copy19:41:193
71430rcu_preempt10454-21copy19:41:193
71430rcu_preempt0-21swapper/322:00:293
71430rcu_preempt0-21swapper/322:00:293
71430rcu_preempt0-21swapper/223:41:202
71430rcu_preempt0-21swapper/223:41:202
71430rcu_preempt0-21swapper/223:41:202
71430rcu_preempt0-21swapper/022:51:100
71430rcu_preempt0-21swapper/022:51:100
213399432cyclictest5180-21df19:21:143
213399432cyclictest5180-21df19:21:143
71420rcu_preempt29975-21kworker/3:023:58:443
71420rcu_preempt29975-21kworker/3:023:58:443
71420rcu_preempt29975-21kworker/3:023:58:443
71420rcu_preempt0-21swapper/323:22:293
71420rcu_preempt0-21swapper/323:22:293
71420rcu_preempt0-21swapper/322:56:043
71420rcu_preempt0-21swapper/322:56:043
71420rcu_preempt0-21swapper/200:15:472
71420rcu_preempt0-21swapper/200:15:472
71420rcu_preempt0-21swapper/100:01:121
71420rcu_preempt0-21swapper/100:01:121
71420rcu_preempt0-21swapper/100:01:121
213399423cyclictest0-21swapper/319:26:263
213399423cyclictest0-21swapper/319:26:263
213399422cyclictest3535-21irqstats21:11:193
213399422cyclictest3535-21irqstats21:11:193
213399422cyclictest3535-21irqstats21:11:193
2133994222cyclictest0-21swapper/322:30:593
2133994222cyclictest0-21swapper/322:30:593
213399421cyclictest1959-21runrttasks19:12:563
213399421cyclictest1959-21runrttasks19:12:563
71410rcu_preempt1659-21latency_hist21:06:031
71410rcu_preempt1659-21latency_hist21:06:031
71410rcu_preempt0-21swapper/322:41:533
71410rcu_preempt0-21swapper/322:41:533
71410rcu_preempt0-21swapper/321:44:053
71410rcu_preempt0-21swapper/321:44:053
71410rcu_preempt0-21swapper/223:21:332
71410rcu_preempt0-21swapper/223:21:332
71410rcu_preempt0-21swapper/223:15:132
71410rcu_preempt0-21swapper/223:15:132
71410rcu_preempt0-21swapper/221:32:092
71410rcu_preempt0-21swapper/221:32:092
71410rcu_preempt0-21swapper/221:32:092
71410rcu_preempt0-21swapper/200:04:032
71410rcu_preempt0-21swapper/200:04:032
71410rcu_preempt0-21swapper/200:04:032
71410rcu_preempt0-21swapper/123:21:401
71410rcu_preempt0-21swapper/123:21:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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