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2026-01-24 - 11:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Jan 24, 2026 00:43:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71770rcu_preempt0-21swapper/322:18:023
71770rcu_preempt0-21swapper/322:18:023
71770rcu_preempt0-21swapper/322:18:023
71770rcu_preempt0-21swapper/021:46:490
71770rcu_preempt0-21swapper/021:46:490
71650rcu_preempt0-21swapper/123:57:021
71650rcu_preempt0-21swapper/123:57:021
71650rcu_preempt0-21swapper/123:57:021
71610rcu_preempt0-21swapper/000:03:270
71610rcu_preempt0-21swapper/000:03:270
71540rcu_preempt0-21swapper/023:52:030
71540rcu_preempt0-21swapper/023:52:030
1599480migration/024949-21taskset19:09:550
1599480migration/024949-21taskset19:09:550
2507799464cyclictest0-21swapper/122:05:361
2507799464cyclictest0-21swapper/122:05:361
2507799453cyclictest0-21swapper/121:00:491
2507799453cyclictest0-21swapper/121:00:491
2507799453cyclictest0-21swapper/121:00:491
2507799452cyclictest17600-21munin-run20:40:501
2507799452cyclictest17600-21munin-run20:40:501
71440rcu_preempt0-21swapper/323:01:003
71440rcu_preempt0-21swapper/323:01:003
2507799443cyclictest0-21swapper/123:06:001
2507799443cyclictest0-21swapper/123:06:001
2507799443cyclictest0-21swapper/123:06:001
2507799443cyclictest0-21swapper/122:26:201
2507799443cyclictest0-21swapper/122:26:201
2507799442cyclictest31346-21irqstats22:16:081
2507799442cyclictest31346-21irqstats22:16:081
2507799442cyclictest31346-21irqstats22:16:081
2507799442cyclictest15321-21irqstats23:41:111
2507799442cyclictest15321-21irqstats23:41:111
2507799442cyclictest13301-21sshd23:36:591
2507799442cyclictest13301-21sshd23:36:591
2507799441cyclictest1959-21runrttasks21:36:171
2507799441cyclictest1959-21runrttasks21:36:171
2507799441cyclictest1959-21runrttasks21:36:171
25077994417cyclictest12618-21meminfo20:21:111
25077994417cyclictest12618-21meminfo20:21:111
71430rcu_preempt15811-21/usr/sbin/munin22:46:000
71430rcu_preempt15811-21/usr/sbin/munin22:46:000
71430rcu_preempt0-21swapper/022:32:210
71430rcu_preempt0-21swapper/022:32:210
71430rcu_preempt0-21swapper/022:32:210
2507799434cyclictest0-21swapper/119:46:161
2507799434cyclictest0-21swapper/119:46:161
2507799434cyclictest0-21swapper/100:40:551
2507799434cyclictest0-21swapper/100:40:551
2507799434cyclictest0-21swapper/100:34:261
2507799434cyclictest0-21swapper/100:34:261
2507799433cyclictest6908-21diskstats20:01:041
2507799433cyclictest6908-21diskstats20:01:041
2507799433cyclictest0-21swapper/123:01:141
2507799433cyclictest0-21swapper/123:01:141
2507799433cyclictest0-21swapper/123:00:371
2507799433cyclictest0-21swapper/123:00:371
2507799433cyclictest0-21swapper/122:55:151
2507799433cyclictest0-21swapper/122:55:151
2507799433cyclictest0-21swapper/121:55:151
2507799433cyclictest0-21swapper/121:55:151
2507799433cyclictest0-21swapper/121:55:151
2507799433cyclictest0-21swapper/121:01:031
2507799433cyclictest0-21swapper/121:01:031
2507799433cyclictest0-21swapper/121:01:031
2507799433cyclictest0-21swapper/119:45:481
2507799433cyclictest0-21swapper/119:45:481
2507799433cyclictest0-21swapper/119:45:481
2507799433cyclictest0-21swapper/119:33:431
2507799433cyclictest0-21swapper/119:33:431
2507799433cyclictest0-21swapper/119:16:111
2507799433cyclictest0-21swapper/119:16:111
2507799433cyclictest0-21swapper/100:16:171
2507799433cyclictest0-21swapper/100:16:171
2507799433cyclictest0-21swapper/100:16:171
2507799432cyclictest5711-21diskstats00:21:051
2507799432cyclictest5711-21diskstats00:21:051
2507799432cyclictest5711-21diskstats00:21:051
2507799432cyclictest29193-21/usr/sbin/munin00:06:101
2507799432cyclictest29193-21/usr/sbin/munin00:06:101
2507799432cyclictest11565-21ntp_states21:41:141
2507799432cyclictest11565-21ntp_states21:41:141
2507799432cyclictest11565-21ntp_states21:41:141
71420rcu_preempt0-21swapper/320:55:593
71420rcu_preempt0-21swapper/320:55:593
71420rcu_preempt0-21swapper/320:55:593
2507799424cyclictest0-21swapper/122:46:181
2507799424cyclictest0-21swapper/122:46:181
2507799423cyclictest0-21swapper/123:15:021
2507799423cyclictest0-21swapper/123:15:021
2507799423cyclictest0-21swapper/123:15:021
2507799423cyclictest0-21swapper/122:41:141
2507799423cyclictest0-21swapper/122:41:141
2507799423cyclictest0-21swapper/122:40:531
2507799423cyclictest0-21swapper/122:40:531
2507799423cyclictest0-21swapper/122:11:151
2507799423cyclictest0-21swapper/122:11:151
2507799423cyclictest0-21swapper/100:01:131
2507799423cyclictest0-21swapper/100:01:131
2507799422cyclictest32258-21ssh00:11:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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