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2026-05-28 - 04:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu May 28, 2026 00:44:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285892790chrt46050irq/122-QMan10:48:550
285892790chrt46050irq/122-QMan10:48:550
285892790chrt46050irq/122-QMan10:48:550
71470rcu_preempt0-21swapper/020:33:140
71470rcu_preempt0-21swapper/020:33:140
71460rcu_preempt0-21swapper/323:45:573
71460rcu_preempt0-21swapper/323:45:573
71460rcu_preempt0-21swapper/323:45:573
71450rcu_preempt12709-21ssh22:53:261
71450rcu_preempt12709-21ssh22:53:261
71450rcu_preempt0-21swapper/021:29:570
71450rcu_preempt0-21swapper/021:29:570
46050430irq/122-QManpo21826-2110:48:550
46050430irq/122-QManpo21826-2110:48:550
46050430irq/122-QManpo21826-2110:48:550
46050430irq/122-QManpo21826-2110:48:550
71420rcu_preempt0-21swapper/023:24:130
71420rcu_preempt0-21swapper/023:24:130
71420rcu_preempt0-21swapper/022:55:100
71420rcu_preempt0-21swapper/022:55:100
71410rcu_preempt7480-1kworker/2:1H23:53:062
71410rcu_preempt7480-1kworker/2:1H23:53:062
71410rcu_preempt7480-1kworker/2:1H23:53:062
71410rcu_preempt7480-1kworker/2:1H23:53:062
71410rcu_preempt0-21swapper/021:50:180
71410rcu_preempt0-21swapper/021:50:180
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
71400rcu_preempt21856-1kworker/0:1H21:13:340
71400rcu_preempt21856-1kworker/0:1H21:13:340
71400rcu_preempt0-21swapper/023:29:290
71400rcu_preempt0-21swapper/023:29:290
71400rcu_preempt0-21swapper/023:29:290
71400rcu_preempt0-21swapper/022:09:230
71400rcu_preempt0-21swapper/022:09:230
71400rcu_preempt0-21swapper/022:09:230
71400rcu_preempt0-21swapper/022:04:070
71400rcu_preempt0-21swapper/022:04:070
71400rcu_preempt0-21swapper/022:04:070
71390rcu_preempt6410-1latency_hist23:43:161
71390rcu_preempt18162-21sh00:04:230
71390rcu_preempt18162-21sh00:04:230
71390rcu_preempt0-21swapper/023:59:240
71390rcu_preempt0-21swapper/023:59:240
71390rcu_preempt0-21swapper/022:28:570
71390rcu_preempt0-21swapper/022:28:570
71390rcu_preempt0-21swapper/021:54:410
71390rcu_preempt0-21swapper/021:54:410
71390rcu_preempt0-21swapper/000:12:540
71390rcu_preempt0-21swapper/000:12:540
71390rcu_preempt0-21swapper/000:12:540
46050390irq/122-QManpo22647-10
46050390irq/122-QManpo22647-10
100650390irq/38-i2c-mpc1958-21snmpd23:17:042
100650390irq/38-i2c-mpc1958-21snmpd23:17:042
71380rcu_preempt6230-21cron23:43:071
71380rcu_preempt6230-21cron23:43:071
71380rcu_preempt23817-21ssh23:13:350
71380rcu_preempt23817-21ssh23:13:350
71380rcu_preempt0-21swapper/122:38:091
71380rcu_preempt0-21swapper/122:38:091
71380rcu_preempt0-21swapper/121:08:301
71380rcu_preempt0-21swapper/121:08:301
71380rcu_preempt0-21swapper/121:08:301
71380rcu_preempt0-21swapper/022:46:300
71380rcu_preempt0-21swapper/022:46:300
71380rcu_preempt0-21swapper/022:35:550
71380rcu_preempt0-21swapper/022:35:550
71380rcu_preempt0-21swapper/022:14:220
71380rcu_preempt0-21swapper/022:14:220
71380rcu_preempt0-21swapper/022:14:220
71380rcu_preempt0-21swapper/019:29:370
71380rcu_preempt0-21swapper/019:29:370
71380rcu_preempt0-21swapper/000:23:090
71380rcu_preempt0-21swapper/000:23:090
71380rcu_preempt0-21swapper/000:23:090
46050380irq/122-QManpo9662-2110:48:550
46050380irq/122-QManpo9662-2110:48:550
46050380irq/122-QManpo9662-2110:48:550
1599380migration/01677-21latency23:33:250
1599380migration/01677-21latency23:33:250
71370rcu_preempt0-21swapper/223:26:462
71370rcu_preempt0-21swapper/223:26:462
71370rcu_preempt0-21swapper/121:43:161
71370rcu_preempt0-21swapper/121:43:161
71370rcu_preempt0-21swapper/121:43:161
71370rcu_preempt0-21swapper/100:41:171
71370rcu_preempt0-21swapper/100:41:171
71370rcu_preempt0-21swapper/100:06:211
71370rcu_preempt0-21swapper/100:06:211
71370rcu_preempt0-21swapper/022:59:040
71370rcu_preempt0-21swapper/022:59:040
71370rcu_preempt0-21swapper/022:59:040
71370rcu_preempt0-21swapper/021:43:320
71370rcu_preempt0-21swapper/021:43:320
71370rcu_preempt0-21swapper/021:43:320
71370rcu_preempt0-21swapper/020:26:060
71370rcu_preempt0-21swapper/020:26:060
71370rcu_preempt0-21swapper/020:26:060
71370rcu_preempt0-21swapper/000:24:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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