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2026-04-15 - 17:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Apr 15, 2026 12:44:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71630rcu_preempt0-21swapper/011:42:300
71630rcu_preempt0-21swapper/011:42:300
1830299523cyclictest0-21swapper/009:19:110
1830299523cyclictest0-21swapper/009:19:110
46050510irq/122-QManpo18190-2110:48:550
46050510irq/122-QManpo18190-2110:48:550
46050510irq/122-QManpo18190-2110:48:550
1830299514cyclictest0-21swapper/009:46:550
1830299514cyclictest0-21swapper/009:46:550
1830299514cyclictest0-21swapper/009:46:550
1830299513cyclictest0-21swapper/010:53:280
1830299513cyclictest0-21swapper/010:53:280
18302995118cyclictest0-21swapper/009:24:360
18302995118cyclictest0-21swapper/009:24:360
18302995118cyclictest0-21swapper/009:24:360
18302995118cyclictest0-21swapper/007:27:400
18302995118cyclictest0-21swapper/007:27:400
18302995118cyclictest0-21swapper/007:27:400
1830299502cyclictest30124-21sed11:27:490
1830299502cyclictest30124-21sed11:27:490
18302995017cyclictest0-21swapper/011:17:470
18302995017cyclictest0-21swapper/011:17:470
18302995017cyclictest0-21swapper/010:37:380
18302995017cyclictest0-21swapper/010:37:380
1830299493cyclictest0-21swapper/012:03:200
1830299493cyclictest0-21swapper/012:03:200
1830299493cyclictest0-21swapper/011:56:380
1830299493cyclictest0-21swapper/011:56:380
1830299493cyclictest0-21swapper/011:50:040
1830299493cyclictest0-21swapper/011:50:040
1830299493cyclictest0-21swapper/010:43:420
1830299493cyclictest0-21swapper/010:43:420
1830299493cyclictest0-21swapper/010:43:420
1830299493cyclictest0-21swapper/009:52:400
1830299493cyclictest0-21swapper/009:52:400
18302994917cyclictest0-21swapper/008:48:110
18302994917cyclictest0-21swapper/008:48:110
1830299484cyclictest0-21swapper/012:02:210
1830299484cyclictest0-21swapper/012:02:210
1830299483cyclictest0-21swapper/012:07:400
1830299483cyclictest0-21swapper/012:07:400
1830299483cyclictest0-21swapper/011:14:510
1830299483cyclictest0-21swapper/011:14:510
1830299483cyclictest0-21swapper/011:14:510
1830299483cyclictest0-21swapper/010:21:190
1830299483cyclictest0-21swapper/010:21:190
1830299483cyclictest0-21swapper/010:04:160
1830299483cyclictest0-21swapper/010:04:160
1830299483cyclictest0-21swapper/010:04:160
18302994817cyclictest0-21swapper/008:22:200
18302994817cyclictest0-21swapper/008:22:200
18302994817cyclictest0-21swapper/008:22:200
1830299473cyclictest0-21swapper/011:12:190
1830299473cyclictest0-21swapper/011:12:190
1830299464cyclictest0-21swapper/012:12:490
1830299464cyclictest0-21swapper/012:12:490
1830299464cyclictest0-21swapper/010:08:450
1830299464cyclictest0-21swapper/010:08:450
1830299464cyclictest0-21swapper/010:08:450
1830299464cyclictest0-21swapper/010:08:450
1830299463cyclictest0-21swapper/011:02:310
1830299463cyclictest0-21swapper/011:02:310
1830299463cyclictest0-21swapper/011:02:310
1830299463cyclictest0-21swapper/010:50:240
1830299463cyclictest0-21swapper/010:50:240
1830299463cyclictest0-21swapper/010:50:240
1830299461cyclictest0-21swapper/007:42:450
1830299461cyclictest0-21swapper/007:42:450
1830299461cyclictest0-21swapper/007:42:450
71440rcu_preempt0-21swapper/012:41:280
71440rcu_preempt0-21swapper/012:41:280
71440rcu_preempt0-21swapper/009:07:300
71440rcu_preempt0-21swapper/009:07:300
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
71430rcu_preempt0-21swapper/310:22:323
71430rcu_preempt0-21swapper/310:22:323
71430rcu_preempt0-21swapper/310:22:323
71420rcu_preempt0-21swapper/010:23:200
71420rcu_preempt0-21swapper/010:23:200
71420rcu_preempt0-21swapper/010:23:200
71420rcu_preempt0-21swapper/007:22:550
71420rcu_preempt0-21swapper/007:22:550
71410rcu_preempt0-21swapper/112:14:321
71410rcu_preempt0-21swapper/112:14:321
46450410irq/118-QManpo16932-212
46450410irq/118-QManpo16932-212
46450410irq/118-QManpo16932-212
71400rcu_preempt24974-21sendmail-msp09:22:501
71400rcu_preempt24974-21sendmail-msp09:22:501
71400rcu_preempt24974-21sendmail-msp09:22:501
71400rcu_preempt0-21swapper/110:23:471
71400rcu_preempt0-21swapper/110:23:471
71400rcu_preempt0-21swapper/110:23:471
71400rcu_preempt0-21swapper/009:37:310
71400rcu_preempt0-21swapper/009:37:310
71390rcu_preempt23734-21/usr/sbin/munin11:17:451
71390rcu_preempt23734-21/usr/sbin/munin11:17:451
71390rcu_preempt0-21swapper/111:03:171
71390rcu_preempt0-21swapper/111:03:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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