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2026-04-21 - 11:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Apr 21, 2026 00:44:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71670rcu_preempt0-21swapper/022:13:400
71670rcu_preempt0-21swapper/022:13:400
71600rcu_preempt0-21swapper/222:28:282
71600rcu_preempt0-21swapper/222:28:282
71600rcu_preempt0-21swapper/222:28:282
71600rcu_preempt0-21swapper/222:28:282
71470rcu_preempt0-21swapper/219:42:362
71470rcu_preempt0-21swapper/219:42:362
71470rcu_preempt0-21swapper/219:42:362
71460rcu_preempt0-21swapper/219:32:412
71460rcu_preempt0-21swapper/219:32:412
322252440sleep023132-1kworker/0:2H19:08:020
322252440sleep023132-1kworker/0:2H19:08:020
71420rcu_preempt6328-21/usr/sbin/munin19:32:473
71420rcu_preempt6328-21/usr/sbin/munin19:32:473
71420rcu_preempt29751-21sendmail-msp23:12:031
71420rcu_preempt29751-21sendmail-msp23:12:031
71420rcu_preempt29751-21sendmail-msp23:12:031
71410rcu_preempt11286-21sh00:26:452
71410rcu_preempt11286-21sh00:26:452
71410rcu_preempt11286-21sh00:26:452
2299410migration/232262-21taskset19:08:312
2299410migration/232262-21taskset19:08:312
71400rcu_preempt367-1/usr/sbin/munin22:07:572
71400rcu_preempt367-1/usr/sbin/munin22:07:572
71400rcu_preempt0-21swapper/223:52:502
71400rcu_preempt0-21swapper/223:52:502
71400rcu_preempt0-21swapper/221:05:242
71400rcu_preempt0-21swapper/221:05:242
71400rcu_preempt0-21swapper/123:27:151
71400rcu_preempt0-21swapper/123:27:151
71400rcu_preempt0-21swapper/123:27:151
71400rcu_preempt0-21swapper/119:45:521
71400rcu_preempt0-21swapper/119:45:521
71400rcu_preempt0-21swapper/119:45:521
1599400migration/09080-21latency19:42:480
1599400migration/09080-21latency19:42:480
1599400migration/09080-21latency19:42:480
71390rcu_preempt0-21swapper/121:27:011
71390rcu_preempt0-21swapper/121:27:011
71390rcu_preempt0-21swapper/121:27:011
46050390irq/122-QManpo19931-2110:48:550
46050390irq/122-QManpo19931-2110:48:550
2899390migration/332526-21taskset19:11:503
2899390migration/332526-21taskset19:11:503
71380rcu_preempt21010-21sh22:46:212
71380rcu_preempt21010-21sh22:46:212
71380rcu_preempt21010-21sh22:46:212
71380rcu_preempt0-21swapper/320:47:453
71380rcu_preempt0-21swapper/320:47:453
71380rcu_preempt0-21swapper/222:49:182
71380rcu_preempt0-21swapper/222:49:182
71380rcu_preempt0-21swapper/222:49:182
71380rcu_preempt0-21swapper/221:28:422
71380rcu_preempt0-21swapper/221:28:422
71380rcu_preempt0-21swapper/200:27:372
71380rcu_preempt0-21swapper/200:27:372
71380rcu_preempt0-21swapper/200:27:372
71380rcu_preempt0-21swapper/121:47:381
71380rcu_preempt0-21swapper/121:47:381
71380rcu_preempt0-21swapper/121:47:381
71380rcu_preempt0-21swapper/119:12:311
71380rcu_preempt0-21swapper/119:12:311
71380rcu_preempt0-21swapper/000:32:370
71380rcu_preempt0-21swapper/000:32:370
46450380irq/118-QManpo2145-212
46450380irq/118-QManpo2145-212
46050380irq/122-QManpo4758-2110:48:550
46050380irq/122-QManpo4758-2110:48:550
46050380irq/122-QManpo29232-2110:48:550
46050380irq/122-QManpo29232-2110:48:550
46050380irq/122-QManpo29232-2110:48:550
46050380irq/122-QManpo23505-2110:48:550
46050380irq/122-QManpo23505-2110:48:550
46050380irq/122-QManpo16933-2110:48:550
46050380irq/122-QManpo16933-2110:48:550
46050380irq/122-QManpo16933-2110:48:550
71370rcu_preempt1593-21unixbench_multi00:07:552
71370rcu_preempt1593-21unixbench_multi00:07:552
71370rcu_preempt10648-21sh00:24:491
71370rcu_preempt10648-21sh00:24:491
71370rcu_preempt10648-21sh00:24:491
71370rcu_preempt0-21swapper/223:57:442
71370rcu_preempt0-21swapper/223:57:442
71370rcu_preempt0-21swapper/223:28:232
71370rcu_preempt0-21swapper/223:28:232
71370rcu_preempt0-21swapper/221:43:052
71370rcu_preempt0-21swapper/221:43:052
71370rcu_preempt0-21swapper/221:22:362
71370rcu_preempt0-21swapper/221:22:362
71370rcu_preempt0-21swapper/221:22:362
71370rcu_preempt0-21swapper/123:48:451
71370rcu_preempt0-21swapper/123:48:451
71370rcu_preempt0-21swapper/123:30:431
71370rcu_preempt0-21swapper/123:30:431
71370rcu_preempt0-21swapper/122:49:581
71370rcu_preempt0-21swapper/122:49:581
71370rcu_preempt0-21swapper/122:49:581
71370rcu_preempt0-21swapper/122:17:451
71370rcu_preempt0-21swapper/122:17:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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