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2026-04-12 - 10:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Apr 12, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71700rcu_preempt0-21swapper/222:59:052
71700rcu_preempt0-21swapper/222:59:052
71700rcu_preempt0-21swapper/222:59:052
71570rcu_preempt0-21swapper/123:24:121
71570rcu_preempt0-21swapper/123:24:121
71520rcu_preempt0-21swapper/223:22:202
71520rcu_preempt0-21swapper/223:22:202
71510rcu_preempt0-21swapper/122:23:181
71510rcu_preempt0-21swapper/122:23:181
71510rcu_preempt0-21swapper/122:23:181
71510rcu_preempt0-21swapper/021:13:350
71510rcu_preempt0-21swapper/021:13:350
46050490irq/122-QManpo25850-2110:48:550
46050490irq/122-QManpo25850-2110:48:550
2595699473cyclictest0-21swapper/221:37:072
2595699473cyclictest0-21swapper/221:37:072
2595699473cyclictest0-21swapper/221:37:072
2595699473cyclictest0-21swapper/200:18:532
2595699473cyclictest0-21swapper/200:18:532
2595699473cyclictest0-21swapper/200:18:532
71460rcu_preempt0-21swapper/100:12:351
71460rcu_preempt0-21swapper/100:12:351
71440rcu_preempt0-21swapper/000:24:400
71440rcu_preempt0-21swapper/000:24:400
71440rcu_preempt0-21swapper/000:24:400
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
2595699443cyclictest8815-21users00:32:472
2595699443cyclictest8815-21users00:32:472
2595699443cyclictest0-21swapper/220:37:462
2595699443cyclictest0-21swapper/220:37:462
2595699443cyclictest0-21swapper/220:37:462
2595699442cyclictest26842-21munin-run21:12:172
2595699442cyclictest26842-21munin-run21:12:172
2595699442cyclictest26842-21munin-run21:12:172
71430rcu_preempt3350-1sh21:27:341
71430rcu_preempt3350-1sh21:27:341
71430rcu_preempt20325-1kworker/0:1H22:02:230
71430rcu_preempt14009-1kworker/1:0H20:25:511
71430rcu_preempt14009-1kworker/1:0H20:25:511
71430rcu_preempt0-21swapper/019:27:460
71430rcu_preempt0-21swapper/019:27:460
2595699434cyclictest0-21swapper/221:25:222
2595699434cyclictest0-21swapper/221:25:222
2595699434cyclictest0-21swapper/221:25:222
2595699433cyclictest6587-21meminfo22:32:382
2595699433cyclictest6587-21meminfo22:32:382
2595699433cyclictest0-21swapper/223:42:492
2595699433cyclictest0-21swapper/223:42:492
2595699433cyclictest0-21swapper/223:42:492
2595699432cyclictest17801-21ntp_states22:52:412
2595699432cyclictest17801-21ntp_states22:52:412
2595699432cyclictest17801-21ntp_states22:52:412
71420rcu_preempt0-21swapper/022:35:230
71420rcu_preempt0-21swapper/022:35:230
2595699425cyclictest0-21swapper/223:30:002
2595699425cyclictest0-21swapper/223:30:002
2595699424cyclictest0-21swapper/223:33:102
2595699424cyclictest0-21swapper/223:33:102
2595699424cyclictest0-21swapper/223:33:102
2595699423cyclictest0-21swapper/222:50:072
2595699423cyclictest0-21swapper/222:50:072
2595699423cyclictest0-21swapper/222:50:072
2595699423cyclictest0-21swapper/222:28:582
2595699423cyclictest0-21swapper/222:28:582
2595699423cyclictest0-21swapper/221:57:372
2595699423cyclictest0-21swapper/221:57:372
2595699423cyclictest0-21swapper/221:12:302
2595699423cyclictest0-21swapper/221:12:302
2595699423cyclictest0-21swapper/220:23:222
2595699423cyclictest0-21swapper/220:23:222
2595699422cyclictest29702-21/usr/sbin/munin00:12:402
2595699422cyclictest29702-21/usr/sbin/munin00:12:402
2595699422cyclictest16556-21ssh23:48:222
2595699422cyclictest16556-21ssh23:48:222
2595699422cyclictest14979-21ntp_states20:27:422
2595699422cyclictest14979-21ntp_states20:27:422
71410rcu_preempt5633-21taskset23:28:490
71410rcu_preempt5633-21taskset23:28:490
71410rcu_preempt20929-21timerandwakeup22:57:470
71410rcu_preempt20929-21timerandwakeup22:57:470
71410rcu_preempt20929-21timerandwakeup22:57:470
71410rcu_preempt12568-21munin-run23:42:152
71410rcu_preempt12568-21munin-run23:42:152
71410rcu_preempt0-21swapper/323:22:243
71410rcu_preempt0-21swapper/323:22:243
71410rcu_preempt0-21swapper/123:59:401
71410rcu_preempt0-21swapper/123:59:401
71410rcu_preempt0-21swapper/122:47:371
71410rcu_preempt0-21swapper/122:47:371
71410rcu_preempt0-21swapper/122:47:371
71410rcu_preempt0-21swapper/122:31:031
71410rcu_preempt0-21swapper/122:31:031
71410rcu_preempt0-21swapper/121:50:471
71410rcu_preempt0-21swapper/121:50:471
71410rcu_preempt0-21swapper/100:02:321
71410rcu_preempt0-21swapper/100:02:321
71410rcu_preempt0-21swapper/022:54:120
71410rcu_preempt0-21swapper/022:54:120
71410rcu_preempt0-21swapper/022:54:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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