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2026-06-27 - 12:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Jun 27, 2026 00:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71630rcu_preempt15504-21kworker/0:419:53:390
71630rcu_preempt15504-21kworker/0:419:53:390
71630rcu_preempt15504-21kworker/0:419:53:390
843299534cyclictest0-21swapper/000:27:380
843299534cyclictest0-21swapper/000:27:380
843299514cyclictest0-21swapper/022:46:020
843299514cyclictest0-21swapper/022:46:020
843299514cyclictest0-21swapper/022:46:020
843299514cyclictest0-21swapper/000:18:570
843299514cyclictest0-21swapper/000:18:570
843299514cyclictest0-21swapper/000:18:570
843599504cyclictest0-21swapper/321:48:493
843599504cyclictest0-21swapper/321:48:493
843599504cyclictest0-21swapper/321:48:493
71500rcu_preempt0-21swapper/022:03:300
71500rcu_preempt0-21swapper/022:03:300
71500rcu_preempt0-21swapper/022:03:300
843599482cyclictest11856-21meminfo00:23:563
843599482cyclictest11856-21meminfo00:23:563
8435994823cyclictest32205-21grep22:59:033
8435994823cyclictest32205-21grep22:59:033
8435994619cyclictest26306-21diskstats20:18:523
8435994619cyclictest26306-21diskstats20:18:523
8435994619cyclictest26306-21diskstats20:18:523
46050460irq/122-QManpo16294-2110:48:550
46050460irq/122-QManpo16294-2110:48:550
843599456cyclictest0-21swapper/300:16:443
843599456cyclictest0-21swapper/300:16:443
843599454cyclictest0-21swapper/300:10:243
843599454cyclictest0-21swapper/300:10:243
843599452cyclictest27479-21/usr/sbin/munin20:23:473
843599452cyclictest27479-21/usr/sbin/munin20:23:473
843599443cyclictest16463-21df19:43:513
843599443cyclictest16463-21df19:43:513
843599443cyclictest0-21swapper/323:43:493
843599443cyclictest0-21swapper/323:43:493
843599443cyclictest0-21swapper/323:28:543
843599443cyclictest0-21swapper/323:28:543
843599443cyclictest0-21swapper/323:04:003
843599443cyclictest0-21swapper/323:04:003
843599443cyclictest0-21swapper/323:04:003
843599434cyclictest0-21swapper/322:51:013
843599434cyclictest0-21swapper/322:51:013
843599434cyclictest0-21swapper/322:51:013
843599434cyclictest0-21swapper/321:14:013
843599434cyclictest0-21swapper/321:14:013
843599434cyclictest0-21swapper/321:14:013
843599431cyclictest13618-21/usr/sbin/munin22:23:553
843599431cyclictest13618-21/usr/sbin/munin22:23:553
843599431cyclictest13618-21/usr/sbin/munin22:23:553
8435994316cyclictest19199-21wget19:53:513
8435994316cyclictest19199-21wget19:53:513
8435994316cyclictest19199-21wget19:53:513
71430rcu_preempt0-21swapper/320:59:063
71430rcu_preempt0-21swapper/320:59:063
46050430irq/122-QManpo8162-2110:48:550
46050430irq/122-QManpo8162-2110:48:550
46050430irq/122-QManpo8162-2110:48:550
843599423cyclictest0-21swapper/323:26:133
843599423cyclictest0-21swapper/323:26:133
843599423cyclictest0-21swapper/323:26:133
843599423cyclictest0-21swapper/322:39:013
843599423cyclictest0-21swapper/322:39:013
843599423cyclictest0-21swapper/322:36:133
843599423cyclictest0-21swapper/322:36:133
843599423cyclictest0-21swapper/322:36:133
843599423cyclictest0-21swapper/321:54:003
843599423cyclictest0-21swapper/321:54:003
843599423cyclictest0-21swapper/321:54:003
843599423cyclictest0-21swapper/300:08:063
843599423cyclictest0-21swapper/300:08:063
843599423cyclictest0-21swapper/300:08:063
843599422cyclictest0-21swapper/300:42:093
843599422cyclictest0-21swapper/300:42:093
843599422cyclictest0-21swapper/300:42:093
8435994218cyclictest31281-21meminfo23:58:583
8435994218cyclictest31281-21meminfo23:58:583
8435994218cyclictest31281-21meminfo23:58:583
8435994217cyclictest6532-21irqstats21:03:583
8435994217cyclictest6532-21irqstats21:03:583
8435994217cyclictest6532-21irqstats21:03:583
71420rcu_preempt3549-21ntp_states22:04:020
71420rcu_preempt3549-21ntp_states22:04:020
71420rcu_preempt3549-21ntp_states22:04:020
71420rcu_preempt0-21swapper/119:38:461
71420rcu_preempt0-21swapper/119:38:461
71420rcu_preempt0-21swapper/022:18:420
71420rcu_preempt0-21swapper/022:18:420
46250420irq/120-QManpo8164-2110:48:551
46250420irq/120-QManpo8164-2110:48:551
46250420irq/120-QManpo8164-2110:48:551
843599419cyclictest3349-21/usr/sbin/munin22:03:573
843599419cyclictest3349-21/usr/sbin/munin22:03:573
843599419cyclictest3349-21/usr/sbin/munin22:03:573
843599414cyclictest0-21swapper/322:48:423
843599414cyclictest0-21swapper/322:48:423
843599414cyclictest0-21swapper/322:48:423
843599413cyclictest10985-21diskstats22:18:513
843599413cyclictest10985-21diskstats22:18:513
843599413cyclictest0-21swapper/323:57:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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