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2026-02-11 - 12:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Feb 11, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71550rcu_preempt0-21swapper/322:42:343
71550rcu_preempt0-21swapper/322:42:343
71500rcu_preempt0-21swapper/119:51:371
71500rcu_preempt0-21swapper/119:51:371
71500rcu_preempt0-21swapper/119:51:371
71500rcu_preempt0-21swapper/100:14:541
71500rcu_preempt0-21swapper/100:14:541
71490rcu_preempt0-21swapper/023:35:590
71490rcu_preempt0-21swapper/023:35:590
71490rcu_preempt0-21swapper/023:35:590
71460rcu_preempt0-21swapper/123:59:241
71460rcu_preempt0-21swapper/123:59:241
71460rcu_preempt0-21swapper/123:59:241
71460rcu_preempt0-21swapper/122:51:541
71460rcu_preempt0-21swapper/122:51:541
71460rcu_preempt0-21swapper/122:51:541
71460rcu_preempt0-21swapper/121:31:191
71460rcu_preempt0-21swapper/121:31:191
71460rcu_preempt0-21swapper/121:15:371
71460rcu_preempt0-21swapper/121:15:371
71460rcu_preempt0-21swapper/121:15:371
71450rcu_preempt12575-21sh22:21:561
71450rcu_preempt12575-21sh22:21:561
71450rcu_preempt0-21swapper/123:37:491
71450rcu_preempt0-21swapper/123:37:491
71450rcu_preempt0-21swapper/123:37:491
71450rcu_preempt0-21swapper/100:22:071
71450rcu_preempt0-21swapper/100:22:071
71450rcu_preempt0-21swapper/100:22:071
71440rcu_preempt5585-21crond22:11:091
71440rcu_preempt5585-21crond22:11:091
71440rcu_preempt5585-21crond22:11:091
71440rcu_preempt24980-21crond20:31:091
71440rcu_preempt24980-21crond20:31:091
71440rcu_preempt13139-21ssh21:26:402
71440rcu_preempt13139-21ssh21:26:402
71440rcu_preempt11368-1kworker/1:2H22:31:201
71440rcu_preempt11368-1kworker/1:2H22:31:201
71440rcu_preempt0-21swapper/123:21:111
71440rcu_preempt0-21swapper/123:21:111
71440rcu_preempt0-21swapper/123:21:111
71440rcu_preempt0-21swapper/122:42:511
71440rcu_preempt0-21swapper/122:42:511
71430rcu_preempt3703-21diskmemload22:15:391
71430rcu_preempt3703-21diskmemload22:15:391
71430rcu_preempt3703-21diskmemload22:15:391
71430rcu_preempt0-21swapper/222:24:172
71430rcu_preempt0-21swapper/222:24:172
71430rcu_preempt0-21swapper/121:06:281
71430rcu_preempt0-21swapper/121:06:281
71430rcu_preempt0-21swapper/121:06:281
71430rcu_preempt0-21swapper/100:06:391
71430rcu_preempt0-21swapper/100:06:391
71430rcu_preempt0-21swapper/100:06:391
71430rcu_preempt0-21swapper/100:02:191
71430rcu_preempt0-21swapper/100:02:191
71420rcu_preempt21081-21/usr/sbin/munin21:41:191
71420rcu_preempt21081-21/usr/sbin/munin21:41:191
71420rcu_preempt0-21swapper/223:31:322
71420rcu_preempt0-21swapper/223:31:322
71420rcu_preempt0-21swapper/223:31:322
71420rcu_preempt0-21swapper/222:33:532
71420rcu_preempt0-21swapper/222:33:532
71420rcu_preempt0-21swapper/123:54:351
71420rcu_preempt0-21swapper/123:54:351
71420rcu_preempt0-21swapper/123:06:411
71420rcu_preempt0-21swapper/123:06:411
71420rcu_preempt0-21swapper/122:03:071
71420rcu_preempt0-21swapper/122:03:071
71420rcu_preempt0-21swapper/122:03:071
71420rcu_preempt0-21swapper/121:24:071
71420rcu_preempt0-21swapper/121:24:071
71410rcu_preempt20965-21latency_hist21:41:121
71410rcu_preempt20965-21latency_hist21:41:121
71410rcu_preempt20965-21latency_hist21:41:121
71410rcu_preempt0-21swapper/221:56:402
71410rcu_preempt0-21swapper/221:56:402
71410rcu_preempt0-21swapper/221:56:402
71410rcu_preempt0-21swapper/123:02:421
71410rcu_preempt0-21swapper/123:02:421
71410rcu_preempt0-21swapper/122:17:261
71410rcu_preempt0-21swapper/122:17:261
71410rcu_preempt0-21swapper/122:17:261
71410rcu_preempt0-21swapper/122:01:141
71410rcu_preempt0-21swapper/122:01:141
71410rcu_preempt0-21swapper/122:01:141
71410rcu_preempt0-21swapper/121:47:381
71410rcu_preempt0-21swapper/121:47:381
71410rcu_preempt0-21swapper/121:47:381
71410rcu_preempt0-21swapper/121:29:291
71410rcu_preempt0-21swapper/121:29:291
71410rcu_preempt0-21swapper/121:19:301
71410rcu_preempt0-21swapper/121:19:301
71410rcu_preempt0-21swapper/120:51:141
71410rcu_preempt0-21swapper/120:51:141
71410rcu_preempt0-21swapper/119:21:181
71410rcu_preempt0-21swapper/119:21:181
71410rcu_preempt0-21swapper/100:37:521
71410rcu_preempt0-21swapper/100:37:521
71410rcu_preempt0-21swapper/100:37:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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