You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-19 - 18:50
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Dec 19, 2025 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71690rcu_preempt0-21swapper/010:28:110
71690rcu_preempt0-21swapper/010:28:110
71670rcu_preempt0-21swapper/310:02:453
71670rcu_preempt0-21swapper/310:02:453
71630rcu_preempt20150-1kworker/0:1H09:05:190
71630rcu_preempt20150-1kworker/0:1H09:05:190
71620rcu_preempt0-21swapper/112:32:131
71620rcu_preempt0-21swapper/112:32:131
71620rcu_preempt0-21swapper/110:43:341
71620rcu_preempt0-21swapper/110:43:341
71620rcu_preempt0-21swapper/110:43:341
71590rcu_preempt0-21swapper/110:05:541
71590rcu_preempt0-21swapper/110:05:541
71590rcu_preempt0-21swapper/110:05:541
1599480migration/022276-21taskset07:10:010
1599480migration/022276-21taskset07:10:010
71470rcu_preempt25589-21copy10:10:221
71470rcu_preempt25589-21copy10:10:221
71470rcu_preempt25589-21copy10:10:221
2231699472cyclictest31314-21ssh12:12:042
2231699472cyclictest31314-21ssh12:12:042
2231699434cyclictest0-21swapper/209:50:282
2231699434cyclictest0-21swapper/209:50:282
2231699433cyclictest0-21swapper/211:19:192
2231699433cyclictest0-21swapper/211:19:192
2231699433cyclictest0-21swapper/211:19:192
2231699433cyclictest0-21swapper/211:00:362
2231699433cyclictest0-21swapper/211:00:362
2231699433cyclictest0-21swapper/210:46:052
2231699433cyclictest0-21swapper/210:46:052
71420rcu_preempt0-21swapper/110:19:351
71420rcu_preempt0-21swapper/110:19:351
2231699424cyclictest0-21swapper/211:50:242
2231699424cyclictest0-21swapper/211:50:242
2231699424cyclictest0-21swapper/211:50:242
2231699424cyclictest0-21swapper/208:40:322
2231699424cyclictest0-21swapper/208:40:322
2231699423cyclictest7915-21df_inode10:35:242
2231699423cyclictest7915-21df_inode10:35:242
2231699423cyclictest7915-21df_inode10:35:242
2231699422cyclictest1358-21diskstats11:20:272
2231699422cyclictest1358-21diskstats11:20:272
22316994216cyclictest20427-21ssh10:56:312
22316994216cyclictest20427-21ssh10:56:312
22316994216cyclictest20427-21ssh10:56:312
2231699414cyclictest0-21swapper/211:27:242
2231699414cyclictest0-21swapper/211:27:242
2231699414cyclictest0-21swapper/210:02:352
2231699414cyclictest0-21swapper/210:02:352
2231699413cyclictest0-21swapper/210:30:232
2231699413cyclictest0-21swapper/210:30:232
2231699413cyclictest0-21swapper/210:30:232
2231699413cyclictest0-21swapper/209:25:372
2231699413cyclictest0-21swapper/209:25:372
2231699413cyclictest0-21swapper/209:25:372
2231699413cyclictest0-21swapper/207:30:382
2231699413cyclictest0-21swapper/207:30:382
2231699412cyclictest9777-21grep12:30:402
2231699412cyclictest9777-21grep12:30:402
2231699412cyclictest7111-21df_inode11:30:272
2231699412cyclictest7111-21df_inode11:30:272
22316994117cyclictest0-21swapper/212:38:572
22316994117cyclictest0-21swapper/212:38:572
22316994116cyclictest0-21swapper/212:00:522
22316994116cyclictest0-21swapper/212:00:522
71400rcu_preempt20604-21runrttasks11:54:080
71400rcu_preempt20604-21runrttasks11:54:080
71400rcu_preempt20604-21runrttasks11:54:080
71400rcu_preempt0-21swapper/312:30:223
71400rcu_preempt0-21swapper/312:30:223
71400rcu_preempt0-21swapper/307:30:203
71400rcu_preempt0-21swapper/307:30:203
2231699403cyclictest0-21swapper/212:05:282
2231699403cyclictest0-21swapper/212:05:282
2231699403cyclictest0-21swapper/211:13:352
2231699403cyclictest0-21swapper/211:13:352
2231699403cyclictest0-21swapper/210:53:222
2231699403cyclictest0-21swapper/210:53:222
2231699403cyclictest0-21swapper/210:53:222
2231699403cyclictest0-21swapper/210:20:102
2231699403cyclictest0-21swapper/210:20:102
2231699403cyclictest0-21swapper/209:15:362
2231699403cyclictest0-21swapper/209:15:362
2231699403cyclictest0-21swapper/207:20:152
2231699403cyclictest0-21swapper/207:20:152
22316994016cyclictest0-21swapper/212:25:462
22316994016cyclictest0-21swapper/212:25:462
22316994015cyclictest0-21swapper/210:29:572
22316994015cyclictest0-21swapper/210:29:572
99750390irq/38-i2c-mpc17557-21taskset10:51:310
99750390irq/38-i2c-mpc17557-21taskset10:51:310
99750390irq/38-i2c-mpc17557-21taskset10:51:310
99750390irq/38-i2c-mpc0-21swapper/012:11:480
99750390irq/38-i2c-mpc0-21swapper/012:11:480
71390rcu_preempt25840-21sh09:14:170
71390rcu_preempt25840-21sh09:14:170
71390rcu_preempt0-21swapper/209:40:172
71390rcu_preempt0-21swapper/209:40:172
71390rcu_preempt0-21swapper/009:40:320
71390rcu_preempt0-21swapper/009:40:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional