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2025-12-11 - 06:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Dec 11, 2025 00:53:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71820rcu_preempt0-21swapper/000:54:410
71820rcu_preempt0-21swapper/000:54:410
71750rcu_preempt0-21swapper/022:46:040
71750rcu_preempt0-21swapper/022:46:040
71580rcu_preempt0-21swapper/022:40:080
71580rcu_preempt0-21swapper/022:40:080
71560rcu_preempt0-21swapper/022:00:370
71560rcu_preempt0-21swapper/022:00:370
24399995210cyclictest0-21swapper/122:21:361
24399995210cyclictest0-21swapper/122:21:361
71510rcu_preempt0-21swapper/021:44:320
71510rcu_preempt0-21swapper/021:44:320
71450rcu_preempt0-21swapper/023:55:100
71450rcu_preempt0-21swapper/023:55:100
71440rcu_preempt29247-21runrttasks19:58:150
71440rcu_preempt29247-21runrttasks19:58:150
71440rcu_preempt29247-21runrttasks19:58:150
71430rcu_preempt28879-21copy19:58:000
71430rcu_preempt28879-21copy19:58:000
71420rcu_preempt0-21swapper/000:52:410
71420rcu_preempt0-21swapper/000:52:410
71420rcu_preempt0-21swapper/000:08:100
71420rcu_preempt0-21swapper/000:08:100
46650420irq/116-QManpo29002-213
46650420irq/116-QManpo29002-213
46650420irq/116-QManpo29002-213
71410rcu_preempt0-21swapper/023:49:080
71410rcu_preempt0-21swapper/023:49:080
71410rcu_preempt0-21swapper/022:35:590
71410rcu_preempt0-21swapper/022:35:590
71410rcu_preempt0-21swapper/000:29:570
71410rcu_preempt0-21swapper/000:29:570
71400rcu_preempt9630-21sh00:07:580
71400rcu_preempt9630-21sh00:07:580
71400rcu_preempt15096-21crond00:17:550
71400rcu_preempt15096-21crond00:17:550
71400rcu_preempt15096-21crond00:17:550
71400rcu_preempt0-21swapper/222:58:332
71400rcu_preempt0-21swapper/222:58:332
71400rcu_preempt0-21swapper/222:08:142
71400rcu_preempt0-21swapper/222:08:142
71400rcu_preempt0-21swapper/222:08:142
71400rcu_preempt0-21swapper/122:38:151
71400rcu_preempt0-21swapper/122:38:151
71400rcu_preempt0-21swapper/022:33:030
71390rcu_preempt21699-21runrttasks22:31:311
71390rcu_preempt21699-21runrttasks22:31:311
71390rcu_preempt21699-21runrttasks22:31:311
71390rcu_preempt0-21swapper/322:42:593
71390rcu_preempt0-21swapper/322:42:593
71390rcu_preempt0-21swapper/221:23:182
71390rcu_preempt0-21swapper/221:23:182
71390rcu_preempt0-21swapper/221:23:182
71390rcu_preempt0-21swapper/123:34:051
71390rcu_preempt0-21swapper/123:34:051
71390rcu_preempt0-21swapper/123:34:051
71390rcu_preempt0-21swapper/100:26:021
71390rcu_preempt0-21swapper/100:26:021
71390rcu_preempt0-21swapper/100:26:021
71390rcu_preempt0-21swapper/100:08:001
71390rcu_preempt0-21swapper/100:08:001
71380rcu_preempt26305-21/usr/sbin/munin00:38:112
71380rcu_preempt26305-21/usr/sbin/munin00:38:112
71380rcu_preempt1244-21ssh22:53:130
71380rcu_preempt1244-21ssh22:53:130
71380rcu_preempt1244-21ssh22:53:130
71380rcu_preempt0-21swapper/321:38:103
71380rcu_preempt0-21swapper/321:38:103
71380rcu_preempt0-21swapper/300:38:253
71380rcu_preempt0-21swapper/300:38:253
71380rcu_preempt0-21swapper/223:32:442
71380rcu_preempt0-21swapper/223:32:442
71380rcu_preempt0-21swapper/022:08:160
71380rcu_preempt0-21swapper/022:08:160
71380rcu_preempt0-21swapper/022:08:160
71380rcu_preempt0-21swapper/021:38:070
71380rcu_preempt0-21swapper/021:38:070
71380rcu_preempt0-21swapper/020:28:190
71380rcu_preempt0-21swapper/020:28:190
71380rcu_preempt0-21swapper/020:28:190
71380rcu_preempt0-21swapper/000:33:200
71380rcu_preempt0-21swapper/000:33:200
24399993818cyclictest7947-21diskstats20:38:121
24399993818cyclictest7947-21diskstats20:38:121
24399993816cyclictest31206-21ntp_states22:48:201
24399993816cyclictest31206-21ntp_states22:48:201
24399993815cyclictest0-21swapper/101:08:211
24399993815cyclictest0-21swapper/101:08:211
71370rcu_preempt0-21swapper/319:53:113
71370rcu_preempt0-21swapper/319:53:113
71370rcu_preempt0-21swapper/222:18:092
71370rcu_preempt0-21swapper/222:18:092
71370rcu_preempt0-21swapper/123:50:191
71370rcu_preempt0-21swapper/123:50:191
71370rcu_preempt0-21swapper/123:19:391
71370rcu_preempt0-21swapper/123:19:391
71370rcu_preempt0-21swapper/122:15:321
71370rcu_preempt0-21swapper/122:15:321
71370rcu_preempt0-21swapper/121:59:081
71370rcu_preempt0-21swapper/121:59:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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