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2026-07-13 - 05:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Jul 13, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71700rcu_preempt5582-1kworker/1:2H21:54:111
71700rcu_preempt5582-1kworker/1:2H21:54:111
71700rcu_preempt5582-1kworker/1:2H21:54:111
255772640chrt46250irq/120-QMan10:48:551
255772640chrt46250irq/120-QMan10:48:551
71692530chrt46450irq/118-QMan10:48:552
71692530chrt46450irq/118-QMan10:48:552
71692530chrt46450irq/118-QMan10:48:552
71500rcu_preempt0-21swapper/020:38:550
71500rcu_preempt0-21swapper/020:38:550
71500rcu_preempt0-21swapper/020:38:550
71440rcu_preempt0-21swapper/322:29:043
71440rcu_preempt0-21swapper/322:29:043
71420rcu_preempt24703-21copy00:33:573
71420rcu_preempt24703-21copy00:33:573
71420rcu_preempt24703-21copy00:33:573
71420rcu_preempt0-21swapper/320:38:573
71420rcu_preempt0-21swapper/320:38:573
71420rcu_preempt0-21swapper/320:38:573
71420rcu_preempt0-21swapper/200:11:562
71420rcu_preempt0-21swapper/200:11:562
71410rcu_preempt22793-21sendmail-msp22:29:392
71410rcu_preempt22793-21sendmail-msp22:29:392
71410rcu_preempt10828-1kworker/2:2H23:04:192
71410rcu_preempt10828-1kworker/2:2H23:04:192
71410rcu_preempt10828-1kworker/2:2H23:04:192
71410rcu_preempt0-21swapper/200:16:402
71410rcu_preempt0-21swapper/200:16:402
71410rcu_preempt0-21swapper/200:16:402
71400rcu_preempt0-21swapper/321:19:033
71400rcu_preempt0-21swapper/321:19:033
71400rcu_preempt0-21swapper/221:44:412
71400rcu_preempt0-21swapper/221:44:412
71390rcu_preempt17491-21sh23:15:592
71390rcu_preempt17491-21sh23:15:592
71390rcu_preempt17491-21sh23:15:592
71390rcu_preempt0-21swapper/223:35:162
71390rcu_preempt0-21swapper/223:35:162
71390rcu_preempt0-21swapper/223:02:042
71390rcu_preempt0-21swapper/223:02:042
71390rcu_preempt0-21swapper/223:02:042
71390rcu_preempt0-21swapper/221:51:462
71390rcu_preempt0-21swapper/221:51:462
71390rcu_preempt0-21swapper/221:51:462
71390rcu_preempt0-21swapper/200:03:462
71390rcu_preempt0-21swapper/200:03:462
71390rcu_preempt0-21swapper/200:03:462
46050390irq/122-QManpo23107-2110:48:550
46050390irq/122-QManpo23107-2110:48:550
46050390irq/122-QManpo18167-2110:48:550
46050390irq/122-QManpo18167-2110:48:550
46050390irq/122-QManpo15564-2110:48:550
46050390irq/122-QManpo15564-2110:48:550
71380rcu_preempt9976-21/usr/sbin/munin00:04:262
71380rcu_preempt9976-21/usr/sbin/munin00:04:262
71380rcu_preempt9976-21/usr/sbin/munin00:04:262
71380rcu_preempt8359-1kworker/1:1H22:11:231
71380rcu_preempt8359-1kworker/1:1H22:11:231
71380rcu_preempt8359-1kworker/1:1H22:11:231
71380rcu_preempt0-21swapper/323:13:483
71380rcu_preempt0-21swapper/323:13:483
71380rcu_preempt0-21swapper/323:13:483
71380rcu_preempt0-21swapper/323:13:483
71380rcu_preempt0-21swapper/300:01:583
71380rcu_preempt0-21swapper/300:01:583
71380rcu_preempt0-21swapper/300:01:583
71380rcu_preempt0-21swapper/223:24:302
71380rcu_preempt0-21swapper/223:24:302
71380rcu_preempt0-21swapper/223:24:302
71380rcu_preempt0-21swapper/222:28:362
71380rcu_preempt0-21swapper/222:28:362
71380rcu_preempt0-21swapper/222:28:362
71380rcu_preempt0-21swapper/222:16:492
71380rcu_preempt0-21swapper/222:16:492
71380rcu_preempt0-21swapper/200:34:122
71380rcu_preempt0-21swapper/200:34:122
71380rcu_preempt0-21swapper/200:34:122
46050380irq/122-QManpo29957-2110:48:550
46050380irq/122-QManpo29957-2110:48:550
46050380irq/122-QManpo29957-2110:48:550
46050380irq/122-QManpo21543-2110:48:550
46050380irq/122-QManpo21543-2110:48:550
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
152002380sleep015033-1kworker/0:3H21:02:370
152002380sleep015033-1kworker/0:3H21:02:370
71370rcu_preempt32679-21/usr/sbin/munin21:39:243
71370rcu_preempt32679-21/usr/sbin/munin21:39:243
71370rcu_preempt32679-21/usr/sbin/munin21:39:243
71370rcu_preempt31157-21sh23:43:452
71370rcu_preempt31157-21sh23:43:452
71370rcu_preempt0-21swapper/323:39:303
71370rcu_preempt0-21swapper/323:39:303
71370rcu_preempt0-21swapper/323:22:153
71370rcu_preempt0-21swapper/323:22:153
71370rcu_preempt0-21swapper/323:22:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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