You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-30 - 09:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Jan 30, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71610rcu_preempt0-21swapper/323:21:003
71610rcu_preempt0-21swapper/323:21:003
71610rcu_preempt0-21swapper/323:21:003
71580rcu_preempt0-21swapper/100:34:521
71580rcu_preempt0-21swapper/100:34:521
71580rcu_preempt0-21swapper/100:34:521
46050510irq/122-QManpo0-210
46050510irq/122-QManpo0-210
46050510irq/122-QManpo0-210
46050480irq/122-QManpo1274-2110:48:550
46050480irq/122-QManpo1274-2110:48:550
1325994710cyclictest30133-21sshd20:52:241
1325994710cyclictest30133-21sshd20:52:241
71460rcu_preempt15329-21apt-get20:01:093
71460rcu_preempt15329-21apt-get20:01:093
132599452cyclictest1959-21runrttasks21:22:191
132599452cyclictest1959-21runrttasks21:22:191
46050440irq/122-QManpo11240-2110:48:550
46050440irq/122-QManpo11240-2110:48:550
46050440irq/122-QManpo11240-2110:48:550
132599438cyclictest18672-21apt-get22:36:071
132599438cyclictest18672-21apt-get22:36:071
132599438cyclictest18672-21apt-get22:36:071
132599433cyclictest26575-21df23:46:111
132599433cyclictest26575-21df23:46:111
132599433cyclictest26575-21df23:46:111
132599432cyclictest4631-21memory19:21:191
132599432cyclictest4631-21memory19:21:191
132599422cyclictest13043-21ntp_states19:51:191
132599422cyclictest13043-21ntp_states19:51:191
132599422cyclictest12408-21df_inode23:21:141
132599422cyclictest12408-21df_inode23:21:141
132599414cyclictest0-21swapper/121:36:171
132599414cyclictest0-21swapper/121:36:171
132599414cyclictest0-21swapper/121:36:171
132599413cyclictest0-21swapper/123:26:191
132599413cyclictest0-21swapper/123:26:191
132599413cyclictest0-21swapper/122:46:161
132599413cyclictest0-21swapper/122:46:161
132599413cyclictest0-21swapper/121:36:011
132599413cyclictest0-21swapper/121:36:011
132599413cyclictest0-21swapper/121:16:211
132599413cyclictest0-21swapper/121:16:211
132599413cyclictest0-21swapper/121:16:211
132599413cyclictest0-21swapper/120:11:141
132599413cyclictest0-21swapper/120:11:141
132599412cyclictest32464-21ntp_states21:01:211
132599412cyclictest32464-21ntp_states21:01:211
132599412cyclictest31986-21awk22:01:291
132599412cyclictest31986-21awk22:01:291
132599412cyclictest31986-21awk22:01:291
132599412cyclictest2963-21ntp_states21:11:211
132599412cyclictest2963-21ntp_states21:11:211
132599412cyclictest23805-21ssh23:41:111
132599412cyclictest23805-21ssh23:41:111
132599412cyclictest23805-21ssh23:41:111
132599412cyclictest20428-21sshd20:17:241
132599412cyclictest20428-21sshd20:17:241
132599412cyclictest14619-21ntp_states00:21:221
132599412cyclictest14619-21ntp_states00:21:221
132599412cyclictest1448-21apt22:06:061
132599412cyclictest1448-21apt22:06:061
132599412cyclictest1448-21apt22:06:061
132599411cyclictest23512-21ssh22:44:081
132599411cyclictest23512-21ssh22:44:081
46450400irq/118-QManpo0-2110:48:552
46450400irq/118-QManpo0-2110:48:552
46050400irq/122-QManpo3470-2110:48:550
46050400irq/122-QManpo3470-2110:48:550
46050400irq/122-QManpo2526-10
46050400irq/122-QManpo2526-10
1599400migration/029992-21latency_hist22:55:580
1599400migration/029992-21latency_hist22:55:580
132599404cyclictest0-21swapper/122:31:241
132599404cyclictest0-21swapper/122:31:241
132599404cyclictest0-21swapper/122:31:241
132599404cyclictest0-21swapper/100:01:221
132599404cyclictest0-21swapper/100:01:221
132599403cyclictest0-21swapper/123:10:271
132599403cyclictest0-21swapper/123:10:271
132599403cyclictest0-21swapper/123:05:341
132599403cyclictest0-21swapper/123:05:341
132599403cyclictest0-21swapper/122:21:211
132599403cyclictest0-21swapper/122:21:211
132599403cyclictest0-21swapper/121:56:201
132599403cyclictest0-21swapper/121:56:201
132599403cyclictest0-21swapper/121:26:531
132599403cyclictest0-21swapper/121:26:531
132599402cyclictest4695-21irqstats22:11:151
132599402cyclictest4695-21irqstats22:11:151
132599402cyclictest32694-21ntp_states23:56:201
132599402cyclictest32694-21ntp_states23:56:201
132599402cyclictest32694-21ntp_states23:56:201
132599402cyclictest23412-21munin-run23:40:561
132599402cyclictest23412-21munin-run23:40:561
132599402cyclictest23412-21munin-run23:40:561
132599402cyclictest0-21swapper/120:36:141
132599402cyclictest0-21swapper/120:36:141
132599402cyclictest0-21swapper/119:31:201
132599402cyclictest0-21swapper/119:31:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional