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2026-02-09 - 00:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Feb 08, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71450rcu_preempt16864-21taskset11:47:380
71450rcu_preempt16864-21taskset11:47:380
71450rcu_preempt16864-21taskset11:47:380
2298999442cyclictest30261-21memory12:11:293
2298999442cyclictest30261-21memory12:11:293
1599440migration/022560-21/usr/sbin/munin07:06:340
1599440migration/022560-21/usr/sbin/munin07:06:340
2298999434cyclictest0-21swapper/311:06:083
2298999434cyclictest0-21swapper/311:06:083
2298999433cyclictest0-21swapper/309:45:393
2298999433cyclictest0-21swapper/309:45:393
2298999433cyclictest0-21swapper/308:16:263
2298999433cyclictest0-21swapper/308:16:263
2298999433cyclictest0-21swapper/308:16:263
71420rcu_preempt0-21swapper/310:39:223
71420rcu_preempt0-21swapper/310:39:223
71420rcu_preempt0-21swapper/310:39:223
71420rcu_preempt0-21swapper/011:06:170
71420rcu_preempt0-21swapper/011:06:170
71420rcu_preempt0-21swapper/011:06:170
2298999424cyclictest0-21swapper/308:41:073
2298999424cyclictest0-21swapper/308:41:073
2298999424cyclictest0-21swapper/308:41:073
2298999423cyclictest26514-21memory10:11:303
2298999423cyclictest26514-21memory10:11:303
2298999423cyclictest26514-21memory10:11:303
2298999423cyclictest0-21swapper/312:18:523
2298999423cyclictest0-21swapper/312:18:523
2298999423cyclictest0-21swapper/312:18:523
2298999423cyclictest0-21swapper/311:30:023
2298999423cyclictest0-21swapper/311:30:023
2298999423cyclictest0-21swapper/310:41:243
2298999423cyclictest0-21swapper/310:41:243
2298999423cyclictest0-21swapper/310:31:253
2298999423cyclictest0-21swapper/310:31:253
2298999422cyclictest3634-21meminfo12:21:283
2298999422cyclictest3634-21meminfo12:21:283
2298999422cyclictest3634-21meminfo12:21:283
2298999422cyclictest27171-21df09:16:243
2298999422cyclictest27171-21df09:16:243
22989994218cyclictest0-21swapper/311:01:093
22989994218cyclictest0-21swapper/311:01:093
22989994216cyclictest20935-21ntp_states10:01:333
22989994216cyclictest20935-21ntp_states10:01:333
2298999414cyclictest0-21swapper/309:46:473
2298999414cyclictest0-21swapper/309:46:473
2298999414cyclictest0-21swapper/309:11:093
2298999414cyclictest0-21swapper/309:11:093
2298999414cyclictest0-21swapper/309:11:093
2298999413cyclictest0-21swapper/312:35:243
2298999413cyclictest0-21swapper/312:35:243
2298999413cyclictest0-21swapper/311:22:333
2298999413cyclictest0-21swapper/311:22:333
2298999412cyclictest9829-21apt11:36:173
2298999412cyclictest9829-21apt11:36:173
2298999412cyclictest9829-21apt11:36:173
2298999412cyclictest16184-21/usr/sbin/munin08:41:323
2298999412cyclictest16184-21/usr/sbin/munin08:41:323
2298999412cyclictest16184-21/usr/sbin/munin08:41:323
22989994120cyclictest0-21swapper/309:31:303
22989994120cyclictest0-21swapper/309:31:303
22989994120cyclictest0-21swapper/309:31:303
71400rcu_preempt0-21swapper/310:53:113
71400rcu_preempt0-21swapper/310:53:113
46050400irq/122-QManpo22095-2110:48:550
46050400irq/122-QManpo22095-2110:48:550
2298999404cyclictest0-21swapper/311:35:253
2298999404cyclictest0-21swapper/311:35:253
2298999403cyclictest0-21swapper/312:01:353
2298999403cyclictest0-21swapper/312:01:353
2298999403cyclictest0-21swapper/311:06:313
2298999403cyclictest0-21swapper/311:06:313
2298999403cyclictest0-21swapper/311:06:313
2298999403cyclictest0-21swapper/310:17:273
2298999403cyclictest0-21swapper/310:17:273
2298999403cyclictest0-21swapper/310:17:273
2298999403cyclictest0-21swapper/308:01:323
2298999403cyclictest0-21swapper/308:01:323
2298999403cyclictest0-21swapper/307:56:073
2298999403cyclictest0-21swapper/307:56:073
2298999402cyclictest8263-21ssh12:30:043
2298999402cyclictest8263-21ssh12:30:043
2298999402cyclictest4842-21ssh10:30:583
2298999402cyclictest4842-21ssh10:30:583
2298999402cyclictest31155-21irqstats11:16:263
2298999402cyclictest31155-21irqstats11:16:263
22989994015cyclictest24324-21munin-run07:16:063
22989994015cyclictest24324-21munin-run07:16:063
22989994015cyclictest24324-21munin-run07:16:063
22989994014cyclictest24167-21ssh10:06:423
22989994014cyclictest24167-21ssh10:06:423
22989994014cyclictest14417-21munin-run12:41:083
22989994014cyclictest14417-21munin-run12:41:083
22989994014cyclictest14417-21munin-run12:41:083
22989994011cyclictest28891-21/usr/sbin/munin07:31:223
22989994011cyclictest28891-21/usr/sbin/munin07:31:223
46050390irq/122-QManpo3764-2110:48:550
46050390irq/122-QManpo3764-2110:48:550
46050390irq/122-QManpo3764-2110:48:550
46050390irq/122-QManpo30139-2110:48:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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