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2026-01-16 - 14:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Jan 16, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71700rcu_preempt0-21swapper/212:29:392
71700rcu_preempt0-21swapper/212:29:392
71660rcu_preempt0-21swapper/311:19:073
71660rcu_preempt0-21swapper/311:19:073
71660rcu_preempt0-21swapper/311:19:073
71530rcu_preempt17592-21ssh09:20:522
71530rcu_preempt17592-21ssh09:20:522
1066299538cyclictest3881-21/usr/sbin/munin08:41:042
1066299538cyclictest3881-21/usr/sbin/munin08:41:042
71510rcu_preempt0-21swapper/011:37:410
71510rcu_preempt0-21swapper/011:37:410
71510rcu_preempt0-21swapper/011:37:410
1599490migration/010395-21taskset07:08:020
1599490migration/010395-21taskset07:08:020
71470rcu_preempt0-21swapper/008:30:550
71470rcu_preempt0-21swapper/008:30:550
71470rcu_preempt0-21swapper/008:30:550
71450rcu_preempt0-21swapper/108:35:541
71450rcu_preempt0-21swapper/108:35:541
71450rcu_preempt0-21swapper/108:35:541
1066299453cyclictest11103-21df10:05:542
1066299453cyclictest11103-21df10:05:542
1066299443cyclictest8260-21df10:00:542
1066299443cyclictest8260-21df10:00:542
46250430irq/120-QManpo1958-2110:48:551
46250430irq/120-QManpo1958-2110:48:551
1066299437cyclictest10261-21taskset11:00:552
1066299437cyclictest10261-21taskset11:00:552
1066299434cyclictest0-21swapper/211:35:542
1066299434cyclictest0-21swapper/211:35:542
1066299434cyclictest0-21swapper/211:35:542
1066299434cyclictest0-21swapper/210:39:072
1066299434cyclictest0-21swapper/210:39:072
1066299434cyclictest0-21swapper/210:39:072
10662994312cyclictest30735-21ntp_states08:21:052
10662994312cyclictest30735-21ntp_states08:21:052
71420rcu_preempt25275-21taskset09:33:550
71420rcu_preempt25275-21taskset09:33:550
71420rcu_preempt25275-21taskset09:33:550
71420rcu_preempt0-21swapper/011:30:540
71420rcu_preempt0-21swapper/011:30:540
1066299424cyclictest0-21swapper/210:55:592
1066299424cyclictest0-21swapper/210:55:592
1066299424cyclictest0-21swapper/210:55:592
1066299423cyclictest0-21swapper/211:59:412
1066299423cyclictest0-21swapper/211:59:412
1066299423cyclictest0-21swapper/211:59:412
1066299423cyclictest0-21swapper/211:51:082
1066299423cyclictest0-21swapper/211:51:082
1066299423cyclictest0-21swapper/211:51:082
1066299423cyclictest0-21swapper/211:46:542
1066299423cyclictest0-21swapper/211:46:542
1066299423cyclictest0-21swapper/211:46:542
1066299423cyclictest0-21swapper/209:20:292
1066299423cyclictest0-21swapper/209:20:292
1066299423cyclictest0-21swapper/209:10:422
1066299423cyclictest0-21swapper/209:10:422
1066299423cyclictest0-21swapper/207:51:022
1066299423cyclictest0-21swapper/207:51:022
1066299422cyclictest4886-21ntp_states10:51:042
1066299422cyclictest4886-21ntp_states10:51:042
71410rcu_preempt31394-21taskset09:45:011
71410rcu_preempt31394-21taskset09:45:011
71410rcu_preempt26933-1kworker/1:0H08:16:001
71410rcu_preempt26933-1kworker/1:0H08:16:001
71410rcu_preempt0-21swapper/112:16:301
71410rcu_preempt0-21swapper/112:16:301
71410rcu_preempt0-21swapper/112:16:301
71410rcu_preempt0-21swapper/011:05:550
71410rcu_preempt0-21swapper/011:05:550
1066299414cyclictest0-21swapper/210:31:062
1066299414cyclictest0-21swapper/210:31:062
1066299414cyclictest0-21swapper/210:31:062
1066299413cyclictest0-21swapper/211:31:092
1066299413cyclictest0-21swapper/211:31:092
1066299413cyclictest0-21swapper/211:15:412
1066299413cyclictest0-21swapper/211:15:412
1066299413cyclictest0-21swapper/208:30:562
1066299413cyclictest0-21swapper/208:30:562
1066299413cyclictest0-21swapper/208:30:562
1066299413cyclictest0-21swapper/207:10:552
1066299413cyclictest0-21swapper/207:10:552
1066299412cyclictest20078-21irqstats12:16:012
1066299412cyclictest20078-21irqstats12:16:012
1066299412cyclictest20078-21irqstats12:16:012
71400rcu_preempt5600-1kworker/2:1H09:01:082
71400rcu_preempt5600-1kworker/2:1H09:01:082
71400rcu_preempt0-21swapper/109:12:421
71400rcu_preempt0-21swapper/109:12:421
1066299404cyclictest0-21swapper/211:41:452
1066299404cyclictest0-21swapper/211:41:452
1066299404cyclictest0-21swapper/210:42:452
1066299404cyclictest0-21swapper/210:42:452
1066299403cyclictest0-21swapper/211:15:492
1066299403cyclictest0-21swapper/211:15:492
1066299403cyclictest0-21swapper/211:15:492
1066299403cyclictest0-21swapper/210:23:512
1066299403cyclictest0-21swapper/210:23:512
1066299403cyclictest0-21swapper/209:47:392
1066299403cyclictest0-21swapper/209:47:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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