You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-07 - 13:02
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Jul 07, 2026 00:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301710ksoftirqd/328088-1kworker/3:6H20:28:553
301710ksoftirqd/328088-1kworker/3:6H20:28:553
71540rcu_preempt0-21swapper/119:24:061
71540rcu_preempt0-21swapper/119:24:061
71540rcu_preempt0-21swapper/119:24:061
71510rcu_preempt27846-1kworker/2:0H19:13:492
71510rcu_preempt27846-1kworker/2:0H19:13:492
71510rcu_preempt27846-1kworker/2:0H19:13:492
71510rcu_preempt27846-1kworker/2:0H19:13:492
71510rcu_preempt0-21swapper/000:19:080
71510rcu_preempt0-21swapper/000:19:080
71510rcu_preempt0-21swapper/000:19:080
71500rcu_preempt0-21swapper/119:32:071
71500rcu_preempt0-21swapper/119:32:071
46050500irq/122-QManpo27264-2110:48:550
46050500irq/122-QManpo27264-2110:48:550
46050500irq/122-QManpo27264-2110:48:550
46050500irq/122-QManpo27264-2110:48:550
71490rcu_preempt2533-21kworker/1:023:54:361
71490rcu_preempt2533-21kworker/1:023:54:361
71490rcu_preempt2533-21kworker/1:023:54:361
28166994718cyclictest23938-21latency_hist21:43:500
28166994718cyclictest23938-21latency_hist21:43:500
28166994532cyclictest4230-21apt-get20:58:580
28166994532cyclictest4230-21apt-get20:58:580
28166994521cyclictest4064-21/usr/sbin/munin19:29:110
28166994521cyclictest4064-21/usr/sbin/munin19:29:110
28166994512cyclictest0-21swapper/021:34:160
28166994512cyclictest0-21swapper/021:34:160
28166994512cyclictest0-21swapper/021:34:160
71430rcu_preempt32543-21sh19:27:060
71430rcu_preempt32543-21sh19:27:060
71430rcu_preempt32543-21sh19:27:060
71430rcu_preempt2815-1kworker/1:0H23:09:001
71430rcu_preempt2815-1kworker/1:0H23:09:001
71430rcu_preempt2815-1kworker/1:0H23:09:001
71430rcu_preempt0-21swapper/019:17:060
71430rcu_preempt0-21swapper/019:17:060
71420rcu_preempt0-21swapper/021:23:450
71420rcu_preempt0-21swapper/021:23:450
71420rcu_preempt0-21swapper/021:23:450
28167994219cyclictest5310-21spawn19:23:271
28167994219cyclictest5310-21spawn19:23:271
28167994219cyclictest5310-21spawn19:23:271
28166994217cyclictest0-21swapper/023:49:000
28166994217cyclictest0-21swapper/023:49:000
28166994217cyclictest0-21swapper/023:49:000
28166994215cyclictest27040-21df20:24:010
28166994215cyclictest27040-21df20:24:010
28166994215cyclictest22389-1kworker/0:0H20:23:400
28166994215cyclictest22389-1kworker/0:0H20:23:400
28166994215cyclictest22389-1kworker/0:0H20:23:400
71410rcu_preempt31328-21sh22:59:581
71410rcu_preempt31328-21sh22:59:581
71410rcu_preempt31328-21sh22:59:581
71410rcu_preempt2533-21kworker/1:023:23:411
71410rcu_preempt2533-21kworker/1:023:23:411
71410rcu_preempt23045-21sh23:46:131
71410rcu_preempt23045-21sh23:46:131
71410rcu_preempt17536-21ssh21:30:330
71410rcu_preempt17536-21ssh21:30:330
71410rcu_preempt0-21swapper/100:18:341
71410rcu_preempt0-21swapper/100:18:341
71410rcu_preempt0-21swapper/100:18:341
71410rcu_preempt0-21swapper/023:05:020
71410rcu_preempt0-21swapper/023:05:020
28166994121cyclictest27061-21irqstats21:49:070
28166994121cyclictest27061-21irqstats21:49:070
28166994121cyclictest20313-21meminfo19:59:080
28166994121cyclictest20313-21meminfo19:59:080
28166994120cyclictest28925-21find20:29:170
28166994120cyclictest28925-21find20:29:170
28166994119cyclictest2307-21df_inode22:04:020
28166994119cyclictest2307-21df_inode22:04:020
28166994119cyclictest2307-21df_inode22:04:020
28166994119cyclictest20411-21chrt23:41:280
28166994119cyclictest20411-21chrt23:41:280
28166994117cyclictest0-21swapper/022:59:210
28166994117cyclictest0-21swapper/022:59:210
28166994117cyclictest0-21swapper/022:59:210
28166994116cyclictest0-21swapper/023:54:110
28166994116cyclictest0-21swapper/023:54:110
28166994116cyclictest0-21swapper/023:54:110
28166994116cyclictest0-21swapper/022:35:070
28166994116cyclictest0-21swapper/022:35:070
28166994116cyclictest0-21swapper/022:35:070
28166994114cyclictest29038-21diskstats19:19:000
28166994114cyclictest29038-21diskstats19:19:000
28166994114cyclictest29038-21diskstats19:19:000
28166994112cyclictest0-21swapper/023:22:250
28166994112cyclictest0-21swapper/023:22:250
71400rcu_preempt25080-21spawn19:23:332
71400rcu_preempt25080-21spawn19:23:332
71400rcu_preempt25080-21spawn19:23:332
71400rcu_preempt0-21swapper/219:32:332
71400rcu_preempt0-21swapper/219:32:332
71400rcu_preempt0-21swapper/100:33:291
71400rcu_preempt0-21swapper/100:33:291
71400rcu_preempt0-21swapper/100:33:291
71400rcu_preempt0-21swapper/020:50:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional