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2026-02-06 - 11:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Feb 06, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71530rcu_preempt0-21swapper/000:19:350
71530rcu_preempt0-21swapper/000:19:350
71530rcu_preempt0-21swapper/000:19:350
71500rcu_preempt0-21swapper/322:45:163
71500rcu_preempt0-21swapper/322:45:163
970399463cyclictest0-21swapper/100:35:521
970399463cyclictest0-21swapper/100:35:521
46650450irq/116-QManpo9660-2110:48:553
46650450irq/116-QManpo9660-2110:48:553
9703994422cyclictest0-21swapper/121:41:051
9703994422cyclictest0-21swapper/121:41:051
9703994422cyclictest0-21swapper/121:41:051
970399432cyclictest19408-21aten_r4power_cu21:26:161
970399432cyclictest19408-21aten_r4power_cu21:26:161
9703994318cyclictest10135-21diskstats22:06:221
9703994318cyclictest10135-21diskstats22:06:221
71430rcu_preempt0-21swapper/323:11:253
71430rcu_preempt0-21swapper/323:11:253
71430rcu_preempt0-21swapper/323:11:253
71430rcu_preempt0-21swapper/123:11:271
71430rcu_preempt0-21swapper/123:11:271
71430rcu_preempt0-21swapper/123:11:271
970399424cyclictest0-21swapper/123:07:191
970399424cyclictest0-21swapper/123:07:191
970399423cyclictest0-21swapper/122:11:281
970399423cyclictest0-21swapper/122:11:281
970399423cyclictest0-21swapper/121:41:271
970399423cyclictest0-21swapper/121:41:271
970399423cyclictest0-21swapper/121:41:271
71420rcu_preempt0-21swapper/300:11:183
71420rcu_preempt0-21swapper/300:11:183
71420rcu_preempt0-21swapper/220:46:262
71420rcu_preempt0-21swapper/220:46:262
71420rcu_preempt0-21swapper/023:11:150
71420rcu_preempt0-21swapper/023:11:150
71420rcu_preempt0-21swapper/023:11:150
970399414cyclictest0-21swapper/119:16:191
970399414cyclictest0-21swapper/119:16:191
970399413cyclictest0-21swapper/123:56:411
970399413cyclictest0-21swapper/123:56:411
970399413cyclictest0-21swapper/123:56:411
970399413cyclictest0-21swapper/123:51:251
970399413cyclictest0-21swapper/123:51:251
970399413cyclictest0-21swapper/123:16:331
970399413cyclictest0-21swapper/123:16:331
970399413cyclictest0-21swapper/123:16:331
970399413cyclictest0-21swapper/122:16:381
970399413cyclictest0-21swapper/122:16:381
970399413cyclictest0-21swapper/122:16:381
970399413cyclictest0-21swapper/121:50:241
970399413cyclictest0-21swapper/121:50:241
970399413cyclictest0-21swapper/120:36:331
970399413cyclictest0-21swapper/120:36:331
970399413cyclictest0-21swapper/119:26:251
970399413cyclictest0-21swapper/119:26:251
970399413cyclictest0-21swapper/119:26:251
46050410irq/122-QManpo7082-210
46050410irq/122-QManpo7082-210
46050410irq/122-QManpo7082-210
970399404cyclictest0-21swapper/123:02:491
970399404cyclictest0-21swapper/123:02:491
970399403cyclictest0-21swapper/123:00:311
970399403cyclictest0-21swapper/123:00:311
970399403cyclictest0-21swapper/123:00:311
970399403cyclictest0-21swapper/122:33:561
970399403cyclictest0-21swapper/122:33:561
970399403cyclictest0-21swapper/121:57:241
970399403cyclictest0-21swapper/121:57:241
970399403cyclictest0-21swapper/121:57:241
970399403cyclictest0-21swapper/121:57:241
970399403cyclictest0-21swapper/121:34:131
970399403cyclictest0-21swapper/121:34:131
970399403cyclictest0-21swapper/100:01:541
970399403cyclictest0-21swapper/100:01:541
100650400irq/38-i2c-mpc0-21swapper/020:08:100
100650400irq/38-i2c-mpc0-21swapper/020:08:100
970399394cyclictest0-21swapper/100:19:371
970399394cyclictest0-21swapper/100:19:371
970399394cyclictest0-21swapper/100:19:371
970399393cyclictest0-21swapper/123:43:561
970399393cyclictest0-21swapper/123:43:561
970399393cyclictest0-21swapper/121:21:071
970399393cyclictest0-21swapper/121:21:071
970399393cyclictest0-21swapper/121:21:071
970399393cyclictest0-21swapper/119:11:301
970399393cyclictest0-21swapper/119:11:301
71390rcu_preempt7984-1grep22:01:343
71390rcu_preempt7984-1grep22:01:343
71390rcu_preempt0-21swapper/222:12:412
71390rcu_preempt0-21swapper/222:12:412
71390rcu_preempt0-21swapper/122:41:181
71390rcu_preempt0-21swapper/122:41:181
71380rcu_preempt0-21swapper/221:49:572
71380rcu_preempt0-21swapper/221:49:572
71380rcu_preempt0-21swapper/120:01:101
71380rcu_preempt0-21swapper/120:01:101
71380rcu_preempt0-21swapper/120:01:101
71380rcu_preempt0-21swapper/100:27:431
71380rcu_preempt0-21swapper/100:27:431
71380rcu_preempt0-21swapper/100:27:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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