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2026-05-10 - 00:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat May 09, 2026 12:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46050460irq/122-QManpo0-210
46050460irq/122-QManpo0-210
71450rcu_preempt0-21swapper/110:52:051
71450rcu_preempt0-21swapper/110:52:051
71450rcu_preempt0-21swapper/110:52:051
46050450irq/122-QManpo0-210
46050450irq/122-QManpo0-210
46050450irq/122-QManpo0-210
71430rcu_preempt14169-1kworker/0:2H11:32:470
71430rcu_preempt14169-1kworker/0:2H11:32:470
71430rcu_preempt14169-1kworker/0:2H11:32:470
100650430irq/38-i2c-mpc181ksoftirqd/108:07:141
100650430irq/38-i2c-mpc181ksoftirqd/108:07:141
71420rcu_preempt0-21swapper/011:44:070
71420rcu_preempt0-21swapper/011:44:070
31352420sleep029275-1kworker/0:4H07:08:060
31352420sleep029275-1kworker/0:4H07:08:060
71410rcu_preempt15774-21latency_hist10:32:491
71410rcu_preempt15774-21latency_hist10:32:491
71410rcu_preempt15774-21latency_hist10:32:491
71400rcu_preempt1958-21snmpd12:22:513
71400rcu_preempt1958-21snmpd12:22:513
71400rcu_preempt1958-21snmpd12:22:513
71400rcu_preempt11730-1kworker/0:0H10:28:140
71400rcu_preempt11730-1kworker/0:0H10:28:140
71400rcu_preempt11730-1kworker/0:0H10:28:140
71400rcu_preempt0-21swapper/112:12:531
71400rcu_preempt0-21swapper/112:12:531
71400rcu_preempt0-21swapper/009:55:070
71400rcu_preempt0-21swapper/009:55:070
71380rcu_preempt381-1kworker/1:4H11:07:471
71380rcu_preempt381-1kworker/1:4H11:07:471
71380rcu_preempt17702-21sh10:35:530
71380rcu_preempt17702-21sh10:35:530
71380rcu_preempt0-21swapper/111:00:041
71380rcu_preempt0-21swapper/111:00:041
71380rcu_preempt0-21swapper/111:00:041
71380rcu_preempt0-21swapper/012:40:460
71380rcu_preempt0-21swapper/012:40:460
71380rcu_preempt0-21swapper/012:34:130
71380rcu_preempt0-21swapper/012:34:130
71380rcu_preempt0-21swapper/012:34:130
71380rcu_preempt0-21swapper/012:27:550
71380rcu_preempt0-21swapper/012:27:550
71380rcu_preempt0-21swapper/012:27:550
71380rcu_preempt0-21swapper/010:48:130
71380rcu_preempt0-21swapper/010:48:130
71380rcu_preempt0-21swapper/010:48:130
71380rcu_preempt0-21swapper/007:52:450
71380rcu_preempt0-21swapper/007:52:450
46050380irq/122-QManpo31744-2110:48:550
46050380irq/122-QManpo31744-2110:48:550
46050380irq/122-QManpo26545-2110:48:550
46050380irq/122-QManpo26545-2110:48:550
46050380irq/122-QManpo12856-2110:48:550
46050380irq/122-QManpo12856-2110:48:550
46050380irq/122-QManpo12856-2110:48:550
46050380irq/122-QManpo12856-2110:48:550
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
71370rcu_preempt9792-21copy12:22:561
71370rcu_preempt9792-21copy12:22:561
71370rcu_preempt27551-21/usr/sbin/munin10:53:151
71370rcu_preempt27551-21/usr/sbin/munin10:53:151
71370rcu_preempt27551-21/usr/sbin/munin10:53:151
71370rcu_preempt24133-21kworker/0:110:06:080
71370rcu_preempt24133-21kworker/0:110:06:080
71370rcu_preempt0-21swapper/310:15:353
71370rcu_preempt0-21swapper/310:15:353
71370rcu_preempt0-21swapper/309:52:473
71370rcu_preempt0-21swapper/309:52:473
71370rcu_preempt0-21swapper/112:11:431
71370rcu_preempt0-21swapper/111:54:591
71370rcu_preempt0-21swapper/111:54:591
71370rcu_preempt0-21swapper/111:54:591
71370rcu_preempt0-21swapper/111:17:481
71370rcu_preempt0-21swapper/111:17:481
71370rcu_preempt0-21swapper/010:46:530
71370rcu_preempt0-21swapper/010:46:530
71370rcu_preempt0-21swapper/010:46:530
71370rcu_preempt0-21swapper/009:59:070
71370rcu_preempt0-21swapper/009:59:070
71370rcu_preempt0-21swapper/009:59:070
71370rcu_preempt0-21swapper/007:27:120
71370rcu_preempt0-21swapper/007:27:120
46250370irq/120-QManpo3984-2110:48:551
46250370irq/120-QManpo3984-2110:48:551
46050370irq/122-QManpo8808-2110:48:550
46050370irq/122-QManpo8808-2110:48:550
46050370irq/122-QManpo6399-10
46050370irq/122-QManpo6399-10
46050370irq/122-QManpo3266-10
46050370irq/122-QManpo3266-10
46050370irq/122-QManpo3266-10
46050370irq/122-QManpo3266-10
46050370irq/122-QManpo3266-10
46050370irq/122-QManpo25869-2110:48:550
46050370irq/122-QManpo25869-2110:48:550
46050370irq/122-QManpo12865-2110:48:550
46050370irq/122-QManpo12865-2110:48:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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