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2026-08-11 - 17:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Aug 11, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71540rcu_preempt0-21swapper/111:59:351
71540rcu_preempt0-21swapper/111:59:351
71500rcu_preempt0-21swapper/010:39:320
71500rcu_preempt0-21swapper/010:39:320
71500rcu_preempt0-21swapper/010:39:320
71490rcu_preempt0-21swapper/011:09:350
71490rcu_preempt0-21swapper/011:09:350
71450rcu_preempt0-21swapper/109:47:091
71450rcu_preempt0-21swapper/109:47:091
71450rcu_preempt0-21swapper/007:15:300
71450rcu_preempt0-21swapper/007:15:300
71440rcu_preempt5599-21sh11:13:171
71440rcu_preempt5599-21sh11:13:171
71430rcu_preempt0-21swapper/310:39:433
71430rcu_preempt0-21swapper/310:39:433
71430rcu_preempt0-21swapper/310:39:433
71430rcu_preempt0-21swapper/211:31:402
71430rcu_preempt0-21swapper/211:31:402
71420rcu_preempt0-21swapper/308:44:383
71420rcu_preempt0-21swapper/308:44:383
71420rcu_preempt0-21swapper/109:34:321
71420rcu_preempt0-21swapper/109:34:321
71410rcu_preempt0-21swapper/310:56:593
71410rcu_preempt0-21swapper/310:56:593
71410rcu_preempt0-21swapper/210:24:572
71410rcu_preempt0-21swapper/210:24:572
71410rcu_preempt0-21swapper/209:51:272
71410rcu_preempt0-21swapper/209:51:272
71410rcu_preempt0-21swapper/011:20:180
71410rcu_preempt0-21swapper/011:20:180
71410rcu_preempt0-21swapper/008:36:230
71410rcu_preempt0-21swapper/008:36:230
71400rcu_preempt3612-21apt-get07:19:343
71400rcu_preempt3612-21apt-get07:19:343
71400rcu_preempt0-21swapper/311:09:433
71400rcu_preempt0-21swapper/311:09:433
71400rcu_preempt0-21swapper/210:07:022
71400rcu_preempt0-21swapper/210:07:022
71400rcu_preempt0-21swapper/009:34:320
71400rcu_preempt0-21swapper/009:34:320
71400rcu_preempt0-21swapper/009:24:370
71400rcu_preempt0-21swapper/009:24:370
46250400irq/120-QManpo2443-2110:48:551
46250400irq/120-QManpo2443-2110:48:551
71390rcu_preempt5747-21ssh12:09:550
71390rcu_preempt5747-21ssh12:09:550
71390rcu_preempt3368-21kworker/0:011:54:140
71390rcu_preempt27625-21meminfo08:44:442
71390rcu_preempt27625-21meminfo08:44:442
71390rcu_preempt0-21swapper/209:40:052
71390rcu_preempt0-21swapper/209:40:052
71390rcu_preempt0-21swapper/209:40:052
71390rcu_preempt0-21swapper/112:41:221
71390rcu_preempt0-21swapper/112:41:221
71390rcu_preempt0-21swapper/110:54:411
71390rcu_preempt0-21swapper/110:54:411
71390rcu_preempt0-21swapper/110:12:571
71390rcu_preempt0-21swapper/110:12:571
71390rcu_preempt0-21swapper/011:59:510
71390rcu_preempt0-21swapper/011:59:510
71390rcu_preempt0-21swapper/010:22:370
71390rcu_preempt0-21swapper/010:22:370
71390rcu_preempt0-21swapper/010:22:370
71390rcu_preempt0-21swapper/010:14:510
71390rcu_preempt0-21swapper/010:14:510
71390rcu_preempt0-21swapper/010:14:510
46050390irq/122-QManpo496-2110:48:550
46050390irq/122-QManpo496-2110:48:550
46050390irq/122-QManpo496-2110:48:550
46050390irq/122-QManpo21661-2110:48:550
46050390irq/122-QManpo21661-2110:48:550
46050390irq/122-QManpo10579-2110:48:550
46050390irq/122-QManpo10579-2110:48:550
71380rcu_preempt3536-1kworker/0:0H07:19:350
71380rcu_preempt3536-1kworker/0:0H07:19:350
71380rcu_preempt22215-21ntpdc10:44:492
71380rcu_preempt22215-21ntpdc10:44:492
71380rcu_preempt20931-21/usr/sbin/munin09:44:512
71380rcu_preempt20931-21/usr/sbin/munin09:44:512
71380rcu_preempt14471-21cat09:34:272
71380rcu_preempt14471-21cat09:34:272
71380rcu_preempt0-21swapper/211:15:102
71380rcu_preempt0-21swapper/211:15:102
71380rcu_preempt0-21swapper/210:33:032
71380rcu_preempt0-21swapper/210:33:032
71380rcu_preempt0-21swapper/209:54:352
71380rcu_preempt0-21swapper/209:54:352
71380rcu_preempt0-21swapper/111:15:511
71380rcu_preempt0-21swapper/111:15:511
71380rcu_preempt0-21swapper/110:54:261
71380rcu_preempt0-21swapper/110:54:261
71380rcu_preempt0-21swapper/110:54:261
71380rcu_preempt0-21swapper/109:25:591
71380rcu_preempt0-21swapper/109:25:591
71380rcu_preempt0-21swapper/011:45:220
71380rcu_preempt0-21swapper/011:45:220
71380rcu_preempt0-21swapper/011:45:220
71380rcu_preempt0-21swapper/009:43:350
71380rcu_preempt0-21swapper/009:43:350
71380rcu_preempt0-21swapper/009:43:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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