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2026-04-30 - 18:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Apr 30, 2026 08:35:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46450650irq/118-QManpo5855-2110:52:072
46450650irq/118-QManpo5855-2110:52:072
46450650irq/118-QManpo5855-2110:52:072
46450650irq/118-QManpo5855-2110:52:072
1492999453cyclictest0-21swapper/120:27:591
1492999453cyclictest0-21swapper/120:27:591
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
1492999433cyclictest22270-21memory21:22:581
1492999433cyclictest22270-21memory21:22:581
1492999432cyclictest19133-21/usr/sbin/munin19:28:021
1492999432cyclictest19133-21/usr/sbin/munin19:28:021
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
1492999428cyclictest0-21swapper/119:52:591
1492999428cyclictest0-21swapper/119:52:591
1492999423cyclictest0-21swapper/121:49:251
1492999423cyclictest0-21swapper/121:49:251
1492999423cyclictest0-21swapper/121:37:581
1492999423cyclictest0-21swapper/121:37:581
1492999423cyclictest0-21swapper/121:37:581
1492999423cyclictest0-21swapper/120:47:361
1492999423cyclictest0-21swapper/120:47:361
1492999423cyclictest0-21swapper/120:47:361
46650410irq/116-QManpo8929-2110:48:553
46650410irq/116-QManpo8929-2110:48:553
46650410irq/116-QManpo8929-2110:48:553
1492999413cyclictest0-21swapper/121:46:301
1492999413cyclictest0-21swapper/121:46:301
1492999413cyclictest0-21swapper/121:46:301
1492999413cyclictest0-21swapper/121:33:031
1492999413cyclictest0-21swapper/121:33:031
1492999413cyclictest0-21swapper/121:33:031
1492999413cyclictest0-21swapper/121:32:221
1492999413cyclictest0-21swapper/121:32:221
1492999413cyclictest0-21swapper/121:32:221
1492999412cyclictest5169-21/usr/sbin/munin20:32:541
1492999412cyclictest5169-21/usr/sbin/munin20:32:541
14929994114cyclictest18147-21meminfo19:22:581
14929994114cyclictest18147-21meminfo19:22:581
71400rcu_preempt0-21swapper/020:27:020
71400rcu_preempt0-21swapper/020:27:020
71400rcu_preempt0-21swapper/020:27:020
1492999404cyclictest0-21swapper/119:47:461
1492999404cyclictest0-21swapper/119:47:461
1492999403cyclictest0-21swapper/121:02:501
1492999403cyclictest0-21swapper/121:02:501
1492999403cyclictest0-21swapper/121:02:501
1492999403cyclictest0-21swapper/119:43:071
1492999403cyclictest0-21swapper/119:43:071
1492999403cyclictest0-21swapper/119:12:581
1492999403cyclictest0-21swapper/119:12:581
1492999401cyclictest0-21swapper/121:17:471
1492999401cyclictest0-21swapper/121:17:471
14929994015cyclictest6244-21aten_r4power_cu20:37:491
14929994015cyclictest6244-21aten_r4power_cu20:37:491
14929994015cyclictest6244-21aten_r4power_cu20:37:491
71390rcu_preempt26501-1kworker/2:0H21:48:022
71390rcu_preempt26501-1kworker/2:0H21:48:022
46250390irq/120-QManpo14798-2110:48:551
46250390irq/120-QManpo14798-2110:48:551
46050390irq/122-QManpo7476-2110:48:550
46050390irq/122-QManpo7476-2110:48:550
46050390irq/122-QManpo7476-2110:48:550
1492999393cyclictest0-21swapper/120:13:031
1492999393cyclictest0-21swapper/120:13:031
1492999392cyclictest1959-21runrttasks19:35:151
1492999392cyclictest1959-21runrttasks19:35:151
1492999392cyclictest18591-21ssh21:17:191
1492999392cyclictest18591-21ssh21:17:191
1492999392cyclictest18591-21ssh21:17:191
1492999392cyclictest0-21swapper/119:42:371
1492999392cyclictest0-21swapper/119:42:371
14929993915cyclictest14794-21diskstats21:07:531
14929993915cyclictest14794-21diskstats21:07:531
14929993914cyclictest27496-21aten_r4power_cu19:57:471
14929993914cyclictest27496-21aten_r4power_cu19:57:471
14929993912cyclictest12043-21if_eth320:57:531
14929993912cyclictest12043-21if_eth320:57:531
14929993912cyclictest12043-21if_eth320:57:531
71380rcu_preempt6040-21ls22:42:351
71380rcu_preempt6040-21ls22:42:351
71380rcu_preempt6040-21ls22:42:351
71380rcu_preempt6040-21ls22:42:351
71380rcu_preempt0-21swapper/120:52:571
71380rcu_preempt0-21swapper/120:52:571
71380rcu_preempt0-21swapper/120:04:001
71380rcu_preempt0-21swapper/120:04:001
71380rcu_preempt0-21swapper/120:04:001
71380rcu_preempt0-21swapper/021:43:130
71380rcu_preempt0-21swapper/021:43:130
71380rcu_preempt0-21swapper/021:43:130
71380rcu_preempt0-21swapper/019:49:130
71380rcu_preempt0-21swapper/019:49:130
71380rcu_preempt0-21swapper/019:12:560
71380rcu_preempt0-21swapper/019:12:560
1492999383cyclictest0-21swapper/120:26:381
1492999383cyclictest0-21swapper/120:26:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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