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2025-12-08 - 07:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Dec 08, 2025 00:54:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71730rcu_preempt0-21swapper/200:51:052
71730rcu_preempt0-21swapper/200:51:052
71670rcu_preempt0-21swapper/223:15:342
71670rcu_preempt0-21swapper/223:15:342
71490rcu_preempt0-21swapper/023:01:120
71490rcu_preempt0-21swapper/023:01:120
71460rcu_preempt0-21swapper/223:18:492
71460rcu_preempt0-21swapper/223:18:492
26136994624cyclictest30275-21diskstats23:43:103
26136994624cyclictest30275-21diskstats23:43:103
71450rcu_preempt0-21swapper/200:05:512
71450rcu_preempt0-21swapper/200:05:512
71450rcu_preempt0-21swapper/200:05:512
71450rcu_preempt0-21swapper/022:39:090
71450rcu_preempt0-21swapper/022:39:090
2613699454cyclictest0-21swapper/321:03:163
2613699454cyclictest0-21swapper/321:03:163
71440rcu_preempt0-21swapper/123:33:441
71440rcu_preempt0-21swapper/123:33:441
71440rcu_preempt0-21swapper/100:49:551
71440rcu_preempt0-21swapper/100:49:551
2613699444cyclictest0-21swapper/322:25:103
2613699444cyclictest0-21swapper/322:25:103
2613699443cyclictest15164-21users00:13:223
2613699443cyclictest15164-21users00:13:223
26136994417cyclictest22516-21apt-get00:28:073
26136994417cyclictest22516-21apt-get00:28:073
2613699435cyclictest25394-21diskstats00:33:123
2613699435cyclictest25394-21diskstats00:33:123
2613699435cyclictest25394-21diskstats00:33:123
2613699434cyclictest0-21swapper/322:48:183
2613699434cyclictest0-21swapper/322:48:183
2613699434cyclictest0-21swapper/321:13:173
2613699434cyclictest0-21swapper/321:13:173
2613699432cyclictest5052-21df_inode21:58:113
2613699432cyclictest5052-21df_inode21:58:113
2613699432cyclictest10634-21df_inode01:08:113
2613699432cyclictest10634-21df_inode01:08:113
71420rcu_preempt0-21swapper/000:19:290
71420rcu_preempt0-21swapper/000:19:290
71420rcu_preempt0-21swapper/000:00:380
71420rcu_preempt0-21swapper/000:00:380
2613699424cyclictest0-21swapper/320:28:053
2613699424cyclictest0-21swapper/320:28:053
2613699424cyclictest0-21swapper/300:08:243
2613699424cyclictest0-21swapper/300:08:243
2613699422cyclictest18299-21ntp_states21:08:213
2613699422cyclictest18299-21ntp_states21:08:213
2613699422cyclictest17558-21ntp_states00:18:183
2613699422cyclictest17558-21ntp_states00:18:183
2613699421cyclictest21486-21diskstats22:28:103
2613699421cyclictest21486-21diskstats22:28:103
71410rcu_preempt0-21swapper/321:53:333
71410rcu_preempt0-21swapper/321:53:333
71410rcu_preempt0-21swapper/123:39:061
71410rcu_preempt0-21swapper/123:39:061
71410rcu_preempt0-21swapper/023:29:150
71410rcu_preempt0-21swapper/023:29:150
2613699414cyclictest0-21swapper/323:42:563
2613699414cyclictest0-21swapper/323:42:563
2613699414cyclictest0-21swapper/323:23:243
2613699414cyclictest0-21swapper/323:23:243
2613699414cyclictest0-21swapper/300:47:523
2613699414cyclictest0-21swapper/300:47:523
2613699414cyclictest0-21swapper/300:23:233
2613699414cyclictest0-21swapper/300:23:233
2613699413cyclictest0-21swapper/323:48:153
2613699413cyclictest0-21swapper/323:48:153
2613699413cyclictest0-21swapper/321:43:073
2613699413cyclictest0-21swapper/321:43:073
2613699413cyclictest0-21swapper/321:40:443
2613699413cyclictest0-21swapper/321:40:443
2613699413cyclictest0-21swapper/321:40:443
2613699413cyclictest0-21swapper/320:23:083
2613699413cyclictest0-21swapper/320:23:083
2613699413cyclictest0-21swapper/300:03:103
2613699413cyclictest0-21swapper/300:03:103
2613699413cyclictest0-21swapper/300:03:103
2613699412cyclictest5985-21ntp_states00:58:193
2613699412cyclictest5985-21ntp_states00:58:193
2613699412cyclictest3295-21memory00:53:183
2613699412cyclictest3295-21memory00:53:183
2613699412cyclictest27132-21memory22:38:163
2613699412cyclictest27132-21memory22:38:163
2613699412cyclictest16152-21cut23:17:553
2613699412cyclictest16152-21cut23:17:553
2613699412cyclictest15677-21ls22:17:573
2613699412cyclictest15677-21ls22:17:573
2613699412cyclictest11150-21irqstats23:08:133
2613699412cyclictest11150-21irqstats23:08:133
2613699412cyclictest10771-21latency_hist23:07:583
2613699411cyclictest23271-21latency_hist21:27:553
2613699411cyclictest23271-21latency_hist21:27:553
2613699411cyclictest0-21swapper/322:18:063
2613699411cyclictest0-21swapper/322:18:063
2613699411cyclictest0-21swapper/322:18:063
71400rcu_preempt32099-21ssh22:47:571
71400rcu_preempt32099-21ssh22:47:571
71400rcu_preempt0-21swapper/023:17:010
71400rcu_preempt0-21swapper/023:17:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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