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2026-07-16 - 20:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Jul 16, 2026 12:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71450rcu_preempt32256-21latency_hist11:29:060
71450rcu_preempt32256-21latency_hist11:29:060
71450rcu_preempt32256-21latency_hist11:29:060
46050440irq/122-QManpo27135-2110:48:550
46050440irq/122-QManpo27135-2110:48:550
46050440irq/122-QManpo27135-2110:48:550
71430rcu_preempt0-21swapper/012:34:260
71430rcu_preempt0-21swapper/012:34:260
71430rcu_preempt0-21swapper/012:34:260
46450430irq/118-QManpo27141-2110:48:552
46450430irq/118-QManpo27141-2110:48:552
46450430irq/118-QManpo27141-2110:48:552
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
71410rcu_preempt0-21swapper/212:10:462
71410rcu_preempt0-21swapper/212:10:462
46250410irq/120-QManpo26108-2110:48:551
46250410irq/120-QManpo26108-2110:48:551
46250410irq/120-QManpo26108-2110:48:551
46050410irq/122-QManpo14790-210
46050410irq/122-QManpo14790-210
71400rcu_preempt3865-21/usr/sbin/munin07:44:242
71400rcu_preempt3865-21/usr/sbin/munin07:44:242
71400rcu_preempt0-21swapper/210:21:002
71400rcu_preempt0-21swapper/210:21:002
71400rcu_preempt0-21swapper/210:21:002
71400rcu_preempt0-21swapper/210:21:002
163202400sleep116112-1kworker/1:2H10:58:221
163202400sleep116112-1kworker/1:2H10:58:221
71390rcu_preempt0-21swapper/212:21:132
71390rcu_preempt0-21swapper/212:21:132
71390rcu_preempt0-21swapper/212:21:132
71390rcu_preempt0-21swapper/212:14:052
71390rcu_preempt0-21swapper/212:14:052
71390rcu_preempt0-21swapper/212:14:052
71390rcu_preempt0-21swapper/208:45:442
71390rcu_preempt0-21swapper/208:45:442
71390rcu_preempt0-21swapper/012:27:400
71390rcu_preempt0-21swapper/012:27:400
71390rcu_preempt0-21swapper/012:27:400
46050390irq/122-QManpo3093-2110:48:550
46050390irq/122-QManpo3093-2110:48:550
71380rcu_preempt7840-21ssh10:40:422
71380rcu_preempt7840-21ssh10:40:422
71380rcu_preempt7840-21ssh10:40:422
71380rcu_preempt27059-21cat11:19:000
71380rcu_preempt27059-21cat11:19:000
71380rcu_preempt27059-21cat11:19:000
71380rcu_preempt11881-1kworker/0:1H12:08:180
71380rcu_preempt11881-1kworker/0:1H12:08:180
71380rcu_preempt0-21swapper/210:46:332
71380rcu_preempt0-21swapper/210:46:332
71380rcu_preempt0-21swapper/009:49:230
71380rcu_preempt0-21swapper/009:49:230
71380rcu_preempt0-21swapper/009:49:230
71380rcu_preempt0-21swapper/008:47:560
71380rcu_preempt0-21swapper/008:47:560
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
1599380migration/016781-21runrttasks09:55:090
1599380migration/016781-21runrttasks09:55:090
1599380migration/016781-21runrttasks09:55:090
71370rcu_preempt1959-21runrttasks10:12:582
71370rcu_preempt1959-21runrttasks10:12:582
71370rcu_preempt1959-21runrttasks10:12:582
71370rcu_preempt15165-21sh09:52:582
71370rcu_preempt15165-21sh09:52:582
71370rcu_preempt15165-21sh09:52:582
71370rcu_preempt0-21swapper/212:32:492
71370rcu_preempt0-21swapper/212:32:492
71370rcu_preempt0-21swapper/212:24:072
71370rcu_preempt0-21swapper/212:24:072
71370rcu_preempt0-21swapper/212:24:072
71370rcu_preempt0-21swapper/211:57:442
71370rcu_preempt0-21swapper/211:57:442
71370rcu_preempt0-21swapper/211:57:442
71370rcu_preempt0-21swapper/211:50:032
71370rcu_preempt0-21swapper/211:50:032
71370rcu_preempt0-21swapper/211:40:022
71370rcu_preempt0-21swapper/211:40:022
71370rcu_preempt0-21swapper/211:40:022
71370rcu_preempt0-21swapper/211:23:452
71370rcu_preempt0-21swapper/211:23:452
71370rcu_preempt0-21swapper/211:23:452
71370rcu_preempt0-21swapper/207:29:062
71370rcu_preempt0-21swapper/207:29:062
71370rcu_preempt0-21swapper/012:17:110
71370rcu_preempt0-21swapper/012:17:110
71370rcu_preempt0-21swapper/012:17:110
71370rcu_preempt0-21swapper/011:38:590
71370rcu_preempt0-21swapper/011:38:590
71370rcu_preempt0-21swapper/011:10:590
71370rcu_preempt0-21swapper/011:10:590
71370rcu_preempt0-21swapper/011:10:590
71370rcu_preempt0-21swapper/010:48:460
71370rcu_preempt0-21swapper/010:48:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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