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2026-07-23 - 19:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Jul 23, 2026 12:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71770rcu_preempt0-21swapper/108:29:251
71770rcu_preempt0-21swapper/108:29:251
46050480irq/122-QManpo26842-2110:48:550
46050480irq/122-QManpo26842-2110:48:550
71430rcu_preempt0-21swapper/309:44:473
71430rcu_preempt0-21swapper/309:44:473
71430rcu_preempt0-21swapper/309:44:473
2714799433cyclictest0-21swapper/312:03:043
2714799433cyclictest0-21swapper/312:03:043
2714799433cyclictest0-21swapper/312:03:043
2714799433cyclictest0-21swapper/308:59:203
2714799433cyclictest0-21swapper/308:59:203
27147994318cyclictest0-21swapper/310:44:203
27147994318cyclictest0-21swapper/310:44:203
27147994318cyclictest0-21swapper/310:44:203
27147994218cyclictest0-21swapper/311:56:483
27147994218cyclictest0-21swapper/311:56:483
27147994218cyclictest0-21swapper/311:56:483
71410rcu_preempt0-21swapper/010:59:040
71410rcu_preempt0-21swapper/010:59:040
71410rcu_preempt0-21swapper/010:59:040
71410rcu_preempt0-21swapper/010:36:520
71410rcu_preempt0-21swapper/010:36:520
71410rcu_preempt0-21swapper/010:36:520
2714799413cyclictest0-21swapper/311:48:113
2714799413cyclictest0-21swapper/311:48:113
2714799413cyclictest0-21swapper/311:48:113
71400rcu_preempt0-21swapper/208:29:332
71400rcu_preempt0-21swapper/208:29:332
71400rcu_preempt0-21swapper/110:29:021
71400rcu_preempt0-21swapper/110:29:021
71400rcu_preempt0-21swapper/110:29:021
71400rcu_preempt0-21swapper/011:07:050
71400rcu_preempt0-21swapper/011:07:050
71400rcu_preempt0-21swapper/011:07:050
71400rcu_preempt0-21swapper/011:07:050
2714799403cyclictest0-21swapper/308:44:293
2714799403cyclictest0-21swapper/308:44:293
2714799403cyclictest0-21swapper/308:44:293
71390rcu_preempt0-21swapper/312:10:223
71390rcu_preempt0-21swapper/312:10:223
71390rcu_preempt0-21swapper/110:49:161
71390rcu_preempt0-21swapper/110:49:161
71390rcu_preempt0-21swapper/110:49:161
71390rcu_preempt0-21swapper/109:43:141
71390rcu_preempt0-21swapper/109:43:141
71390rcu_preempt0-21swapper/012:06:220
71390rcu_preempt0-21swapper/012:06:220
71390rcu_preempt0-21swapper/012:02:560
71390rcu_preempt0-21swapper/012:02:560
71390rcu_preempt0-21swapper/012:02:560
71390rcu_preempt0-21swapper/011:57:570
71390rcu_preempt0-21swapper/011:57:570
71390rcu_preempt0-21swapper/011:57:570
71390rcu_preempt0-21swapper/009:14:260
71390rcu_preempt0-21swapper/009:14:260
71390rcu_preempt0-21swapper/008:29:410
71390rcu_preempt0-21swapper/008:29:410
71380rcu_preempt23068-1kworker/2:2H10:11:192
71380rcu_preempt23068-1kworker/2:2H10:11:192
71380rcu_preempt20017-21mailstats11:04:321
71380rcu_preempt20017-21mailstats11:04:321
71380rcu_preempt20017-21mailstats11:04:321
71380rcu_preempt20017-21mailstats11:04:321
71380rcu_preempt0-21swapper/309:19:303
71380rcu_preempt0-21swapper/309:19:303
71380rcu_preempt0-21swapper/211:57:112
71380rcu_preempt0-21swapper/211:57:112
71380rcu_preempt0-21swapper/211:57:112
71380rcu_preempt0-21swapper/211:51:532
71380rcu_preempt0-21swapper/211:51:532
71380rcu_preempt0-21swapper/211:51:532
71380rcu_preempt0-21swapper/211:06:412
71380rcu_preempt0-21swapper/211:06:412
71380rcu_preempt0-21swapper/211:06:412
71380rcu_preempt0-21swapper/211:06:412
71380rcu_preempt0-21swapper/208:56:212
71380rcu_preempt0-21swapper/208:56:212
71380rcu_preempt0-21swapper/208:56:212
71380rcu_preempt0-21swapper/109:20:451
71380rcu_preempt0-21swapper/109:20:451
71380rcu_preempt0-21swapper/108:26:571
71380rcu_preempt0-21swapper/108:26:571
71380rcu_preempt0-21swapper/012:11:200
71380rcu_preempt0-21swapper/012:11:200
71380rcu_preempt0-21swapper/010:27:020
71380rcu_preempt0-21swapper/010:27:020
71380rcu_preempt0-21swapper/010:27:020
71380rcu_preempt0-21swapper/010:05:280
71380rcu_preempt0-21swapper/010:05:280
71380rcu_preempt0-21swapper/010:05:280
71380rcu_preempt0-21swapper/009:39:110
71380rcu_preempt0-21swapper/009:39:110
71380rcu_preempt0-21swapper/009:39:110
71380rcu_preempt0-21swapper/009:32:300
71380rcu_preempt0-21swapper/009:32:300
71380rcu_preempt0-21swapper/007:23:360
71380rcu_preempt0-21swapper/007:23:360
46650380irq/116-QManpo0-2110:48:553
46650380irq/116-QManpo0-2110:48:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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