You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-26 - 07:12
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Dec 26, 2025 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71810rcu_preempt0-21swapper/123:09:391
71810rcu_preempt0-21swapper/123:09:391
71560rcu_preempt0-21swapper/222:05:582
71560rcu_preempt0-21swapper/222:05:582
71550rcu_preempt28838-21sh21:50:450
71550rcu_preempt28838-21sh21:50:450
391999534cyclictest0-21swapper/021:10:500
391999534cyclictest0-21swapper/021:10:500
3919995217cyclictest0-21swapper/020:20:420
3919995217cyclictest0-21swapper/020:20:420
71510rcu_preempt28014-21copy21:50:222
71510rcu_preempt28014-21copy21:50:222
71510rcu_preempt28014-21copy21:50:222
391999514cyclictest0-21swapper/021:32:110
391999514cyclictest0-21swapper/021:32:110
391999513cyclictest0-21swapper/022:00:160
391999513cyclictest0-21swapper/022:00:160
391999513cyclictest0-21swapper/022:00:160
391999513cyclictest0-21swapper/000:30:540
391999513cyclictest0-21swapper/000:30:540
391999513cyclictest0-21swapper/000:30:540
391999503cyclictest0-21swapper/023:50:400
391999503cyclictest0-21swapper/023:50:400
391999503cyclictest0-21swapper/023:03:100
391999503cyclictest0-21swapper/023:03:100
391999503cyclictest0-21swapper/022:05:350
391999503cyclictest0-21swapper/022:05:350
391999503cyclictest0-21swapper/000:20:340
391999503cyclictest0-21swapper/000:20:340
391999503cyclictest0-21swapper/000:20:340
391999503cyclictest0-21swapper/000:05:170
391999503cyclictest0-21swapper/000:05:170
3919995017cyclictest0-21swapper/022:45:460
3919995017cyclictest0-21swapper/022:45:460
71490rcu_preempt0-21swapper/122:56:031
71490rcu_preempt0-21swapper/122:56:031
71490rcu_preempt0-21swapper/122:56:031
391999494cyclictest0-21swapper/023:40:180
391999494cyclictest0-21swapper/023:40:180
391999494cyclictest0-21swapper/023:40:180
391999493cyclictest0-21swapper/023:47:190
391999493cyclictest0-21swapper/023:47:190
391999493cyclictest0-21swapper/023:24:140
391999493cyclictest0-21swapper/023:24:140
391999493cyclictest0-21swapper/023:24:140
391999493cyclictest0-21swapper/023:15:340
391999493cyclictest0-21swapper/023:15:340
391999493cyclictest0-21swapper/023:15:340
391999493cyclictest0-21swapper/022:17:360
391999493cyclictest0-21swapper/022:17:360
391999493cyclictest0-21swapper/022:17:360
391999493cyclictest0-21swapper/021:25:560
391999493cyclictest0-21swapper/021:25:560
391999493cyclictest0-21swapper/020:40:340
391999493cyclictest0-21swapper/020:40:340
391999493cyclictest0-21swapper/000:12:570
391999493cyclictest0-21swapper/000:12:570
391999493cyclictest0-21swapper/000:12:570
3919994915cyclictest0-21swapper/022:57:140
3919994915cyclictest0-21swapper/022:57:140
3919994915cyclictest0-21swapper/022:57:140
391999483cyclictest0-21swapper/022:11:010
391999483cyclictest0-21swapper/022:11:010
391999483cyclictest0-21swapper/021:23:400
391999483cyclictest0-21swapper/021:23:400
391999483cyclictest0-21swapper/021:23:400
391999483cyclictest0-21swapper/019:45:350
391999483cyclictest0-21swapper/019:45:350
391999483cyclictest0-21swapper/000:16:590
391999483cyclictest0-21swapper/000:16:590
391999463cyclictest0-21swapper/022:32:530
391999463cyclictest0-21swapper/022:32:530
71430rcu_preempt0-21swapper/223:33:572
71430rcu_preempt0-21swapper/223:33:572
71430rcu_preempt0-21swapper/100:06:441
71430rcu_preempt0-21swapper/100:06:441
71430rcu_preempt0-21swapper/100:06:441
71410rcu_preempt15522-21diskmemload23:20:391
71410rcu_preempt15522-21diskmemload23:20:391
71410rcu_preempt15522-21diskmemload23:20:391
391999413cyclictest0-21swapper/023:41:350
391999413cyclictest0-21swapper/023:41:350
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
46050390irq/122-QManpo20672-2110:48:550
46050390irq/122-QManpo20672-2110:48:550
46050390irq/122-QManpo20672-2110:48:550
71380rcu_preempt28103-21chrt20:35:442
71380rcu_preempt28103-21chrt20:35:442
71380rcu_preempt28103-21chrt20:35:442
71380rcu_preempt19992-21sh00:25:302
71380rcu_preempt19992-21sh00:25:302
71380rcu_preempt19992-21sh00:25:302
71380rcu_preempt19530-1kworker/0:0H22:40:290
71380rcu_preempt19530-1kworker/0:0H22:40:290
71380rcu_preempt19530-1kworker/0:0H22:40:290
71380rcu_preempt0-21swapper/200:10:302
71380rcu_preempt0-21swapper/200:10:302
71380rcu_preempt0-21swapper/200:10:302
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional