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2026-02-04 - 23:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Feb 04, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71530rcu_preempt0-21swapper/012:28:360
71530rcu_preempt0-21swapper/012:28:360
71460rcu_preempt20465-21kworker/2:209:41:072
71460rcu_preempt20465-21kworker/2:209:41:072
71460rcu_preempt20465-21kworker/2:209:41:072
71450rcu_preempt0-21swapper/009:56:240
71450rcu_preempt0-21swapper/009:56:240
450599428cyclictest0-21swapper/010:11:170
450599428cyclictest0-21swapper/010:11:170
4505994119cyclictest22398-21fw_packets12:31:190
4505994119cyclictest22398-21fw_packets12:31:190
71400rcu_preempt0-21swapper/109:51:391
71400rcu_preempt0-21swapper/109:51:391
71400rcu_preempt0-21swapper/109:51:391
71400rcu_preempt0-21swapper/011:42:200
71400rcu_preempt0-21swapper/011:42:200
71390rcu_preempt14468-21df_inode09:26:171
71390rcu_preempt14468-21df_inode09:26:171
71390rcu_preempt0-21swapper/107:51:141
71390rcu_preempt0-21swapper/107:51:141
71390rcu_preempt0-21swapper/012:18:180
71390rcu_preempt0-21swapper/012:18:180
71390rcu_preempt0-21swapper/012:18:180
71390rcu_preempt0-21swapper/011:55:360
71390rcu_preempt0-21swapper/011:55:360
71390rcu_preempt0-21swapper/008:31:170
71390rcu_preempt0-21swapper/008:31:170
71390rcu_preempt0-21swapper/008:31:170
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
71380rcu_preempt14026-21crond09:26:010
71380rcu_preempt14026-21crond09:26:010
71380rcu_preempt0-21swapper/312:30:333
71380rcu_preempt0-21swapper/312:30:333
71380rcu_preempt0-21swapper/211:22:202
71380rcu_preempt0-21swapper/211:22:202
71380rcu_preempt0-21swapper/112:36:071
71380rcu_preempt0-21swapper/112:36:071
71380rcu_preempt0-21swapper/112:04:571
71380rcu_preempt0-21swapper/112:04:571
71380rcu_preempt0-21swapper/011:03:450
71380rcu_preempt0-21swapper/011:03:450
71380rcu_preempt0-21swapper/011:03:450
71380rcu_preempt0-21swapper/009:42:230
71380rcu_preempt0-21swapper/009:42:230
71370rcu_preempt30882-21copy08:46:110
71370rcu_preempt30882-21copy08:46:110
71370rcu_preempt0-21swapper/211:16:052
71370rcu_preempt0-21swapper/211:16:052
71370rcu_preempt0-21swapper/211:16:052
71370rcu_preempt0-21swapper/209:48:112
71370rcu_preempt0-21swapper/209:48:112
71370rcu_preempt0-21swapper/207:24:002
71370rcu_preempt0-21swapper/207:24:002
71370rcu_preempt0-21swapper/207:24:002
71370rcu_preempt0-21swapper/012:37:330
71370rcu_preempt0-21swapper/012:37:330
71370rcu_preempt0-21swapper/012:37:330
71370rcu_preempt0-21swapper/012:13:260
71370rcu_preempt0-21swapper/012:13:260
71370rcu_preempt0-21swapper/012:13:260
71370rcu_preempt0-21swapper/011:48:360
71370rcu_preempt0-21swapper/011:48:360
71370rcu_preempt0-21swapper/010:58:000
71370rcu_preempt0-21swapper/010:58:000
71370rcu_preempt0-21swapper/010:58:000
71370rcu_preempt0-21swapper/010:55:140
71370rcu_preempt0-21swapper/010:55:140
71370rcu_preempt0-21swapper/010:37:110
71370rcu_preempt0-21swapper/010:37:110
71370rcu_preempt0-21swapper/010:02:310
71370rcu_preempt0-21swapper/010:02:310
71370rcu_preempt0-21swapper/010:02:310
71370rcu_preempt0-21swapper/008:46:050
71370rcu_preempt0-21swapper/008:46:050
46650370irq/116-QManpo0-2110:48:553
46650370irq/116-QManpo0-2110:48:553
4505993717cyclictest13371-21diskstats10:21:180
4505993717cyclictest13371-21diskstats10:21:180
4505993716cyclictest5412-21munin-run09:11:030
4505993716cyclictest5412-21munin-run09:11:030
4505993716cyclictest24467-21meminfo08:21:260
4505993716cyclictest24467-21meminfo08:21:260
4505993716cyclictest21513-21munin-run10:36:020
4505993716cyclictest21513-21munin-run10:36:020
4505993715cyclictest16858-21cat12:21:230
4505993715cyclictest16858-21cat12:21:230
4505993712cyclictest18473-21meminfo11:26:230
4505993712cyclictest18473-21meminfo11:26:230
4505993712cyclictest18473-21meminfo11:26:230
4505993712cyclictest0-21swapper/007:26:140
4505993712cyclictest0-21swapper/007:26:140
71360rcu_preempt4366-21taskset07:10:062
71360rcu_preempt4366-21taskset07:10:062
71360rcu_preempt31545-21df09:56:162
71360rcu_preempt31545-21df09:56:162
71360rcu_preempt0-21swapper/312:07:483
71360rcu_preempt0-21swapper/312:07:483
71360rcu_preempt0-21swapper/312:07:483
71360rcu_preempt0-21swapper/212:11:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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