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2026-05-13 - 07:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed May 13, 2026 00:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3102821180chrt46050irq/122-QMan10:48:550
3102821180chrt46050irq/122-QMan10:48:550
71520rcu_preempt9930-1kworker/3:2H19:12:543
71520rcu_preempt9930-1kworker/3:2H19:12:543
71520rcu_preempt30744-21ssh21:28:011
71520rcu_preempt30744-21ssh21:28:011
71520rcu_preempt30744-21ssh21:28:011
71510rcu_preempt0-21swapper/000:15:400
71510rcu_preempt0-21swapper/000:15:400
71470rcu_preempt28069-21apt-get19:38:093
71470rcu_preempt28069-21apt-get19:38:093
46050470irq/122-QManpo1408-2110:48:550
46050470irq/122-QManpo1408-2110:48:550
71460rcu_preempt1260-21apt-get19:58:102
71460rcu_preempt1260-21apt-get19:58:102
71450rcu_preempt9657-21apt-get20:28:091
71450rcu_preempt9657-21apt-get20:28:091
71450rcu_preempt9657-21apt-get20:28:091
71450rcu_preempt0-21swapper/119:10:211
71450rcu_preempt0-21swapper/119:10:211
71440rcu_preempt0-21swapper/000:12:540
71440rcu_preempt0-21swapper/000:12:540
71440rcu_preempt0-21swapper/000:12:540
46050440irq/122-QManpo12673-210
46050440irq/122-QManpo12673-210
2125699447cyclictest32616-21ssh23:29:483
2125699447cyclictest32616-21ssh23:29:483
2125699447cyclictest32616-21ssh23:29:483
2125699443cyclictest0-21swapper/323:08:273
2125699443cyclictest0-21swapper/323:08:273
46450430irq/118-QManpo12021-2110:48:552
46450430irq/118-QManpo12021-2110:48:552
2125699439cyclictest13365-21diskmemload21:55:113
2125699439cyclictest13365-21diskmemload21:55:113
2125699439cyclictest13365-21diskmemload21:55:113
2125699435cyclictest0-21swapper/321:43:013
2125699435cyclictest0-21swapper/321:43:013
2125699435cyclictest0-21swapper/321:43:013
2125699434cyclictest0-21swapper/300:28:163
2125699434cyclictest0-21swapper/300:28:163
2125699434cyclictest0-21swapper/300:28:163
71420rcu_preempt21887-1kworker/0:1H21:34:470
71420rcu_preempt21887-1kworker/0:1H21:34:470
71420rcu_preempt0-21swapper/122:35:291
71420rcu_preempt0-21swapper/122:35:291
71420rcu_preempt0-21swapper/122:35:291
71420rcu_preempt0-21swapper/022:04:500
71420rcu_preempt0-21swapper/022:04:500
71420rcu_preempt0-21swapper/021:30:250
71420rcu_preempt0-21swapper/021:30:250
71420rcu_preempt0-21swapper/021:30:250
2125699424cyclictest0-21swapper/323:53:143
2125699424cyclictest0-21swapper/323:53:143
2125699424cyclictest0-21swapper/300:19:413
2125699424cyclictest0-21swapper/300:19:413
2125699424cyclictest0-21swapper/300:19:413
2125699423cyclictest23746-21ntp_states00:13:213
2125699423cyclictest23746-21ntp_states00:13:213
2125699423cyclictest0-21swapper/323:48:043
2125699423cyclictest0-21swapper/323:48:043
2125699423cyclictest0-21swapper/323:48:043
2125699423cyclictest0-21swapper/323:33:223
2125699423cyclictest0-21swapper/323:33:223
2125699423cyclictest0-21swapper/323:33:223
2125699421cyclictest31265-21df_inode19:48:053
2125699421cyclictest31265-21df_inode19:48:053
71410rcu_preempt31310-21/usr/sbin/munin21:28:182
71410rcu_preempt31310-21/usr/sbin/munin21:28:182
71410rcu_preempt31310-21/usr/sbin/munin21:28:182
71410rcu_preempt0-21swapper/023:27:570
71410rcu_preempt0-21swapper/023:27:570
71410rcu_preempt0-21swapper/022:44:100
71410rcu_preempt0-21swapper/022:44:100
2125699414cyclictest0-21swapper/300:38:223
2125699414cyclictest0-21swapper/300:38:223
2125699414cyclictest0-21swapper/300:12:553
2125699414cyclictest0-21swapper/300:12:553
2125699414cyclictest0-21swapper/300:12:553
2125699413cyclictest4473-21diskstats20:08:053
2125699413cyclictest4473-21diskstats20:08:053
2125699413cyclictest0-21swapper/323:43:033
2125699413cyclictest0-21swapper/323:43:033
2125699413cyclictest0-21swapper/323:03:093
2125699413cyclictest0-21swapper/323:03:093
2125699413cyclictest0-21swapper/322:59:503
2125699413cyclictest0-21swapper/322:59:503
2125699413cyclictest0-21swapper/321:34:073
2125699413cyclictest0-21swapper/321:34:073
2125699413cyclictest0-21swapper/321:27:013
2125699413cyclictest0-21swapper/321:27:013
2125699413cyclictest0-21swapper/321:18:263
2125699413cyclictest0-21swapper/321:18:263
2125699413cyclictest0-21swapper/319:28:073
2125699413cyclictest0-21swapper/319:28:073
2125699413cyclictest0-21swapper/300:23:303
2125699413cyclictest0-21swapper/300:23:303
2125699413cyclictest0-21swapper/300:23:303
2125699412cyclictest18320-21memory00:03:183
2125699412cyclictest18320-21memory00:03:183
2125699412cyclictest0-21swapper/323:42:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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