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2026-03-17 - 04:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Mar 17, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71700rcu_preempt0-21swapper/122:33:521
71700rcu_preempt0-21swapper/122:33:521
71490rcu_preempt3514-1kworker/0:2H00:25:390
71490rcu_preempt3514-1kworker/0:2H00:25:390
71490rcu_preempt3514-1kworker/0:2H00:25:390
71450rcu_preempt0-21swapper/100:24:521
71450rcu_preempt0-21swapper/100:24:521
71450rcu_preempt0-21swapper/100:24:521
71440rcu_preempt9369-21sendmail-msp21:44:441
71440rcu_preempt9369-21sendmail-msp21:44:441
71440rcu_preempt9369-21sendmail-msp21:44:441
46050440irq/122-QManpo24843-2110:48:550
46050440irq/122-QManpo24843-2110:48:550
46050440irq/122-QManpo24843-2110:48:550
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
71410rcu_preempt29051-1kworker/1:1H21:41:531
71410rcu_preempt29051-1kworker/1:1H21:41:531
71410rcu_preempt29051-1kworker/1:1H21:41:531
71410rcu_preempt10784-1kworker/2:1H21:43:142
71410rcu_preempt10784-1kworker/2:1H21:43:142
71410rcu_preempt10784-1kworker/2:1H21:43:142
71410rcu_preempt0-21swapper/122:22:291
71410rcu_preempt0-21swapper/122:22:291
46250410irq/120-QManpo23664-2110:48:551
46250410irq/120-QManpo23664-2110:48:551
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
23737994110cyclictest0-21swapper/120:43:001
23737994110cyclictest0-21swapper/120:43:001
71400rcu_preempt18001-21ssh23:52:062
71400rcu_preempt18001-21ssh23:52:062
71400rcu_preempt18001-21ssh23:52:062
23737994011cyclictest25180-21irqstats21:12:041
23737994011cyclictest25180-21irqstats21:12:041
23737994011cyclictest1256-21irqstats21:27:061
23737994011cyclictest1256-21irqstats21:27:061
23737994011cyclictest1256-21irqstats21:27:061
71390rcu_preempt9432-21taskset21:41:513
71390rcu_preempt9432-21taskset21:41:513
71390rcu_preempt9432-21taskset21:41:513
71390rcu_preempt0-21swapper/323:32:393
71390rcu_preempt0-21swapper/323:32:393
71390rcu_preempt0-21swapper/223:38:182
71390rcu_preempt0-21swapper/223:38:182
71390rcu_preempt0-21swapper/223:38:182
71390rcu_preempt0-21swapper/200:25:562
71390rcu_preempt0-21swapper/200:25:562
71390rcu_preempt0-21swapper/200:25:562
71390rcu_preempt0-21swapper/123:44:511
71390rcu_preempt0-21swapper/123:44:511
71390rcu_preempt0-21swapper/121:21:081
71390rcu_preempt0-21swapper/121:21:081
71390rcu_preempt0-21swapper/121:21:081
71390rcu_preempt0-21swapper/100:38:471
71390rcu_preempt0-21swapper/100:38:471
46050390irq/122-QManpo9350-2110:48:550
46050390irq/122-QManpo9350-2110:48:550
46050390irq/122-QManpo9350-2110:48:550
46050390irq/122-QManpo19091-2110:48:550
46050390irq/122-QManpo19091-2110:48:550
46050390irq/122-QManpo19091-2110:48:550
71380rcu_preempt4759-21ssh23:27:401
71380rcu_preempt4759-21ssh23:27:401
71380rcu_preempt24817-1kworker/1:1H00:29:021
71380rcu_preempt24817-1kworker/1:1H00:29:021
71380rcu_preempt0-21swapper/220:56:512
71380rcu_preempt0-21swapper/220:56:512
71380rcu_preempt0-21swapper/122:56:591
71380rcu_preempt0-21swapper/122:56:591
71380rcu_preempt0-21swapper/122:56:591
71380rcu_preempt0-21swapper/122:27:581
71380rcu_preempt0-21swapper/122:27:581
46050380irq/122-QManpo5566-2110:48:550
46050380irq/122-QManpo5566-2110:48:550
46050380irq/122-QManpo32513-2110:48:550
46050380irq/122-QManpo32513-2110:48:550
46050380irq/122-QManpo31615-2110:48:550
46050380irq/122-QManpo31615-2110:48:550
46050380irq/122-QManpo27862-2110:48:550
46050380irq/122-QManpo27862-2110:48:550
46050380irq/122-QManpo23268-2110:48:550
46050380irq/122-QManpo23268-2110:48:550
23737993816cyclictest22534-21/usr/sbin/munin21:02:111
23737993816cyclictest22534-21/usr/sbin/munin21:02:111
23737993816cyclictest22534-21/usr/sbin/munin21:02:111
23737993814cyclictest0-21swapper/123:51:561
23737993814cyclictest0-21swapper/123:51:561
23737993814cyclictest0-21swapper/123:51:561
1599380migration/028032-21sh22:14:150
1599380migration/028032-21sh22:14:150
71370rcu_preempt3338-21ssh23:26:162
71370rcu_preempt3338-21ssh23:26:162
71370rcu_preempt3338-21ssh23:26:162
71370rcu_preempt24759-21ssh22:08:113
71370rcu_preempt24759-21ssh22:08:113
71370rcu_preempt20507-21copy20:56:561
71370rcu_preempt20507-21copy20:56:561
71370rcu_preempt20507-21copy20:56:561
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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