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2026-01-07 - 11:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Jan 07, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71700rcu_preempt0-21swapper/123:01:581
71700rcu_preempt0-21swapper/123:01:581
71650rcu_preempt0-21swapper/123:25:281
71650rcu_preempt0-21swapper/123:25:281
71540rcu_preempt0-21swapper/323:07:533
71540rcu_preempt0-21swapper/323:07:533
71540rcu_preempt0-21swapper/323:07:533
71490rcu_preempt0-21swapper/221:21:182
71490rcu_preempt0-21swapper/221:21:182
46450480irq/118-QManpo8634-2110:48:552
46450480irq/118-QManpo8634-2110:48:552
967799463cyclictest0-21swapper/100:38:151
967799463cyclictest0-21swapper/100:38:151
71460rcu_preempt16409-21copy21:20:413
71460rcu_preempt16409-21copy21:20:413
9677994517cyclictest17027-21memory21:20:581
9677994517cyclictest17027-21memory21:20:581
71450rcu_preempt18731-21ssh21:24:170
71450rcu_preempt18731-21ssh21:24:170
71450rcu_preempt0-21swapper/021:25:530
71450rcu_preempt0-21swapper/021:25:530
967799442cyclictest18000-21diskstats23:15:471
967799442cyclictest18000-21diskstats23:15:471
967799442cyclictest18000-21diskstats23:15:471
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
967799433cyclictest0-21swapper/123:34:221
967799433cyclictest0-21swapper/123:34:221
9677994317cyclictest18402-21munin-run22:20:311
9677994317cyclictest18402-21munin-run22:20:311
9677994317cyclictest18402-21munin-run22:20:311
71430rcu_preempt0-21swapper/123:49:441
71430rcu_preempt0-21swapper/123:49:441
71430rcu_preempt0-21swapper/123:49:441
46250430irq/120-QManpo8628-2110:48:551
46250430irq/120-QManpo8628-2110:48:551
967799424cyclictest0-21swapper/121:51:241
967799424cyclictest0-21swapper/121:51:241
967799424cyclictest0-21swapper/121:51:241
967799423cyclictest0-21swapper/123:37:351
967799423cyclictest0-21swapper/123:37:351
967799423cyclictest0-21swapper/123:37:351
967799423cyclictest0-21swapper/122:10:461
967799423cyclictest0-21swapper/122:10:461
967799423cyclictest0-21swapper/119:25:461
967799423cyclictest0-21swapper/119:25:461
967799413cyclictest20179-21memory00:15:531
967799413cyclictest20179-21memory00:15:531
967799413cyclictest20179-21memory00:15:531
967799413cyclictest0-21swapper/123:52:221
967799413cyclictest0-21swapper/123:52:221
967799413cyclictest0-21swapper/123:52:221
967799413cyclictest0-21swapper/123:41:221
967799413cyclictest0-21swapper/123:41:221
967799413cyclictest0-21swapper/122:50:431
967799413cyclictest0-21swapper/122:50:431
967799413cyclictest0-21swapper/122:44:051
967799413cyclictest0-21swapper/122:44:051
967799413cyclictest0-21swapper/122:38:531
967799413cyclictest0-21swapper/122:38:531
967799413cyclictest0-21swapper/122:38:531
967799413cyclictest0-21swapper/121:05:301
967799413cyclictest0-21swapper/121:05:301
967799413cyclictest0-21swapper/119:10:451
967799413cyclictest0-21swapper/119:10:451
967799413cyclictest0-21swapper/119:10:451
967799413cyclictest0-21swapper/100:05:501
967799413cyclictest0-21swapper/100:05:501
967799413cyclictest0-21swapper/100:05:501
967799412cyclictest19916-21meminfo19:45:501
967799412cyclictest19916-21meminfo19:45:501
9677994115cyclictest23166-21ntp_states00:20:561
9677994115cyclictest23166-21ntp_states00:20:561
9677994113cyclictest23541-21munin-run20:00:311
9677994113cyclictest23541-21munin-run20:00:311
71410rcu_preempt0-21swapper/122:56:591
71410rcu_preempt0-21swapper/122:56:591
71410rcu_preempt0-21swapper/122:56:591
71410rcu_preempt0-21swapper/120:30:291
71410rcu_preempt0-21swapper/120:30:291
71410rcu_preempt0-21swapper/120:30:291
46050410irq/122-QManpo8274-210
46050410irq/122-QManpo8274-210
967799404cyclictest0-21swapper/119:40:581
967799404cyclictest0-21swapper/119:40:581
967799403cyclictest0-21swapper/123:25:561
967799403cyclictest0-21swapper/123:25:561
967799403cyclictest0-21swapper/122:45:481
967799403cyclictest0-21swapper/122:45:481
967799403cyclictest0-21swapper/122:20:531
967799403cyclictest0-21swapper/122:20:531
967799403cyclictest0-21swapper/121:57:551
967799403cyclictest0-21swapper/121:57:551
967799403cyclictest0-21swapper/121:57:551
967799403cyclictest0-21swapper/121:00:301
967799403cyclictest0-21swapper/121:00:301
967799403cyclictest0-21swapper/120:45:501
967799403cyclictest0-21swapper/120:45:501
967799403cyclictest0-21swapper/120:35:401
967799403cyclictest0-21swapper/120:35:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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