You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-24 - 22:09
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun May 24, 2026 12:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71520rcu_preempt1061-21kworker/1:110:28:151
71520rcu_preempt1061-21kworker/1:110:28:151
71520rcu_preempt1061-21kworker/1:110:28:151
71470rcu_preempt10055-21copy08:13:130
71470rcu_preempt10055-21copy08:13:130
111460rcuc/06638-1kworker/0:0H10:08:130
111460rcuc/06638-1kworker/0:0H10:08:130
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
71420rcu_preempt0-21swapper/310:28:083
71420rcu_preempt0-21swapper/310:28:083
71420rcu_preempt0-21swapper/310:28:083
71420rcu_preempt0-21swapper/009:25:020
71420rcu_preempt0-21swapper/009:25:020
46050420irq/122-QManpo28449-10
46050420irq/122-QManpo28449-10
46050420irq/122-QManpo28449-10
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
71410rcu_preempt6638-1kworker/0:0H09:52:290
71410rcu_preempt6638-1kworker/0:0H09:52:290
71410rcu_preempt6638-1kworker/0:0H09:52:290
71410rcu_preempt22415-1cat11:08:030
71410rcu_preempt22415-1cat11:08:030
71410rcu_preempt22415-1cat11:08:030
71410rcu_preempt21330-1kworker/2:0H10:04:392
71410rcu_preempt21330-1kworker/2:0H10:04:392
71410rcu_preempt21330-1kworker/2:0H10:04:392
71400rcu_preempt521-21sh12:29:470
71400rcu_preempt521-21sh12:29:470
71400rcu_preempt0-21swapper/011:13:520
71400rcu_preempt0-21swapper/011:13:520
71400rcu_preempt0-21swapper/011:13:520
71400rcu_preempt0-21swapper/007:38:240
71400rcu_preempt0-21swapper/007:38:240
71390rcu_preempt8620-21sh10:42:110
71390rcu_preempt8620-21sh10:42:110
71390rcu_preempt8620-21sh10:42:110
71390rcu_preempt0-21swapper/209:20:422
71390rcu_preempt0-21swapper/209:20:422
71390rcu_preempt0-21swapper/209:20:422
71390rcu_preempt0-21swapper/112:23:051
71390rcu_preempt0-21swapper/112:23:051
71390rcu_preempt0-21swapper/112:23:051
71390rcu_preempt0-21swapper/012:18:140
71390rcu_preempt0-21swapper/012:18:140
71390rcu_preempt0-21swapper/012:18:140
71390rcu_preempt0-21swapper/012:03:080
71390rcu_preempt0-21swapper/012:03:080
71390rcu_preempt0-21swapper/012:03:080
46050390irq/122-QManpo25458-2110:48:550
46050390irq/122-QManpo25458-2110:48:550
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
1599390migration/019022-21sh08:43:270
1599390migration/019022-21sh08:43:270
71380rcu_preempt18921-21apt-get12:03:150
71380rcu_preempt18921-21apt-get12:03:150
71380rcu_preempt10080-21grep08:13:053
71380rcu_preempt10080-21grep08:13:053
71380rcu_preempt0-21swapper/212:17:382
71380rcu_preempt0-21swapper/212:17:382
71380rcu_preempt0-21swapper/212:17:382
71380rcu_preempt0-21swapper/107:38:191
71380rcu_preempt0-21swapper/107:38:191
71380rcu_preempt0-21swapper/012:38:200
71380rcu_preempt0-21swapper/012:38:200
71380rcu_preempt0-21swapper/012:38:200
71380rcu_preempt0-21swapper/011:43:520
71380rcu_preempt0-21swapper/011:43:520
71380rcu_preempt0-21swapper/009:28:140
71380rcu_preempt0-21swapper/009:28:140
71380rcu_preempt0-21swapper/009:28:140
46250380irq/120-QManpo22591-2110:48:551
46250380irq/120-QManpo22591-2110:48:551
46250380irq/120-QManpo22591-2110:48:551
46050380irq/122-QManpo22134-2110:48:550
46050380irq/122-QManpo22134-2110:48:550
46050380irq/122-QManpo22134-2110:48:550
46050380irq/122-QManpo1830-2110:48:550
46050380irq/122-QManpo1830-2110:48:550
46050380irq/122-QManpo1830-2110:48:550
71370rcu_preempt29330-21ssh12:23:193
71370rcu_preempt29330-21ssh12:23:193
71370rcu_preempt29330-21ssh12:23:193
71370rcu_preempt19962-21cat11:03:072
71370rcu_preempt19962-21cat11:03:072
71370rcu_preempt0-21swapper/312:28:143
71370rcu_preempt0-21swapper/312:28:143
71370rcu_preempt0-21swapper/212:30:142
71370rcu_preempt0-21swapper/212:30:142
71370rcu_preempt0-21swapper/211:18:362
71370rcu_preempt0-21swapper/211:18:362
71370rcu_preempt0-21swapper/211:18:362
71370rcu_preempt0-21swapper/208:13:192
71370rcu_preempt0-21swapper/208:13:192
71370rcu_preempt0-21swapper/012:09:550
71370rcu_preempt0-21swapper/012:09:550
71370rcu_preempt0-21swapper/012:09:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional