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2026-06-30 - 17:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Jun 30, 2026 12:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71690rcu_preempt23053-21sendmail-msp11:09:070
71690rcu_preempt23053-21sendmail-msp11:09:070
46050520irq/122-QManpo16401-2110:48:550
46050520irq/122-QManpo16401-2110:48:550
46050520irq/122-QManpo16401-2110:48:550
71470rcu_preempt0-21swapper/010:35:320
71470rcu_preempt0-21swapper/010:35:320
71470rcu_preempt0-21swapper/010:35:320
71460rcu_preempt0-21swapper/212:28:552
71460rcu_preempt0-21swapper/212:28:552
71430rcu_preempt652-21sendmail-msp10:21:010
71430rcu_preempt652-21sendmail-msp10:21:010
71430rcu_preempt652-21sendmail-msp10:21:010
71430rcu_preempt0-21swapper/209:49:242
71430rcu_preempt0-21swapper/209:49:242
71430rcu_preempt0-21swapper/209:49:242
71430rcu_preempt0-21swapper/008:36:150
71430rcu_preempt0-21swapper/008:36:150
71420rcu_preempt16045-21copy09:08:510
71420rcu_preempt16045-21copy09:08:510
71410rcu_preempt1699migration/111:12:281
71410rcu_preempt1699migration/111:12:281
71400rcu_preempt652-21sendmail-msp09:49:220
71400rcu_preempt652-21sendmail-msp09:49:220
71400rcu_preempt652-21sendmail-msp09:49:220
71400rcu_preempt27287-1kworker/0:1H11:58:410
71400rcu_preempt27287-1kworker/0:1H11:58:410
71400rcu_preempt27287-1kworker/0:1H11:58:410
71400rcu_preempt19943-21latency_hist09:18:420
71400rcu_preempt19943-21latency_hist09:18:420
71400rcu_preempt19943-21latency_hist09:18:420
71400rcu_preempt0-21swapper/210:24:332
71400rcu_preempt0-21swapper/210:24:332
71400rcu_preempt0-21swapper/209:20:122
71400rcu_preempt0-21swapper/209:20:122
71400rcu_preempt0-21swapper/209:20:122
71400rcu_preempt0-21swapper/109:44:101
71400rcu_preempt0-21swapper/109:44:101
71400rcu_preempt0-21swapper/109:44:101
71400rcu_preempt0-21swapper/109:14:401
71400rcu_preempt0-21swapper/109:14:401
71400rcu_preempt0-21swapper/109:14:401
71400rcu_preempt0-21swapper/012:22:480
71400rcu_preempt0-21swapper/012:22:480
1599400migration/025016-21runrttasks10:29:460
1599400migration/025016-21runrttasks10:29:460
1599400migration/025016-21runrttasks10:29:460
71390rcu_preempt6430-21meminfo09:54:020
71390rcu_preempt6430-21meminfo09:54:020
71390rcu_preempt6430-21meminfo09:54:020
71390rcu_preempt0-21swapper/309:56:283
71390rcu_preempt0-21swapper/309:56:283
71390rcu_preempt0-21swapper/309:56:283
71390rcu_preempt0-21swapper/112:09:231
71390rcu_preempt0-21swapper/112:09:231
71390rcu_preempt0-21swapper/112:09:231
71390rcu_preempt0-21swapper/112:03:291
71390rcu_preempt0-21swapper/112:03:291
71390rcu_preempt0-21swapper/112:03:291
71390rcu_preempt0-21swapper/108:54:051
71390rcu_preempt0-21swapper/108:54:051
71390rcu_preempt0-21swapper/012:34:120
71390rcu_preempt0-21swapper/012:34:120
71390rcu_preempt0-21swapper/012:34:120
46050390irq/122-QManpo14756-2110:48:550
46050390irq/122-QManpo14756-2110:48:550
46050390irq/122-QManpo14756-2110:48:550
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
1599390migration/022863-21df_abs09:23:540
1599390migration/022863-21df_abs09:23:540
1599390migration/022863-21df_abs09:23:540
71380rcu_preempt0-21swapper/312:03:483
71380rcu_preempt0-21swapper/312:03:483
71380rcu_preempt0-21swapper/312:03:483
71380rcu_preempt0-21swapper/209:18:412
71380rcu_preempt0-21swapper/209:18:412
71380rcu_preempt0-21swapper/209:18:412
71380rcu_preempt0-21swapper/208:47:182
71380rcu_preempt0-21swapper/208:47:182
71380rcu_preempt0-21swapper/208:47:182
71380rcu_preempt0-21swapper/112:21:441
71380rcu_preempt0-21swapper/112:21:441
71380rcu_preempt0-21swapper/111:29:131
71380rcu_preempt0-21swapper/111:29:131
71380rcu_preempt0-21swapper/111:29:131
71380rcu_preempt0-21swapper/111:29:131
71380rcu_preempt0-21swapper/110:24:001
71380rcu_preempt0-21swapper/110:24:001
71380rcu_preempt0-21swapper/011:04:040
71380rcu_preempt0-21swapper/011:04:040
71380rcu_preempt0-21swapper/011:04:040
71380rcu_preempt0-21swapper/011:00:380
71380rcu_preempt0-21swapper/011:00:380
71380rcu_preempt0-21swapper/011:00:380
71380rcu_preempt0-21swapper/010:53:210
71380rcu_preempt0-21swapper/010:53:210
71380rcu_preempt0-21swapper/010:53:210
46650380irq/116-QManpo15898-2110:48:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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