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2026-06-25 - 06:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Jun 25, 2026 00:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
198502870chrt46250irq/120-QMan10:48:551
198502870chrt46250irq/120-QMan10:48:551
71640rcu_preempt0-21swapper/100:18:171
71640rcu_preempt0-21swapper/100:18:171
71560rcu_preempt0-21swapper/023:58:500
71560rcu_preempt0-21swapper/023:58:500
71560rcu_preempt0-21swapper/023:58:500
46050490irq/122-QManpo17207-2110:48:550
17550994722cyclictest0-21swapper/123:54:501
17550994722cyclictest0-21swapper/123:54:501
17550994722cyclictest0-21swapper/123:54:501
71460rcu_preempt0-21swapper/119:10:461
1755099454cyclictest0-21swapper/123:34:031
1755099454cyclictest0-21swapper/123:34:031
1755099453cyclictest399-21ntp_states20:08:581
1755099453cyclictest399-21ntp_states20:08:581
1755099453cyclictest399-21ntp_states20:08:581
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
1755099444cyclictest0-21swapper/123:13:271
1755099444cyclictest0-21swapper/123:13:271
1755099444cyclictest0-21swapper/123:13:271
1755099444cyclictest0-21swapper/123:13:271
1755099443cyclictest27717-21df_inode00:38:501
1755099443cyclictest27717-21df_inode00:38:501
1755099443cyclictest27717-21df_inode00:38:501
1755099443cyclictest27312-21ntp_states19:48:591
1755099443cyclictest27312-21ntp_states19:48:591
1755099434cyclictest0-21swapper/122:26:431
1755099434cyclictest0-21swapper/122:26:431
1755099433cyclictest0-21swapper/123:49:361
1755099433cyclictest0-21swapper/123:49:361
1755099433cyclictest0-21swapper/123:02:311
1755099433cyclictest0-21swapper/123:02:311
71420rcu_preempt0-21swapper/120:53:441
71420rcu_preempt0-21swapper/120:53:441
1755099424cyclictest0-21swapper/120:58:551
1755099424cyclictest0-21swapper/120:58:551
1755099424cyclictest0-21swapper/120:58:551
1755099424cyclictest0-21swapper/119:58:471
1755099424cyclictest0-21swapper/119:58:471
1755099424cyclictest0-21swapper/100:26:551
1755099424cyclictest0-21swapper/100:26:551
1755099424cyclictest0-21swapper/100:26:551
1755099423cyclictest0-21swapper/123:14:191
1755099423cyclictest0-21swapper/123:14:191
1755099423cyclictest0-21swapper/123:14:191
1755099422cyclictest4008-21munin-run20:23:341
1755099422cyclictest4008-21munin-run20:23:341
1755099422cyclictest15521-21diskstats21:03:501
1755099422cyclictest15521-21diskstats21:03:501
1755099422cyclictest15521-21diskstats21:03:501
1755099422cyclictest0-21swapper/121:53:511
1755099422cyclictest0-21swapper/121:53:511
17550994218cyclictest14441-21ssh22:07:561
17550994218cyclictest14441-21ssh22:07:561
17550994218cyclictest14441-21ssh22:07:561
71410rcu_preempt27108-21ssh22:32:012
71410rcu_preempt27108-21ssh22:32:012
71410rcu_preempt27108-21ssh22:32:012
71410rcu_preempt17930-21diskmemload21:53:450
71410rcu_preempt0-21swapper/200:07:222
71410rcu_preempt0-21swapper/200:07:222
46050410irq/122-QManpo28422-2110:48:550
46050410irq/122-QManpo28422-2110:48:550
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
1755099413cyclictest0-21swapper/123:06:351
1755099413cyclictest0-21swapper/123:06:351
1755099413cyclictest0-21swapper/123:06:351
1755099413cyclictest0-21swapper/122:47:351
1755099413cyclictest0-21swapper/122:47:351
1755099413cyclictest0-21swapper/122:47:351
1755099413cyclictest0-21swapper/121:28:461
1755099413cyclictest0-21swapper/121:28:461
1755099413cyclictest0-21swapper/120:13:581
1755099413cyclictest0-21swapper/120:13:581
1755099413cyclictest0-21swapper/120:13:581
1755099413cyclictest0-21swapper/119:28:571
1755099413cyclictest0-21swapper/119:28:571
1755099412cyclictest21636-21irqstats23:23:531
1755099412cyclictest21636-21irqstats23:23:531
1755099411cyclictest23859-21ntp_states21:23:591
1755099411cyclictest23859-21ntp_states21:23:591
1755099411cyclictest0-21swapper/122:38:491
1755099411cyclictest0-21swapper/122:38:491
1755099411cyclictest0-21swapper/122:38:491
17550994117cyclictest0-21swapper/123:22:351
17550994117cyclictest0-21swapper/123:22:351
17550994117cyclictest0-21swapper/123:22:351
17550994116cyclictest25380-21date19:43:381
17550994116cyclictest25380-21date19:43:381
17550994115cyclictest1959-21runrttasks20:41:121
17550994115cyclictest1959-21runrttasks20:41:121
71400rcu_preempt14491-21multi.sh19:11:442
71400rcu_preempt0-21swapper/121:14:471
71400rcu_preempt0-21swapper/121:14:471
71400rcu_preempt0-21swapper/121:14:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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