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2025-11-25 - 20:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Nov 25, 2025 12:53:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71700rcu_preempt0-21swapper/012:58:380
71700rcu_preempt0-21swapper/012:58:380
71700rcu_preempt0-21swapper/012:58:380
71530rcu_preempt0-21swapper/011:46:430
71530rcu_preempt0-21swapper/011:46:430
71510rcu_preempt0-21swapper/112:33:231
71510rcu_preempt0-21swapper/112:33:231
71460rcu_preempt29730-21head12:28:103
71460rcu_preempt29730-21head12:28:103
71460rcu_preempt0-21swapper/209:39:532
71460rcu_preempt0-21swapper/209:39:532
46050460irq/122-QManpo1052-2109:24:360
46050460irq/122-QManpo1052-2109:24:360
71420rcu_preempt0-21swapper/011:57:500
71420rcu_preempt0-21swapper/011:57:500
71410rcu_preempt7343-21sh09:37:441
71410rcu_preempt7343-21sh09:37:441
71410rcu_preempt7343-21sh09:37:441
71410rcu_preempt24231-21ssh10:11:521
71410rcu_preempt24231-21ssh10:11:521
71410rcu_preempt24231-21ssh10:11:521
71410rcu_preempt0-21swapper/211:29:362
71410rcu_preempt0-21swapper/211:29:362
71400rcu_preempt31452-21apt-get09:07:522
71400rcu_preempt31452-21apt-get09:07:522
71400rcu_preempt31452-21apt-get09:07:522
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
71390rcu_preempt0-21swapper/011:03:070
71390rcu_preempt0-21swapper/011:03:070
46050390irq/122-QManpo26415-2109:24:360
46050390irq/122-QManpo26415-2109:24:360
46050390irq/122-QManpo25745-2109:24:360
46050390irq/122-QManpo25745-2109:24:360
46050390irq/122-QManpo25745-2109:24:360
1599390migration/030943-21runrttasks12:31:540
1599390migration/030943-21runrttasks12:31:540
71380rcu_preempt8626-21runrttasks10:37:511
71380rcu_preempt8626-21runrttasks10:37:511
71380rcu_preempt0-21swapper/110:42:511
71380rcu_preempt0-21swapper/110:42:511
71380rcu_preempt0-21swapper/110:42:511
71380rcu_preempt0-21swapper/109:51:101
71380rcu_preempt0-21swapper/109:51:101
71380rcu_preempt0-21swapper/109:51:101
71380rcu_preempt0-21swapper/109:18:021
71380rcu_preempt0-21swapper/109:18:021
46050380irq/122-QManpo4968-2109:24:360
46050380irq/122-QManpo4968-2109:24:360
46050380irq/122-QManpo402-2109:24:360
46050380irq/122-QManpo402-2109:24:360
46050380irq/122-QManpo2936-210
46050380irq/122-QManpo2936-210
46050380irq/122-QManpo2936-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
132332380sleep046050irq/122-QMan09:24:360
132332380sleep046050irq/122-QMan09:24:360
71370rcu_preempt0-21swapper/210:45:322
71370rcu_preempt0-21swapper/210:45:322
71370rcu_preempt0-21swapper/210:45:322
71370rcu_preempt0-21swapper/210:38:102
71370rcu_preempt0-21swapper/210:38:102
71370rcu_preempt0-21swapper/209:32:522
71370rcu_preempt0-21swapper/209:32:522
71370rcu_preempt0-21swapper/209:32:522
71370rcu_preempt0-21swapper/112:29:141
71370rcu_preempt0-21swapper/112:29:141
71370rcu_preempt0-21swapper/109:05:041
71370rcu_preempt0-21swapper/109:05:041
71370rcu_preempt0-21swapper/109:05:041
46050370irq/122-QManpo7063-2109:24:360
46050370irq/122-QManpo7063-2109:24:360
46050370irq/122-QManpo17616-210
46050370irq/122-QManpo17616-210
46050370irq/122-QManpo15074-210
46050370irq/122-QManpo15074-210
46050370irq/122-QManpo0-210
46050370irq/122-QManpo0-210
7390993615cyclictest16164-21/usr/sbin/munin08:12:471
7390993615cyclictest16164-21/usr/sbin/munin08:12:471
71360rcu_preempt7186-21aten_r4power_vo12:47:551
71360rcu_preempt7186-21aten_r4power_vo12:47:551
71360rcu_preempt29172-21sh11:24:071
71360rcu_preempt29172-21sh11:24:071
71360rcu_preempt25783-21ssh12:21:522
71360rcu_preempt25783-21ssh12:21:522
71360rcu_preempt25783-21ssh12:21:522
71360rcu_preempt19380-21ssh11:05:241
71360rcu_preempt19380-21ssh11:05:241
71360rcu_preempt0-21swapper/211:37:442
71360rcu_preempt0-21swapper/210:14:442
71360rcu_preempt0-21swapper/210:14:442
71360rcu_preempt0-21swapper/112:54:521
71360rcu_preempt0-21swapper/112:54:521
71360rcu_preempt0-21swapper/112:54:521
71360rcu_preempt0-21swapper/112:24:021
71360rcu_preempt0-21swapper/112:24:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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