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2026-06-04 - 14:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Jun 04, 2026 12:44:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71620rcu_preempt0-21swapper/109:46:381
71620rcu_preempt0-21swapper/109:46:381
100650550irq/38-i2c-mpc241ksoftirqd/209:58:252
100650550irq/38-i2c-mpc241ksoftirqd/209:58:252
100650550irq/38-i2c-mpc241ksoftirqd/209:58:252
71540rcu_preempt0-21swapper/011:48:250
71540rcu_preempt0-21swapper/011:48:250
71540rcu_preempt0-21swapper/011:48:250
71480rcu_preempt0-21swapper/108:18:351
71480rcu_preempt0-21swapper/108:18:351
71460rcu_preempt0-21swapper/112:10:001
71460rcu_preempt0-21swapper/112:10:001
4187994613cyclictest22261-21/usr/sbin/munin08:18:332
4187994613cyclictest22261-21/usr/sbin/munin08:18:332
71450rcu_preempt0-21swapper/012:11:360
71450rcu_preempt0-21swapper/012:11:360
71440rcu_preempt0-21swapper/307:12:523
71440rcu_preempt0-21swapper/307:12:523
71440rcu_preempt0-21swapper/109:23:251
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
4187994426cyclictest9651-21apt-get11:28:232
4187994426cyclictest9651-21apt-get11:28:232
4187994422cyclictest29080-21munin-run08:43:132
4187994422cyclictest29080-21munin-run08:43:132
71430rcu_preempt26770-21diskmemload11:59:361
71430rcu_preempt26770-21diskmemload11:59:361
71430rcu_preempt26770-21diskmemload11:59:361
71430rcu_preempt0-21swapper/012:41:300
71430rcu_preempt0-21swapper/012:41:300
71430rcu_preempt0-21swapper/011:32:000
71430rcu_preempt0-21swapper/011:32:000
71430rcu_preempt0-21swapper/011:11:280
71430rcu_preempt0-21swapper/011:11:280
71430rcu_preempt0-21swapper/011:11:280
71430rcu_preempt0-21swapper/010:04:380
71430rcu_preempt0-21swapper/010:04:380
71430rcu_preempt0-21swapper/010:04:380
71420rcu_preempt8187-21ntp_states09:18:473
71420rcu_preempt8187-21ntp_states09:18:473
71420rcu_preempt8187-21ntp_states09:18:473
71420rcu_preempt8187-21ntp_states09:18:473
71420rcu_preempt0-21swapper/009:55:010
71420rcu_preempt0-21swapper/009:55:010
71420rcu_preempt0-21swapper/009:19:060
71420rcu_preempt0-21swapper/009:19:060
71420rcu_preempt0-21swapper/009:19:060
71420rcu_preempt0-21swapper/009:19:060
71410rcu_preempt0-21swapper/211:03:402
71410rcu_preempt0-21swapper/211:03:402
71410rcu_preempt0-21swapper/211:03:402
71410rcu_preempt0-21swapper/112:28:021
71410rcu_preempt0-21swapper/112:28:021
71410rcu_preempt0-21swapper/112:28:021
71410rcu_preempt0-21swapper/111:08:391
71410rcu_preempt0-21swapper/111:08:391
71410rcu_preempt0-21swapper/111:08:391
71410rcu_preempt0-21swapper/111:00:471
71410rcu_preempt0-21swapper/111:00:471
71410rcu_preempt0-21swapper/110:29:511
71410rcu_preempt0-21swapper/110:29:511
71410rcu_preempt0-21swapper/110:29:511
71410rcu_preempt0-21swapper/010:35:180
71410rcu_preempt0-21swapper/010:35:180
4187994122cyclictest30922-21irqstats08:48:312
4187994122cyclictest30922-21irqstats08:48:312
4187994122cyclictest30922-21irqstats08:48:312
4187994122cyclictest15549-21df_inode07:53:282
4187994122cyclictest15549-21df_inode07:53:282
4187994122cyclictest14435-21ntp_states07:48:362
4187994122cyclictest14435-21ntp_states07:48:362
4187994122cyclictest14435-21ntp_states07:48:362
4187994118cyclictest0-21swapper/211:02:342
4187994118cyclictest0-21swapper/211:02:342
71400rcu_preempt0-21swapper/312:09:263
71400rcu_preempt0-21swapper/312:09:263
71400rcu_preempt0-21swapper/210:14:122
71400rcu_preempt0-21swapper/210:14:122
71400rcu_preempt0-21swapper/109:18:391
71400rcu_preempt0-21swapper/109:18:391
71400rcu_preempt0-21swapper/109:18:391
71400rcu_preempt0-21swapper/009:38:540
71400rcu_preempt0-21swapper/009:38:540
71400rcu_preempt0-21swapper/009:38:540
46050400irq/122-QManpo19656-2110:48:550
46050400irq/122-QManpo19656-2110:48:550
4187994020cyclictest32393-21munin-run10:08:142
4187994020cyclictest32393-21munin-run10:08:142
4187994020cyclictest32393-21munin-run10:08:142
4187994020cyclictest25065-21/usr/sbin/munin08:28:322
4187994020cyclictest25065-21/usr/sbin/munin08:28:322
4187994020cyclictest22820-21memory09:48:372
4187994020cyclictest22820-21memory09:48:372
4187994020cyclictest18657-21/usr/sbin/munin10:43:252
4187994020cyclictest18657-21/usr/sbin/munin10:43:252
4187994020cyclictest18657-21/usr/sbin/munin10:43:252
4187994020cyclictest15609-21ntp_states11:38:372
4187994020cyclictest15609-21ntp_states11:38:372
4187994017cyclictest0-21swapper/212:12:302
4187994017cyclictest0-21swapper/212:12:302
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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