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2026-02-09 - 13:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Feb 09, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71710rcu_preempt0-21swapper/022:13:140
71710rcu_preempt0-21swapper/022:13:140
71710rcu_preempt0-21swapper/022:13:140
71630rcu_preempt0-21swapper/022:19:560
71630rcu_preempt0-21swapper/022:19:560
1599520migration/02202-21/usr/sbin/munin19:06:270
1599520migration/02202-21/usr/sbin/munin19:06:270
71490rcu_preempt0-21swapper/219:11:202
71490rcu_preempt0-21swapper/219:11:202
71480rcu_preempt0-21swapper/222:26:292
71480rcu_preempt0-21swapper/222:26:292
319599483cyclictest0-21swapper/119:41:271
319599483cyclictest0-21swapper/119:41:271
319599483cyclictest0-21swapper/119:41:271
71460rcu_preempt0-21swapper/122:01:521
71460rcu_preempt0-21swapper/122:01:521
71440rcu_preempt26483-21sh21:49:462
71440rcu_preempt26483-21sh21:49:462
71440rcu_preempt26483-21sh21:49:462
71440rcu_preempt0-21swapper/120:11:181
71440rcu_preempt0-21swapper/120:11:181
71440rcu_preempt0-21swapper/000:06:210
71440rcu_preempt0-21swapper/000:06:210
319599442cyclictest1959-21runrttasks21:48:331
319599442cyclictest1959-21runrttasks21:48:331
319599442cyclictest1959-21runrttasks21:48:331
319599442cyclictest15586-21munin-run00:21:071
319599442cyclictest15586-21munin-run00:21:071
319599442cyclictest15586-21munin-run00:21:071
46450430irq/118-QManpo2749-2110:48:552
46450430irq/118-QManpo2749-2110:48:552
319599433cyclictest23171-21memory20:21:281
319599433cyclictest23171-21memory20:21:281
319599433cyclictest16040-21diskstats21:31:231
319599433cyclictest16040-21diskstats21:31:231
319599433cyclictest16040-21diskstats21:31:231
319599432cyclictest10048-21users22:16:361
319599432cyclictest10048-21users22:16:361
319599431cyclictest31943-21/usr/sbin/munin22:56:231
319599431cyclictest31943-21/usr/sbin/munin22:56:231
71420rcu_preempt0-21swapper/119:16:181
71420rcu_preempt0-21swapper/119:16:181
71420rcu_preempt0-21swapper/119:16:181
319599424cyclictest0-21swapper/120:51:231
319599424cyclictest0-21swapper/120:51:231
319599422cyclictest7459-21diskstats21:16:231
319599422cyclictest7459-21diskstats21:16:231
319599422cyclictest3539-21df22:06:221
319599422cyclictest3539-21df22:06:221
319599422cyclictest1959-21runrttasks19:21:391
319599422cyclictest1959-21runrttasks19:21:391
319599422cyclictest1959-21runrttasks00:30:541
319599422cyclictest1959-21runrttasks00:30:541
319599422cyclictest18237-21ntp_states22:31:321
319599422cyclictest18237-21ntp_states22:31:321
3195994218cyclictest17602-21memory20:01:281
3195994218cyclictest17602-21memory20:01:281
71410rcu_preempt0-21swapper/221:56:252
71410rcu_preempt0-21swapper/221:56:252
71410rcu_preempt0-21swapper/221:37:582
71410rcu_preempt0-21swapper/221:37:582
71410rcu_preempt0-21swapper/221:37:582
71410rcu_preempt0-21swapper/021:52:140
71410rcu_preempt0-21swapper/021:52:140
46650410irq/116-QManpo2398-2110:48:553
46650410irq/116-QManpo2398-2110:48:553
319599413cyclictest0-21swapper/120:46:221
319599413cyclictest0-21swapper/120:46:221
319599412cyclictest8353-21ssh23:11:231
319599412cyclictest8353-21ssh23:11:231
319599412cyclictest3781-21ssh23:02:431
319599412cyclictest3781-21ssh23:02:431
319599412cyclictest3781-21ssh23:02:431
319599412cyclictest28715-21meminfo20:41:291
319599412cyclictest28715-21meminfo20:41:291
319599412cyclictest26351-1kworker/1:1H00:02:291
319599412cyclictest26351-1kworker/1:1H00:02:291
319599412cyclictest21923-21memory00:31:281
319599412cyclictest21923-21memory00:31:281
319599412cyclictest21782-21df_inode21:41:231
319599412cyclictest21782-21df_inode21:41:231
319599412cyclictest1683-21df_inode23:56:231
319599412cyclictest1683-21df_inode23:56:231
319599412cyclictest1683-21df_inode23:56:231
319599412cyclictest1683-21df_inode23:56:231
319599412cyclictest15810-21aten_r4power_cu00:21:191
319599412cyclictest15810-21aten_r4power_cu00:21:191
319599412cyclictest15810-21aten_r4power_cu00:21:191
319599412cyclictest10389-21sed00:11:271
319599412cyclictest10389-21sed00:11:271
319599411cyclictest9934-21sendmail-msp21:21:281
319599411cyclictest9934-21sendmail-msp21:21:281
3195994117cyclictest21878-21ntp_states20:16:331
3195994117cyclictest21878-21ntp_states20:16:331
3195994117cyclictest21878-21ntp_states20:16:331
71400rcu_preempt29095-21ssh22:51:202
71400rcu_preempt29095-21ssh22:51:202
71400rcu_preempt1770-21in:imuxsock23:46:070
71400rcu_preempt1770-21in:imuxsock23:46:070
71400rcu_preempt0-21swapper/222:01:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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