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2026-08-24 - 03:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Aug 24, 2026 00:44:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71570rcu_preempt0-21swapper/000:26:000
71570rcu_preempt0-21swapper/000:26:000
71510rcu_preempt0-21swapper/222:39:192
71510rcu_preempt0-21swapper/222:39:192
71490rcu_preempt0-21swapper/221:51:272
71490rcu_preempt0-21swapper/221:51:272
166662460chrt46450irq/118-QMan10:48:552
166662460chrt46450irq/118-QMan10:48:552
71450rcu_preempt0-21swapper/300:22:113
71450rcu_preempt0-21swapper/300:22:113
46050450irq/122-QManpo12188-2110:48:550
46050450irq/122-QManpo12188-2110:48:550
71440rcu_preempt0-21swapper/022:24:430
71440rcu_preempt0-21swapper/022:24:430
71440rcu_preempt0-21swapper/022:24:430
71430rcu_preempt27343-21kworker/2:221:40:042
71430rcu_preempt27343-21kworker/2:221:40:042
71430rcu_preempt27343-21kworker/2:221:40:042
71430rcu_preempt0-21swapper/023:57:170
71430rcu_preempt0-21swapper/023:57:170
71420rcu_preempt0-21swapper/023:03:540
71420rcu_preempt0-21swapper/023:03:540
12469994225cyclictest6175-21apt-get20:49:470
12469994225cyclictest6175-21apt-get20:49:470
71410rcu_preempt0-21swapper/320:24:473
71410rcu_preempt0-21swapper/320:24:473
71410rcu_preempt0-21swapper/223:29:382
71410rcu_preempt0-21swapper/223:29:382
71410rcu_preempt0-21swapper/019:55:030
71410rcu_preempt0-21swapper/019:55:030
71410rcu_preempt0-21swapper/000:31:000
71410rcu_preempt0-21swapper/000:31:000
12469994123cyclictest17254-21sh23:15:030
12469994123cyclictest17254-21sh23:15:030
12469994118cyclictest10362-21memory23:59:590
12469994118cyclictest10362-21memory23:59:590
12469994118cyclictest10362-21memory23:59:590
71400rcu_preempt27427-21ssh21:39:463
71400rcu_preempt27427-21ssh21:39:463
71400rcu_preempt27427-21ssh21:39:463
71400rcu_preempt0-21swapper/323:06:483
71400rcu_preempt0-21swapper/323:06:483
71400rcu_preempt0-21swapper/223:00:292
71400rcu_preempt0-21swapper/223:00:292
71400rcu_preempt0-21swapper/200:42:172
71400rcu_preempt0-21swapper/200:42:172
71400rcu_preempt0-21swapper/200:42:172
71400rcu_preempt0-21swapper/121:16:271
71400rcu_preempt0-21swapper/121:16:271
71400rcu_preempt0-21swapper/021:09:170
71400rcu_preempt0-21swapper/021:09:170
71390rcu_preempt29071-21ssh00:33:161
71390rcu_preempt29071-21ssh00:33:161
71390rcu_preempt0-21swapper/321:52:013
71390rcu_preempt0-21swapper/321:52:013
71390rcu_preempt0-21swapper/321:32:073
71390rcu_preempt0-21swapper/321:32:073
71390rcu_preempt0-21swapper/023:09:580
71390rcu_preempt0-21swapper/023:09:580
71390rcu_preempt0-21swapper/021:37:480
71390rcu_preempt0-21swapper/021:37:480
71390rcu_preempt0-21swapper/020:05:020
71390rcu_preempt0-21swapper/000:12:580
71390rcu_preempt0-21swapper/000:12:580
12469993918cyclictest1204-21munin-run23:44:370
12469993918cyclictest1204-21munin-run23:44:370
12469993918cyclictest1204-21munin-run23:44:370
12469993916cyclictest1110-21grep00:40:050
12469993916cyclictest1110-21grep00:40:050
12469993916cyclictest1110-21grep00:40:050
71380rcu_preempt16583-21kworker/0:200:06:570
71380rcu_preempt16583-21kworker/0:200:06:570
71380rcu_preempt16224-21sh22:15:580
71380rcu_preempt16224-21sh22:15:580
71380rcu_preempt0-21swapper/319:15:483
71380rcu_preempt0-21swapper/319:15:483
71380rcu_preempt0-21swapper/222:29:382
71380rcu_preempt0-21swapper/222:29:382
71380rcu_preempt0-21swapper/200:32:112
71380rcu_preempt0-21swapper/200:32:112
71380rcu_preempt0-21swapper/023:30:420
71380rcu_preempt0-21swapper/023:30:420
71380rcu_preempt0-21swapper/022:44:470
71380rcu_preempt0-21swapper/022:44:470
71380rcu_preempt0-21swapper/022:12:210
71380rcu_preempt0-21swapper/022:12:210
71380rcu_preempt0-21swapper/021:50:280
71380rcu_preempt0-21swapper/021:50:280
71380rcu_preempt0-21swapper/021:16:470
71380rcu_preempt0-21swapper/021:16:470
71380rcu_preempt0-21swapper/019:20:160
71380rcu_preempt0-21swapper/019:20:160
1246999387cyclictest0-21swapper/022:35:290
1246999387cyclictest0-21swapper/022:35:290
1246999387cyclictest0-21swapper/022:26:520
1246999387cyclictest0-21swapper/022:26:520
12469993817cyclictest21600-21irqstats00:19:560
12469993817cyclictest21600-21irqstats00:19:560
12469993810cyclictest0-21swapper/021:22:280
12469993810cyclictest0-21swapper/021:22:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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