You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-01 - 04:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Mar 01, 2026 00:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
150032570chrt46650irq/116-QMan10:48:553
150032570chrt46650irq/116-QMan10:48:553
150032570chrt46650irq/116-QMan10:48:553
46050480irq/122-QManpo29966-2110:48:550
46050480irq/122-QManpo29966-2110:48:550
3003999461cyclictest1235-21/usr/sbin/munin00:31:593
3003999461cyclictest1235-21/usr/sbin/munin00:31:593
3003999461cyclictest1235-21/usr/sbin/munin00:31:593
71450rcu_preempt2179-21sh21:41:392
71450rcu_preempt2179-21sh21:41:392
3003999453cyclictest0-21swapper/321:51:483
3003999453cyclictest0-21swapper/321:51:483
3003999451cyclictest9424-21/usr/sbin/munin22:52:003
3003999451cyclictest9424-21/usr/sbin/munin22:52:003
3003999451cyclictest27564-21/usr/sbin/munin22:26:553
3003999451cyclictest27564-21/usr/sbin/munin22:26:553
71440rcu_preempt0-21swapper/100:25:291
71440rcu_preempt0-21swapper/100:25:291
71440rcu_preempt0-21swapper/100:25:291
71430rcu_preempt15020-21sendmail-msp23:03:231
71430rcu_preempt15020-21sendmail-msp23:03:231
71430rcu_preempt15020-21sendmail-msp23:03:231
30039994310cyclictest20044-21users22:11:583
30039994310cyclictest20044-21users22:11:583
30039994310cyclictest20044-21users22:11:583
30038994313cyclictest28652-21ntp_states00:21:542
30038994313cyclictest28652-21ntp_states00:21:542
30038994313cyclictest28652-21ntp_states00:21:542
3003999424cyclictest0-21swapper/323:05:083
3003999424cyclictest0-21swapper/323:05:083
3003999424cyclictest0-21swapper/323:05:083
3003999423cyclictest0-21swapper/323:07:123
3003999423cyclictest0-21swapper/323:07:123
3003999423cyclictest0-21swapper/323:07:123
3003999423cyclictest0-21swapper/321:56:393
3003999423cyclictest0-21swapper/321:56:393
3003999423cyclictest0-21swapper/321:56:393
3003999423cyclictest0-21swapper/321:43:303
3003999423cyclictest0-21swapper/321:43:303
3003999422cyclictest5715-1kworker/3:2H22:44:593
3003999422cyclictest5715-1kworker/3:2H22:44:593
3003999422cyclictest31047-21df_inode00:26:453
3003999422cyclictest31047-21df_inode00:26:453
3003999422cyclictest31047-21df_inode00:26:453
3003999422cyclictest0-21swapper/322:26:353
3003999421cyclictest23609-21ssh00:12:473
3003999421cyclictest23609-21ssh00:12:473
3003999421cyclictest23609-21ssh00:12:473
30038994214cyclictest6798-21munin-run00:41:302
30038994214cyclictest6798-21munin-run00:41:302
30038994214cyclictest6798-21munin-run00:41:302
71410rcu_preempt0-21swapper/121:44:011
71410rcu_preempt0-21swapper/121:44:011
3003999414cyclictest0-21swapper/323:36:363
3003999414cyclictest0-21swapper/322:02:473
3003999414cyclictest0-21swapper/322:02:473
3003999413cyclictest0-21swapper/323:51:423
3003999413cyclictest0-21swapper/323:51:423
3003999413cyclictest0-21swapper/322:23:403
3003999413cyclictest0-21swapper/321:25:013
3003999413cyclictest0-21swapper/321:25:013
3003999413cyclictest0-21swapper/300:08:153
3003999413cyclictest0-21swapper/300:08:153
3003999412cyclictest4457-21irqstats00:36:493
3003999412cyclictest4457-21irqstats00:36:493
3003999412cyclictest4457-21irqstats00:36:493
30039994118cyclictest0-21swapper/300:26:303
30039994118cyclictest0-21swapper/300:26:303
30039994118cyclictest0-21swapper/300:26:303
30038994123cyclictest11430-21irqstats23:51:492
30038994123cyclictest11430-21irqstats23:51:492
30038994119cyclictest5851-21df_inode20:01:452
30038994119cyclictest5851-21df_inode20:01:452
30038994117cyclictest12290-21/usr/sbin/munin22:56:462
30038994117cyclictest12290-21/usr/sbin/munin22:56:462
30038994117cyclictest12290-21/usr/sbin/munin22:56:462
30038994114cyclictest23477-21df_inode21:21:442
30038994114cyclictest23477-21df_inode21:21:442
71400rcu_preempt19826-21kworker/1:122:39:571
71400rcu_preempt19826-21kworker/1:122:39:571
71400rcu_preempt19826-21kworker/1:122:39:571
71400rcu_preempt0-21swapper/123:26:521
71400rcu_preempt0-21swapper/123:26:521
71400rcu_preempt0-21swapper/123:13:201
71400rcu_preempt0-21swapper/123:13:201
71400rcu_preempt0-21swapper/121:41:251
71400rcu_preempt0-21swapper/121:41:251
71400rcu_preempt0-21swapper/000:10:050
71400rcu_preempt0-21swapper/000:10:050
3003999404cyclictest0-21swapper/322:39:533
3003999404cyclictest0-21swapper/322:39:533
3003999404cyclictest0-21swapper/322:39:533
3003999403cyclictest0-21swapper/323:48:493
3003999403cyclictest0-21swapper/323:48:493
3003999403cyclictest0-21swapper/323:31:053
3003999403cyclictest0-21swapper/323:31:053
3003999403cyclictest0-21swapper/323:16:473
3003999403cyclictest0-21swapper/323:16:473
3003999403cyclictest0-21swapper/323:16:473
3003999403cyclictest0-21swapper/320:01:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional