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2026-02-05 - 11:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Feb 05, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2591199543cyclictest0-21swapper/000:37:260
2591199543cyclictest0-21swapper/000:37:260
2591199543cyclictest0-21swapper/000:37:260
2591199532cyclictest4464-21df_inode23:21:190
2591199532cyclictest4464-21df_inode23:21:190
25911995218cyclictest0-21swapper/000:06:260
25911995218cyclictest0-21swapper/000:06:260
2591199512cyclictest30682-21ntp_states19:26:260
2591199512cyclictest30682-21ntp_states19:26:260
2591199504cyclictest0-21swapper/023:41:270
2591199504cyclictest0-21swapper/023:41:270
2591199503cyclictest0-21swapper/021:41:270
2591199503cyclictest0-21swapper/021:41:270
2591199503cyclictest0-21swapper/021:31:240
2591199503cyclictest0-21swapper/021:31:240
2591199502cyclictest8930-21users22:31:340
2591199502cyclictest8930-21users22:31:340
2591199502cyclictest1959-21runrttasks22:18:380
2591199502cyclictest1959-21runrttasks22:18:380
25911995018cyclictest0-21swapper/023:48:090
25911995018cyclictest0-21swapper/023:48:090
25911995016cyclictest1959-21runrttasks23:54:150
25911995016cyclictest1959-21runrttasks23:54:150
2591199493cyclictest0-21swapper/023:15:370
2591199493cyclictest0-21swapper/023:15:370
2591199493cyclictest0-21swapper/022:21:150
2591199493cyclictest0-21swapper/022:21:150
2591199493cyclictest0-21swapper/022:21:150
2591199493cyclictest0-21swapper/021:19:190
2591199493cyclictest0-21swapper/021:19:190
2591199493cyclictest0-21swapper/021:19:190
2591199493cyclictest0-21swapper/020:51:170
2591199493cyclictest0-21swapper/020:51:170
2591199493cyclictest0-21swapper/000:16:290
2591199493cyclictest0-21swapper/000:16:290
2591199493cyclictest0-21swapper/000:16:290
2591199493cyclictest0-21swapper/000:14:010
2591199493cyclictest0-21swapper/000:14:010
2591199492cyclictest7087-21users00:21:320
2591199492cyclictest7087-21users00:21:320
2591199492cyclictest31956-21meminfo19:31:220
2591199492cyclictest31956-21meminfo19:31:220
2591199492cyclictest26035-21/usr/sbin/munin22:06:150
2591199492cyclictest26035-21/usr/sbin/munin22:06:150
25911994917cyclictest0-21swapper/019:21:300
25911994917cyclictest0-21swapper/019:21:300
2591199483cyclictest0-21swapper/022:53:010
2591199483cyclictest0-21swapper/022:53:010
2591199483cyclictest0-21swapper/021:51:160
2591199483cyclictest0-21swapper/021:51:160
2591199483cyclictest0-21swapper/021:26:480
2591199483cyclictest0-21swapper/021:26:480
2591199483cyclictest0-21swapper/021:26:480
2591199483cyclictest0-21swapper/000:02:130
2591199483cyclictest0-21swapper/000:02:130
2591199482cyclictest29077-21ssh23:06:560
2591199482cyclictest29077-21ssh23:06:560
2591199482cyclictest0-21swapper/021:36:480
2591199482cyclictest0-21swapper/021:36:480
2591199482cyclictest0-21swapper/021:36:480
2591199482cyclictest0-21swapper/019:11:240
2591199482cyclictest0-21swapper/019:11:240
25911994816cyclictest0-21swapper/000:26:330
25911994816cyclictest0-21swapper/000:26:330
25911994815cyclictest0-21swapper/022:40:330
25911994815cyclictest0-21swapper/022:40:330
25911994815cyclictest0-21swapper/022:40:330
2591199473cyclictest0-21swapper/023:01:270
2591199473cyclictest0-21swapper/023:01:270
2591199473cyclictest0-21swapper/023:01:270
2591199473cyclictest0-21swapper/022:01:160
2591199473cyclictest0-21swapper/022:01:160
2591199473cyclictest0-21swapper/019:51:230
2591199473cyclictest0-21swapper/019:51:230
2591199473cyclictest0-21swapper/019:51:230
2591199472cyclictest7754-21diskstats20:01:180
2591199472cyclictest7754-21diskstats20:01:180
2591199472cyclictest28893-21ssh21:14:000
2591199472cyclictest28893-21ssh21:14:000
2591199472cyclictest2483-21ssh23:17:030
2591199472cyclictest2483-21ssh23:17:030
2591199472cyclictest2483-21ssh23:17:030
2591199472cyclictest24278-21aten_r4power_en23:56:150
2591199472cyclictest24278-21aten_r4power_en23:56:150
2591199472cyclictest24278-21aten_r4power_en23:56:150
2591199472cyclictest0-21swapper/021:24:500
2591199472cyclictest0-21swapper/021:24:500
2591199472cyclictest0-21swapper/019:51:020
2591199472cyclictest0-21swapper/019:51:020
2591199463cyclictest0-21swapper/022:57:250
2591199463cyclictest0-21swapper/022:57:250
2591199463cyclictest0-21swapper/022:57:250
2591199463cyclictest0-21swapper/022:41:280
2591199463cyclictest0-21swapper/022:41:280
2591199453cyclictest0-21swapper/023:31:350
2591199453cyclictest0-21swapper/023:31:350
2591199453cyclictest0-21swapper/022:30:280
2591199453cyclictest0-21swapper/022:30:280
2591199453cyclictest0-21swapper/000:35:020
2591199453cyclictest0-21swapper/000:35:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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