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2025-12-08 - 16:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Dec 08, 2025 12:53:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27459994313cyclictest0-21swapper/212:03:162
27459994313cyclictest0-21swapper/212:03:162
27459994313cyclictest0-21swapper/212:03:162
71410rcu_preempt0-21swapper/211:43:522
71410rcu_preempt0-21swapper/211:43:522
27459994119cyclictest12301-21irqstats10:13:142
27459994119cyclictest12301-21irqstats10:13:142
27459994111cyclictest0-21swapper/213:01:502
27459994111cyclictest0-21swapper/213:01:502
27459994111cyclictest0-21swapper/213:01:502
71400rcu_preempt0-21swapper/112:05:331
71400rcu_preempt0-21swapper/112:05:331
71400rcu_preempt0-21swapper/112:05:331
71400rcu_preempt0-21swapper/111:18:291
71400rcu_preempt0-21swapper/111:18:291
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
27459994018cyclictest5489-21ntp_states12:08:212
27459994018cyclictest5489-21ntp_states12:08:212
27459994018cyclictest5489-21ntp_states12:08:212
71390rcu_preempt0-21swapper/209:55:202
71390rcu_preempt0-21swapper/209:55:202
71390rcu_preempt0-21swapper/209:55:202
46050390irq/122-QManpo28503-2109:24:360
46050390irq/122-QManpo28503-2109:24:360
46050390irq/122-QManpo28503-2109:24:360
46050390irq/122-QManpo25568-2109:24:360
46050390irq/122-QManpo25568-2109:24:360
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
27459993920cyclictest19324-21munin-run10:27:542
27459993920cyclictest19324-21munin-run10:27:542
27459993919cyclictest22761-21ntp_states11:38:202
27459993919cyclictest22761-21ntp_states11:38:202
27459993919cyclictest22761-21ntp_states11:38:202
27459993917cyclictest5037-21diskstats09:58:152
27459993917cyclictest5037-21diskstats09:58:152
27459993917cyclictest5037-21diskstats09:58:152
27459993915cyclictest0-21swapper/211:53:072
27459993915cyclictest0-21swapper/211:53:072
27459993914cyclictest19835-21irqstats10:28:132
27459993914cyclictest19835-21irqstats10:28:132
27459993914cyclictest0-21swapper/210:58:262
27459993914cyclictest0-21swapper/210:58:262
71380rcu_preempt8409-1kworker/1:1H11:16:031
71380rcu_preempt8409-1kworker/1:1H11:16:031
71380rcu_preempt27299-21diskmemload11:33:372
71380rcu_preempt27299-21diskmemload11:33:372
71380rcu_preempt27299-1diskmemload09:51:421
71380rcu_preempt27299-1diskmemload09:51:421
46050380irq/122-QManpo10313-2109:24:360
46050380irq/122-QManpo10313-2109:24:360
27459993818cyclictest0-21swapper/209:40:412
27459993818cyclictest0-21swapper/209:40:412
27459993818cyclictest0-21swapper/209:40:412
27459993816cyclictest32033-21/usr/sbin/munin07:58:182
27459993816cyclictest32033-21/usr/sbin/munin07:58:182
27459993816cyclictest0-21swapper/210:42:532
27459993816cyclictest0-21swapper/210:42:532
27459993815cyclictest0-21swapper/213:08:162
27459993815cyclictest0-21swapper/213:08:162
27459993815cyclictest0-21swapper/212:28:172
27459993815cyclictest0-21swapper/212:28:172
27459993814cyclictest0-21swapper/211:19:242
27459993814cyclictest0-21swapper/211:19:242
71370rcu_preempt28937-21ssh10:46:560
71370rcu_preempt28937-21ssh10:46:560
71370rcu_preempt28937-21ssh10:46:560
71370rcu_preempt16040-1kworker/2:0H12:39:172
71370rcu_preempt16040-1kworker/2:0H12:39:172
71370rcu_preempt16040-1kworker/2:0H12:39:172
71370rcu_preempt10654-21kworker/0:313:09:240
71370rcu_preempt10654-21kworker/0:313:09:240
71370rcu_preempt0-21swapper/211:17:382
71370rcu_preempt0-21swapper/211:17:382
71370rcu_preempt0-21swapper/112:58:051
71370rcu_preempt0-21swapper/112:58:051
71370rcu_preempt0-21swapper/112:58:051
71370rcu_preempt0-21swapper/111:39:001
71370rcu_preempt0-21swapper/111:39:001
71370rcu_preempt0-21swapper/111:39:001
71370rcu_preempt0-21swapper/109:57:301
71370rcu_preempt0-21swapper/109:57:301
71370rcu_preempt0-21swapper/109:57:301
46050370irq/122-QManpo23263-2109:24:360
46050370irq/122-QManpo23263-2109:24:360
46050370irq/122-QManpo22183-2109:24:360
46050370irq/122-QManpo22183-2109:24:360
46050370irq/122-QManpo22183-2109:24:360
46050370irq/122-QManpo20312-2109:24:360
46050370irq/122-QManpo20312-2109:24:360
46050370irq/122-QManpo0-210
46050370irq/122-QManpo0-210
27459993721cyclictest7645-21df12:13:082
27459993721cyclictest7645-21df12:13:082
27459993719cyclictest0-21swapper/210:12:472
27459993719cyclictest0-21swapper/210:12:472
27459993715cyclictest23265-21/usr/sbin/munin09:23:112
27459993715cyclictest23265-21/usr/sbin/munin09:23:112
27459993715cyclictest0-21swapper/210:49:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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