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2026-09-20 - 07:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Sep 20, 2026 00:44:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71650rcu_preempt0-21swapper/121:05:071
71650rcu_preempt0-21swapper/121:05:071
1336399547cyclictest31040-21pluginstate21:45:050
1336399547cyclictest31040-21pluginstate21:45:050
1336399547cyclictest31040-21pluginstate21:45:050
13363995421cyclictest25707-21ssh00:26:270
13363995421cyclictest25707-21ssh00:26:270
1336399533cyclictest0-21swapper/022:58:380
1336399533cyclictest0-21swapper/022:58:380
1336399523cyclictest0-21swapper/023:49:250
1336399523cyclictest0-21swapper/023:49:250
1336399521cyclictest28287-1kworker/0:0H22:40:040
1336399521cyclictest28287-1kworker/0:0H22:40:040
13363995217cyclictest4423-21/usr/sbin/munin21:55:260
13363995217cyclictest4423-21/usr/sbin/munin21:55:260
1336399513cyclictest0-21swapper/022:35:040
1336399513cyclictest0-21swapper/022:35:040
1336399513cyclictest0-21swapper/022:35:040
1336399513cyclictest0-21swapper/021:54:210
1336399513cyclictest0-21swapper/021:54:210
1336399513cyclictest0-21swapper/021:45:260
1336399513cyclictest0-21swapper/021:45:260
1336399513cyclictest0-21swapper/000:30:290
1336399513cyclictest0-21swapper/000:30:290
13363995117cyclictest0-21swapper/000:07:040
13363995117cyclictest0-21swapper/000:07:040
1336399503cyclictest0-21swapper/022:25:180
1336399503cyclictest0-21swapper/022:25:180
13363995018cyclictest0-21swapper/022:20:290
13363995018cyclictest0-21swapper/022:20:290
13363995018cyclictest0-21swapper/022:20:290
13363995017cyclictest0-21swapper/021:26:120
13363995017cyclictest0-21swapper/021:26:120
13363995017cyclictest0-21swapper/020:30:050
13363995017cyclictest0-21swapper/020:30:050
13363995017cyclictest0-21swapper/000:19:090
13363995017cyclictest0-21swapper/000:19:090
1336399494cyclictest0-21swapper/020:55:160
1336399494cyclictest0-21swapper/020:55:160
1336399493cyclictest0-21swapper/023:00:440
1336399493cyclictest0-21swapper/023:00:440
1336399493cyclictest0-21swapper/022:10:360
1336399493cyclictest0-21swapper/022:10:360
1336399493cyclictest0-21swapper/021:19:200
1336399493cyclictest0-21swapper/021:19:200
1336399493cyclictest0-21swapper/019:58:270
1336399493cyclictest0-21swapper/019:58:270
1336399493cyclictest0-21swapper/000:00:290
1336399493cyclictest0-21swapper/000:00:290
13363994917cyclictest0-21swapper/023:18:010
13363994917cyclictest0-21swapper/023:18:010
13363994917cyclictest0-21swapper/023:18:010
71480rcu_preempt0-21swapper/000:42:130
71480rcu_preempt0-21swapper/000:42:130
1336399483cyclictest0-21swapper/023:31:230
1336399483cyclictest0-21swapper/023:31:230
1336399483cyclictest0-21swapper/023:31:230
1336399483cyclictest0-21swapper/022:15:150
1336399483cyclictest0-21swapper/022:15:150
1336399483cyclictest0-21swapper/021:35:200
1336399483cyclictest0-21swapper/021:35:200
1336399483cyclictest0-21swapper/021:00:180
1336399483cyclictest0-21swapper/021:00:180
13363994816cyclictest0-21swapper/000:12:160
13363994816cyclictest0-21swapper/000:12:160
1336399473cyclictest0-21swapper/023:41:210
1336399473cyclictest0-21swapper/023:41:210
1336399473cyclictest0-21swapper/023:26:230
1336399473cyclictest0-21swapper/023:26:230
1336399473cyclictest0-21swapper/023:25:050
1336399473cyclictest0-21swapper/023:25:050
1336399473cyclictest0-21swapper/023:25:050
13363994716cyclictest0-21swapper/019:15:300
13363994716cyclictest0-21swapper/019:15:300
71460rcu_preempt25457-21copy20:00:180
71460rcu_preempt25457-21copy20:00:180
71460rcu_preempt0-21swapper/021:05:130
71460rcu_preempt0-21swapper/021:05:130
1336399463cyclictest0-21swapper/022:48:230
1336399463cyclictest0-21swapper/022:48:230
1336399463cyclictest0-21swapper/022:44:160
1336399463cyclictest0-21swapper/022:44:160
1336399463cyclictest0-21swapper/022:44:160
1336399463cyclictest0-21swapper/019:40:190
1336399463cyclictest0-21swapper/019:40:190
1336399463cyclictest0-21swapper/019:40:190
1336399463cyclictest0-21swapper/019:30:200
1336399463cyclictest0-21swapper/019:30:200
1336399463cyclictest0-21swapper/000:39:420
1336399463cyclictest0-21swapper/000:39:420
1336399463cyclictest0-21swapper/000:20:170
1336399463cyclictest0-21swapper/000:20:170
13363994515cyclictest0-21swapper/023:55:410
13363994515cyclictest0-21swapper/023:55:410
71430rcu_preempt0-21swapper/019:25:160
71430rcu_preempt0-21swapper/019:25:160
1336399432cyclictest0-21swapper/020:20:080
1336399432cyclictest0-21swapper/020:20:080
71420rcu_preempt0-21swapper/122:09:571
71420rcu_preempt0-21swapper/122:09:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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