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2026-02-12 - 02:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Feb 12, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71750rcu_preempt0-21swapper/300:34:413
71750rcu_preempt0-21swapper/300:34:413
10876994520cyclictest11801-21diskmemload21:45:013
10876994520cyclictest11801-21diskmemload21:45:013
10876994520cyclictest11801-21diskmemload21:45:013
1087699434cyclictest0-21swapper/323:21:373
1087699434cyclictest0-21swapper/323:21:373
71420rcu_preempt0-21swapper/223:23:122
71420rcu_preempt0-21swapper/223:23:122
71420rcu_preempt0-21swapper/100:19:301
71420rcu_preempt0-21swapper/100:19:301
71420rcu_preempt0-21swapper/100:19:301
46050420irq/122-QManpo10195-2110:48:550
46050420irq/122-QManpo10195-2110:48:550
1087699424cyclictest0-21swapper/322:11:353
1087699424cyclictest0-21swapper/322:11:353
1087699423cyclictest0-21swapper/321:16:043
1087699423cyclictest0-21swapper/321:16:043
1087699423cyclictest0-21swapper/319:21:403
1087699423cyclictest0-21swapper/319:21:403
46050410irq/122-QManpo456-2110:48:550
46050410irq/122-QManpo456-2110:48:550
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
1087699414cyclictest0-21swapper/323:04:573
1087699414cyclictest0-21swapper/323:04:573
1087699414cyclictest0-21swapper/322:16:383
1087699414cyclictest0-21swapper/322:16:383
1087699414cyclictest0-21swapper/322:16:383
1087699414cyclictest0-21swapper/321:28:093
1087699414cyclictest0-21swapper/321:28:093
1087699414cyclictest0-21swapper/300:25:073
1087699414cyclictest0-21swapper/300:25:073
1087699413cyclictest0-21swapper/323:59:393
1087699413cyclictest0-21swapper/323:59:393
1087699413cyclictest0-21swapper/323:59:393
1087699413cyclictest0-21swapper/323:26:383
1087699413cyclictest0-21swapper/323:26:383
1087699413cyclictest0-21swapper/323:26:383
1087699413cyclictest0-21swapper/323:06:333
1087699413cyclictest0-21swapper/323:06:333
1087699413cyclictest0-21swapper/321:56:413
1087699413cyclictest0-21swapper/321:56:413
1087699413cyclictest0-21swapper/320:26:323
1087699413cyclictest0-21swapper/320:26:323
10876994117cyclictest0-21swapper/322:07:123
10876994117cyclictest0-21swapper/322:07:123
10876994117cyclictest0-21swapper/322:07:123
71400rcu_preempt15773-21unixbench_multi21:16:411
71400rcu_preempt15773-21unixbench_multi21:16:411
71400rcu_preempt15773-21unixbench_multi21:16:411
71400rcu_preempt0-21swapper/119:11:261
71400rcu_preempt0-21swapper/119:11:261
1087699403cyclictest15282-21ntp_states00:06:373
1087699403cyclictest15282-21ntp_states00:06:373
1087699403cyclictest15282-21ntp_states00:06:373
1087699403cyclictest0-21swapper/322:41:403
1087699403cyclictest0-21swapper/322:41:403
1087699403cyclictest0-21swapper/322:26:333
1087699403cyclictest0-21swapper/322:26:333
71390rcu_preempt2445-21kworker/0:022:00:260
71390rcu_preempt2445-21kworker/0:022:00:260
71390rcu_preempt23271-21copy21:31:192
71390rcu_preempt23271-21copy21:31:192
71390rcu_preempt21958-21copy19:51:263
71390rcu_preempt21958-21copy19:51:263
71390rcu_preempt0-21swapper/123:37:391
71390rcu_preempt0-21swapper/123:37:391
71390rcu_preempt0-21swapper/123:37:391
71390rcu_preempt0-21swapper/120:46:221
71390rcu_preempt0-21swapper/120:46:221
71390rcu_preempt0-21swapper/120:46:221
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
1087699394cyclictest0-21swapper/323:51:093
1087699394cyclictest0-21swapper/323:51:093
1087699393cyclictest0-21swapper/323:45:143
1087699393cyclictest0-21swapper/323:45:143
1087699393cyclictest0-21swapper/322:01:533
1087699393cyclictest0-21swapper/322:01:533
71380rcu_preempt9170-21aten_r4power_cu21:01:241
71380rcu_preempt9170-21aten_r4power_cu21:01:241
71380rcu_preempt29616-21meminfo21:41:330
71380rcu_preempt29616-21meminfo21:41:330
71380rcu_preempt29616-21meminfo21:41:330
71380rcu_preempt27028-21copy23:31:220
71380rcu_preempt27028-21copy23:31:220
71380rcu_preempt0-21swapper/222:59:482
71380rcu_preempt0-21swapper/222:59:482
71380rcu_preempt0-21swapper/222:59:482
71380rcu_preempt0-21swapper/123:45:391
71380rcu_preempt0-21swapper/123:45:391
71380rcu_preempt0-21swapper/100:23:171
71380rcu_preempt0-21swapper/100:23:171
71380rcu_preempt0-21swapper/022:17:310
71380rcu_preempt0-21swapper/022:17:310
71380rcu_preempt0-21swapper/022:17:310
46050380irq/122-QManpo25258-2110:48:550
46050380irq/122-QManpo25258-2110:48:550
46050380irq/122-QManpo25258-2110:48:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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