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2026-04-26 - 23:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Apr 26, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71550rcu_preempt7755-21meminfo07:27:572
71550rcu_preempt7755-21meminfo07:27:572
71550rcu_preempt2713-1kworker/2:1H07:12:422
71550rcu_preempt2713-1kworker/2:1H07:12:422
71550rcu_preempt0-21swapper/010:32:530
71550rcu_preempt0-21swapper/010:32:530
71550rcu_preempt0-21swapper/010:32:530
46450480irq/118-QManpo1715-2110:48:552
46450480irq/118-QManpo1715-2110:48:552
46450480irq/118-QManpo1715-2110:48:552
71460rcu_preempt27025-1kworker/0:0H12:23:450
71460rcu_preempt27025-1kworker/0:0H12:23:450
71460rcu_preempt0-21swapper/007:12:410
71460rcu_preempt0-21swapper/007:12:410
71440rcu_preempt0-21swapper/007:27:520
71440rcu_preempt0-21swapper/007:27:520
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
71420rcu_preempt0-21swapper/310:24:083
71420rcu_preempt0-21swapper/310:24:083
71420rcu_preempt0-21swapper/209:24:552
71420rcu_preempt0-21swapper/209:24:552
71420rcu_preempt0-21swapper/209:24:552
71420rcu_preempt0-21swapper/208:05:272
71420rcu_preempt0-21swapper/208:05:272
71420rcu_preempt0-21swapper/208:05:272
71420rcu_preempt0-21swapper/008:44:260
71420rcu_preempt0-21swapper/008:44:260
3102994218cyclictest1959-21runrttasks09:32:250
3102994218cyclictest1959-21runrttasks09:32:250
3102994218cyclictest1959-21runrttasks09:32:250
3102994012cyclictest0-21swapper/010:31:530
3102994012cyclictest0-21swapper/010:31:530
71390rcu_preempt6439-21ntpdc07:22:571
71390rcu_preempt6439-21ntpdc07:22:571
71390rcu_preempt0-21swapper/012:07:270
71390rcu_preempt0-21swapper/012:07:270
71390rcu_preempt0-21swapper/011:54:030
71390rcu_preempt0-21swapper/011:54:030
71390rcu_preempt0-21swapper/011:32:280
71390rcu_preempt0-21swapper/011:32:280
71390rcu_preempt0-21swapper/011:32:280
71390rcu_preempt0-21swapper/010:19:260
71390rcu_preempt0-21swapper/010:19:260
71390rcu_preempt0-21swapper/009:57:210
71390rcu_preempt0-21swapper/009:57:210
71390rcu_preempt0-21swapper/009:57:210
3102993918cyclictest31802-21meminfo11:02:550
3102993918cyclictest31802-21meminfo11:02:550
3102993917cyclictest31949-21ntp_states10:02:570
3102993917cyclictest31949-21ntp_states10:02:570
71380rcu_preempt32482-21ssh10:03:292
71380rcu_preempt32482-21ssh10:03:292
71380rcu_preempt23251-21/usr/sbin/munin11:48:022
71380rcu_preempt23251-21/usr/sbin/munin11:48:022
71380rcu_preempt23251-21/usr/sbin/munin11:48:022
71380rcu_preempt0-21swapper/211:15:322
71380rcu_preempt0-21swapper/211:15:322
71380rcu_preempt0-21swapper/210:28:212
71380rcu_preempt0-21swapper/210:28:212
71380rcu_preempt0-21swapper/109:21:041
71380rcu_preempt0-21swapper/109:21:041
71380rcu_preempt0-21swapper/012:33:120
71380rcu_preempt0-21swapper/012:33:120
71380rcu_preempt0-21swapper/010:22:540
71380rcu_preempt0-21swapper/010:22:540
71380rcu_preempt0-21swapper/009:23:360
71380rcu_preempt0-21swapper/009:23:360
71380rcu_preempt0-21swapper/009:23:360
3102993817cyclictest2285-21/usr/sbin/munin10:08:000
3102993817cyclictest2285-21/usr/sbin/munin10:08:000
3102993817cyclictest2285-21/usr/sbin/munin10:08:000
3102993810cyclictest3145-21memory09:07:540
3102993810cyclictest3145-21memory09:07:540
71370rcu_preempt4170-21sh09:12:432
71370rcu_preempt4170-21sh09:12:432
71370rcu_preempt27024-1kworker/3:0H12:05:033
71370rcu_preempt27024-1kworker/3:0H12:05:033
71370rcu_preempt13633-21sh11:28:482
71370rcu_preempt13633-21sh11:28:482
71370rcu_preempt13633-21sh11:28:482
71370rcu_preempt11745-21kworker/u8:211:05:332
71370rcu_preempt11745-21kworker/u8:211:05:332
71370rcu_preempt0-21swapper/312:18:363
71370rcu_preempt0-21swapper/312:18:363
71370rcu_preempt0-21swapper/310:38:003
71370rcu_preempt0-21swapper/310:38:003
71370rcu_preempt0-21swapper/212:06:122
71370rcu_preempt0-21swapper/212:06:122
71370rcu_preempt0-21swapper/211:44:202
71370rcu_preempt0-21swapper/211:44:202
71370rcu_preempt0-21swapper/211:44:202
71370rcu_preempt0-21swapper/211:33:342
71370rcu_preempt0-21swapper/211:33:342
71370rcu_preempt0-21swapper/211:33:342
71370rcu_preempt0-21swapper/210:53:182
71370rcu_preempt0-21swapper/210:53:182
71370rcu_preempt0-21swapper/210:18:132
71370rcu_preempt0-21swapper/210:18:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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