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2026-07-26 - 22:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Jul 26, 2026 12:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
171670rcuc/111321-1kworker/1:1H09:39:351
171670rcuc/111321-1kworker/1:1H09:39:351
171670rcuc/111321-1kworker/1:1H09:39:351
46050570irq/122-QManpo28965-2110:48:550
46050570irq/122-QManpo28965-2110:48:550
46250490irq/120-QManpo28993-211
46250490irq/120-QManpo28993-211
46050460irq/122-QManpo0-210
46050460irq/122-QManpo0-210
71450rcu_preempt2456-21kworker/2:110:26:562
71450rcu_preempt2456-21kworker/2:110:26:562
2918999443cyclictest0-21swapper/112:39:251
2918999443cyclictest0-21swapper/112:39:251
2918999443cyclictest0-21swapper/110:49:291
2918999443cyclictest0-21swapper/110:49:291
2918999442cyclictest31678-21ntp_states12:09:311
2918999442cyclictest31678-21ntp_states12:09:311
2918999442cyclictest31678-21ntp_states12:09:311
2918999442cyclictest17630-21ntp_states09:49:311
2918999442cyclictest17630-21ntp_states09:49:311
29189994417cyclictest7670-21memory10:29:351
29189994417cyclictest7670-21memory10:29:351
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
2918999433cyclictest0-21swapper/111:19:281
2918999433cyclictest0-21swapper/111:19:281
2918999433cyclictest0-21swapper/109:32:281
2918999433cyclictest0-21swapper/109:32:281
2918999432cyclictest31377-21/usr/sbin/munin10:14:231
2918999432cyclictest31377-21/usr/sbin/munin10:14:231
29189994317cyclictest0-21swapper/110:23:401
29189994317cyclictest0-21swapper/110:23:401
29189994317cyclictest0-21swapper/109:28:201
29189994317cyclictest0-21swapper/109:28:201
71420rcu_preempt3491-21ntp_states11:19:330
71420rcu_preempt3491-21ntp_states11:19:330
2918999423cyclictest0-21swapper/109:58:111
2918999423cyclictest0-21swapper/109:58:111
2918999422cyclictest6412-21meminfo07:49:261
2918999422cyclictest6412-21meminfo07:49:261
29189994218cyclictest0-21swapper/107:34:241
29189994218cyclictest0-21swapper/107:34:241
2918999413cyclictest0-21swapper/111:41:511
2918999413cyclictest0-21swapper/111:41:511
2918999413cyclictest0-21swapper/111:09:201
2918999413cyclictest0-21swapper/111:09:201
2918999413cyclictest0-21swapper/110:59:331
2918999413cyclictest0-21swapper/110:59:331
2918999413cyclictest0-21swapper/110:09:071
2918999413cyclictest0-21swapper/110:09:071
2918999413cyclictest0-21swapper/110:09:071
2918999413cyclictest0-21swapper/109:49:091
2918999413cyclictest0-21swapper/109:49:091
2918999413cyclictest0-21swapper/107:54:321
2918999413cyclictest0-21swapper/107:54:321
2918999411cyclictest30526-21unixbench_multi09:14:401
2918999411cyclictest30526-21unixbench_multi09:14:401
29189994116cyclictest0-21swapper/110:43:411
29189994116cyclictest0-21swapper/110:43:411
29189994116cyclictest0-21swapper/110:43:411
29189994113cyclictest0-21swapper/110:13:201
29189994113cyclictest0-21swapper/110:13:201
29189994113cyclictest0-21swapper/110:13:201
71400rcu_preempt0-21swapper/010:42:370
71400rcu_preempt0-21swapper/010:42:370
71400rcu_preempt0-21swapper/010:42:370
71400rcu_preempt0-21swapper/010:19:320
71400rcu_preempt0-21swapper/010:19:320
71400rcu_preempt0-21swapper/009:59:200
71400rcu_preempt0-21swapper/009:59:200
46450400irq/118-QManpo28917-212
46450400irq/118-QManpo28917-212
46050400irq/122-QManpo7897-2110:48:550
46050400irq/122-QManpo7897-2110:48:550
2918999403cyclictest0-21swapper/112:29:221
2918999403cyclictest0-21swapper/112:29:221
2918999403cyclictest0-21swapper/112:17:191
2918999403cyclictest0-21swapper/112:17:191
2918999403cyclictest0-21swapper/111:46:471
2918999403cyclictest0-21swapper/111:46:471
29189994015cyclictest378-21irqstats11:14:291
29189994015cyclictest378-21irqstats11:14:291
29189994015cyclictest378-21irqstats11:14:291
29189994015cyclictest0-21swapper/112:22:151
29189994015cyclictest0-21swapper/112:22:151
29189994015cyclictest0-21swapper/112:22:151
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
2918999393cyclictest0-21swapper/111:29:351
2918999393cyclictest0-21swapper/111:29:351
2918999391cyclictest27048-21df11:04:211
2918999391cyclictest27048-21df11:04:211
29189993912cyclictest0-21swapper/112:04:351
29189993912cyclictest0-21swapper/112:04:351
29189993912cyclictest0-21swapper/112:04:351
71380rcu_preempt0-21swapper/311:14:113
71380rcu_preempt0-21swapper/311:14:113
71380rcu_preempt0-21swapper/112:24:181
71380rcu_preempt0-21swapper/112:24:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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