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2025-12-16 - 03:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Dec 16, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71800rcu_preempt0-21swapper/121:20:131
71800rcu_preempt0-21swapper/121:20:131
71650rcu_preempt0-21swapper/222:33:512
71650rcu_preempt0-21swapper/222:33:512
71640rcu_preempt0-21swapper/123:01:371
71640rcu_preempt0-21swapper/123:01:371
71620rcu_preempt0-21swapper/022:12:240
71620rcu_preempt0-21swapper/022:12:240
71600rcu_preempt0-21swapper/022:41:090
71590rcu_preempt0-21swapper/222:24:082
71540rcu_preempt0-21swapper/321:46:333
22298995110cyclictest32047-21sed00:10:331
71460rcu_preempt0-21swapper/100:34:221
71460rcu_preempt0-21swapper/100:34:221
22298994518cyclictest3176-21ntp_states22:25:291
22298994518cyclictest3176-21ntp_states22:25:291
2229899434cyclictest0-21swapper/123:25:311
2229899434cyclictest0-21swapper/123:25:311
2229899433cyclictest0-21swapper/122:30:181
2229899433cyclictest0-21swapper/122:30:181
22298994321cyclictest0-21swapper/120:40:051
22298994321cyclictest0-21swapper/120:40:051
22298994318cyclictest0-21swapper/100:05:451
46050420irq/122-QManpo22296-2110:48:540
46050420irq/122-QManpo22296-2110:48:540
2229899423cyclictest0-21swapper/123:56:451
2229899423cyclictest0-21swapper/123:56:451
2229899423cyclictest0-21swapper/122:10:201
2229899423cyclictest0-21swapper/122:10:201
2229899423cyclictest0-21swapper/119:30:171
2229899423cyclictest0-21swapper/119:30:171
22298994218cyclictest0-21swapper/123:18:191
22298994218cyclictest0-21swapper/123:18:191
22298994218cyclictest0-21swapper/122:20:061
22298994218cyclictest0-21swapper/122:20:061
71410rcu_preempt0-21swapper/000:00:060
71410rcu_preempt0-21swapper/000:00:060
2299410migration/221928-21taskset19:05:422
2299410migration/221928-21taskset19:05:422
2229899413cyclictest0-21swapper/123:45:231
2229899413cyclictest0-21swapper/123:45:231
2229899413cyclictest0-21swapper/123:41:341
2229899413cyclictest0-21swapper/122:37:171
2229899413cyclictest0-21swapper/122:37:171
2229899413cyclictest0-21swapper/121:28:041
2229899413cyclictest0-21swapper/121:28:041
2229899413cyclictest0-21swapper/121:16:061
2229899413cyclictest0-21swapper/121:16:061
2229899413cyclictest0-21swapper/121:16:061
2229899413cyclictest0-21swapper/120:47:561
2229899413cyclictest0-21swapper/120:47:561
2229899413cyclictest0-21swapper/120:30:171
2229899413cyclictest0-21swapper/120:13:481
2229899413cyclictest0-21swapper/120:13:481
2229899413cyclictest0-21swapper/120:05:211
2229899413cyclictest0-21swapper/120:05:211
2229899412cyclictest16148-21seq22:48:071
2229899412cyclictest15043-21ntp_states21:50:301
2229899412cyclictest15043-21ntp_states21:50:301
71400rcu_preempt0-21swapper/122:09:151
71400rcu_preempt0-21swapper/122:09:151
2229899403cyclictest0-21swapper/123:30:241
2229899403cyclictest0-21swapper/123:30:241
2229899403cyclictest0-21swapper/123:10:231
2229899403cyclictest0-21swapper/123:10:231
2229899403cyclictest0-21swapper/121:48:041
2229899403cyclictest0-21swapper/121:10:271
2229899403cyclictest0-21swapper/121:05:271
2229899403cyclictest0-21swapper/121:05:271
2229899403cyclictest0-21swapper/120:15:231
2229899403cyclictest0-21swapper/120:15:231
2229899403cyclictest0-21swapper/119:20:271
2229899402cyclictest4836-21diskstats00:20:221
2229899402cyclictest4836-21diskstats00:20:221
71390rcu_preempt8959-21irqstats21:40:262
71390rcu_preempt8959-21irqstats21:40:262
71390rcu_preempt0-21swapper/019:15:070
46050390irq/122-QManpo15293-2110:48:540
2229899393cyclictest0-21swapper/121:56:561
2229899393cyclictest0-21swapper/121:56:561
2229899392cyclictest0-21swapper/122:20:181
71380rcu_preempt0-21swapper/223:45:112
71380rcu_preempt0-21swapper/223:45:112
71380rcu_preempt0-21swapper/022:07:030
71380rcu_preempt0-21swapper/022:07:030
71380rcu_preempt0-21swapper/021:30:010
71380rcu_preempt0-21swapper/021:30:010
2229899383cyclictest0-21swapper/123:35:451
2229899383cyclictest0-21swapper/123:35:451
2229899383cyclictest0-21swapper/122:52:371
2229899383cyclictest0-21swapper/122:52:371
2229899383cyclictest0-21swapper/122:04:591
2229899383cyclictest0-21swapper/122:04:591
99750370irq/38-i2c-mpc0-21swapper/019:22:280
71370rcu_preempt22869-1kworker/0:0H21:10:170
71370rcu_preempt0-21swapper/322:43:033
71370rcu_preempt0-21swapper/222:20:032
71370rcu_preempt0-21swapper/222:20:032
71370rcu_preempt0-21swapper/200:34:042
71370rcu_preempt0-21swapper/200:34:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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