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2026-03-06 - 03:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Mar 06, 2026 00:44:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71730rcu_preempt0-21swapper/200:32:492
71730rcu_preempt0-21swapper/200:32:492
71670rcu_preempt0-21swapper/221:15:432
71670rcu_preempt0-21swapper/221:15:432
71620rcu_preempt0-21swapper/223:48:272
71620rcu_preempt0-21swapper/223:48:272
71540rcu_preempt31092-21ssh00:37:043
71540rcu_preempt31092-21ssh00:37:043
71540rcu_preempt31092-21ssh00:37:043
46650490irq/116-QManpo10459-2110:48:553
46650490irq/116-QManpo10459-2110:48:553
46050490irq/122-QManpo0-210
46050490irq/122-QManpo0-210
71470rcu_preempt0-21swapper/219:06:502
71470rcu_preempt0-21swapper/219:06:502
71450rcu_preempt0-21swapper/321:26:383
71450rcu_preempt0-21swapper/321:26:383
71440rcu_preempt0-21swapper/000:13:570
71440rcu_preempt0-21swapper/000:13:570
71430rcu_preempt0-21swapper/000:02:180
71430rcu_preempt0-21swapper/000:02:180
71410rcu_preempt18805-21ssh21:23:201
71410rcu_preempt18805-21ssh21:23:201
71410rcu_preempt0-21swapper/019:46:590
71410rcu_preempt0-21swapper/019:46:590
71400rcu_preempt0-21swapper/123:34:031
71400rcu_preempt0-21swapper/123:34:031
71400rcu_preempt0-21swapper/123:34:031
71400rcu_preempt0-21swapper/100:06:461
71400rcu_preempt0-21swapper/100:06:461
71400rcu_preempt0-21swapper/023:42:270
71400rcu_preempt0-21swapper/023:42:270
71400rcu_preempt0-21swapper/023:42:270
71400rcu_preempt0-21swapper/000:41:410
71400rcu_preempt0-21swapper/000:41:410
71400rcu_preempt0-21swapper/000:41:410
71390rcu_preempt27826-21/usr/sbin/munin00:31:510
71390rcu_preempt27826-21/usr/sbin/munin00:31:510
71390rcu_preempt20330-21sed21:26:511
71390rcu_preempt20330-21sed21:26:511
71390rcu_preempt0-21swapper/020:02:020
71390rcu_preempt0-21swapper/020:02:020
71390rcu_preempt0-21swapper/000:17:340
71390rcu_preempt0-21swapper/000:17:340
71390rcu_preempt0-21swapper/000:17:340
46250390irq/120-QManpo0-2110:48:551
46250390irq/120-QManpo0-2110:48:551
71380rcu_preempt29761-1kworker/0:2H21:42:300
71380rcu_preempt29761-1kworker/0:2H21:42:300
71380rcu_preempt21955-21sh23:23:340
71380rcu_preempt21955-21sh23:23:340
71380rcu_preempt19290-1kworker/0:2H21:30:380
71380rcu_preempt19290-1kworker/0:2H21:30:380
71380rcu_preempt15749-1kworker/0:1H21:58:560
71380rcu_preempt15749-1kworker/0:1H21:58:560
71380rcu_preempt0-21swapper/223:27:072
71380rcu_preempt0-21swapper/223:27:072
71380rcu_preempt0-21swapper/023:57:470
71380rcu_preempt0-21swapper/023:57:470
71380rcu_preempt0-21swapper/023:57:470
71380rcu_preempt0-21swapper/023:02:120
71380rcu_preempt0-21swapper/023:02:120
71380rcu_preempt0-21swapper/000:23:500
71380rcu_preempt0-21swapper/000:23:500
71380rcu_preempt0-21swapper/000:23:500
71380rcu_preempt0-21swapper/000:06:550
71380rcu_preempt0-21swapper/000:06:550
46050380irq/122-QManpo31411-2110:48:550
46050380irq/122-QManpo31411-2110:48:550
46050380irq/122-QManpo17609-2110:48:550
46050380irq/122-QManpo17609-2110:48:550
46050380irq/122-QManpo17609-2110:48:550
71370rcu_preempt9762-21sh23:02:042
71370rcu_preempt9762-21sh23:02:042
71370rcu_preempt21651-21sh22:26:470
71370rcu_preempt21651-21sh22:26:470
71370rcu_preempt0-21swapper/320:31:583
71370rcu_preempt0-21swapper/320:31:583
71370rcu_preempt0-21swapper/123:48:311
71370rcu_preempt0-21swapper/123:48:311
71370rcu_preempt0-21swapper/123:19:011
71370rcu_preempt0-21swapper/123:19:011
71370rcu_preempt0-21swapper/123:19:011
71370rcu_preempt0-21swapper/122:22:131
71370rcu_preempt0-21swapper/122:22:131
71370rcu_preempt0-21swapper/121:42:071
71370rcu_preempt0-21swapper/121:42:071
71370rcu_preempt0-21swapper/023:14:550
71370rcu_preempt0-21swapper/023:14:550
71370rcu_preempt0-21swapper/023:14:550
71370rcu_preempt0-21swapper/022:59:410
71370rcu_preempt0-21swapper/022:59:410
71370rcu_preempt0-21swapper/022:59:410
71370rcu_preempt0-21swapper/022:22:450
71370rcu_preempt0-21swapper/022:22:450
71370rcu_preempt0-21swapper/022:13:360
71370rcu_preempt0-21swapper/022:13:360
71370rcu_preempt0-21swapper/021:31:540
71370rcu_preempt0-21swapper/021:31:540
71370rcu_preempt0-21swapper/021:22:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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