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2026-07-21 - 18:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Jul 21, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131512870chrt46250irq/120-QMan10:48:551
131512870chrt46250irq/120-QMan10:48:551
131512870chrt46250irq/120-QMan10:48:551
71500rcu_preempt0-21swapper/209:19:402
71500rcu_preempt0-21swapper/209:19:402
71500rcu_preempt0-21swapper/209:19:402
46050470irq/122-QManpo591-2110:48:550
46050470irq/122-QManpo591-2110:48:550
46050470irq/122-QManpo591-2110:48:550
71450rcu_preempt0-21swapper/010:39:270
71450rcu_preempt0-21swapper/010:39:270
71450rcu_preempt0-21swapper/010:39:270
71440rcu_preempt0-21swapper/208:15:312
71440rcu_preempt0-21swapper/208:15:312
71430rcu_preempt1486-21diskmemload10:02:052
71430rcu_preempt1486-21diskmemload10:02:052
71430rcu_preempt0-21swapper/311:55:323
71430rcu_preempt0-21swapper/311:55:323
71420rcu_preempt0-21swapper/011:04:140
71420rcu_preempt0-21swapper/011:04:140
71420rcu_preempt0-21swapper/011:04:140
71410rcu_preempt0-21swapper/209:45:182
71410rcu_preempt0-21swapper/209:45:182
71410rcu_preempt0-21swapper/209:45:182
71410rcu_preempt0-21swapper/007:31:010
71410rcu_preempt0-21swapper/007:31:010
46050410irq/122-QManpo2039-2110:48:550
46050410irq/122-QManpo2039-2110:48:550
71400rcu_preempt19153-21taskset10:50:132
71400rcu_preempt19153-21taskset10:50:132
71400rcu_preempt19153-21taskset10:50:132
71400rcu_preempt0-21swapper/308:26:523
71400rcu_preempt0-21swapper/308:26:523
71400rcu_preempt0-21swapper/308:26:523
71400rcu_preempt0-21swapper/212:30:162
71400rcu_preempt0-21swapper/212:30:162
46050400irq/122-QManpo14420-2110:48:550
46050400irq/122-QManpo14420-2110:48:550
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
849993914cyclictest3285-21grep10:19:321
849993914cyclictest3285-21grep10:19:321
71390rcu_preempt0-21swapper/211:52:132
71390rcu_preempt0-21swapper/211:52:132
71390rcu_preempt0-21swapper/211:52:132
71390rcu_preempt0-21swapper/211:03:002
71390rcu_preempt0-21swapper/211:03:002
71390rcu_preempt0-21swapper/211:03:002
71390rcu_preempt0-21swapper/210:11:182
71390rcu_preempt0-21swapper/210:11:182
71390rcu_preempt0-21swapper/210:11:182
71390rcu_preempt0-21swapper/210:07:492
71390rcu_preempt0-21swapper/210:07:492
71390rcu_preempt0-21swapper/210:07:492
71390rcu_preempt0-21swapper/209:40:442
71390rcu_preempt0-21swapper/209:40:442
71390rcu_preempt0-21swapper/012:24:540
71390rcu_preempt0-21swapper/012:24:540
71390rcu_preempt0-21swapper/012:24:540
71390rcu_preempt0-21swapper/012:07:470
71390rcu_preempt0-21swapper/012:07:470
71390rcu_preempt0-21swapper/012:07:470
71390rcu_preempt0-21swapper/011:09:100
71390rcu_preempt0-21swapper/011:09:100
71390rcu_preempt0-21swapper/011:09:100
71380rcu_preempt0-21swapper/310:29:283
71380rcu_preempt0-21swapper/310:29:283
71380rcu_preempt0-21swapper/210:18:362
71380rcu_preempt0-21swapper/210:18:362
71380rcu_preempt0-21swapper/210:18:362
71380rcu_preempt0-21swapper/209:37:452
71380rcu_preempt0-21swapper/209:37:452
71380rcu_preempt0-21swapper/209:37:452
71380rcu_preempt0-21swapper/209:01:142
71380rcu_preempt0-21swapper/209:01:142
71380rcu_preempt0-21swapper/209:01:142
71380rcu_preempt0-21swapper/207:29:542
71380rcu_preempt0-21swapper/207:29:542
71380rcu_preempt0-21swapper/010:29:550
71380rcu_preempt0-21swapper/010:29:550
71380rcu_preempt0-21swapper/009:39:460
71380rcu_preempt0-21swapper/009:39:460
46050380irq/122-QManpo16172-210
46050380irq/122-QManpo16172-210
46050380irq/122-QManpo16172-210
46050380irq/122-QManpo14420-2110:48:550
46050380irq/122-QManpo14420-2110:48:550
46050380irq/122-QManpo14420-2110:48:550
46050380irq/122-QManpo13386-2110:48:550
46050380irq/122-QManpo13386-2110:48:550
46050380irq/122-QManpo13386-2110:48:550
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
71370rcu_preempt8338-21sh12:36:272
71370rcu_preempt8338-21sh12:36:272
71370rcu_preempt22026-21seq10:56:192
71370rcu_preempt22026-21seq10:56:192
71370rcu_preempt22026-21seq10:56:192
71370rcu_preempt0-21swapper/312:14:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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