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2026-05-08 - 20:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri May 08, 2026 12:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71760rcu_preempt0-21swapper/209:45:462
71760rcu_preempt0-21swapper/209:45:462
71760rcu_preempt0-21swapper/209:45:462
66302580chrt46650irq/116-QMan10:48:553
66302580chrt46650irq/116-QMan10:48:553
71480rcu_preempt0-21swapper/311:42:553
71480rcu_preempt0-21swapper/311:42:553
71450rcu_preempt0-21swapper/211:48:332
71450rcu_preempt0-21swapper/211:48:332
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
71410rcu_preempt22790-21cat07:12:470
71410rcu_preempt22790-21cat07:12:470
46050410irq/122-QManpo4237-2110:48:550
46050410irq/122-QManpo4237-2110:48:550
46050410irq/122-QManpo31075-2110:48:550
46050410irq/122-QManpo31075-2110:48:550
46050410irq/122-QManpo14582-2110:48:550
46050410irq/122-QManpo14582-2110:48:550
71400rcu_preempt22732-21crond07:12:441
71400rcu_preempt22732-21crond07:12:441
71400rcu_preempt17537-21sendmail-msp12:06:342
71400rcu_preempt17537-21sendmail-msp12:06:342
71400rcu_preempt15099-21ssh11:57:583
71400rcu_preempt15099-21ssh11:57:583
71400rcu_preempt0-21swapper/212:35:012
71400rcu_preempt0-21swapper/212:35:012
71400rcu_preempt0-21swapper/209:36:532
71400rcu_preempt0-21swapper/209:36:532
71400rcu_preempt0-21swapper/209:36:532
46050400irq/122-QManpo25496-2110:48:550
46050400irq/122-QManpo25496-2110:48:550
46050400irq/122-QManpo25496-2110:48:550
99750390irq/38-i2c-mpc5535-21ssh11:39:070
99750390irq/38-i2c-mpc5535-21ssh11:39:070
71390rcu_preempt4884-21ssh12:38:262
71390rcu_preempt4884-21ssh12:38:262
71390rcu_preempt28708-21/usr/sbin/munin11:23:112
71390rcu_preempt28708-21/usr/sbin/munin11:23:112
71390rcu_preempt28708-21/usr/sbin/munin11:23:112
71390rcu_preempt2692-21ssh09:33:053
71390rcu_preempt2692-21ssh09:33:053
71390rcu_preempt2692-21ssh09:33:053
71390rcu_preempt0-21swapper/311:12:243
71390rcu_preempt0-21swapper/311:12:243
71390rcu_preempt0-21swapper/311:12:243
71390rcu_preempt0-21swapper/011:47:490
71390rcu_preempt0-21swapper/011:47:490
46050390irq/122-QManpo23665-2110:48:550
46050390irq/122-QManpo23665-2110:48:550
46050390irq/122-QManpo23665-2110:48:550
46050390irq/122-QManpo21827-2110:48:550
46050390irq/122-QManpo21827-2110:48:550
46050390irq/122-QManpo21827-2110:48:550
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
71380rcu_preempt24224-1kworker/2:0H10:33:372
71380rcu_preempt24224-1kworker/2:0H10:33:372
71380rcu_preempt24224-1kworker/2:0H10:33:372
71380rcu_preempt0-21swapper/211:09:032
71380rcu_preempt0-21swapper/211:09:032
71380rcu_preempt0-21swapper/211:09:032
71380rcu_preempt0-21swapper/210:52:022
71380rcu_preempt0-21swapper/210:52:022
71380rcu_preempt0-21swapper/209:54:082
71380rcu_preempt0-21swapper/209:54:082
71380rcu_preempt0-21swapper/209:54:082
71380rcu_preempt0-21swapper/209:54:082
71380rcu_preempt0-21swapper/209:26:572
71380rcu_preempt0-21swapper/209:26:572
71380rcu_preempt0-21swapper/209:26:572
71380rcu_preempt0-21swapper/207:27:482
71380rcu_preempt0-21swapper/207:27:482
71380rcu_preempt0-21swapper/207:27:482
71380rcu_preempt0-21swapper/012:33:310
71380rcu_preempt0-21swapper/012:33:310
71380rcu_preempt0-21swapper/012:14:250
71380rcu_preempt0-21swapper/012:14:250
71380rcu_preempt0-21swapper/009:05:320
71380rcu_preempt0-21swapper/009:05:320
71380rcu_preempt0-21swapper/009:05:320
71380rcu_preempt0-21swapper/009:05:320
46050380irq/122-QManpo9734-2110:48:550
46050380irq/122-QManpo9734-2110:48:550
46050380irq/122-QManpo15070-2110:48:550
46050380irq/122-QManpo15070-2110:48:550
71370rcu_preempt22255-21sh12:11:200
71370rcu_preempt22255-21sh12:11:200
71370rcu_preempt22255-21sh12:11:200
71370rcu_preempt0-21swapper/311:27:533
71370rcu_preempt0-21swapper/211:35:132
71370rcu_preempt0-21swapper/211:35:132
71370rcu_preempt0-21swapper/210:44:452
71370rcu_preempt0-21swapper/210:44:452
71370rcu_preempt0-21swapper/210:44:452
71370rcu_preempt0-21swapper/209:30:482
71370rcu_preempt0-21swapper/209:30:482
71370rcu_preempt0-21swapper/209:30:482
71370rcu_preempt0-21swapper/209:30:482
71370rcu_preempt0-21swapper/208:27:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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