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2026-02-19 - 13:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Feb 19, 2026 00:44:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71860rcu_preempt0-21swapper/021:52:330
71860rcu_preempt0-21swapper/021:52:330
71680rcu_preempt0-21swapper/000:07:550
71680rcu_preempt0-21swapper/000:07:550
71530rcu_preempt0-21swapper/000:16:280
71530rcu_preempt0-21swapper/000:16:280
71530rcu_preempt0-21swapper/000:16:280
71490rcu_preempt0-21swapper/019:42:480
71490rcu_preempt0-21swapper/019:42:480
2356199483cyclictest0-21swapper/122:56:341
2356199483cyclictest0-21swapper/122:56:341
71470rcu_preempt18549-21copy23:51:300
71470rcu_preempt18549-21copy23:51:300
2356199461cyclictest9042-21apt-get00:31:271
2356199461cyclictest9042-21apt-get00:31:271
2356199461cyclictest29181-21apt-get19:31:291
2356199461cyclictest29181-21apt-get19:31:291
2356199461cyclictest29181-21apt-get19:31:291
2356199453cyclictest0-21swapper/123:26:381
2356199453cyclictest0-21swapper/123:26:381
2356199453cyclictest0-21swapper/100:02:221
2356199453cyclictest0-21swapper/100:02:221
2356199453cyclictest0-21swapper/100:02:221
71440rcu_preempt0-21swapper/322:41:223
71440rcu_preempt0-21swapper/322:41:223
2356199446cyclictest0-21swapper/123:41:191
2356199446cyclictest0-21swapper/123:41:191
2356199446cyclictest0-21swapper/123:41:191
2356199443cyclictest0-21swapper/121:49:061
2356199443cyclictest0-21swapper/121:49:061
1599440migration/022741-21/usr/sbin/munin19:06:400
1599440migration/022741-21/usr/sbin/munin19:06:400
2356199433cyclictest0-21swapper/123:23:511
2356199433cyclictest0-21swapper/123:23:511
2356199432cyclictest10838-21df20:21:311
2356199432cyclictest10838-21df20:21:311
2356199423cyclictest0-21swapper/122:36:191
2356199423cyclictest0-21swapper/122:36:191
2356199423cyclictest0-21swapper/122:29:241
2356199423cyclictest0-21swapper/122:29:241
2356199423cyclictest0-21swapper/121:11:321
2356199423cyclictest0-21swapper/121:11:321
2356199423cyclictest0-21swapper/121:11:321
2356199423cyclictest0-21swapper/120:31:371
2356199423cyclictest0-21swapper/120:31:371
2356199423cyclictest0-21swapper/120:11:451
2356199423cyclictest0-21swapper/120:11:451
2356199423cyclictest0-21swapper/100:16:191
2356199423cyclictest0-21swapper/100:16:191
23561994218cyclictest0-21swapper/122:21:421
23561994218cyclictest0-21swapper/122:21:421
23561994216cyclictest6563-21apt21:36:291
23561994216cyclictest6563-21apt21:36:291
71410rcu_preempt15673-21kworker/u8:123:40:482
71410rcu_preempt15673-21kworker/u8:123:40:482
71410rcu_preempt15673-21kworker/u8:123:40:482
71410rcu_preempt0-21swapper/322:56:283
71410rcu_preempt0-21swapper/322:56:283
71410rcu_preempt0-21swapper/300:03:043
71410rcu_preempt0-21swapper/300:03:043
71410rcu_preempt0-21swapper/300:03:043
71410rcu_preempt0-21swapper/221:37:442
71410rcu_preempt0-21swapper/221:37:442
71410rcu_preempt0-21swapper/020:36:400
71410rcu_preempt0-21swapper/020:36:400
71410rcu_preempt0-21swapper/020:36:400
71410rcu_preempt0-21swapper/020:36:400
46050410irq/122-QManpo12196-210
46050410irq/122-QManpo12196-210
2356199413cyclictest0-21swapper/123:43:391
2356199413cyclictest0-21swapper/123:43:391
2356199413cyclictest0-21swapper/122:51:391
2356199413cyclictest0-21swapper/122:51:391
2356199413cyclictest0-21swapper/122:11:421
2356199413cyclictest0-21swapper/122:11:421
2356199413cyclictest0-21swapper/122:02:061
2356199413cyclictest0-21swapper/122:02:061
2356199413cyclictest0-21swapper/121:31:361
2356199413cyclictest0-21swapper/121:31:361
2356199413cyclictest0-21swapper/121:26:341
2356199413cyclictest0-21swapper/121:26:341
2356199413cyclictest0-21swapper/100:26:321
2356199413cyclictest0-21swapper/100:26:321
2356199413cyclictest0-21swapper/100:26:321
2356199412cyclictest31958-21/usr/sbin/munin19:41:351
2356199412cyclictest31958-21/usr/sbin/munin19:41:351
2356199412cyclictest0-21swapper/123:52:191
2356199412cyclictest0-21swapper/123:52:191
2356199411cyclictest23603-21users23:01:471
2356199411cyclictest23603-21users23:01:471
2356199411cyclictest23603-21users23:01:471
23561994114cyclictest21631-21apt21:01:171
23561994114cyclictest21631-21apt21:01:171
23561994114cyclictest21631-21apt21:01:171
23561994111cyclictest0-21swapper/119:26:181
23561994111cyclictest0-21swapper/119:26:181
23561994111cyclictest0-21swapper/119:26:181
1599410migration/09330-21/usr/sbin/munin22:36:480
1599410migration/09330-21/usr/sbin/munin22:36:480
71400rcu_preempt5816-21sh23:27:542
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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