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2026-05-12 - 05:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue May 12, 2026 00:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71850rcu_preempt0-21swapper/300:07:023
71850rcu_preempt0-21swapper/300:07:023
71690rcu_preempt0-21swapper/021:15:270
71690rcu_preempt0-21swapper/021:15:270
71660rcu_preempt0-21swapper/000:34:150
71660rcu_preempt0-21swapper/000:34:150
71650rcu_preempt0-21swapper/122:09:321
71650rcu_preempt0-21swapper/122:09:321
71650rcu_preempt0-21swapper/122:09:321
71640rcu_preempt0-21swapper/123:15:551
71640rcu_preempt0-21swapper/123:15:551
71580rcu_preempt0-21swapper/323:28:013
71580rcu_preempt0-21swapper/323:28:013
71570rcu_preempt0-21swapper/122:47:201
71570rcu_preempt0-21swapper/122:47:201
71530rcu_preempt0-21swapper/321:19:153
71530rcu_preempt0-21swapper/321:19:153
71490rcu_preempt18101-21kworker/0:222:12:260
71490rcu_preempt18101-21kworker/0:222:12:260
71490rcu_preempt18101-21kworker/0:222:12:260
71470rcu_preempt10375-1kworker/0:3H21:22:590
71470rcu_preempt10375-1kworker/0:3H21:22:590
71470rcu_preempt10375-1kworker/0:3H21:22:590
71460rcu_preempt31984-21apt-get23:48:013
71460rcu_preempt31984-21apt-get23:48:013
71460rcu_preempt31984-21apt-get23:48:013
46050460irq/122-QManpo11189-2110:48:550
46050460irq/122-QManpo11189-2110:48:550
46050450irq/122-QManpo14082-2110:48:550
46050450irq/122-QManpo14082-2110:48:550
1127099456cyclictest18063-21seq00:21:492
1127099456cyclictest18063-21seq00:21:492
71440rcu_preempt13852-21sh22:14:060
71440rcu_preempt13852-21sh22:14:060
71440rcu_preempt0-21swapper/121:25:201
71440rcu_preempt0-21swapper/121:25:201
71440rcu_preempt0-21swapper/121:25:201
71440rcu_preempt0-21swapper/120:30:361
71440rcu_preempt0-21swapper/120:30:361
2299440migration/28837-21aten_r4power_en19:08:012
2299440migration/28837-21aten_r4power_en19:08:012
1127099444cyclictest0-21swapper/223:22:492
1127099444cyclictest0-21swapper/223:22:492
11270994419cyclictest0-21swapper/222:58:132
11270994419cyclictest0-21swapper/222:58:132
71430rcu_preempt0-21swapper/223:28:102
71430rcu_preempt0-21swapper/223:28:102
46050430irq/122-QManpo29147-2110:48:550
46050430irq/122-QManpo29147-2110:48:550
46050430irq/122-QManpo29147-2110:48:550
46050430irq/122-QManpo29147-2110:48:550
46050430irq/122-QManpo20947-2110:48:550
46050430irq/122-QManpo20947-2110:48:550
1127099434cyclictest0-21swapper/223:48:032
1127099434cyclictest0-21swapper/223:48:032
1127099434cyclictest0-21swapper/223:48:032
71420rcu_preempt0-21swapper/123:24:341
71420rcu_preempt0-21swapper/123:24:341
71420rcu_preempt0-21swapper/123:24:341
71420rcu_preempt0-21swapper/122:51:471
71420rcu_preempt0-21swapper/122:51:471
71420rcu_preempt0-21swapper/121:58:431
71420rcu_preempt0-21swapper/121:58:431
71420rcu_preempt0-21swapper/121:58:431
46050420irq/122-QManpo20747-2110:48:550
46050420irq/122-QManpo20747-2110:48:550
46050420irq/122-QManpo19488-2110:48:550
46050420irq/122-QManpo19488-2110:48:550
46050420irq/122-QManpo19488-2110:48:550
1127099424cyclictest0-21swapper/219:13:132
1127099424cyclictest0-21swapper/219:13:132
1127099423cyclictest0-21swapper/223:43:172
1127099423cyclictest0-21swapper/223:43:172
1127099423cyclictest0-21swapper/223:43:172
1127099423cyclictest0-21swapper/223:43:172
1127099423cyclictest0-21swapper/223:34:522
1127099423cyclictest0-21swapper/223:34:522
1127099423cyclictest0-21swapper/222:18:102
1127099423cyclictest0-21swapper/222:18:102
1127099423cyclictest0-21swapper/222:13:192
1127099423cyclictest0-21swapper/222:13:192
1127099423cyclictest0-21swapper/221:28:112
1127099423cyclictest0-21swapper/221:28:112
1127099423cyclictest0-21swapper/221:13:072
1127099423cyclictest0-21swapper/221:13:072
1127099423cyclictest0-21swapper/200:38:002
1127099423cyclictest0-21swapper/200:38:002
11270994216cyclictest0-21swapper/223:15:112
11270994216cyclictest0-21swapper/223:15:112
71410rcu_preempt4912-21sed22:58:041
71410rcu_preempt4912-21sed22:58:041
71410rcu_preempt0-21swapper/100:08:211
71410rcu_preempt0-21swapper/100:08:211
71410rcu_preempt0-21swapper/100:08:211
71410rcu_preempt0-21swapper/100:08:211
71410rcu_preempt0-21swapper/000:30:060
71410rcu_preempt0-21swapper/000:30:060
71410rcu_preempt0-21swapper/000:30:060
46050410irq/122-QManpo12927-2110:48:550
46050410irq/122-QManpo12927-2110:48:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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