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2026-03-03 - 17:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Mar 03, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71710rcu_preempt0-21swapper/211:43:092
71710rcu_preempt0-21swapper/211:43:092
71550rcu_preempt0-21swapper/211:36:432
71550rcu_preempt0-21swapper/211:36:432
71550rcu_preempt0-21swapper/211:36:432
2013299552cyclictest27324-21irqstats09:21:510
2013299552cyclictest27324-21irqstats09:21:510
2013299551cyclictest26076-21apt-get12:11:430
2013299551cyclictest26076-21apt-get12:11:430
2013299544cyclictest0-21swapper/009:16:560
2013299544cyclictest0-21swapper/009:16:560
2013299544cyclictest0-21swapper/009:16:560
2013299542cyclictest4588-21/usr/sbin/munin10:36:560
2013299542cyclictest4588-21/usr/sbin/munin10:36:560
2013299542cyclictest4588-21/usr/sbin/munin10:36:560
2013299542cyclictest19926-21/usr/sbin/munin10:06:530
2013299542cyclictest19926-21/usr/sbin/munin10:06:530
2013299533cyclictest0-21swapper/008:16:470
2013299533cyclictest0-21swapper/008:16:470
2013299532cyclictest7743-21diskstats10:41:480
2013299532cyclictest7743-21diskstats10:41:480
2013299532cyclictest28981-21meminfo10:21:550
2013299532cyclictest28981-21meminfo10:21:550
2013299532cyclictest13117-21irqstats08:41:500
2013299532cyclictest13117-21irqstats08:41:500
2013299531cyclictest10195-21/usr/sbin/munin10:46:480
2013299531cyclictest10195-21/usr/sbin/munin10:46:480
2013299524cyclictest0-21swapper/010:03:530
2013299524cyclictest0-21swapper/010:03:530
2013299524cyclictest0-21swapper/008:46:580
2013299524cyclictest0-21swapper/008:46:580
2013299524cyclictest0-21swapper/007:41:330
2013299524cyclictest0-21swapper/007:41:330
2013299524cyclictest0-21swapper/007:41:330
2013299523cyclictest0-21swapper/011:21:510
2013299523cyclictest0-21swapper/011:21:510
2013299523cyclictest0-21swapper/009:51:580
2013299523cyclictest0-21swapper/009:51:580
2013299523cyclictest0-21swapper/009:26:530
2013299523cyclictest0-21swapper/009:26:530
2013299522cyclictest5584-21ntp_states12:31:560
2013299522cyclictest5584-21ntp_states12:31:560
2013299522cyclictest5584-21ntp_states12:31:560
2013299521cyclictest24020-21ssh11:11:030
2013299521cyclictest24020-21ssh11:11:030
2013299514cyclictest0-21swapper/011:12:380
2013299514cyclictest0-21swapper/011:12:380
2013299514cyclictest0-21swapper/007:26:320
2013299514cyclictest0-21swapper/007:26:320
2013299513cyclictest21088-21ntp_states12:01:570
2013299513cyclictest21088-21ntp_states12:01:570
2013299513cyclictest1897-21df10:31:450
2013299513cyclictest1897-21df10:31:450
2013299513cyclictest1897-21df10:31:450
2013299513cyclictest0-21swapper/012:37:000
2013299513cyclictest0-21swapper/012:37:000
2013299513cyclictest0-21swapper/011:49:100
2013299513cyclictest0-21swapper/011:49:100
2013299513cyclictest0-21swapper/011:49:100
2013299513cyclictest0-21swapper/008:26:510
2013299513cyclictest0-21swapper/008:26:510
2013299513cyclictest0-21swapper/007:51:580
2013299513cyclictest0-21swapper/007:51:580
2013299513cyclictest0-21swapper/007:51:580
2013299513cyclictest0-21swapper/007:11:570
2013299513cyclictest0-21swapper/007:11:570
2013299513cyclictest0-21swapper/007:11:570
2013299512cyclictest3574-21ntp_kernel_pll_09:36:540
2013299512cyclictest3574-21ntp_kernel_pll_09:36:540
2013299512cyclictest3574-21ntp_kernel_pll_09:36:540
2013299512cyclictest30001-21munin-run11:21:330
2013299512cyclictest30001-21munin-run11:21:330
2013299512cyclictest29046-21ntp_states07:41:580
2013299512cyclictest29046-21ntp_states07:41:580
2013299512cyclictest1540-21munin-run08:01:320
2013299512cyclictest1540-21munin-run08:01:320
2013299512cyclictest1540-21munin-run08:01:320
2013299512cyclictest15338-21ntp_states11:51:570
2013299512cyclictest15338-21ntp_states11:51:570
2013299504cyclictest0-21swapper/012:00:110
2013299504cyclictest0-21swapper/012:00:110
2013299504cyclictest0-21swapper/011:36:400
2013299504cyclictest0-21swapper/010:16:540
2013299504cyclictest0-21swapper/010:16:540
2013299504cyclictest0-21swapper/010:16:540
2013299503cyclictest0-21swapper/011:29:360
2013299503cyclictest0-21swapper/011:29:360
2013299503cyclictest0-21swapper/010:56:520
2013299503cyclictest0-21swapper/010:56:520
2013299503cyclictest0-21swapper/010:56:520
2013299503cyclictest0-21swapper/010:14:360
2013299503cyclictest0-21swapper/010:14:360
2013299503cyclictest0-21swapper/010:01:260
2013299503cyclictest0-21swapper/010:01:260
2013299503cyclictest0-21swapper/010:01:260
2013299503cyclictest0-21swapper/009:01:520
2013299503cyclictest0-21swapper/009:01:520
2013299503cyclictest0-21swapper/008:36:540
2013299503cyclictest0-21swapper/008:36:540
2013299503cyclictest0-21swapper/008:36:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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