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2026-03-27 - 07:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Mar 27, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71640rcu_preempt0-21swapper/323:19:123
71640rcu_preempt0-21swapper/323:19:123
71620rcu_preempt0-21swapper/122:37:591
71620rcu_preempt0-21swapper/122:37:591
71620rcu_preempt0-21swapper/122:37:591
46050540irq/122-QManpo5564-2110:48:550
46050540irq/122-QManpo5564-2110:48:550
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
46050440irq/122-QManpo0-210
46050420irq/122-QManpo22464-2110:48:550
46050420irq/122-QManpo22464-2110:48:550
46050420irq/122-QManpo22464-2110:48:550
71410rcu_preempt22587-1kworker/3:2H23:47:323
71410rcu_preempt22587-1kworker/3:2H23:47:323
71410rcu_preempt22587-1kworker/3:2H23:47:323
71410rcu_preempt0-21swapper/023:03:090
71410rcu_preempt0-21swapper/023:03:090
71410rcu_preempt0-21swapper/023:03:090
71410rcu_preempt0-21swapper/022:32:120
71410rcu_preempt0-21swapper/022:32:120
71410rcu_preempt0-21swapper/000:05:270
71410rcu_preempt0-21swapper/000:05:270
46450410irq/118-QManpo6018-2110:48:552
46450410irq/118-QManpo6018-2110:48:552
71400rcu_preempt1773-21rs:main2
71400rcu_preempt1773-21rs:main2
71400rcu_preempt0-21swapper/223:24:232
71400rcu_preempt0-21swapper/223:24:232
71400rcu_preempt0-21swapper/022:03:080
71400rcu_preempt0-21swapper/022:03:080
46050400irq/122-QManpo1959-2110:48:550
46050400irq/122-QManpo1959-2110:48:550
46050400irq/122-QManpo1959-2110:48:550
71390rcu_preempt20791-21taskset21:36:130
71390rcu_preempt20791-21taskset21:36:130
71390rcu_preempt0-21swapper/322:47:053
71390rcu_preempt0-21swapper/322:47:053
71390rcu_preempt0-21swapper/322:47:053
71390rcu_preempt0-21swapper/019:52:120
71390rcu_preempt0-21swapper/019:52:120
71390rcu_preempt0-21swapper/000:17:060
71390rcu_preempt0-21swapper/000:17:060
71390rcu_preempt0-21swapper/000:17:060
46050390irq/122-QManpo19917-2110:48:550
46050390irq/122-QManpo19917-2110:48:550
71380rcu_preempt8885-21latency_hist22:21:590
71380rcu_preempt8885-21latency_hist22:21:590
71380rcu_preempt8885-21latency_hist22:21:590
71380rcu_preempt6885-1kworker/1:1H00:22:291
71380rcu_preempt6885-1kworker/1:1H00:22:291
71380rcu_preempt6885-1kworker/1:1H00:22:291
71380rcu_preempt27386-21taskset20:27:181
71380rcu_preempt27386-21taskset20:27:181
71380rcu_preempt13018-21sh22:28:330
71380rcu_preempt13018-21sh22:28:330
71380rcu_preempt0-21swapper/323:46:023
71380rcu_preempt0-21swapper/323:46:023
71380rcu_preempt0-21swapper/321:22:023
71380rcu_preempt0-21swapper/321:22:023
71380rcu_preempt0-21swapper/321:22:023
71380rcu_preempt0-21swapper/123:56:391
71380rcu_preempt0-21swapper/123:56:391
71380rcu_preempt0-21swapper/123:56:391
71380rcu_preempt0-21swapper/123:37:091
71380rcu_preempt0-21swapper/123:37:091
71380rcu_preempt0-21swapper/123:37:091
71380rcu_preempt0-21swapper/123:37:091
71380rcu_preempt0-21swapper/100:05:331
71380rcu_preempt0-21swapper/100:05:331
71380rcu_preempt0-21swapper/023:24:430
71380rcu_preempt0-21swapper/023:24:430
71380rcu_preempt0-21swapper/022:42:330
71380rcu_preempt0-21swapper/022:42:330
71380rcu_preempt0-21swapper/022:42:330
71380rcu_preempt0-21swapper/021:44:200
71380rcu_preempt0-21swapper/021:44:200
71370rcu_preempt0-21swapper/323:53:383
71370rcu_preempt0-21swapper/323:53:383
71370rcu_preempt0-21swapper/323:53:383
71370rcu_preempt0-21swapper/222:28:462
71370rcu_preempt0-21swapper/222:28:462
71370rcu_preempt0-21swapper/123:44:461
71370rcu_preempt0-21swapper/123:44:461
71370rcu_preempt0-21swapper/122:46:311
71370rcu_preempt0-21swapper/122:46:311
71370rcu_preempt0-21swapper/122:46:311
71370rcu_preempt0-21swapper/121:55:151
71370rcu_preempt0-21swapper/121:55:151
71370rcu_preempt0-21swapper/121:42:341
71370rcu_preempt0-21swapper/121:42:341
71370rcu_preempt0-21swapper/121:41:311
71370rcu_preempt0-21swapper/121:41:311
71370rcu_preempt0-21swapper/022:37:500
71370rcu_preempt0-21swapper/022:37:500
71370rcu_preempt0-21swapper/022:37:500
71370rcu_preempt0-21swapper/021:47:250
71370rcu_preempt0-21swapper/021:47:250
71370rcu_preempt0-21swapper/021:47:250
71370rcu_preempt0-21swapper/021:27:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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