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2026-08-20 - 22:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Aug 20, 2026 12:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71570rcu_preempt0-21swapper/207:54:422
71570rcu_preempt0-21swapper/207:54:422
71480rcu_preempt0-21swapper/012:40:170
71480rcu_preempt0-21swapper/012:40:170
71430rcu_preempt0-21swapper/007:34:270
71430rcu_preempt0-21swapper/007:34:270
71420rcu_preempt0-21swapper/309:27:343
71420rcu_preempt0-21swapper/309:27:343
71400rcu_preempt23928-21copy08:54:370
71400rcu_preempt23928-21copy08:54:370
71400rcu_preempt0-21swapper/312:42:543
71400rcu_preempt0-21swapper/312:42:543
71400rcu_preempt0-21swapper/311:05:043
71400rcu_preempt0-21swapper/311:05:043
71400rcu_preempt0-21swapper/311:05:043
71400rcu_preempt0-21swapper/311:04:373
71400rcu_preempt0-21swapper/311:04:373
71400rcu_preempt0-21swapper/311:04:373
71400rcu_preempt0-21swapper/308:14:343
71390rcu_preempt8767-1kworker/3:1H07:59:543
71390rcu_preempt8767-1kworker/3:1H07:59:543
71390rcu_preempt30841-21runrttasks09:15:380
71390rcu_preempt30841-21runrttasks09:15:380
71390rcu_preempt28394-21ssh10:09:483
71390rcu_preempt28394-21ssh10:09:483
71390rcu_preempt0-21swapper/309:23:063
71390rcu_preempt0-21swapper/309:23:063
71390rcu_preempt0-21swapper/309:23:063
46250390irq/120-QManpo28810-2110:48:551
46250390irq/120-QManpo28810-2110:48:551
71380rcu_preempt23928-21copy08:54:430
71380rcu_preempt23928-21copy08:54:430
71380rcu_preempt0-21swapper/312:20:153
71380rcu_preempt0-21swapper/312:20:153
71380rcu_preempt0-21swapper/312:20:153
71380rcu_preempt0-21swapper/311:17:463
71380rcu_preempt0-21swapper/311:17:463
71380rcu_preempt0-21swapper/311:14:303
71380rcu_preempt0-21swapper/311:14:303
71380rcu_preempt0-21swapper/309:58:263
71380rcu_preempt0-21swapper/309:58:263
71380rcu_preempt0-21swapper/309:58:263
71380rcu_preempt0-21swapper/111:03:281
71380rcu_preempt0-21swapper/111:03:281
71380rcu_preempt0-21swapper/111:03:281
71380rcu_preempt0-21swapper/011:07:010
71380rcu_preempt0-21swapper/011:07:010
71380rcu_preempt0-21swapper/011:07:010
46650380irq/116-QManpo22419-2110:48:553
46650380irq/116-QManpo22419-2110:48:553
46450380irq/118-QManpo28645-2110:48:552
46450380irq/118-QManpo28645-2110:48:552
46050380irq/122-QManpo28808-210
46050380irq/122-QManpo28808-210
46050380irq/122-QManpo15385-2110:48:550
46050380irq/122-QManpo15385-2110:48:550
46050380irq/122-QManpo15385-2110:48:550
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
83082370sleep06943-1kworker/0:2H09:34:250
83082370sleep06943-1kworker/0:2H09:34:250
71370rcu_preempt5858-21latency_hist07:49:323
71370rcu_preempt5858-21latency_hist07:49:323
71370rcu_preempt3628-21grep11:20:003
71370rcu_preempt3628-21grep11:20:003
71370rcu_preempt29134-1awk07:14:533
71370rcu_preempt29134-1awk07:14:533
71370rcu_preempt26436-21ssh10:05:140
71370rcu_preempt26436-21ssh10:05:140
71370rcu_preempt0-21swapper/312:11:503
71370rcu_preempt0-21swapper/312:11:503
71370rcu_preempt0-21swapper/311:25:093
71370rcu_preempt0-21swapper/311:25:093
71370rcu_preempt0-21swapper/310:44:343
71370rcu_preempt0-21swapper/310:44:343
71370rcu_preempt0-21swapper/310:44:343
71370rcu_preempt0-21swapper/310:29:353
71370rcu_preempt0-21swapper/310:29:353
71370rcu_preempt0-21swapper/310:08:083
71370rcu_preempt0-21swapper/310:08:083
71370rcu_preempt0-21swapper/308:59:423
71370rcu_preempt0-21swapper/308:59:423
71370rcu_preempt0-21swapper/210:05:342
71370rcu_preempt0-21swapper/210:05:342
71370rcu_preempt0-21swapper/209:56:022
71370rcu_preempt0-21swapper/209:56:022
71370rcu_preempt0-21swapper/209:56:022
71370rcu_preempt0-21swapper/109:47:581
71370rcu_preempt0-21swapper/109:47:581
71370rcu_preempt0-21swapper/109:47:581
71370rcu_preempt0-21swapper/012:34:430
71370rcu_preempt0-21swapper/012:34:430
71370rcu_preempt0-21swapper/011:40:330
71370rcu_preempt0-21swapper/011:40:330
46050370irq/122-QManpo27338-2110:48:550
46050370irq/122-QManpo27338-2110:48:550
46050370irq/122-QManpo23945-10
46050370irq/122-QManpo23945-10
46050370irq/122-QManpo14084-2110:48:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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