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2026-06-05 - 16:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Jun 05, 2026 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154152780chrt46450irq/118-QMan10:48:552
154152780chrt46450irq/118-QMan10:48:552
71490rcu_preempt29903-21apt-get11:13:260
71490rcu_preempt29903-21apt-get11:13:260
71470rcu_preempt0-21swapper/007:28:440
71470rcu_preempt0-21swapper/007:28:440
71470rcu_preempt0-21swapper/007:28:440
3111899479cyclictest88502chrt11:33:412
3111899479cyclictest88502chrt11:33:412
3111899479cyclictest88502chrt11:33:412
3111899472cyclictest7542-21/usr/sbin/munin09:28:472
3111899472cyclictest7542-21/usr/sbin/munin09:28:472
3111899471cyclictest24114-21sendmail-msp12:06:282
3111899471cyclictest24114-21sendmail-msp12:06:282
3111899471cyclictest24114-21sendmail-msp12:06:282
71460rcu_preempt0-21swapper/009:05:160
71460rcu_preempt0-21swapper/009:05:160
46050460irq/122-QManpo0-210
46050460irq/122-QManpo0-210
71450rcu_preempt0-21swapper/111:49:241
71450rcu_preempt0-21swapper/111:49:241
71450rcu_preempt0-21swapper/111:49:241
3111899454cyclictest0-21swapper/210:02:202
3111899454cyclictest0-21swapper/210:02:202
3111899453cyclictest0-21swapper/209:38:272
3111899453cyclictest0-21swapper/209:38:272
3111899452cyclictest3427-21ntp_states07:28:392
3111899452cyclictest3427-21ntp_states07:28:392
3111899452cyclictest3427-21ntp_states07:28:392
71440rcu_preempt0-21swapper/012:33:560
71440rcu_preempt0-21swapper/012:33:560
3111899446cyclictest14542-21cat10:43:202
3111899444cyclictest0-21swapper/208:23:142
3111899444cyclictest0-21swapper/208:23:142
71430rcu_preempt29363-21sh11:12:050
71430rcu_preempt29363-21sh11:12:050
71430rcu_preempt29363-21sh11:12:050
71430rcu_preempt0-21swapper/210:15:382
71430rcu_preempt0-21swapper/210:15:382
71430rcu_preempt0-21swapper/210:15:382
71430rcu_preempt0-21swapper/009:33:280
71430rcu_preempt0-21swapper/009:33:280
46050430irq/122-QManpo25014-2110:48:550
46050430irq/122-QManpo25014-2110:48:550
46050430irq/122-QManpo25014-2110:48:550
3111899434cyclictest0-21swapper/208:13:182
3111899434cyclictest0-21swapper/208:13:182
3111899433cyclictest24279-21ntp_states08:43:392
3111899433cyclictest24279-21ntp_states08:43:392
3111899433cyclictest24279-21ntp_states08:43:392
3111899433cyclictest0-21swapper/210:26:372
3111899433cyclictest0-21swapper/210:26:372
3111899432cyclictest25970-21/usr/sbin/munin10:03:282
3111899432cyclictest25970-21/usr/sbin/munin10:03:282
3111899432cyclictest25970-21/usr/sbin/munin10:03:282
3111899432cyclictest18922-1kworker/2:2H09:49:392
3111899432cyclictest18922-1kworker/2:2H09:49:392
3111899432cyclictest18922-1kworker/2:2H09:49:392
3111899432cyclictest18502-21latency11:53:382
3111899432cyclictest18502-21latency11:53:382
3111899432cyclictest18502-21latency11:53:382
3111899431cyclictest7514-21/usr/sbin/munin07:43:372
3111899431cyclictest7514-21/usr/sbin/munin07:43:372
3111899431cyclictest7514-21/usr/sbin/munin07:43:372
31118994318cyclictest8702-21df_inode07:48:312
31118994318cyclictest8702-21df_inode07:48:312
71420rcu_preempt0-21swapper/207:11:102
71420rcu_preempt0-21swapper/207:11:102
46050420irq/122-QManpo1359-2110:48:550
46050420irq/122-QManpo1359-2110:48:550
3111899427cyclictest3055-21ssh12:28:142
3111899427cyclictest3055-21ssh12:28:142
3111899427cyclictest3055-21ssh12:28:142
3111899424cyclictest0-21swapper/211:23:582
3111899424cyclictest0-21swapper/211:23:582
3111899424cyclictest0-21swapper/211:23:582
3111899424cyclictest0-21swapper/211:18:272
3111899424cyclictest0-21swapper/211:18:272
3111899424cyclictest0-21swapper/209:26:192
3111899424cyclictest0-21swapper/209:26:192
3111899424cyclictest0-21swapper/209:26:192
3111899423cyclictest0-21swapper/211:58:342
3111899423cyclictest0-21swapper/211:58:342
3111899423cyclictest0-21swapper/211:58:342
3111899423cyclictest0-21swapper/207:27:492
3111899423cyclictest0-21swapper/207:27:492
3111899422cyclictest6368-21/usr/sbin/munin10:28:402
3111899422cyclictest6368-21/usr/sbin/munin10:28:402
3111899422cyclictest29738-21meminfo09:03:322
3111899422cyclictest29738-21meminfo09:03:322
3111899422cyclictest16052-21irqstats11:48:372
3111899422cyclictest16052-21irqstats11:48:372
3111899422cyclictest16052-21irqstats11:48:372
3111899422cyclictest13747-21meminfo11:43:382
3111899422cyclictest13747-21meminfo11:43:382
3111899422cyclictest13747-21meminfo11:43:382
3111899422cyclictest13747-21meminfo11:43:382
3111899422cyclictest12800-21df08:03:272
3111899422cyclictest12800-21df08:03:272
3111899421cyclictest31363-21diskstats07:13:302
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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