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2026-07-20 - 00:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Jul 19, 2026 12:44:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71610rcu_preempt0-21swapper/309:55:513
71610rcu_preempt0-21swapper/309:55:513
71610rcu_preempt0-21swapper/309:55:513
2871799589cyclictest24732-21basename08:49:130
2871799589cyclictest24732-21basename08:49:130
2871799553cyclictest0-21swapper/010:39:250
2871799553cyclictest0-21swapper/010:39:250
2871799553cyclictest0-21swapper/010:39:250
2871799523cyclictest2377-21apt-get07:29:090
2871799523cyclictest2377-21apt-get07:29:090
2871799523cyclictest2377-21apt-get07:29:090
2871799523cyclictest0-21swapper/011:19:260
2871799523cyclictest0-21swapper/011:19:260
2871799523cyclictest0-21swapper/011:19:260
2871799523cyclictest0-21swapper/011:19:260
46050510irq/122-QManpo20219-2110:48:550
46050510irq/122-QManpo20219-2110:48:550
2871799514cyclictest0-21swapper/009:34:290
2871799514cyclictest0-21swapper/009:34:290
2871799514cyclictest0-21swapper/009:34:290
2871799513cyclictest0-21swapper/011:46:230
2871799513cyclictest0-21swapper/011:46:230
2871799513cyclictest0-21swapper/010:10:590
2871799513cyclictest0-21swapper/010:10:590
2871799513cyclictest0-21swapper/009:52:520
2871799513cyclictest0-21swapper/009:52:520
28717995117cyclictest5114-21df09:24:130
28717995117cyclictest5114-21df09:24:130
28717995117cyclictest5114-21df09:24:130
2871799504cyclictest0-21swapper/011:33:290
2871799504cyclictest0-21swapper/011:33:290
2871799504cyclictest0-21swapper/010:29:130
2871799504cyclictest0-21swapper/010:29:130
2871799504cyclictest0-21swapper/010:29:130
2871799503cyclictest0-21swapper/012:13:060
2871799503cyclictest0-21swapper/012:13:060
2871799503cyclictest0-21swapper/012:13:060
2871799503cyclictest0-21swapper/011:58:380
2871799503cyclictest0-21swapper/011:58:380
2871799503cyclictest0-21swapper/011:58:380
2871799502cyclictest2001-21meminfo12:29:220
2871799502cyclictest2001-21meminfo12:29:220
2871799502cyclictest2001-21meminfo12:29:220
2871799502cyclictest14367-21users08:09:300
2871799502cyclictest14367-21users08:09:300
2871799502cyclictest14367-21users08:09:300
2871799502cyclictest1048-21aten_r4power_vo07:24:140
2871799502cyclictest1048-21aten_r4power_vo07:24:140
2871799502cyclictest1048-21aten_r4power_vo07:24:140
28717995018cyclictest15165-21ssh11:51:250
28717995018cyclictest15165-21ssh11:51:250
28717995013cyclictest6029-21taskset07:39:370
28717995013cyclictest6029-21taskset07:39:370
2871799493cyclictest0-21swapper/012:38:530
2871799493cyclictest0-21swapper/012:38:530
2871799493cyclictest0-21swapper/012:38:530
2871799493cyclictest0-21swapper/012:14:170
2871799493cyclictest0-21swapper/012:14:170
2871799493cyclictest0-21swapper/012:14:170
2871799493cyclictest0-21swapper/011:17:260
2871799493cyclictest0-21swapper/011:17:260
2871799493cyclictest0-21swapper/011:17:260
2871799493cyclictest0-21swapper/011:17:260
2871799493cyclictest0-21swapper/011:04:520
2871799493cyclictest0-21swapper/011:04:520
2871799493cyclictest0-21swapper/011:04:520
2871799492cyclictest15392-21ntp_states08:14:240
2871799492cyclictest15392-21ntp_states08:14:240
2871799492cyclictest15392-21ntp_states08:14:240
2871799491cyclictest30405-21ssh12:21:240
2871799491cyclictest30405-21ssh12:21:240
2871799491cyclictest30405-21ssh12:21:240
2871799491cyclictest0-21swapper/010:19:220
2871799491cyclictest0-21swapper/010:19:220
28717994919cyclictest12153-1kworker/0:1H11:59:260
28717994919cyclictest12153-1kworker/0:1H11:59:260
28717994916cyclictest0-21swapper/010:24:510
28717994916cyclictest0-21swapper/010:24:510
28717994916cyclictest0-21swapper/010:24:510
28717994914cyclictest3540-21ssh09:20:480
28717994914cyclictest3540-21ssh09:20:480
28717994914cyclictest3540-21ssh09:20:480
71480rcu_preempt0-21swapper/311:00:413
71480rcu_preempt0-21swapper/311:00:413
71480rcu_preempt0-21swapper/311:00:413
2871799483cyclictest0-21swapper/012:28:270
2871799483cyclictest0-21swapper/012:28:270
2871799483cyclictest0-21swapper/012:28:270
2871799483cyclictest0-21swapper/010:52:150
2871799483cyclictest0-21swapper/010:52:150
2871799483cyclictest0-21swapper/010:35:330
2871799483cyclictest0-21swapper/010:35:330
2871799483cyclictest0-21swapper/009:56:170
2871799483cyclictest0-21swapper/009:56:170
2871799483cyclictest0-21swapper/009:56:170
2871799482cyclictest23758-21ntp_states08:44:260
2871799482cyclictest23758-21ntp_states08:44:260
2871799482cyclictest19303-21diskstats08:29:160
2871799482cyclictest19303-21diskstats08:29:160
2871799481cyclictest0-21swapper/009:29:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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