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2026-08-15 - 12:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Aug 15, 2026 00:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71690rcu_preempt0-21swapper/121:56:381
71690rcu_preempt0-21swapper/121:56:381
71600rcu_preempt0-21swapper/322:48:213
71600rcu_preempt0-21swapper/322:48:213
71590rcu_preempt0-21swapper/123:30:351
71590rcu_preempt0-21swapper/123:30:351
71580rcu_preempt0-21swapper/322:44:053
71580rcu_preempt0-21swapper/322:44:053
71580rcu_preempt0-21swapper/322:44:053
71560rcu_preempt0-21swapper/019:49:350
71560rcu_preempt0-21swapper/019:49:350
71530rcu_preempt10495-21ssh00:39:381
71530rcu_preempt10495-21ssh00:39:381
71530rcu_preempt10495-21ssh00:39:381
71450rcu_preempt0-21swapper/019:24:360
71450rcu_preempt0-21swapper/019:24:360
71430rcu_preempt0-21swapper/021:42:500
71430rcu_preempt0-21swapper/021:42:500
71430rcu_preempt0-21swapper/021:42:500
71420rcu_preempt0-21swapper/122:14:201
71420rcu_preempt0-21swapper/122:14:201
71410rcu_preempt22238-21diskmemload21:44:451
71410rcu_preempt22238-21diskmemload21:44:451
71400rcu_preempt10380-1kworker/0:2H00:39:480
71400rcu_preempt10380-1kworker/0:2H00:39:480
71400rcu_preempt10380-1kworker/0:2H00:39:480
71400rcu_preempt0-21swapper/300:24:393
71400rcu_preempt0-21swapper/300:24:393
71400rcu_preempt0-21swapper/022:37:580
71400rcu_preempt0-21swapper/022:37:580
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
71390rcu_preempt650-21/usr/sbin/munin22:29:551
71390rcu_preempt650-21/usr/sbin/munin22:29:551
71390rcu_preempt23955-21kworker/1:100:08:371
71390rcu_preempt23955-21kworker/1:100:08:371
71390rcu_preempt23955-21kworker/1:100:08:371
71390rcu_preempt1047-21grep22:29:483
71390rcu_preempt1047-21grep22:29:483
71390rcu_preempt10060-21sort21:49:300
71390rcu_preempt10060-21sort21:49:300
71390rcu_preempt0-21swapper/122:44:501
71390rcu_preempt0-21swapper/122:44:501
71390rcu_preempt0-21swapper/021:18:290
71390rcu_preempt0-21swapper/021:18:290
71390rcu_preempt0-21swapper/019:33:180
71390rcu_preempt0-21swapper/019:33:180
71380rcu_preempt21750-21cyclictest22:09:420
71380rcu_preempt21750-21cyclictest22:09:420
71380rcu_preempt0-21swapper/323:29:493
71380rcu_preempt0-21swapper/323:29:493
71380rcu_preempt0-21swapper/121:20:121
71380rcu_preempt0-21swapper/121:20:121
71380rcu_preempt0-21swapper/100:29:481
71380rcu_preempt0-21swapper/100:29:481
71380rcu_preempt0-21swapper/100:29:301
71380rcu_preempt0-21swapper/100:29:301
71380rcu_preempt0-21swapper/100:11:001
71380rcu_preempt0-21swapper/100:11:001
71380rcu_preempt0-21swapper/022:53:410
71380rcu_preempt0-21swapper/022:53:410
71380rcu_preempt0-21swapper/022:32:470
71380rcu_preempt0-21swapper/022:32:470
71370rcu_preempt29779-21ssh00:15:430
71370rcu_preempt29779-21ssh00:15:430
71370rcu_preempt0-21swapper/320:44:523
71370rcu_preempt0-21swapper/320:44:523
71370rcu_preempt0-21swapper/123:39:391
71370rcu_preempt0-21swapper/123:39:391
71370rcu_preempt0-21swapper/120:56:121
71370rcu_preempt0-21swapper/120:56:121
71370rcu_preempt0-21swapper/023:49:160
71370rcu_preempt0-21swapper/023:49:160
71370rcu_preempt0-21swapper/023:19:570
71370rcu_preempt0-21swapper/023:19:570
71370rcu_preempt0-21swapper/022:08:000
71370rcu_preempt0-21swapper/022:08:000
71370rcu_preempt0-21swapper/000:02:350
71370rcu_preempt0-21swapper/000:02:350
71370rcu_preempt0-21swapper/000:02:350
71360rcu_preempt8355-21crond20:24:261
71360rcu_preempt8355-21crond20:24:261
71360rcu_preempt5590-21crond20:14:261
71360rcu_preempt5590-21crond20:14:261
71360rcu_preempt31278-21sh00:19:301
71360rcu_preempt31278-21sh00:19:301
71360rcu_preempt2414-21tail21:34:520
71360rcu_preempt2414-21tail21:34:520
71360rcu_preempt21750-21cyclictest00:34:530
71360rcu_preempt21750-21cyclictest00:34:530
71360rcu_preempt0-21swapper/321:59:543
71360rcu_preempt0-21swapper/321:59:543
71360rcu_preempt0-21swapper/319:24:463
71360rcu_preempt0-21swapper/319:24:463
71360rcu_preempt0-21swapper/123:59:531
71360rcu_preempt0-21swapper/123:59:531
71360rcu_preempt0-21swapper/123:59:531
71360rcu_preempt0-21swapper/122:49:331
71360rcu_preempt0-21swapper/122:49:331
71360rcu_preempt0-21swapper/122:27:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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