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2026-02-05 - 21:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Feb 05, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71670rcu_preempt0-21swapper/209:17:172
71670rcu_preempt0-21swapper/209:17:172
71610rcu_preempt5542-21copy07:11:143
71610rcu_preempt5542-21copy07:11:143
71610rcu_preempt5542-21copy07:11:143
556499523cyclictest0-21swapper/009:16:320
556499523cyclictest0-21swapper/009:16:320
556499514cyclictest0-21swapper/010:11:160
556499514cyclictest0-21swapper/010:11:160
556499513cyclictest0-21swapper/010:25:210
556499513cyclictest0-21swapper/010:25:210
556499513cyclictest0-21swapper/010:25:210
5564995119cyclictest0-21swapper/011:06:420
5564995119cyclictest0-21swapper/011:06:420
5564995119cyclictest0-21swapper/011:06:420
5564995118cyclictest0-21swapper/009:11:520
5564995118cyclictest0-21swapper/009:11:520
46050510irq/122-QManpo4260-210
46050510irq/122-QManpo4260-210
556499503cyclictest0-21swapper/010:42:330
556499503cyclictest0-21swapper/010:42:330
556499503cyclictest0-21swapper/010:42:330
556499493cyclictest0-21swapper/011:56:290
556499493cyclictest0-21swapper/011:56:290
556499493cyclictest0-21swapper/011:54:050
556499493cyclictest0-21swapper/011:54:050
556499493cyclictest0-21swapper/011:54:050
556499493cyclictest0-21swapper/010:51:030
556499493cyclictest0-21swapper/010:51:030
556499493cyclictest0-21swapper/010:35:300
556499493cyclictest0-21swapper/010:35:300
556499493cyclictest0-21swapper/009:53:590
556499493cyclictest0-21swapper/009:53:590
556499493cyclictest0-21swapper/009:21:130
556499493cyclictest0-21swapper/009:21:130
556499493cyclictest0-21swapper/009:21:130
556499493cyclictest0-21swapper/008:51:040
556499493cyclictest0-21swapper/008:51:040
556499493cyclictest0-21swapper/007:33:130
556499493cyclictest0-21swapper/007:33:130
556499483cyclictest0-21swapper/010:26:260
556499483cyclictest0-21swapper/010:26:260
556499483cyclictest0-21swapper/010:26:260
556499483cyclictest0-21swapper/007:46:270
556499483cyclictest0-21swapper/007:46:270
71450rcu_preempt2832-21/usr/sbin/munin08:56:261
71450rcu_preempt2832-21/usr/sbin/munin08:56:261
71450rcu_preempt2832-21/usr/sbin/munin08:56:261
556499453cyclictest0-21swapper/011:13:320
556499453cyclictest0-21swapper/011:13:320
556499453cyclictest0-21swapper/011:13:320
71430rcu_preempt0-21swapper/111:37:211
71430rcu_preempt0-21swapper/111:37:211
71430rcu_preempt0-21swapper/111:37:211
71430rcu_preempt0-21swapper/111:37:211
556799434cyclictest0-21swapper/310:11:263
556799434cyclictest0-21swapper/310:11:263
71420rcu_preempt5738-21ssh10:06:132
71420rcu_preempt5738-21ssh10:06:132
71420rcu_preempt5504-21ls07:11:031
71420rcu_preempt5504-21ls07:11:031
71420rcu_preempt0-21swapper/108:37:111
71420rcu_preempt0-21swapper/108:37:111
71420rcu_preempt0-21swapper/108:37:111
71420rcu_preempt0-21swapper/010:06:150
71420rcu_preempt0-21swapper/010:06:150
71410rcu_preempt4100-1kworker/3:2H10:06:063
71410rcu_preempt4100-1kworker/3:2H10:06:063
71410rcu_preempt0-21swapper/208:56:072
71410rcu_preempt0-21swapper/208:56:072
71410rcu_preempt0-21swapper/207:11:142
71410rcu_preempt0-21swapper/207:11:142
71410rcu_preempt0-21swapper/207:11:142
71400rcu_preempt4291-21kworker/1:210:06:191
71400rcu_preempt4291-21kworker/1:210:06:191
71400rcu_preempt3098-21runrttasks11:54:271
71400rcu_preempt3098-21runrttasks11:54:271
71400rcu_preempt3098-21runrttasks11:54:271
71400rcu_preempt0-21swapper/011:17:390
71400rcu_preempt0-21swapper/011:17:390
71400rcu_preempt0-21swapper/011:17:390
71400rcu_preempt0-21swapper/010:17:370
71400rcu_preempt0-21swapper/010:17:370
71390rcu_preempt0-21swapper/209:55:202
71390rcu_preempt0-21swapper/209:55:202
71390rcu_preempt0-21swapper/107:31:131
71390rcu_preempt0-21swapper/107:31:131
71390rcu_preempt0-21swapper/012:26:120
71390rcu_preempt0-21swapper/012:26:120
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
71380rcu_preempt0-21swapper/211:49:192
71380rcu_preempt0-21swapper/211:49:192
71380rcu_preempt0-21swapper/211:49:192
71380rcu_preempt0-21swapper/208:16:272
71380rcu_preempt0-21swapper/208:16:272
71380rcu_preempt0-21swapper/112:15:371
71380rcu_preempt0-21swapper/112:15:371
71380rcu_preempt0-21swapper/111:41:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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