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2026-03-31 - 01:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Mar 30, 2026 12:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71550rcu_preempt0-21swapper/308:32:243
71550rcu_preempt0-21swapper/308:32:243
71550rcu_preempt0-21swapper/211:25:292
71550rcu_preempt0-21swapper/211:25:292
71550rcu_preempt0-21swapper/211:25:292
71550rcu_preempt0-21swapper/209:58:012
71550rcu_preempt0-21swapper/209:58:012
71550rcu_preempt0-21swapper/209:58:012
71550rcu_preempt0-21swapper/011:32:030
71550rcu_preempt0-21swapper/011:32:030
71530rcu_preempt0-21swapper/012:24:140
71530rcu_preempt0-21swapper/012:24:140
71530rcu_preempt0-21swapper/011:18:000
71530rcu_preempt0-21swapper/011:18:000
71530rcu_preempt0-21swapper/011:18:000
71520rcu_preempt0-21swapper/312:05:283
71520rcu_preempt0-21swapper/312:05:283
71520rcu_preempt0-21swapper/212:12:052
71520rcu_preempt0-21swapper/212:12:052
71520rcu_preempt0-21swapper/212:02:362
71520rcu_preempt0-21swapper/212:02:362
71510rcu_preempt0-21swapper/011:35:010
71510rcu_preempt0-21swapper/011:35:010
71500rcu_preempt0-21swapper/211:46:332
71500rcu_preempt0-21swapper/211:46:332
71500rcu_preempt0-21swapper/211:46:332
71490rcu_preempt0-21swapper/011:46:480
71490rcu_preempt0-21swapper/011:46:480
71490rcu_preempt0-21swapper/011:46:480
100650490irq/38-i2c-mpc0-21swapper/010:11:480
100650490irq/38-i2c-mpc0-21swapper/010:11:480
71470rcu_preempt0-21swapper/211:39:152
71470rcu_preempt0-21swapper/211:39:152
71470rcu_preempt0-21swapper/211:39:152
71470rcu_preempt0-21swapper/208:27:122
71470rcu_preempt0-21swapper/208:27:122
71460rcu_preempt0-21swapper/210:46:162
71460rcu_preempt0-21swapper/210:46:162
71460rcu_preempt0-21swapper/210:46:162
71450rcu_preempt0-21swapper/208:07:272
71450rcu_preempt0-21swapper/208:07:272
71450rcu_preempt0-21swapper/208:07:272
71440rcu_preempt0-21swapper/311:32:123
71440rcu_preempt0-21swapper/311:32:123
71430rcu_preempt0-21swapper/207:37:132
71430rcu_preempt0-21swapper/207:37:132
71430rcu_preempt0-21swapper/207:37:132
46050420irq/122-QManpo29311-2110:48:550
46050420irq/122-QManpo29311-2110:48:550
46050420irq/122-QManpo29311-2110:48:550
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
71410rcu_preempt0-21swapper/012:12:140
71410rcu_preempt0-21swapper/012:12:140
71410rcu_preempt0-21swapper/009:52:140
71410rcu_preempt0-21swapper/009:52:140
71410rcu_preempt0-21swapper/009:52:140
46050410irq/122-QManpo342-2110:48:550
46050410irq/122-QManpo342-2110:48:550
71400rcu_preempt26643-21copy08:47:060
71400rcu_preempt26643-21copy08:47:060
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
71390rcu_preempt0-21swapper/207:25:572
71390rcu_preempt0-21swapper/207:25:572
71390rcu_preempt0-21swapper/011:04:330
71390rcu_preempt0-21swapper/011:04:330
46250390irq/120-QManpo0-2110:48:551
46250390irq/120-QManpo0-2110:48:551
46050390irq/122-QManpo19608-2110:48:550
46050390irq/122-QManpo19608-2110:48:550
46050390irq/122-QManpo19608-2110:48:550
71380rcu_preempt0-21swapper/212:41:342
71380rcu_preempt0-21swapper/212:41:342
71380rcu_preempt0-21swapper/212:41:342
71380rcu_preempt0-21swapper/212:27:532
71380rcu_preempt0-21swapper/212:27:532
71380rcu_preempt0-21swapper/212:24:312
71380rcu_preempt0-21swapper/212:24:312
71380rcu_preempt0-21swapper/210:22:142
71380rcu_preempt0-21swapper/210:22:142
71380rcu_preempt0-21swapper/209:26:102
71380rcu_preempt0-21swapper/209:26:102
71380rcu_preempt0-21swapper/209:26:102
71380rcu_preempt0-21swapper/109:14:451
71380rcu_preempt0-21swapper/109:14:451
71380rcu_preempt0-21swapper/008:27:110
71380rcu_preempt0-21swapper/008:27:110
46050380irq/122-QManpo18196-2110:48:550
46050380irq/122-QManpo18196-2110:48:550
46050380irq/122-QManpo18196-2110:48:550
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
71370rcu_preempt7274-21/usr/sbin/munin07:37:240
71370rcu_preempt7274-21/usr/sbin/munin07:37:240
71370rcu_preempt7274-21/usr/sbin/munin07:37:240
71370rcu_preempt0-21swapper/209:42:042
71370rcu_preempt0-21swapper/209:42:042
71370rcu_preempt0-21swapper/209:42:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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