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2026-06-19 - 19:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Fri Jun 19, 2026 12:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71620rcu_preempt0-21swapper/211:51:352
71620rcu_preempt0-21swapper/211:51:352
46050450irq/122-QManpo0-210
46050450irq/122-QManpo0-210
46050450irq/122-QManpo0-210
46050440irq/122-QManpo7663-2110:48:550
46050440irq/122-QManpo7663-2110:48:550
779499433cyclictest0-21swapper/312:23:363
779499433cyclictest0-21swapper/310:40:583
779499433cyclictest0-21swapper/310:40:583
779499432cyclictest0-21swapper/309:43:313
779499432cyclictest0-21swapper/309:43:313
779499432cyclictest0-21swapper/309:43:313
71430rcu_preempt0-21swapper/109:20:191
71430rcu_preempt0-21swapper/109:20:191
71430rcu_preempt0-21swapper/109:20:191
779499424cyclictest0-21swapper/311:23:413
779499424cyclictest0-21swapper/311:23:413
779499424cyclictest0-21swapper/311:23:413
779499424cyclictest0-21swapper/311:21:523
779499424cyclictest0-21swapper/311:21:523
779499424cyclictest0-21swapper/310:23:293
779499424cyclictest0-21swapper/310:23:293
46050420irq/122-QManpo24887-210
46050420irq/122-QManpo24887-210
46050420irq/122-QManpo24887-210
779499413cyclictest0-21swapper/311:30:293
779499413cyclictest0-21swapper/311:30:293
779499413cyclictest0-21swapper/311:09:123
779499413cyclictest0-21swapper/311:09:123
779499413cyclictest0-21swapper/311:09:123
779499413cyclictest0-21swapper/310:31:303
779499413cyclictest0-21swapper/310:31:303
779499413cyclictest0-21swapper/310:31:303
779499413cyclictest0-21swapper/310:16:533
779499413cyclictest0-21swapper/310:16:533
779499413cyclictest0-21swapper/310:06:533
779499413cyclictest0-21swapper/310:06:533
779499413cyclictest0-21swapper/310:06:533
779499413cyclictest0-21swapper/309:53:593
779499413cyclictest0-21swapper/309:53:593
779499413cyclictest0-21swapper/309:52:053
779499413cyclictest0-21swapper/309:52:053
779499413cyclictest0-21swapper/309:52:053
779499413cyclictest0-21swapper/307:53:543
779499413cyclictest0-21swapper/307:53:543
779499412cyclictest1959-21runrttasks09:21:123
779499412cyclictest1959-21runrttasks09:21:123
779499412cyclictest1959-21runrttasks09:21:123
71410rcu_preempt0-21swapper/007:48:490
71410rcu_preempt0-21swapper/007:48:490
71410rcu_preempt0-21swapper/007:48:490
46450410irq/118-QManpo7264-2110:48:552
46450410irq/118-QManpo7264-2110:48:552
779499404cyclictest0-21swapper/310:00:433
779499404cyclictest0-21swapper/310:00:433
779499404cyclictest0-21swapper/310:00:433
779499404cyclictest0-21swapper/307:38:503
779499404cyclictest0-21swapper/307:38:503
779499403cyclictest0-21swapper/311:38:033
779499403cyclictest0-21swapper/311:38:033
779499403cyclictest0-21swapper/311:38:033
779499403cyclictest0-21swapper/311:15:273
779499403cyclictest0-21swapper/311:15:273
779499403cyclictest0-21swapper/311:15:273
779499403cyclictest0-21swapper/310:47:133
779499403cyclictest0-21swapper/310:47:133
779499403cyclictest0-21swapper/310:10:443
779499403cyclictest0-21swapper/310:10:443
779499403cyclictest0-21swapper/310:10:443
779499403cyclictest0-21swapper/309:47:183
779499403cyclictest0-21swapper/309:47:183
779499403cyclictest0-21swapper/309:47:183
779499403cyclictest0-21swapper/307:33:493
779499403cyclictest0-21swapper/307:33:493
779499403cyclictest0-21swapper/307:33:493
71400rcu_preempt0-21swapper/311:39:583
71400rcu_preempt0-21swapper/311:39:583
71400rcu_preempt0-21swapper/309:26:243
71400rcu_preempt0-21swapper/309:26:243
71400rcu_preempt0-21swapper/108:23:301
71400rcu_preempt0-21swapper/108:23:301
71400rcu_preempt0-21swapper/108:23:301
71400rcu_preempt0-21swapper/011:05:210
71400rcu_preempt0-21swapper/011:05:210
71400rcu_preempt0-21swapper/011:05:210
71400rcu_preempt0-21swapper/010:55:560
71400rcu_preempt0-21swapper/010:55:560
71400rcu_preempt0-21swapper/010:55:560
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
779499393cyclictest0-21swapper/312:14:003
779499393cyclictest0-21swapper/312:14:003
779499393cyclictest0-21swapper/312:14:003
779499393cyclictest0-21swapper/311:46:593
779499393cyclictest0-21swapper/311:46:593
779499393cyclictest0-21swapper/311:46:593
71390rcu_preempt32333-21ntp_states12:03:560
71390rcu_preempt32333-21ntp_states12:03:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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