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2026-05-13 - 20:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed May 13, 2026 12:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1281021000chrt46650irq/116-QMan10:48:553
1281021000chrt46650irq/116-QMan10:48:553
1281021000chrt46650irq/116-QMan10:48:553
198602620chrt46650irq/116-QMan10:48:553
198602620chrt46650irq/116-QMan10:48:553
198602620chrt46650irq/116-QMan10:48:553
32634995022cyclictest12818-21/usr/sbin/munin07:58:040
32634995022cyclictest12818-21/usr/sbin/munin07:58:040
32634995022cyclictest12818-21/usr/sbin/munin07:58:040
71490rcu_preempt16884-21apt-get08:13:080
71490rcu_preempt16884-21apt-get08:13:080
71460rcu_preempt0-21swapper/009:26:050
71460rcu_preempt0-21swapper/009:26:050
71460rcu_preempt0-21swapper/009:26:050
71450rcu_preempt0-21swapper/010:12:130
71450rcu_preempt0-21swapper/010:12:130
71450rcu_preempt0-21swapper/010:12:130
71440rcu_preempt0-21swapper/010:50:380
71440rcu_preempt0-21swapper/010:50:380
71440rcu_preempt0-21swapper/010:50:380
32634994422cyclictest15237-21/usr/sbin/munin09:38:070
32634994422cyclictest15237-21/usr/sbin/munin09:38:070
71420rcu_preempt11640-21sh09:31:203
71420rcu_preempt11640-21sh09:31:203
71420rcu_preempt11640-21sh09:31:203
46050420irq/122-QManpo0-210
46050420irq/122-QManpo0-210
32634994232cyclictest12042-21apt-get10:33:000
32634994232cyclictest12042-21apt-get10:33:000
32634994220cyclictest24166-21ssh10:54:470
32634994220cyclictest24166-21ssh10:54:470
32634994219cyclictest11751-21apt-get11:33:010
32634994219cyclictest11751-21apt-get11:33:010
32634994217cyclictest18780-21sh11:45:100
32634994217cyclictest18780-21sh11:45:100
32634994217cyclictest18780-21sh11:45:100
32634994212cyclictest0-21swapper/011:48:180
32634994212cyclictest0-21swapper/011:48:180
32634994212cyclictest0-21swapper/011:48:180
32634994211cyclictest0-21swapper/012:05:070
32634994211cyclictest0-21swapper/012:05:070
71410rcu_preempt0-21swapper/111:48:131
71410rcu_preempt0-21swapper/111:48:131
71410rcu_preempt0-21swapper/111:48:131
71410rcu_preempt0-21swapper/109:20:221
71410rcu_preempt0-21swapper/109:20:221
71410rcu_preempt0-21swapper/109:20:221
32634994120cyclictest10443-1kworker/0:0H10:31:050
32634994120cyclictest10443-1kworker/0:0H10:31:050
32634994120cyclictest10443-1kworker/0:0H10:31:050
32634994119cyclictest9697-21ntp_states11:28:150
32634994119cyclictest9697-21ntp_states11:28:150
32634994119cyclictest20987-21ntp_states09:48:170
32634994119cyclictest20987-21ntp_states09:48:170
32634994113cyclictest4932-21ssh12:21:120
32634994113cyclictest4932-21ssh12:21:120
32634994113cyclictest4932-21ssh12:21:120
71400rcu_preempt0-21swapper/309:26:023
71400rcu_preempt0-21swapper/309:26:023
71400rcu_preempt0-21swapper/309:26:023
71400rcu_preempt0-21swapper/211:21:242
71400rcu_preempt0-21swapper/211:21:242
71400rcu_preempt0-21swapper/112:40:251
71400rcu_preempt0-21swapper/112:40:251
71400rcu_preempt0-21swapper/111:08:371
71400rcu_preempt0-21swapper/111:08:371
71400rcu_preempt0-21swapper/109:43:201
71400rcu_preempt0-21swapper/109:43:201
71400rcu_preempt0-21swapper/109:43:201
71400rcu_preempt0-21swapper/109:14:421
71400rcu_preempt0-21swapper/109:14:421
71400rcu_preempt0-21swapper/109:14:421
71400rcu_preempt0-21swapper/108:09:261
71400rcu_preempt0-21swapper/108:09:261
71400rcu_preempt0-21swapper/012:02:210
71400rcu_preempt0-21swapper/012:02:210
71400rcu_preempt0-21swapper/011:16:030
71400rcu_preempt0-21swapper/011:16:030
71400rcu_preempt0-21swapper/011:16:030
32634994021cyclictest22727-21df_inode11:53:080
32634994021cyclictest22727-21df_inode11:53:080
32634994020cyclictest7097-21ntp_states11:23:170
32634994020cyclictest7097-21ntp_states11:23:170
32634994020cyclictest13794-21meminfo12:38:100
32634994020cyclictest13794-21meminfo12:38:100
32634994019cyclictest16136-21ntp_states08:08:130
32634994019cyclictest16136-21ntp_states08:08:130
32634994017cyclictest26078-21sendmail_mailst10:58:160
32634994017cyclictest26078-21sendmail_mailst10:58:160
32634994017cyclictest11344-21ntpq12:33:170
32634994017cyclictest11344-21ntpq12:33:170
32634994017cyclictest11344-21ntpq12:33:170
32634994016cyclictest6649-21sendmail-msp10:26:280
32634994016cyclictest6649-21sendmail-msp10:26:280
32634994016cyclictest0-21swapper/011:08:030
32634994016cyclictest0-21swapper/011:08:030
32634994016cyclictest0-21swapper/009:33:130
32634994016cyclictest0-21swapper/009:33:130
32634994012cyclictest17804-21ssh09:42:590
32634994012cyclictest17804-21ssh09:42:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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