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2025-11-26 - 18:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Wed Nov 26, 2025 12:53:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71640rcu_preempt0-21swapper/011:40:450
71640rcu_preempt0-21swapper/011:40:450
71560rcu_preempt0-21swapper/111:28:091
71560rcu_preempt0-21swapper/111:28:091
71560rcu_preempt0-21swapper/111:28:091
17220995417cyclictest0-21swapper/009:07:400
17220995417cyclictest0-21swapper/009:07:400
1722099532cyclictest8626-21runrttasks11:54:140
1722099532cyclictest8626-21runrttasks11:54:140
1722099532cyclictest8626-21runrttasks11:54:140
1722099513cyclictest0-21swapper/011:22:530
1722099513cyclictest0-21swapper/011:22:530
17220995119cyclictest0-21swapper/009:53:220
17220995119cyclictest0-21swapper/009:53:220
1722099503cyclictest0-21swapper/012:57:550
1722099503cyclictest0-21swapper/012:57:550
1722099503cyclictest0-21swapper/012:06:340
1722099503cyclictest0-21swapper/012:06:340
1722099503cyclictest0-21swapper/010:42:560
1722099503cyclictest0-21swapper/010:42:560
1722099502cyclictest31084-21diskstats12:12:570
1722099502cyclictest31084-21diskstats12:12:570
17220995018cyclictest0-21swapper/012:43:170
17220995018cyclictest0-21swapper/012:43:170
1722099493cyclictest0-21swapper/012:18:020
1722099493cyclictest0-21swapper/012:18:020
1722099493cyclictest0-21swapper/012:18:020
1722099493cyclictest0-21swapper/008:53:040
1722099493cyclictest0-21swapper/008:53:040
71480rcu_preempt0-21swapper/312:32:513
71480rcu_preempt0-21swapper/312:32:513
71480rcu_preempt0-21swapper/312:32:513
1722099483cyclictest0-21swapper/012:08:380
1722099483cyclictest0-21swapper/012:08:380
1722099483cyclictest0-21swapper/012:08:380
1722099483cyclictest0-21swapper/011:45:530
1722099483cyclictest0-21swapper/011:45:530
1722099483cyclictest0-21swapper/011:13:030
1722099483cyclictest0-21swapper/011:13:030
1722099483cyclictest0-21swapper/011:08:350
1722099483cyclictest0-21swapper/011:08:350
1722099483cyclictest0-21swapper/011:08:350
1722099483cyclictest0-21swapper/010:23:010
1722099483cyclictest0-21swapper/010:23:010
1722099483cyclictest0-21swapper/010:03:110
1722099483cyclictest0-21swapper/010:03:110
46050470irq/122-QManpo0-210
46050470irq/122-QManpo0-210
71460rcu_preempt7585-21apt-get11:27:532
71460rcu_preempt7585-21apt-get11:27:532
71460rcu_preempt7585-21apt-get11:27:532
71460rcu_preempt0-21swapper/310:57:493
71460rcu_preempt0-21swapper/310:57:493
71460rcu_preempt0-21swapper/012:53:010
71460rcu_preempt0-21swapper/012:53:010
71460rcu_preempt0-21swapper/012:53:010
1722099454cyclictest0-21swapper/010:30:360
1722099454cyclictest0-21swapper/010:30:360
1722099454cyclictest0-21swapper/010:30:360
17220994517cyclictest0-21swapper/012:28:010
17220994517cyclictest0-21swapper/012:28:010
71430rcu_preempt22536-21grep10:53:092
71430rcu_preempt22536-21grep10:53:092
71430rcu_preempt0-21swapper/008:03:060
71430rcu_preempt0-21swapper/008:03:060
71410rcu_preempt0-21swapper/110:57:491
71410rcu_preempt0-21swapper/110:57:491
71410rcu_preempt0-21swapper/009:50:280
71410rcu_preempt0-21swapper/009:50:280
71400rcu_preempt15097-21cron11:42:401
71400rcu_preempt15097-21cron11:42:401
71400rcu_preempt0-21swapper/108:23:051
71400rcu_preempt0-21swapper/108:23:051
71390rcu_preempt6137-21/usr/sbin/munin12:27:541
71390rcu_preempt6137-21/usr/sbin/munin12:27:541
71390rcu_preempt2428-21kworker/0:309:17:530
71390rcu_preempt2428-21kworker/0:309:17:530
71390rcu_preempt2428-21kworker/0:309:17:530
71390rcu_preempt0-21swapper/212:52:452
71390rcu_preempt0-21swapper/212:52:452
71390rcu_preempt0-21swapper/111:16:391
71390rcu_preempt0-21swapper/111:16:391
71390rcu_preempt0-21swapper/010:54:160
71390rcu_preempt0-21swapper/010:54:160
71380rcu_preempt24701-21ssh13:02:491
71380rcu_preempt24701-21ssh13:02:491
71380rcu_preempt0-21swapper/209:25:332
71380rcu_preempt0-21swapper/209:25:332
71380rcu_preempt0-21swapper/112:07:221
71380rcu_preempt0-21swapper/112:07:221
71380rcu_preempt0-21swapper/011:27:510
71380rcu_preempt0-21swapper/011:27:510
71380rcu_preempt0-21swapper/011:27:510
71370rcu_preempt0-21swapper/212:53:032
71370rcu_preempt0-21swapper/212:53:032
71370rcu_preempt0-21swapper/212:53:032
71370rcu_preempt0-21swapper/211:43:042
71370rcu_preempt0-21swapper/211:43:042
71370rcu_preempt0-21swapper/210:52:452
71370rcu_preempt0-21swapper/110:29:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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