You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-10 - 12:44
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Aug 10, 2026 00:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71700rcu_preempt0-21swapper/221:36:082
71700rcu_preempt0-21swapper/221:36:082
71700rcu_preempt0-21swapper/122:30:451
71700rcu_preempt0-21swapper/122:30:451
71510rcu_preempt12209-21ssh23:34:333
71510rcu_preempt12209-21ssh23:34:333
71450rcu_preempt13118-21grep23:34:510
71450rcu_preempt13118-21grep23:34:510
71440rcu_preempt0-21swapper/021:24:320
71440rcu_preempt0-21swapper/021:24:320
71440rcu_preempt0-21swapper/020:59:360
71440rcu_preempt0-21swapper/020:59:360
71430rcu_preempt0-21swapper/100:24:161
71430rcu_preempt0-21swapper/100:24:161
100650430irq/38-i2c-mpc171rcuc/100:35:361
100650430irq/38-i2c-mpc171rcuc/100:35:361
100650430irq/38-i2c-mpc171rcuc/100:35:361
71420rcu_preempt0-21swapper/023:42:160
71420rcu_preempt0-21swapper/023:42:160
28452994221cyclictest25179-21munin-run22:04:211
28452994221cyclictest25179-21munin-run22:04:211
28452994219cyclictest23866-21df23:54:361
28452994219cyclictest23866-21df23:54:361
28452994219cyclictest23866-21df23:54:361
28452994219cyclictest21706-21aten_r4power_cu22:54:331
28452994219cyclictest21706-21aten_r4power_cu22:54:331
28452994218cyclictest0-21swapper/100:14:441
28452994218cyclictest0-21swapper/100:14:441
71410rcu_preempt29139-21/usr/sbin/munin22:09:503
71410rcu_preempt29139-21/usr/sbin/munin22:09:503
71410rcu_preempt29139-21/usr/sbin/munin22:09:503
71410rcu_preempt23251-21taskset23:53:440
71410rcu_preempt23251-21taskset23:53:440
71410rcu_preempt0-21swapper/200:04:542
71410rcu_preempt0-21swapper/200:04:542
71410rcu_preempt0-21swapper/023:29:250
71410rcu_preempt0-21swapper/023:29:250
46650410irq/116-QManpo28052-2110:48:553
46650410irq/116-QManpo28052-2110:48:553
28452994119cyclictest0-21swapper/122:05:561
28452994119cyclictest0-21swapper/122:05:561
28452994119cyclictest0-21swapper/119:14:431
28452994119cyclictest0-21swapper/119:14:431
28452994110cyclictest0-21swapper/120:52:431
28452994110cyclictest0-21swapper/120:52:431
71400rcu_preempt24694-1kworker/2:1H20:09:372
71400rcu_preempt0-21swapper/122:17:201
71400rcu_preempt0-21swapper/122:17:201
28452994022cyclictest5750-21meminfo21:29:421
28452994022cyclictest5750-21meminfo21:29:421
28452994021cyclictest22594-1kworker/1:0H20:59:301
28452994021cyclictest22594-1kworker/1:0H20:59:301
28452994018cyclictest14312-21awk20:19:471
28452994018cyclictest14312-21awk20:19:471
28452994017cyclictest2913-21meminfo21:24:461
28452994017cyclictest2913-21meminfo21:24:461
28452994017cyclictest0-21swapper/122:59:451
28452994017cyclictest0-21swapper/122:59:451
28452994017cyclictest0-21swapper/122:59:451
71390rcu_preempt31816-21copy21:19:302
71390rcu_preempt31816-21copy21:19:302
71390rcu_preempt0-21swapper/323:14:393
71390rcu_preempt0-21swapper/323:14:393
71390rcu_preempt0-21swapper/122:49:341
71390rcu_preempt0-21swapper/122:49:341
71390rcu_preempt0-21swapper/022:44:140
71390rcu_preempt0-21swapper/022:44:140
71390rcu_preempt0-21swapper/000:05:020
71390rcu_preempt0-21swapper/000:05:020
46450390irq/118-QManpo27913-2110:48:552
46450390irq/118-QManpo27913-2110:48:552
46050390irq/122-QManpo6115-2110:48:550
46050390irq/122-QManpo6115-2110:48:550
46050390irq/122-QManpo0-210
46050390irq/122-QManpo0-210
28452993917cyclictest32640-21irqstats00:09:461
28452993917cyclictest32640-21irqstats00:09:461
28452993917cyclictest0-21swapper/122:09:351
28452993917cyclictest0-21swapper/122:09:351
28452993917cyclictest0-21swapper/122:09:351
28452993916cyclictest0-21swapper/119:54:511
28452993916cyclictest0-21swapper/119:54:511
28452993915cyclictest0-21swapper/120:24:451
28452993915cyclictest0-21swapper/120:24:451
28452993914cyclictest0-21swapper/123:24:361
28452993914cyclictest0-21swapper/123:24:361
71380rcu_preempt31816-21copy21:19:361
71380rcu_preempt31816-21copy21:19:361
71380rcu_preempt0-21swapper/121:39:371
71380rcu_preempt0-21swapper/121:39:371
71380rcu_preempt0-21swapper/021:37:370
71380rcu_preempt0-21swapper/021:37:370
71380rcu_preempt0-21swapper/020:04:400
71380rcu_preempt0-21swapper/020:04:400
71380rcu_preempt0-21swapper/000:26:110
71380rcu_preempt0-21swapper/000:26:110
46050380irq/122-QManpo9343-210
46050380irq/122-QManpo9343-210
28452993824cyclictest6115-21snmpd19:51:491
28452993819cyclictest29705-21df_inode00:04:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional