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2026-01-29 - 06:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Jan 29, 2026 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71530rcu_preempt0-21swapper/122:13:331
71530rcu_preempt0-21swapper/122:13:331
71530rcu_preempt0-21swapper/122:13:331
71510rcu_preempt0-21swapper/221:24:132
71510rcu_preempt0-21swapper/221:24:132
71510rcu_preempt0-21swapper/221:24:132
91399491cyclictest9395-21/usr/sbin/munin19:41:212
91399491cyclictest9395-21/usr/sbin/munin19:41:212
91399471cyclictest1959-21runrttasks00:39:322
91399471cyclictest1959-21runrttasks00:39:322
91399463cyclictest0-21swapper/220:00:552
91399463cyclictest0-21swapper/220:00:552
91399463cyclictest0-21swapper/220:00:552
71450rcu_preempt0-21swapper/222:17:332
71450rcu_preempt0-21swapper/222:17:332
91399445cyclictest0-21swapper/223:21:082
91399445cyclictest0-21swapper/223:21:082
91399443cyclictest0-21swapper/223:58:102
91399443cyclictest0-21swapper/223:58:102
91399443cyclictest0-21swapper/223:58:102
91399443cyclictest0-21swapper/223:06:392
91399443cyclictest0-21swapper/223:06:392
91399443cyclictest0-21swapper/222:47:272
91399443cyclictest0-21swapper/222:47:272
91399443cyclictest0-21swapper/221:26:142
91399443cyclictest0-21swapper/221:26:142
91399442cyclictest14183-21meminfo00:21:172
91399442cyclictest14183-21meminfo00:21:172
91399434cyclictest0-21swapper/222:28:242
91399434cyclictest0-21swapper/222:28:242
91399433cyclictest20500-21df23:36:082
91399433cyclictest20500-21df23:36:082
91399433cyclictest20500-21df23:36:082
91399433cyclictest19102-21munin-run21:40:542
91399433cyclictest19102-21munin-run21:40:542
91399433cyclictest19102-21munin-run21:40:542
91399433cyclictest0-21swapper/222:21:122
91399433cyclictest0-21swapper/222:21:122
91399433cyclictest0-21swapper/221:11:172
91399433cyclictest0-21swapper/221:11:172
91399433cyclictest0-21swapper/200:30:412
91399433cyclictest0-21swapper/200:30:412
91399433cyclictest0-21swapper/200:30:412
91399432cyclictest512-21if_eth323:01:132
91399432cyclictest512-21if_eth323:01:132
91399432cyclictest5105-21df21:16:092
91399432cyclictest5105-21df21:16:092
91399432cyclictest15160-21ntp_states23:26:202
91399432cyclictest15160-21ntp_states23:26:202
91399432cyclictest15160-21ntp_states23:26:202
71430rcu_preempt0-21swapper/021:23:060
71430rcu_preempt0-21swapper/021:23:060
71430rcu_preempt0-21swapper/021:23:060
91399424cyclictest0-21swapper/223:16:192
91399424cyclictest0-21swapper/223:16:192
91399424cyclictest0-21swapper/223:16:192
91399423cyclictest0-21swapper/222:51:232
91399423cyclictest0-21swapper/222:51:232
91399423cyclictest0-21swapper/222:33:422
91399423cyclictest0-21swapper/222:33:422
91399423cyclictest0-21swapper/222:15:382
91399423cyclictest0-21swapper/222:15:382
91399423cyclictest0-21swapper/222:15:382
91399423cyclictest0-21swapper/220:51:202
91399423cyclictest0-21swapper/220:51:202
91399423cyclictest0-21swapper/220:26:222
91399423cyclictest0-21swapper/220:26:222
91399423cyclictest0-21swapper/219:51:172
91399423cyclictest0-21swapper/219:51:172
91399423cyclictest0-21swapper/219:51:172
91399423cyclictest0-21swapper/219:31:202
91399423cyclictest0-21swapper/219:31:202
91399423cyclictest0-21swapper/200:08:142
91399423cyclictest0-21swapper/200:08:142
91399423cyclictest0-21swapper/200:08:142
91399422cyclictest0-21swapper/220:01:052
91399422cyclictest0-21swapper/220:01:052
71420rcu_preempt0-21swapper/121:57:591
71420rcu_preempt0-21swapper/121:57:591
71420rcu_preempt0-21swapper/121:57:591
71420rcu_preempt0-21swapper/021:46:220
71420rcu_preempt0-21swapper/021:46:220
71420rcu_preempt0-21swapper/021:46:220
71420rcu_preempt0-21swapper/021:13:550
71420rcu_preempt0-21swapper/021:13:550
91399414cyclictest0-21swapper/220:06:112
91399414cyclictest0-21swapper/220:06:112
91399413cyclictest0-21swapper/223:41:392
91399413cyclictest0-21swapper/223:41:392
91399413cyclictest0-21swapper/222:01:342
91399413cyclictest0-21swapper/222:01:342
91399413cyclictest0-21swapper/221:46:202
91399413cyclictest0-21swapper/221:46:202
91399413cyclictest0-21swapper/221:46:202
91399413cyclictest0-21swapper/221:06:242
91399413cyclictest0-21swapper/221:06:242
91399413cyclictest0-21swapper/221:06:242
91399413cyclictest0-21swapper/220:24:542
91399413cyclictest0-21swapper/220:24:542
91399413cyclictest0-21swapper/220:11:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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