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2026-04-07 - 13:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Tue Apr 07, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41492770chrt46450irq/118-QMan10:48:552
41492770chrt46450irq/118-QMan10:48:552
71700rcu_preempt0-21swapper/223:03:422
71700rcu_preempt0-21swapper/223:03:422
71700rcu_preempt0-21swapper/223:03:422
71580rcu_preempt0-21swapper/021:37:280
71580rcu_preempt0-21swapper/021:37:280
71480rcu_preempt0-21swapper/321:28:593
71480rcu_preempt0-21swapper/321:28:593
71480rcu_preempt0-21swapper/123:13:441
71480rcu_preempt0-21swapper/123:13:441
71470rcu_preempt0-21swapper/123:52:161
71470rcu_preempt0-21swapper/123:52:161
71460rcu_preempt0-21swapper/223:23:222
71460rcu_preempt0-21swapper/223:23:222
71460rcu_preempt0-21swapper/200:02:182
71460rcu_preempt0-21swapper/200:02:182
1699450migration/118345-21taskset19:10:491
1699450migration/118345-21taskset19:10:491
71440rcu_preempt0-21swapper/200:33:132
71440rcu_preempt0-21swapper/200:33:132
1858699443cyclictest0-21swapper/100:07:231
1858699443cyclictest0-21swapper/100:07:231
1858699443cyclictest0-21swapper/100:07:231
1858699434cyclictest0-21swapper/123:52:241
1858699434cyclictest0-21swapper/123:52:241
1858699433cyclictest496-21meminfo20:02:321
1858699433cyclictest496-21meminfo20:02:321
1858699433cyclictest0-21swapper/122:07:381
1858699433cyclictest0-21swapper/122:07:381
71420rcu_preempt0-21swapper/123:43:361
71420rcu_preempt0-21swapper/123:43:361
71420rcu_preempt0-21swapper/123:43:361
71420rcu_preempt0-21swapper/119:37:361
71420rcu_preempt0-21swapper/119:37:361
71420rcu_preempt0-21swapper/021:29:000
71420rcu_preempt0-21swapper/021:29:000
1858699424cyclictest0-21swapper/122:56:331
1858699424cyclictest0-21swapper/122:56:331
1858699424cyclictest0-21swapper/122:56:331
1858699424cyclictest0-21swapper/121:14:011
1858699424cyclictest0-21swapper/121:14:011
1858699424cyclictest0-21swapper/100:27:361
1858699424cyclictest0-21swapper/100:27:361
1858699424cyclictest0-21swapper/100:27:361
1858699423cyclictest0-21swapper/122:47:411
1858699423cyclictest0-21swapper/122:47:411
1858699423cyclictest0-21swapper/121:32:341
1858699423cyclictest0-21swapper/121:32:341
1858699422cyclictest5544-21diskstats22:42:261
1858699422cyclictest5544-21diskstats22:42:261
1858699422cyclictest5544-21diskstats22:42:261
1858699422cyclictest17356-21ntp_states21:02:371
1858699422cyclictest17356-21ntp_states21:02:371
18586994216cyclictest0-21swapper/121:59:261
18586994216cyclictest0-21swapper/121:59:261
71410rcu_preempt8423-1kworker/1:0H20:32:211
71410rcu_preempt8423-1kworker/1:0H20:32:211
71410rcu_preempt8423-1kworker/1:0H20:32:211
71410rcu_preempt18497-21cat19:12:120
71410rcu_preempt18497-21cat19:12:120
71410rcu_preempt0-21swapper/119:27:211
71410rcu_preempt0-21swapper/119:27:211
71410rcu_preempt0-21swapper/021:46:080
71410rcu_preempt0-21swapper/021:46:080
71410rcu_preempt0-21swapper/021:46:080
71410rcu_preempt0-21swapper/019:27:330
71410rcu_preempt0-21swapper/019:27:330
1858699416cyclictest20658-21ssh23:09:231
1858699416cyclictest20658-21ssh23:09:231
1858699416cyclictest20658-21ssh23:09:231
1858699413cyclictest0-21swapper/123:18:361
1858699413cyclictest0-21swapper/123:18:361
1858699413cyclictest0-21swapper/122:59:591
1858699413cyclictest0-21swapper/122:59:591
1858699413cyclictest0-21swapper/122:59:591
1858699413cyclictest0-21swapper/122:37:311
1858699413cyclictest0-21swapper/122:37:311
1858699413cyclictest0-21swapper/122:20:311
1858699413cyclictest0-21swapper/122:20:311
1858699413cyclictest0-21swapper/122:07:111
1858699413cyclictest0-21swapper/122:07:111
1858699412cyclictest31911-21/usr/sbin/munin22:32:381
1858699412cyclictest31911-21/usr/sbin/munin22:32:381
1858699412cyclictest1833-21diskstats00:32:261
1858699412cyclictest1833-21diskstats00:32:261
1858699412cyclictest11140-21munin-run20:42:111
1858699412cyclictest11140-21munin-run20:42:111
1858699412cyclictest11140-21munin-run20:42:111
1858699412cyclictest0-21swapper/123:59:421
1858699412cyclictest0-21swapper/123:59:421
1858699412cyclictest0-21swapper/123:59:421
18586994118cyclictest0-21swapper/100:17:351
18586994118cyclictest0-21swapper/100:17:351
18586994118cyclictest0-21swapper/100:17:351
18586994117cyclictest0-21swapper/121:31:561
18586994117cyclictest0-21swapper/121:31:561
18586994116cyclictest0-21swapper/122:30:121
18586994116cyclictest0-21swapper/122:30:121
18586994116cyclictest0-21swapper/100:12:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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