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2026-01-19 - 03:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Mon Jan 19, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71860rcu_preempt0-21swapper/000:16:450
71860rcu_preempt0-21swapper/000:16:450
71800rcu_preempt0-21swapper/022:02:230
71800rcu_preempt0-21swapper/022:02:230
71650rcu_preempt0-21swapper/200:04:032
71650rcu_preempt0-21swapper/200:04:032
71650rcu_preempt0-21swapper/200:04:032
71650rcu_preempt0-21swapper/100:17:431
71650rcu_preempt0-21swapper/100:17:431
100650480irq/38-i2c-mpc0-21swapper/021:09:020
100650480irq/38-i2c-mpc0-21swapper/021:09:020
100650480irq/38-i2c-mpc0-21swapper/021:09:020
306372470sleep246450irq/118-QMan10:48:552
306372470sleep246450irq/118-QMan10:48:552
1976699462cyclictest0-21swapper/223:11:152
1976699462cyclictest0-21swapper/223:11:152
19766994519cyclictest0-21swapper/221:51:012
19766994519cyclictest0-21swapper/221:51:012
1599450migration/024877-21/usr/sbin/munin00:06:140
1599450migration/024877-21/usr/sbin/munin00:06:140
71440rcu_preempt0-21swapper/221:20:542
71440rcu_preempt0-21swapper/221:20:542
46650440irq/116-QManpo18711-2110:48:553
46650440irq/116-QManpo18711-2110:48:553
1976699443cyclictest0-21swapper/222:54:252
1976699443cyclictest0-21swapper/222:54:252
1976699443cyclictest0-21swapper/222:54:252
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
1976699434cyclictest0-21swapper/221:16:172
1976699434cyclictest0-21swapper/221:16:172
1976699434cyclictest0-21swapper/221:16:172
1976699432cyclictest0-21swapper/223:32:142
1976699432cyclictest0-21swapper/223:32:142
1976699432cyclictest0-21swapper/223:32:142
1599430migration/023739-21taskset21:15:500
1599430migration/023739-21taskset21:15:500
71420rcu_preempt0-21swapper/121:49:431
71420rcu_preempt0-21swapper/121:49:431
1976699424cyclictest0-21swapper/221:40:442
1976699424cyclictest0-21swapper/221:40:442
1976699424cyclictest0-21swapper/221:40:442
1976699423cyclictest0-21swapper/200:26:042
1976699423cyclictest0-21swapper/200:26:042
71410rcu_preempt0-21swapper/121:10:541
71410rcu_preempt0-21swapper/121:10:541
1976699413cyclictest0-21swapper/223:21:042
1976699413cyclictest0-21swapper/223:21:042
1976699413cyclictest0-21swapper/223:07:302
1976699413cyclictest0-21swapper/223:07:302
1976699413cyclictest0-21swapper/222:50:432
1976699413cyclictest0-21swapper/222:50:432
1976699413cyclictest0-21swapper/222:17:242
1976699413cyclictest0-21swapper/222:17:242
1976699413cyclictest0-21swapper/222:17:242
1976699413cyclictest0-21swapper/200:32:422
1976699413cyclictest0-21swapper/200:32:422
1976699413cyclictest0-21swapper/200:32:422
1976699413cyclictest0-21swapper/200:05:582
1976699413cyclictest0-21swapper/200:05:582
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
1976699403cyclictest0-21swapper/222:21:062
1976699403cyclictest0-21swapper/222:21:062
1976699403cyclictest0-21swapper/222:21:062
1976699403cyclictest0-21swapper/220:16:002
1976699403cyclictest0-21swapper/220:16:002
142172400sleep013867-1kworker/0:2H23:48:030
142172400sleep013867-1kworker/0:2H23:48:030
71390rcu_preempt17740-21seq23:54:472
71390rcu_preempt17740-21seq23:54:472
71390rcu_preempt0-21swapper/222:45:482
71390rcu_preempt0-21swapper/222:45:482
46050390irq/122-QManpo614-2110:48:550
46050390irq/122-QManpo614-2110:48:550
1976699394cyclictest0-21swapper/223:46:002
1976699394cyclictest0-21swapper/223:46:002
1976699393cyclictest0-21swapper/221:11:092
1976699393cyclictest0-21swapper/221:11:092
71380rcu_preempt13246-21rt-features23:46:121
71380rcu_preempt13246-21rt-features23:46:121
71380rcu_preempt0-21swapper/222:57:462
71380rcu_preempt0-21swapper/222:57:462
71380rcu_preempt0-21swapper/222:57:462
71380rcu_preempt0-21swapper/222:57:462
71380rcu_preempt0-21swapper/122:55:481
71380rcu_preempt0-21swapper/122:55:481
71380rcu_preempt0-21swapper/122:55:481
273562380sleep016346-1kworker/0:1H23:15:090
273562380sleep016346-1kworker/0:1H23:15:090
71370rcu_preempt32436-1sendmail-msp00:21:442
71370rcu_preempt32436-1sendmail-msp00:21:442
71370rcu_preempt31352-21ssh21:28:360
71370rcu_preempt31352-21ssh21:28:360
71370rcu_preempt25146-21runrttasks22:14:392
71370rcu_preempt25146-21runrttasks22:14:392
71370rcu_preempt25146-21runrttasks22:14:392
71370rcu_preempt21932-21ssh23:05:460
71370rcu_preempt21932-21ssh23:05:460
71370rcu_preempt0-21swapper/200:12:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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