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2026-02-22 - 07:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Feb 22, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71590rcu_preempt0-21swapper/300:03:203
71590rcu_preempt0-21swapper/300:03:203
2962299544cyclictest0-21swapper/023:46:470
2962299544cyclictest0-21swapper/023:46:470
2962299534cyclictest0-21swapper/023:16:010
2962299534cyclictest0-21swapper/023:16:010
2962299523cyclictest0-21swapper/023:16:410
2962299523cyclictest0-21swapper/023:16:410
2962299523cyclictest0-21swapper/023:16:410
2962299523cyclictest0-21swapper/023:16:410
2962299514cyclictest0-21swapper/023:21:480
2962299514cyclictest0-21swapper/023:21:480
2962299503cyclictest0-21swapper/023:09:480
2962299503cyclictest0-21swapper/023:09:480
2962299503cyclictest0-21swapper/021:44:030
2962299503cyclictest0-21swapper/021:44:030
2962299503cyclictest0-21swapper/021:44:030
2962299503cyclictest0-21swapper/021:21:320
2962299503cyclictest0-21swapper/021:21:320
2962299503cyclictest0-21swapper/020:41:490
2962299503cyclictest0-21swapper/020:41:490
2962299493cyclictest0-21swapper/023:56:520
2962299493cyclictest0-21swapper/023:56:520
2962299493cyclictest0-21swapper/023:56:520
2962299493cyclictest0-21swapper/023:43:150
2962299493cyclictest0-21swapper/023:43:150
2962299493cyclictest0-21swapper/023:03:070
2962299493cyclictest0-21swapper/023:03:070
2962299493cyclictest0-21swapper/023:03:070
2962299493cyclictest0-21swapper/022:25:330
2962299493cyclictest0-21swapper/022:25:330
2962299493cyclictest0-21swapper/022:03:170
2962299493cyclictest0-21swapper/022:03:170
2962299493cyclictest0-21swapper/021:27:060
2962299493cyclictest0-21swapper/021:27:060
2962299493cyclictest0-21swapper/000:22:470
2962299493cyclictest0-21swapper/000:22:470
2962299493cyclictest0-21swapper/000:20:390
2962299493cyclictest0-21swapper/000:20:390
2962299493cyclictest0-21swapper/000:20:390
2962299483cyclictest0-21swapper/022:49:450
2962299483cyclictest0-21swapper/022:49:450
2962299483cyclictest0-21swapper/022:11:220
2962299483cyclictest0-21swapper/022:11:220
2962299483cyclictest0-21swapper/020:51:460
2962299483cyclictest0-21swapper/020:51:460
71460rcu_preempt0-21swapper/023:32:230
71460rcu_preempt0-21swapper/023:32:230
71460rcu_preempt0-21swapper/019:11:220
71460rcu_preempt0-21swapper/019:11:220
2962299463cyclictest0-21swapper/023:51:450
2962299463cyclictest0-21swapper/023:51:450
71440rcu_preempt0-21swapper/000:31:590
71440rcu_preempt0-21swapper/000:31:590
71430rcu_preempt0-21swapper/219:36:262
71430rcu_preempt0-21swapper/219:36:262
71420rcu_preempt0-21swapper/323:46:073
71420rcu_preempt0-21swapper/323:46:073
71420rcu_preempt0-21swapper/022:31:320
71420rcu_preempt0-21swapper/022:31:320
71420rcu_preempt0-21swapper/022:31:320
46450420irq/118-QManpo28302-212
46450420irq/118-QManpo28302-212
71410rcu_preempt0-21swapper/200:31:492
71410rcu_preempt0-21swapper/200:31:492
71400rcu_preempt27003-21kworker/2:121:41:422
71400rcu_preempt27003-21kworker/2:121:41:422
71400rcu_preempt27003-21kworker/2:121:41:422
71400rcu_preempt0-21swapper/322:22:573
71400rcu_preempt0-21swapper/322:22:573
29630994018cyclictest25091-21memory23:51:433
29630994018cyclictest25091-21memory23:51:433
71390rcu_preempt8723-21sed22:26:372
71390rcu_preempt8723-21sed22:26:372
71390rcu_preempt3746-21sed22:16:490
71390rcu_preempt3746-21sed22:16:490
71390rcu_preempt3746-21sed22:16:490
71390rcu_preempt0-21swapper/223:23:252
71390rcu_preempt0-21swapper/223:23:252
29630993917cyclictest27672-21munin-run21:01:213
29630993917cyclictest27672-21munin-run21:01:213
29630993915cyclictest0-21swapper/319:26:403
29630993915cyclictest0-21swapper/319:26:403
29630993911cyclictest21594-21ssh22:48:483
29630993911cyclictest21594-21ssh22:48:483
71380rcu_preempt30470-21diskmemload21:51:430
71380rcu_preempt30470-21diskmemload21:51:430
71380rcu_preempt30470-21diskmemload21:51:430
71380rcu_preempt0-21swapper/019:36:390
71380rcu_preempt0-21swapper/019:36:390
71380rcu_preempt0-21swapper/019:36:390
2963099389cyclictest0-21swapper/320:36:363
2963099389cyclictest0-21swapper/320:36:363
29630993818cyclictest4976-21irqstats23:16:413
29630993818cyclictest4976-21irqstats23:16:413
29630993818cyclictest4976-21irqstats23:16:413
29630993818cyclictest4976-21irqstats23:16:413
29630993817cyclictest316-21irqstats19:21:413
29630993817cyclictest316-21irqstats19:21:413
29630993813cyclictest0-21swapper/321:01:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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