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2026-04-16 - 15:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Thu Apr 16, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71530rcu_preempt0-21swapper/212:23:332
71530rcu_preempt0-21swapper/212:23:332
71530rcu_preempt0-21swapper/212:23:332
1912199488cyclictest27201-21ssh09:23:381
1912199488cyclictest27201-21ssh09:23:381
46050470irq/122-QManpo18290-2110:48:550
46050470irq/122-QManpo18290-2110:48:550
71460rcu_preempt0-21swapper/209:24:192
71460rcu_preempt0-21swapper/209:24:192
19121994517cyclictest11619-21munin-run08:42:201
19121994517cyclictest11619-21munin-run08:42:201
19121994517cyclictest11619-21munin-run08:42:201
71440rcu_preempt1599migration/010:32:150
71440rcu_preempt1599migration/010:32:150
71440rcu_preempt1599migration/010:32:150
19123994410cyclictest0-21swapper/312:25:103
19123994410cyclictest0-21swapper/312:25:103
19123994410cyclictest0-21swapper/312:25:103
19122994410cyclictest0-21swapper/210:23:112
19122994410cyclictest0-21swapper/210:23:112
19122994410cyclictest0-21swapper/210:23:112
1912199443cyclictest16861-21memory11:02:451
1912199443cyclictest16861-21memory11:02:451
1912199443cyclictest16861-21memory11:02:451
1912199442cyclictest22007-21aten_r4power_po07:22:331
1912199442cyclictest22007-21aten_r4power_po07:22:331
1912199442cyclictest22007-21aten_r4power_po07:22:331
71430rcu_preempt0-21swapper/212:06:222
71430rcu_preempt0-21swapper/212:06:222
71430rcu_preempt0-21swapper/212:06:222
19121994317cyclictest0-21swapper/111:02:231
19121994317cyclictest0-21swapper/111:02:231
71420rcu_preempt0-21swapper/111:31:091
71420rcu_preempt0-21swapper/111:31:091
71420rcu_preempt0-21swapper/111:17:471
71420rcu_preempt0-21swapper/111:17:471
71420rcu_preempt0-21swapper/009:23:420
71420rcu_preempt0-21swapper/009:23:420
46650420irq/116-QManpo17750-213
46650420irq/116-QManpo17750-213
46450420irq/118-QManpo17916-2110:48:552
46450420irq/118-QManpo17916-2110:48:552
46250420irq/120-QManpo19007-2110:48:551
46250420irq/120-QManpo19007-2110:48:551
19123994210cyclictest0-21swapper/309:32:033
19123994210cyclictest0-21swapper/309:32:033
19123994210cyclictest0-21swapper/309:32:033
1912199423cyclictest0-21swapper/112:32:211
1912199423cyclictest0-21swapper/112:32:211
1912199423cyclictest0-21swapper/110:22:221
1912199423cyclictest0-21swapper/110:22:221
1912199423cyclictest0-21swapper/110:22:221
19121994218cyclictest0-21swapper/110:16:481
19121994218cyclictest0-21swapper/110:16:481
19121994217cyclictest0-21swapper/110:43:571
19121994217cyclictest0-21swapper/110:43:571
19121994217cyclictest0-21swapper/110:43:571
19121994217cyclictest0-21swapper/107:57:481
19121994217cyclictest0-21swapper/107:57:481
71410rcu_preempt31923-21kworker/2:310:12:492
71410rcu_preempt31923-21kworker/2:310:12:492
71410rcu_preempt0-21swapper/010:18:590
71410rcu_preempt0-21swapper/010:18:590
71410rcu_preempt0-21swapper/010:18:590
46050410irq/122-QManpo28302-2110:48:550
46050410irq/122-QManpo28302-2110:48:550
46050410irq/122-QManpo28302-2110:48:550
19123994112cyclictest0-21swapper/309:02:383
19123994112cyclictest0-21swapper/309:02:383
19123994112cyclictest0-21swapper/309:02:383
19122994114cyclictest9396-1kworker/2:0H10:57:512
19122994114cyclictest9396-1kworker/2:0H10:57:512
1912199414cyclictest0-21swapper/111:35:591
1912199414cyclictest0-21swapper/111:35:591
1912199414cyclictest0-21swapper/110:32:511
1912199414cyclictest0-21swapper/110:32:511
1912199414cyclictest0-21swapper/110:31:401
1912199414cyclictest0-21swapper/110:31:401
1912199414cyclictest0-21swapper/110:31:401
1912199413cyclictest0-21swapper/112:25:031
1912199413cyclictest0-21swapper/112:25:031
1912199413cyclictest0-21swapper/112:25:031
1912199413cyclictest0-21swapper/112:16:341
1912199413cyclictest0-21swapper/112:16:341
1912199413cyclictest0-21swapper/112:10:051
1912199413cyclictest0-21swapper/112:10:051
1912199413cyclictest0-21swapper/110:47:331
1912199413cyclictest0-21swapper/110:47:331
1912199413cyclictest0-21swapper/110:11:131
1912199413cyclictest0-21swapper/110:11:131
1912199413cyclictest0-21swapper/110:11:131
1912199413cyclictest0-21swapper/109:48:171
1912199413cyclictest0-21swapper/109:48:171
1912199413cyclictest0-21swapper/109:48:171
1912199413cyclictest0-21swapper/109:46:571
1912199413cyclictest0-21swapper/109:46:571
1912199413cyclictest0-21swapper/109:13:261
1912199413cyclictest0-21swapper/109:13:261
1912199413cyclictest0-21swapper/108:57:211
1912199413cyclictest0-21swapper/108:57:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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