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2026-09-28 - 01:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sun Sep 27, 2026 12:44:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71570rcu_preempt0-21swapper/009:48:080
71570rcu_preempt0-21swapper/009:48:080
46050480irq/122-QManpo31776-2110:48:550
46050480irq/122-QManpo31776-2110:48:550
46450440irq/118-QManpo31822-2110:48:552
46450440irq/118-QManpo31822-2110:48:552
71430rcu_preempt8347-21copy09:30:222
71430rcu_preempt8347-21copy09:30:222
71430rcu_preempt8347-21copy09:30:222
71410rcu_preempt0-21swapper/011:50:230
71410rcu_preempt0-21swapper/011:50:230
46250410irq/120-QManpo31355-2110:48:551
46250410irq/120-QManpo31355-2110:48:551
71400rcu_preempt0-21swapper/109:48:161
71400rcu_preempt0-21swapper/109:48:161
71400rcu_preempt0-21swapper/010:45:530
71400rcu_preempt0-21swapper/010:45:530
71400rcu_preempt0-21swapper/010:45:530
71400rcu_preempt0-21swapper/010:35:230
71400rcu_preempt0-21swapper/010:35:230
71390rcu_preempt0-21swapper/111:38:401
71390rcu_preempt0-21swapper/111:38:401
71390rcu_preempt0-21swapper/011:00:350
71390rcu_preempt0-21swapper/011:00:350
71390rcu_preempt0-21swapper/011:00:350
71390rcu_preempt0-21swapper/008:53:040
71390rcu_preempt0-21swapper/008:53:040
71380rcu_preempt20507-21ssh09:50:402
71380rcu_preempt20507-21ssh09:50:402
71380rcu_preempt0-21swapper/310:38:523
71380rcu_preempt0-21swapper/310:38:523
71380rcu_preempt0-21swapper/211:10:142
71380rcu_preempt0-21swapper/211:10:142
71380rcu_preempt0-21swapper/012:05:360
71380rcu_preempt0-21swapper/012:05:360
71380rcu_preempt0-21swapper/011:26:080
71380rcu_preempt0-21swapper/011:26:080
71380rcu_preempt0-21swapper/010:34:390
71380rcu_preempt0-21swapper/010:34:390
71380rcu_preempt0-21swapper/010:27:490
71380rcu_preempt0-21swapper/010:27:490
71380rcu_preempt0-21swapper/010:09:040
71380rcu_preempt0-21swapper/010:09:040
71380rcu_preempt0-21swapper/008:30:310
71380rcu_preempt0-21swapper/008:30:310
99750370irq/38-i2c-mpc0-21swapper/312:39:383
99750370irq/38-i2c-mpc0-21swapper/312:39:383
71370rcu_preempt8949-21memory09:30:373
71370rcu_preempt8949-21memory09:30:373
71370rcu_preempt8949-21memory09:30:373
71370rcu_preempt8384-1kworker/0:4H09:32:550
71370rcu_preempt8384-1kworker/0:4H09:32:550
71370rcu_preempt8384-1kworker/0:4H09:32:550
71370rcu_preempt2516-21/usr/sbin/munin07:25:402
71370rcu_preempt2516-21/usr/sbin/munin07:25:402
71370rcu_preempt14216-1kworker/1:1H11:40:521
71370rcu_preempt14216-1kworker/1:1H11:40:521
71370rcu_preempt14216-1kworker/1:1H11:40:521
71370rcu_preempt0-21swapper/212:26:522
71370rcu_preempt0-21swapper/212:26:522
71370rcu_preempt0-21swapper/208:20:132
71370rcu_preempt0-21swapper/208:20:132
71370rcu_preempt0-21swapper/108:45:301
71370rcu_preempt0-21swapper/108:45:301
71370rcu_preempt0-21swapper/011:45:000
71370rcu_preempt0-21swapper/011:45:000
71370rcu_preempt0-21swapper/011:45:000
71370rcu_preempt0-21swapper/011:19:590
71370rcu_preempt0-21swapper/011:19:590
71370rcu_preempt0-21swapper/011:07:400
71370rcu_preempt0-21swapper/011:07:400
71370rcu_preempt0-21swapper/007:46:050
71370rcu_preempt0-21swapper/007:36:330
71370rcu_preempt0-21swapper/007:36:330
71370rcu_preempt0-21swapper/007:36:330
71360rcu_preempt7034-21diskmemload09:26:330
71360rcu_preempt7034-21diskmemload09:26:330
71360rcu_preempt31793-21sh12:07:522
71360rcu_preempt31793-21sh12:07:522
71360rcu_preempt2909-21latency_hist09:20:170
71360rcu_preempt2909-21latency_hist09:20:170
71360rcu_preempt1770-21in:imuxsock10:20:131
71360rcu_preempt1770-21in:imuxsock10:20:131
71360rcu_preempt13277-21cat11:35:160
71360rcu_preempt13277-21cat11:35:160
71360rcu_preempt0-21swapper/212:45:112
71360rcu_preempt0-21swapper/212:45:112
71360rcu_preempt0-21swapper/212:45:112
71360rcu_preempt0-21swapper/211:16:282
71360rcu_preempt0-21swapper/211:16:282
71360rcu_preempt0-21swapper/209:10:042
71360rcu_preempt0-21swapper/209:10:042
71360rcu_preempt0-21swapper/112:12:311
71360rcu_preempt0-21swapper/112:12:311
71360rcu_preempt0-21swapper/111:23:041
71360rcu_preempt0-21swapper/111:23:041
71360rcu_preempt0-21swapper/110:40:151
71360rcu_preempt0-21swapper/110:40:151
71360rcu_preempt0-21swapper/110:34:571
71360rcu_preempt0-21swapper/110:34:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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