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2026-06-06 - 17:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Jun 06, 2026 00:44:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71600rcu_preempt0-21swapper/221:57:052
71600rcu_preempt0-21swapper/221:57:052
71560rcu_preempt0-21swapper/322:03:393
71560rcu_preempt0-21swapper/322:03:393
2258899492cyclictest6284-21sendmail-msp23:03:361
2258899492cyclictest6284-21sendmail-msp23:03:361
2258899492cyclictest6284-21sendmail-msp23:03:361
71470rcu_preempt22586-21cyclictest21:41:371
71470rcu_preempt22586-21cyclictest21:41:371
71470rcu_preempt22586-21cyclictest21:41:371
46050460irq/122-QManpo21028-2110:48:550
46050460irq/122-QManpo21028-2110:48:550
71450rcu_preempt0-21swapper/323:19:143
71450rcu_preempt0-21swapper/323:19:143
71450rcu_preempt0-21swapper/022:48:500
71450rcu_preempt0-21swapper/022:48:500
71450rcu_preempt0-21swapper/022:48:500
2258899451cyclictest30955-21/usr/sbin/munin19:43:381
2258899451cyclictest30955-21/usr/sbin/munin19:43:381
2258899451cyclictest30955-21/usr/sbin/munin19:43:381
2258899451cyclictest25266-21sendmail-msp19:23:141
2258899451cyclictest25266-21sendmail-msp19:23:141
22588994518cyclictest1959-21runrttasks23:53:471
22588994518cyclictest1959-21runrttasks23:53:471
22588994518cyclictest1959-21runrttasks23:53:471
2258899444cyclictest0-21swapper/123:30:111
2258899444cyclictest0-21swapper/123:30:111
2258899444cyclictest0-21swapper/123:30:111
2258899443cyclictest0-21swapper/100:15:301
2258899443cyclictest0-21swapper/100:15:301
2258899442cyclictest0-21swapper/121:33:241
2258899442cyclictest0-21swapper/121:33:241
2258899442cyclictest0-21swapper/121:33:241
71430rcu_preempt0-21swapper/222:38:242
71430rcu_preempt0-21swapper/222:38:242
2258899433cyclictest0-21swapper/123:38:261
2258899433cyclictest0-21swapper/123:38:261
2258899433cyclictest0-21swapper/123:38:261
2258899433cyclictest0-21swapper/123:33:411
2258899433cyclictest0-21swapper/123:33:411
2258899433cyclictest0-21swapper/122:48:491
2258899433cyclictest0-21swapper/122:48:491
2258899433cyclictest0-21swapper/122:48:491
2258899432cyclictest21870-21ssh22:10:441
2258899432cyclictest21870-21ssh22:10:441
22588994315cyclictest28482-21irqstats19:33:331
22588994315cyclictest28482-21irqstats19:33:331
22588994315cyclictest23197-21irqstats22:13:341
22588994315cyclictest23197-21irqstats22:13:341
22588994315cyclictest23197-21irqstats22:13:341
71420rcu_preempt30005-21munin-plugin-st23:28:151
71420rcu_preempt30005-21munin-plugin-st23:28:151
71420rcu_preempt30005-21munin-plugin-st23:28:151
71420rcu_preempt0-21swapper/020:00:370
71420rcu_preempt0-21swapper/020:00:370
71420rcu_preempt0-21swapper/020:00:370
46650420irq/116-QManpo20135-2110:48:553
46650420irq/116-QManpo20135-2110:48:553
2258899425cyclictest0-21swapper/121:52:531
2258899425cyclictest0-21swapper/121:52:531
2258899425cyclictest0-21swapper/121:52:531
2258899424cyclictest0-21swapper/123:46:591
2258899424cyclictest0-21swapper/123:46:591
2258899424cyclictest0-21swapper/123:46:591
2258899424cyclictest0-21swapper/123:03:191
2258899424cyclictest0-21swapper/123:03:191
2258899424cyclictest0-21swapper/123:03:191
2258899424cyclictest0-21swapper/120:28:411
2258899424cyclictest0-21swapper/120:28:411
2258899424cyclictest0-21swapper/120:28:411
2258899424cyclictest0-21swapper/120:23:271
2258899424cyclictest0-21swapper/120:23:271
2258899424cyclictest0-21swapper/100:18:321
2258899424cyclictest0-21swapper/100:18:321
2258899424cyclictest0-21swapper/100:18:321
2258899424cyclictest0-21swapper/100:08:471
2258899424cyclictest0-21swapper/100:08:471
2258899424cyclictest0-21swapper/100:08:471
2258899423cyclictest0-21swapper/121:58:431
2258899423cyclictest0-21swapper/121:58:431
2258899423cyclictest0-21swapper/121:58:431
2258899423cyclictest0-21swapper/100:42:571
2258899423cyclictest0-21swapper/100:42:571
2258899423cyclictest0-21swapper/100:42:571
2258899423cyclictest0-21swapper/100:02:501
2258899423cyclictest0-21swapper/100:02:501
2258899422cyclictest28291-21diskstats22:23:311
2258899422cyclictest28291-21diskstats22:23:311
2258899422cyclictest28291-21diskstats22:23:311
2258899422cyclictest25491-21wget19:23:271
2258899422cyclictest25491-21wget19:23:271
2258899422cyclictest16603-21diskstats00:03:321
2258899422cyclictest16603-21diskstats00:03:321
2258899422cyclictest16603-21diskstats00:03:321
22588994219cyclictest20847-21aten_r4power_en21:03:271
22588994219cyclictest20847-21aten_r4power_en21:03:271
22588994219cyclictest20847-21aten_r4power_en21:03:271
71410rcu_preempt30515-21sh00:29:490
71410rcu_preempt30515-21sh00:29:490
71410rcu_preempt30515-21sh00:29:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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