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2026-06-20 - 08:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack4slot4.osadl.org (updated Sat Jun 20, 2026 00:44:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
293192970chrt46650irq/116-QMan10:48:553
293192970chrt46650irq/116-QMan10:48:553
293192970chrt46650irq/116-QMan10:48:553
71550rcu_preempt0-21swapper/000:04:300
71550rcu_preempt0-21swapper/000:04:300
71550rcu_preempt0-21swapper/000:04:300
71550rcu_preempt0-21swapper/000:04:300
46450510irq/118-QManpo1411-2110:48:552
46450510irq/118-QManpo1411-2110:48:552
71480rcu_preempt0-21swapper/023:29:300
71480rcu_preempt0-21swapper/023:29:300
71480rcu_preempt0-21swapper/023:29:300
46050460irq/122-QManpo0-210
46050460irq/122-QManpo0-210
71430rcu_preempt0-21swapper/119:09:471
71430rcu_preempt0-21swapper/119:09:471
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
71420rcu_preempt12610-21sh23:28:360
71420rcu_preempt12610-21sh23:28:360
71420rcu_preempt0-21swapper/221:20:382
71420rcu_preempt0-21swapper/221:20:382
46050420irq/122-QManpo26523-210
46050420irq/122-QManpo26523-210
46050420irq/122-QManpo26523-210
71410rcu_preempt20313-21sendmail-msp00:05:442
71410rcu_preempt20313-21sendmail-msp00:05:442
71410rcu_preempt20313-21sendmail-msp00:05:442
71410rcu_preempt20313-21sendmail-msp00:05:442
1599410migration/02239-21runrttasks20:57:320
1599410migration/02239-21runrttasks20:57:320
1599410migration/02239-21runrttasks20:57:320
71400rcu_preempt1966-21sh23:08:072
71400rcu_preempt1966-21sh23:08:072
71400rcu_preempt1966-21sh23:08:072
71400rcu_preempt14393-21/usr/sbin/munin21:28:562
71400rcu_preempt14393-21/usr/sbin/munin21:28:562
71400rcu_preempt14393-21/usr/sbin/munin21:28:562
71400rcu_preempt0-21swapper/200:02:572
71400rcu_preempt0-21swapper/200:02:572
71400rcu_preempt0-21swapper/200:02:572
71400rcu_preempt0-21swapper/121:33:011
71400rcu_preempt0-21swapper/121:33:011
71400rcu_preempt0-21swapper/121:33:011
46650400irq/116-QManpo1521-2110:48:553
46650400irq/116-QManpo1521-2110:48:553
71390rcu_preempt29590-21kworker/3:319:28:503
71390rcu_preempt29590-21kworker/3:319:28:503
71390rcu_preempt22801-21sh23:48:132
71390rcu_preempt22801-21sh23:48:132
71390rcu_preempt22801-21sh23:48:132
71390rcu_preempt0-21swapper/300:09:123
71390rcu_preempt0-21swapper/300:09:123
71390rcu_preempt0-21swapper/300:09:123
71390rcu_preempt0-21swapper/222:23:382
71390rcu_preempt0-21swapper/222:23:382
71390rcu_preempt0-21swapper/222:23:382
71390rcu_preempt0-21swapper/200:29:342
71390rcu_preempt0-21swapper/200:29:342
71390rcu_preempt0-21swapper/122:28:231
71390rcu_preempt0-21swapper/122:28:231
71390rcu_preempt0-21swapper/122:28:231
46050390irq/122-QManpo14002-2110:48:550
46050390irq/122-QManpo14002-2110:48:550
46050390irq/122-QManpo14002-2110:48:550
71380rcu_preempt0-21swapper/321:45:253
71380rcu_preempt0-21swapper/321:45:253
71380rcu_preempt0-21swapper/321:45:253
71380rcu_preempt0-21swapper/300:37:263
71380rcu_preempt0-21swapper/300:37:263
71380rcu_preempt0-21swapper/223:38:422
71380rcu_preempt0-21swapper/223:38:422
71380rcu_preempt0-21swapper/223:26:092
71380rcu_preempt0-21swapper/223:26:092
71380rcu_preempt0-21swapper/223:26:092
71380rcu_preempt0-21swapper/222:15:042
71380rcu_preempt0-21swapper/222:15:042
71380rcu_preempt0-21swapper/222:15:042
71380rcu_preempt0-21swapper/220:40:042
71380rcu_preempt0-21swapper/220:40:042
71380rcu_preempt0-21swapper/123:20:451
71380rcu_preempt0-21swapper/123:20:451
71380rcu_preempt0-21swapper/122:10:121
71380rcu_preempt0-21swapper/122:10:121
71380rcu_preempt0-21swapper/122:10:121
71380rcu_preempt0-21swapper/021:56:040
71380rcu_preempt0-21swapper/021:56:040
71380rcu_preempt0-21swapper/021:56:040
46050380irq/122-QManpo32060-2110:48:550
46050380irq/122-QManpo32060-2110:48:550
46050380irq/122-QManpo32060-2110:48:550
46050380irq/122-QManpo25526-2110:48:550
46050380irq/122-QManpo25526-2110:48:550
46050380irq/122-QManpo25526-2110:48:550
46050380irq/122-QManpo22576-2110:48:550
46050380irq/122-QManpo22576-2110:48:550
46050380irq/122-QManpo11459-2110:48:550
46050380irq/122-QManpo11459-2110:48:550
46050380irq/122-QManpo0-210
46050380irq/122-QManpo0-210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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