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2025-06-28 - 19:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot4.osadl.org (updated Sat Jun 28, 2025 12:52:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71670rcu_preempt0-21swapper/011:13:370
71670rcu_preempt0-21swapper/011:13:370
71640rcu_preempt0-21swapper/111:25:071
71640rcu_preempt0-21swapper/111:25:071
71600rcu_preempt0-21swapper/310:37:503
71600rcu_preempt0-21swapper/310:37:503
71550rcu_preempt0-21swapper/312:52:173
71550rcu_preempt0-21swapper/312:52:173
71550rcu_preempt0-21swapper/312:52:173
46050530irq/122-QManpo29022-2109:24:360
71500rcu_preempt0-21swapper/311:57:223
71500rcu_preempt0-21swapper/311:57:223
71490rcu_preempt0-21swapper/310:57:383
71490rcu_preempt0-21swapper/310:57:383
71490rcu_preempt0-21swapper/310:57:383
71490rcu_preempt0-21swapper/310:47:023
71490rcu_preempt0-21swapper/310:47:023
71460rcu_preempt0-21swapper/310:18:273
71460rcu_preempt0-21swapper/310:18:273
46050460irq/122-QManpo0-210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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