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2026-07-04 - 22:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack4slot4.osadl.org (updated Sat Jul 04, 2026 12:44:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71460rcu_preempt0-21swapper/308:03:593
71460rcu_preempt0-21swapper/308:03:593
71460rcu_preempt0-21swapper/308:03:593
46050460irq/122-QManpo19501-2110:48:550
46050460irq/122-QManpo19501-2110:48:550
71450rcu_preempt0-21swapper/210:03:492
71450rcu_preempt0-21swapper/210:03:492
71450rcu_preempt0-21swapper/210:03:492
71440rcu_preempt7047-21sh11:55:510
71440rcu_preempt7047-21sh11:55:510
71440rcu_preempt7047-21sh11:55:510
71440rcu_preempt0-21swapper/112:23:561
71440rcu_preempt0-21swapper/112:23:561
71440rcu_preempt0-21swapper/112:23:561
1976999443cyclictest0-21swapper/210:23:592
1976999443cyclictest0-21swapper/210:23:592
19769994419cyclictest0-21swapper/212:38:562
19769994419cyclictest0-21swapper/212:38:562
71430rcu_preempt12822-21copy10:03:550
71430rcu_preempt12822-21copy10:03:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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