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2026-08-07 - 23:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Fri Aug 07, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71500rcu_preempt9722-21diskmemload11:35:061
71500rcu_preempt9722-21diskmemload11:35:061
46650500irq/116-QManpo9167-2110:48:553
46650500irq/116-QManpo9167-2110:48:553
71490rcu_preempt0-21swapper/112:30:531
71490rcu_preempt0-21swapper/112:30:531
71490rcu_preempt0-21swapper/108:39:311
71490rcu_preempt0-21swapper/108:39:311
71460rcu_preempt5907-21apt-get10:04:310
71460rcu_preempt5907-21apt-get10:04:310
71460rcu_preempt0-21swapper/110:31:061
71460rcu_preempt0-21swapper/110:31:061
71450rcu_preempt9722-21diskmemload12:14:442
71450rcu_preempt9722-21diskmemload12:14:442
71450rcu_preempt0-21swapper/112:35:021
71450rcu_preempt0-21swapper/112:35:021
71440rcu_preempt2480-1kworker/2:1H09:24:102
71440rcu_preempt2480-1kworker/2:1H09:24:102
71430rcu_preempt0-21swapper/211:43:502
71430rcu_preempt0-21swapper/211:43:502
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
100650430irq/38-i2c-mpc22285-21ssh09:34:520
100650430irq/38-i2c-mpc22285-21ssh09:34:520
71420rcu_preempt0-21swapper/212:32:372
71420rcu_preempt0-21swapper/212:32:372
71420rcu_preempt0-21swapper/212:25:312
71420rcu_preempt0-21swapper/212:25:312
71420rcu_preempt0-21swapper/209:42:342
71420rcu_preempt0-21swapper/209:42:342
71420rcu_preempt0-21swapper/209:42:342
71420rcu_preempt0-21swapper/109:24:131
71420rcu_preempt0-21swapper/109:24:131
71420rcu_preempt0-21swapper/012:16:420
71420rcu_preempt0-21swapper/012:16:420
71420rcu_preempt0-21swapper/008:59:340
71420rcu_preempt0-21swapper/008:59:340
71410rcu_preempt20243-21sh10:29:342
71410rcu_preempt20243-21sh10:29:342
71410rcu_preempt0-21swapper/312:18:493
71410rcu_preempt0-21swapper/312:18:493
71410rcu_preempt0-21swapper/211:03:282
71410rcu_preempt0-21swapper/211:03:282
71410rcu_preempt0-21swapper/211:03:282
71410rcu_preempt0-21swapper/210:14:122
71410rcu_preempt0-21swapper/209:32:202
71410rcu_preempt0-21swapper/209:32:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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