You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-17 - 04:03
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Wed Jun 17, 2026 00:44:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71750rcu_preempt0-21swapper/321:46:133
71750rcu_preempt0-21swapper/321:46:133
71750rcu_preempt0-21swapper/321:46:133
71490rcu_preempt0-21swapper/100:33:311
71490rcu_preempt0-21swapper/100:33:311
71470rcu_preempt0-21swapper/121:19:011
71470rcu_preempt0-21swapper/121:19:011
46050470irq/122-QManpo0-210
46050470irq/122-QManpo0-210
46050470irq/122-QManpo0-210
46050450irq/122-QManpo27575-110:48:550
46050450irq/122-QManpo27575-110:48:550
46050450irq/122-QManpo27575-110:48:550
28392994516cyclictest25741-21ntp_states20:58:551
28392994516cyclictest25741-21ntp_states20:58:551
71440rcu_preempt7958-21copy23:38:302
71440rcu_preempt7958-21copy23:38:302
71440rcu_preempt7958-21copy23:38:302
71440rcu_preempt0-21swapper/222:08:112
71440rcu_preempt0-21swapper/222:08:112
71440rcu_preempt0-21swapper/121:53:371
71440rcu_preempt0-21swapper/121:53:371
71440rcu_preempt0-21swapper/121:53:371
28392994431cyclictest1959-21runrttasks23:08:221
28392994431cyclictest1959-21runrttasks23:08:221
28392994421cyclictest7360-21diskstats19:53:411
28392994421cyclictest7360-21diskstats19:53:411
28392994421cyclictest7360-21diskstats19:53:411
28392994421cyclictest7221-21ssh23:36:181
28392994421cyclictest7221-21ssh23:36:181
28392994421cyclictest7221-21ssh23:36:181
71420rcu_preempt30380-21sh22:16:011
71420rcu_preempt30380-21sh22:16:011
71420rcu_preempt30380-21sh22:16:011
71420rcu_preempt0-21swapper/323:23:343
71420rcu_preempt0-21swapper/323:23:343
71420rcu_preempt0-21swapper/323:23:343
71420rcu_preempt0-21swapper/122:53:261
71420rcu_preempt0-21swapper/122:53:261
71420rcu_preempt0-21swapper/122:53:261
71420rcu_preempt0-21swapper/122:27:391
71420rcu_preempt0-21swapper/122:27:391
71420rcu_preempt0-21swapper/122:27:391
28392994222cyclictest7176-21diskstats22:33:471
28392994222cyclictest7176-21diskstats22:33:471
28392994222cyclictest7176-21diskstats22:33:471
28392994222cyclictest19807-21df20:38:401
28392994222cyclictest19807-21df20:38:401
28392994222cyclictest1801-21diskstats19:33:421
28392994222cyclictest1801-21diskstats19:33:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional