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2026-02-14 - 11:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Sat Feb 14, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71680rcu_preempt0-21swapper/323:15:303
71680rcu_preempt0-21swapper/323:15:303
71680rcu_preempt0-21swapper/323:15:303
71480rcu_preempt0-21swapper/321:06:253
71480rcu_preempt0-21swapper/321:06:253
1093399462cyclictest18738-21sed21:21:431
1093399462cyclictest18738-21sed21:21:431
1093399462cyclictest18738-21sed21:21:431
71450rcu_preempt0-21swapper/300:08:163
71450rcu_preempt0-21swapper/300:08:163
71450rcu_preempt0-21swapper/300:08:163
1093399457cyclictest32469-21ssh22:43:131
1093399457cyclictest32469-21ssh22:43:131
10933994518cyclictest0-21swapper/121:56:431
10933994518cyclictest0-21swapper/121:56:431
10933994518cyclictest0-21swapper/121:56:431
1093399443cyclictest24345-21df_inode23:26:281
1093399443cyclictest24345-21df_inode23:26:281
71430rcu_preempt0-21swapper/022:01:240
71430rcu_preempt0-21swapper/022:01:240
71430rcu_preempt0-21swapper/022:01:240
1093399434cyclictest0-21swapper/122:06:351
1093399434cyclictest0-21swapper/122:06:351
71420rcu_preempt1959-21runrttasks19:36:241
71420rcu_preempt1959-21runrttasks19:36:241
71420rcu_preempt1959-21runrttasks19:36:241
71420rcu_preempt19489-1kworker/0:1H22:41:380
71420rcu_preempt19489-1kworker/0:1H22:41:380
1093399423cyclictest0-21swapper/122:31:381
1093399423cyclictest0-21swapper/122:31:381
1093399423cyclictest0-21swapper/121:56:071
1093399423cyclictest0-21swapper/121:56:071
1093399423cyclictest0-21swapper/121:56:071
1093399423cyclictest0-21swapper/120:06:261
1093399423cyclictest0-21swapper/120:06:261
10933994218cyclictest0-21swapper/100:11:131
10933994218cyclictest0-21swapper/100:11:131
10933994218cyclictest0-21swapper/100:11:131
71410rcu_preempt0-21swapper/221:51:342
71410rcu_preempt0-21swapper/221:51:342
71410rcu_preempt0-21swapper/221:51:342
1093399414cyclictest0-21swapper/122:26:261
1093399414cyclictest0-21swapper/122:26:261
1093399414cyclictest0-21swapper/100:28:181
1093399414cyclictest0-21swapper/100:28:181
1093399414cyclictest0-21swapper/100:28:181
1093399413cyclictest11411-21meminfo19:11:321
1093399413cyclictest11411-21meminfo19:11:321
1093399413cyclictest0-21swapper/122:46:391
1093399413cyclictest0-21swapper/122:46:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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