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2026-01-21 - 02:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Wed Jan 21, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71540rcu_preempt574-21kswapd021:50:563
71540rcu_preempt574-21kswapd021:50:563
71490rcu_preempt0-21swapper/022:24:070
71490rcu_preempt0-21swapper/022:24:070
71470rcu_preempt0-21swapper/000:13:330
71470rcu_preempt0-21swapper/000:13:330
71470rcu_preempt0-21swapper/000:13:330
71460rcu_preempt17658-21diskstats00:31:040
71460rcu_preempt17658-21diskstats00:31:040
71460rcu_preempt11571-21copy00:20:592
71460rcu_preempt11571-21copy00:20:592
3125399463cyclictest0-21swapper/121:50:541
3125399452cyclictest1959-21runrttasks23:58:341
3125399452cyclictest1959-21runrttasks23:58:341
3125399452cyclictest1959-21runrttasks23:58:341
3125399452cyclictest1959-21runrttasks23:32:321
3125399452cyclictest1959-21runrttasks23:32:321
31256994423cyclictest21530-21irqstats23:41:062
31256994423cyclictest21530-21irqstats23:41:062
31256994420cyclictest10060-21/usr/sbin/munin19:51:012
31256994420cyclictest10060-21/usr/sbin/munin19:51:012
31256994417cyclictest24170-21diskstats20:41:032
31256994417cyclictest24170-21diskstats20:41:032
3125399444cyclictest0-21swapper/121:54:121
3125399444cyclictest0-21swapper/121:54:121
103150440irq/48-mmc0171rcuc/123:10:501
103150440irq/48-mmc0171rcuc/123:10:501
71430rcu_preempt0-21swapper/000:04:360
71430rcu_preempt0-21swapper/000:04:360
46050430irq/122-QManpo31204-2110:48:550
46050430irq/122-QManpo31204-2110:48:550
31256994323cyclictest31788-21ssh22:06:042
31256994323cyclictest31788-21ssh22:06:042
31256994323cyclictest31788-21ssh22:06:042
3125399434cyclictest0-21swapper/100:30:421
3125399434cyclictest0-21swapper/100:30:421
3125399433cyclictest0-21swapper/122:36:401
3125399433cyclictest0-21swapper/122:36:401
3125399433cyclictest0-21swapper/119:51:051
3125399433cyclictest0-21swapper/119:51:051
3125399432cyclictest9974-21diskstats23:21:021
3125399432cyclictest9974-21diskstats23:21:021
31256994225cyclictest19882-21copy21:45:562
31256994225cyclictest19882-21copy21:45:562
31256994223cyclictest23135-21df_inode21:51:032
31256994223cyclictest23135-21df_inode21:51:032
31256994222cyclictest29323-21munin-run21:00:462
31256994222cyclictest29323-21munin-run21:00:462
31256994222cyclictest29323-21munin-run21:00:462
31256994221cyclictest20691-21meminfo00:36:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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