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2025-10-14 - 08:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Tue Oct 14, 2025 00:54:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71650rcu_preempt0-21swapper/222:02:292
71650rcu_preempt0-21swapper/222:02:292
71650rcu_preempt0-21swapper/222:02:292
71590rcu_preempt5834-21sh23:02:010
71590rcu_preempt5834-21sh23:02:010
71590rcu_preempt5834-21sh23:02:010
71560rcu_preempt30599-21irqstats23:47:130
71560rcu_preempt30599-21irqstats23:47:130
71500rcu_preempt24663-21copy23:37:051
71500rcu_preempt24663-21copy23:37:051
71470rcu_preempt0-21swapper/023:29:130
71470rcu_preempt0-21swapper/023:29:130
71470rcu_preempt0-21swapper/023:29:130
46050470irq/122-QManpo10462-2109:24:360
46050470irq/122-QManpo10462-2109:24:360
46050470irq/122-QManpo10462-2109:24:360
2684599464cyclictest0-21swapper/123:02:201
2684599464cyclictest0-21swapper/123:02:201
2684599464cyclictest0-21swapper/123:02:201
2684599464cyclictest0-21swapper/122:37:051
2684599464cyclictest0-21swapper/122:37:051
71440rcu_preempt0-21swapper/222:49:132
71440rcu_preempt0-21swapper/222:49:132
71440rcu_preempt0-21swapper/222:49:132
26845994218cyclictest993-21ntp_states22:52:161
26845994218cyclictest993-21ntp_states22:52:161
71410rcu_preempt8626-21runrttasks00:10:472
71410rcu_preempt8626-21runrttasks00:10:472
71410rcu_preempt0-21swapper/223:37:222
71410rcu_preempt0-21swapper/223:37:222
71410rcu_preempt0-21swapper/222:15:472
71410rcu_preempt0-21swapper/222:15:472
71410rcu_preempt0-21swapper/221:42:182
71410rcu_preempt0-21swapper/221:42:182
46050410irq/122-QManpo31726-2109:24:360
46050410irq/122-QManpo31726-2109:24:360
46050410irq/122-QManpo31726-2109:24:360
71400rcu_preempt0-21swapper/200:44:122
71400rcu_preempt0-21swapper/200:44:122
71400rcu_preempt0-21swapper/200:44:122
71400rcu_preempt0-21swapper/123:26:561
71400rcu_preempt0-21swapper/123:26:561
46050400irq/122-QManpo25784-2109:24:360
46050400irq/122-QManpo25784-2109:24:360
71390rcu_preempt0-21swapper/201:02:112
71390rcu_preempt0-21swapper/201:02:112
71390rcu_preempt0-21swapper/200:13:032
71390rcu_preempt0-21swapper/200:13:032
71390rcu_preempt0-21swapper/200:13:032
46050390irq/122-QManpo6698-10
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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