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2026-01-25 - 05:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Sun Jan 25, 2026 00:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71620rcu_preempt0-21swapper/122:54:111
71620rcu_preempt0-21swapper/122:54:111
71620rcu_preempt0-21swapper/122:54:111
2082399534cyclictest0-21swapper/023:05:500
2082399534cyclictest0-21swapper/023:05:500
2082399523cyclictest0-21swapper/022:41:590
2082399523cyclictest0-21swapper/022:41:590
2082399523cyclictest0-21swapper/022:41:590
2082399522cyclictest8179-21df_inode20:21:050
2082399522cyclictest8179-21df_inode20:21:050
2082399522cyclictest8179-21df_inode20:21:050
2082399522cyclictest18631-21meminfo22:01:110
2082399522cyclictest18631-21meminfo22:01:110
2082399522cyclictest17729-21memory22:56:130
2082399522cyclictest17729-21memory22:56:130
2082399522cyclictest17729-21memory22:56:130
20823995216cyclictest24145-21grep19:21:130
20823995216cyclictest24145-21grep19:21:130
2082699512cyclictest1959-21runrttasks21:52:333
2082699512cyclictest1959-21runrttasks21:52:333
2082399513cyclictest0-21swapper/000:37:020
2082399513cyclictest0-21swapper/000:37:020
2082399513cyclictest0-21swapper/000:37:020
2082399513cyclictest0-21swapper/000:26:010
2082399513cyclictest0-21swapper/000:26:010
2082399513cyclictest0-21swapper/000:06:130
2082399513cyclictest0-21swapper/000:06:130
20823995116cyclictest965-21/usr/sbin/munin19:56:160
20823995116cyclictest965-21/usr/sbin/munin19:56:160
2082399503cyclictest0-21swapper/023:49:360
2082399503cyclictest0-21swapper/023:49:360
2082399503cyclictest0-21swapper/023:11:190
2082399503cyclictest0-21swapper/023:11:190
2082399503cyclictest0-21swapper/021:54:020
2082399503cyclictest0-21swapper/021:54:020
2082399503cyclictest0-21swapper/021:37:390
2082399503cyclictest0-21swapper/021:37:390
2082399503cyclictest0-21swapper/021:21:520
2082399503cyclictest0-21swapper/021:21:520
2082399503cyclictest0-21swapper/000:21:270
2082399503cyclictest0-21swapper/000:21:270
2082399503cyclictest0-21swapper/000:18:210
2082399503cyclictest0-21swapper/000:18:210
2082399502cyclictest30577-21users22:21:210
2082399502cyclictest30577-21users22:21:210
2082399502cyclictest2709-21irqstats20:01:080
2082399502cyclictest2709-21irqstats20:01:080
2082399502cyclictest0-21swapper/022:50:540
2082399502cyclictest0-21swapper/022:50:540
20823995018cyclictest0-21swapper/021:12:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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