You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-17 - 11:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Tue Feb 17, 2026 00:44:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71860rcu_preempt0-21swapper/221:12:512
71860rcu_preempt0-21swapper/221:12:512
71790rcu_preempt0-21swapper/121:51:171
71790rcu_preempt0-21swapper/121:51:171
71550rcu_preempt0-21swapper/222:43:282
71550rcu_preempt0-21swapper/222:43:282
71550rcu_preempt0-21swapper/222:43:282
71510rcu_preempt0-21swapper/221:43:202
71510rcu_preempt0-21swapper/221:43:202
71510rcu_preempt0-21swapper/221:43:202
71500rcu_preempt0-21swapper/323:23:383
71500rcu_preempt0-21swapper/323:23:383
71500rcu_preempt0-21swapper/323:23:383
71500rcu_preempt0-21swapper/100:36:361
71500rcu_preempt0-21swapper/100:36:361
71500rcu_preempt0-21swapper/100:36:361
46650470irq/116-QManpo1958-2110:48:553
46650470irq/116-QManpo1958-2110:48:553
71460rcu_preempt20344-21meminfo00:36:380
71460rcu_preempt20344-21meminfo00:36:380
71460rcu_preempt20344-21meminfo00:36:380
71460rcu_preempt0-21swapper/122:31:431
71460rcu_preempt0-21swapper/122:31:431
71460rcu_preempt0-21swapper/019:51:290
71460rcu_preempt0-21swapper/019:51:290
1599460migration/031268-21taskset19:08:430
1599460migration/031268-21taskset19:08:430
111460rcuc/022303-1kworker/0:3H00:21:210
111460rcuc/022303-1kworker/0:3H00:21:210
71450rcu_preempt0-21swapper/300:26:273
71450rcu_preempt0-21swapper/300:26:273
71430rcu_preempt28863-21grep22:01:190
71430rcu_preempt28863-21grep22:01:190
71430rcu_preempt28863-21grep22:01:190
71430rcu_preempt0-21swapper/322:51:383
71430rcu_preempt0-21swapper/322:51:383
71430rcu_preempt0-21swapper/322:51:383
71420rcu_preempt0-21swapper/120:21:331
71420rcu_preempt0-21swapper/120:21:331
71410rcu_preempt0-21swapper/123:26:261
71410rcu_preempt0-21swapper/123:26:261
71410rcu_preempt0-21swapper/022:39:460
71410rcu_preempt0-21swapper/022:39:460
71410rcu_preempt0-21swapper/022:39:460
71410rcu_preempt0-21swapper/021:30:590
71410rcu_preempt0-21swapper/021:30:590
71400rcu_preempt0-21swapper/123:01:081
71400rcu_preempt0-21swapper/123:01:081
71400rcu_preempt0-21swapper/123:01:081
71400rcu_preempt0-21swapper/023:26:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional