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2026-06-26 - 04:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Fri Jun 26, 2026 00:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71650rcu_preempt9875-21ssh21:34:092
71650rcu_preempt9875-21ssh21:34:092
71650rcu_preempt9875-21ssh21:34:092
71530rcu_preempt15919-1kworker/3:2H19:12:263
71530rcu_preempt15919-1kworker/3:2H19:12:263
71500rcu_preempt0-21swapper/300:17:493
71500rcu_preempt0-21swapper/300:17:493
71480rcu_preempt0-21swapper/122:23:501
71480rcu_preempt0-21swapper/122:23:501
71480rcu_preempt0-21swapper/122:23:501
71470rcu_preempt23535-21spawn19:08:581
71470rcu_preempt23535-21spawn19:08:581
46050470irq/122-QManpo23286-2110:48:550
46050470irq/122-QManpo23286-2110:48:550
71420rcu_preempt0-21swapper/120:43:491
71420rcu_preempt0-21swapper/120:43:491
71420rcu_preempt0-21swapper/120:43:491
46450420irq/118-QManpo15323-2110:48:552
46450420irq/118-QManpo15323-2110:48:552
71410rcu_preempt31448-21diskmemload23:38:570
71410rcu_preempt31448-21diskmemload23:38:570
71410rcu_preempt0-21swapper/220:48:552
71410rcu_preempt0-21swapper/220:48:552
71410rcu_preempt0-21swapper/119:28:461
71410rcu_preempt0-21swapper/119:28:461
71410rcu_preempt0-21swapper/119:28:461
71410rcu_preempt0-21swapper/022:47:190
71410rcu_preempt0-21swapper/022:47:190
71410rcu_preempt0-21swapper/022:47:190
71400rcu_preempt1523-21sshd00:24:460
71400rcu_preempt1523-21sshd00:24:460
71400rcu_preempt1523-21sshd00:24:460
71400rcu_preempt0-21swapper/120:57:021
71400rcu_preempt0-21swapper/120:57:021
46050400irq/122-QManpo5165-2110:48:550
46050400irq/122-QManpo5165-2110:48:550
46050400irq/122-QManpo5165-2110:48:550
46050400irq/122-QManpo16674-2110:48:550
46050400irq/122-QManpo16674-2110:48:550
46050400irq/122-QManpo12162-2110:48:550
46050400irq/122-QManpo12162-2110:48:550
46050400irq/122-QManpo12162-2110:48:550
71390rcu_preempt6732-21ssh21:28:463
71390rcu_preempt6644-21latency_hist21:28:401
71390rcu_preempt6644-21latency_hist21:28:401
71390rcu_preempt6644-21latency_hist21:28:401
71390rcu_preempt24366-1kworker/1:0H19:15:221
71390rcu_preempt24366-1kworker/1:0H19:15:221
71390rcu_preempt24366-1kworker/1:0H19:15:221
71390rcu_preempt24366-1kworker/1:0H19:15:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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