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2026-04-15 - 08:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Wed Apr 15, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1328599481cyclictest1959-21runrttasks22:37:381
1328599481cyclictest1959-21runrttasks22:37:381
46050460irq/122-QManpo12773-2110:48:550
46050460irq/122-QManpo12773-2110:48:550
1328599444cyclictest0-21swapper/100:27:421
1328599444cyclictest0-21swapper/100:27:421
1328599442cyclictest31154-21/usr/sbin/munin21:42:431
1328599442cyclictest31154-21/usr/sbin/munin21:42:431
1328599442cyclictest31154-21/usr/sbin/munin21:42:431
1328599442cyclictest0-21swapper/122:30:431
1328599442cyclictest0-21swapper/122:30:431
1328599441cyclictest32616-21sendmail-msp20:27:401
1328599441cyclictest32616-21sendmail-msp20:27:401
71430rcu_preempt0-21swapper/222:05:122
71430rcu_preempt0-21swapper/222:05:122
71430rcu_preempt0-21swapper/222:05:122
1328599433cyclictest540-21diskstats20:22:351
1328599433cyclictest540-21diskstats20:22:351
1328599433cyclictest12940-21meminfo22:07:411
1328599433cyclictest12940-21meminfo22:07:411
1328599433cyclictest12940-21meminfo22:07:411
1328599432cyclictest7816-21ntp_states20:47:461
1328599432cyclictest7816-21ntp_states20:47:461
1328599432cyclictest20993-21/usr/sbin/munin21:22:491
1328599432cyclictest20993-21/usr/sbin/munin21:22:491
1328599432cyclictest20993-21/usr/sbin/munin21:22:491
1328599432cyclictest14544-21irqstats00:07:411
1328599432cyclictest14544-21irqstats00:07:411
1328599432cyclictest14544-21irqstats00:07:411
1328599432cyclictest0-21swapper/100:22:241
1328599432cyclictest0-21swapper/100:22:241
71420rcu_preempt21135-1kworker/1:0H21:29:551
71420rcu_preempt21135-1kworker/1:0H21:29:551
71420rcu_preempt0-21swapper/219:43:442
71420rcu_preempt0-21swapper/219:43:442
1328599424cyclictest0-21swapper/121:52:331
1328599424cyclictest0-21swapper/121:52:331
1328599424cyclictest0-21swapper/121:52:331
1328599423cyclictest0-21swapper/123:24:561
1328599423cyclictest0-21swapper/123:24:561
1328599423cyclictest0-21swapper/123:24:561
1328599422cyclictest7231-21diskstats21:57:351
1328599422cyclictest7231-21diskstats21:57:351
1328599422cyclictest669-21diskstats23:42:351
1328599422cyclictest669-21diskstats23:42:351
1328599422cyclictest11851-21/usr/sbin/munin00:02:421
1328599422cyclictest11851-21/usr/sbin/munin00:02:421
1328599422cyclictest11851-21/usr/sbin/munin00:02:421
1328599422cyclictest0-21swapper/123:02:461
1328599422cyclictest0-21swapper/123:02:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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