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2026-03-13 - 23:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Fri Mar 13, 2026 12:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71680rcu_preempt0-21swapper/011:07:580
71680rcu_preempt0-21swapper/011:07:580
71680rcu_preempt0-21swapper/011:07:580
71630rcu_preempt0-21swapper/010:40:590
71630rcu_preempt0-21swapper/010:40:590
71630rcu_preempt0-21swapper/010:40:590
71630rcu_preempt0-21swapper/010:40:590
71520rcu_preempt0-21swapper/207:42:222
71520rcu_preempt0-21swapper/207:42:222
3197499473cyclictest20340-21munin-run08:26:422
3197499473cyclictest20340-21munin-run08:26:422
71460rcu_preempt0-21swapper/007:57:040
71460rcu_preempt0-21swapper/007:57:040
71460rcu_preempt0-21swapper/007:57:040
3197499464cyclictest0-21swapper/210:11:592
3197499464cyclictest0-21swapper/210:11:592
3197499463cyclictest0-21swapper/210:57:062
3197499463cyclictest0-21swapper/210:57:062
3197499454cyclictest0-21swapper/211:06:542
3197499454cyclictest0-21swapper/211:06:542
3197499454cyclictest0-21swapper/211:06:542
3197499454cyclictest0-21swapper/208:01:542
3197499454cyclictest0-21swapper/208:01:542
3197499451cyclictest6294-21sendmail-msp09:24:452
3197499451cyclictest6294-21sendmail-msp09:24:452
3197499451cyclictest6294-21sendmail-msp09:24:452
3197499451cyclictest28165-21ssh10:00:042
3197499451cyclictest28165-21ssh10:00:042
3197499451cyclictest28165-21ssh10:00:042
3197499451cyclictest1744-21ssh10:11:122
3197499451cyclictest1744-21ssh10:11:122
3197499444cyclictest0-21swapper/211:03:312
3197499444cyclictest0-21swapper/211:03:312
3197499444cyclictest0-21swapper/209:35:302
3197499444cyclictest0-21swapper/209:35:302
3197499444cyclictest0-21swapper/209:35:302
3197499444cyclictest0-21swapper/207:12:042
3197499444cyclictest0-21swapper/207:12:042
46050430irq/122-QManpo0-210
46050430irq/122-QManpo0-210
3197499434cyclictest0-21swapper/209:53:032
3197499434cyclictest0-21swapper/209:53:032
3197499434cyclictest0-21swapper/209:53:032
3197499434cyclictest0-21swapper/207:20:412
3197499434cyclictest0-21swapper/207:20:412
3197499433cyclictest0-21swapper/212:37:362
3197499433cyclictest0-21swapper/212:37:362
3197499433cyclictest0-21swapper/211:22:122
3197499433cyclictest0-21swapper/211:22:122
3197499433cyclictest0-21swapper/211:22:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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