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2026-08-10 - 23:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Mon Aug 10, 2026 12:44:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46050500irq/122-QManpo2602-2110:48:550
46050500irq/122-QManpo2602-2110:48:550
100650460irq/38-i2c-mpc29326-21meminfo08:49:410
100650460irq/38-i2c-mpc29326-21meminfo08:49:410
71410rcu_preempt0-21swapper/207:53:212
71410rcu_preempt0-21swapper/207:53:212
71410rcu_preempt0-21swapper/011:09:590
71410rcu_preempt0-21swapper/011:09:590
71410rcu_preempt0-21swapper/010:59:400
71410rcu_preempt0-21swapper/010:59:400
71410rcu_preempt0-21swapper/010:59:400
46450410irq/118-QManpo0-2110:48:552
46450410irq/118-QManpo0-2110:48:552
1599410migration/018307-21missed_timers08:09:450
1599410migration/018307-21missed_timers08:09:450
71400rcu_preempt14681-21ssh12:25:130
71400rcu_preempt14681-21ssh12:25:130
71400rcu_preempt0-21swapper/012:16:140
71400rcu_preempt0-21swapper/012:16:140
71400rcu_preempt0-21swapper/010:06:390
71400rcu_preempt0-21swapper/010:06:390
71400rcu_preempt0-21swapper/009:24:310
71400rcu_preempt0-21swapper/009:24:310
71400rcu_preempt0-21swapper/008:24:250
71400rcu_preempt0-21swapper/008:24:250
71390rcu_preempt6030-1kworker/1:2H12:12:111
71390rcu_preempt6030-1kworker/1:2H12:12:111
71390rcu_preempt4398-21ssh09:14:510
71390rcu_preempt4398-21ssh09:14:510
71390rcu_preempt0-21swapper/112:20:191
71390rcu_preempt0-21swapper/112:20:191
71390rcu_preempt0-21swapper/010:59:090
71390rcu_preempt0-21swapper/010:59:090
71390rcu_preempt0-21swapper/008:44:240
71390rcu_preempt0-21swapper/008:44:240
46050390irq/122-QManpo19750-2110:48:550
46050390irq/122-QManpo19750-2110:48:550
1599390migration/020551-21latency_hist08:19:260
1599390migration/020551-21latency_hist08:19:260
71380rcu_preempt0-21swapper/112:27:141
71380rcu_preempt0-21swapper/112:27:141
71380rcu_preempt0-21swapper/011:21:010
71380rcu_preempt0-21swapper/011:21:010
71380rcu_preempt0-21swapper/010:35:530
71380rcu_preempt0-21swapper/010:35:530
46250380irq/120-QManpo2609-2110:48:551
46250380irq/120-QManpo2609-2110:48:551
46050380irq/122-QManpo27181-2110:48:550
46050380irq/122-QManpo27181-2110:48:550
46050380irq/122-QManpo12608-2110:48:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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