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2026-08-23 - 07:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Sun Aug 23, 2026 00:44:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71650rcu_preempt0-21swapper/321:30:423
71650rcu_preempt0-21swapper/321:30:423
71620rcu_preempt588-21copy20:14:472
71620rcu_preempt588-21copy20:14:472
71610rcu_preempt0-21swapper/121:22:251
71610rcu_preempt0-21swapper/121:22:251
71580rcu_preempt0-21swapper/219:34:562
71580rcu_preempt0-21swapper/219:34:562
71570rcu_preempt0-21swapper/223:36:562
71570rcu_preempt0-21swapper/223:36:562
16825995711cyclictest2015-21sshd23:37:290
16825995711cyclictest2015-21sshd23:37:290
1682599547cyclictest19648-21ssh23:11:090
1682599547cyclictest19648-21ssh23:11:090
1682599547cyclictest19648-21ssh23:11:090
1682599523cyclictest0-21swapper/023:44:480
1682599523cyclictest0-21swapper/023:44:480
1682599523cyclictest0-21swapper/021:49:000
1682599523cyclictest0-21swapper/021:49:000
16825995217cyclictest31554-21df00:29:490
16825995217cyclictest31554-21df00:29:490
1682599513cyclictest0-21swapper/023:22:200
1682599513cyclictest0-21swapper/023:22:200
1682599513cyclictest0-21swapper/023:22:200
1682599513cyclictest0-21swapper/000:09:570
1682599513cyclictest0-21swapper/000:09:570
1682599512cyclictest2203-21users22:40:050
1682599512cyclictest2203-21users22:40:050
1682599512cyclictest2203-21users22:40:050
1682599512cyclictest16945-21ntp_states19:15:010
1682599512cyclictest15070-21memory21:04:580
1682599512cyclictest15070-21memory21:04:580
1682599512cyclictest0-21swapper/023:53:450
1682599512cyclictest0-21swapper/023:53:450
1682599511cyclictest22169-1kworker/0:0H22:23:450
1682599511cyclictest22169-1kworker/0:0H22:23:450
1682599511cyclictest22169-1kworker/0:0H22:23:450
1682599503cyclictest0-21swapper/020:54:530
1682599503cyclictest0-21swapper/020:54:530
1682599502cyclictest8129-21meminfo20:39:560
1682599502cyclictest8129-21meminfo20:39:560
1682599497cyclictest13386-21ssh22:04:110
1682599497cyclictest13386-21ssh22:04:110
1682599497cyclictest13386-21ssh22:04:110
1682599493cyclictest0-21swapper/023:05:000
1682599493cyclictest0-21swapper/023:05:000
1682599493cyclictest0-21swapper/022:09:540
1682599493cyclictest0-21swapper/022:09:540
1682599493cyclictest0-21swapper/021:50:030
1682599493cyclictest0-21swapper/021:50:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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