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2026-05-26 - 15:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Tue May 26, 2026 12:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1599550migration/0357-21taskset07:13:090
1599550migration/0357-21taskset07:13:090
71530rcu_preempt0-21swapper/312:17:283
71530rcu_preempt0-21swapper/312:17:283
71530rcu_preempt0-21swapper/312:17:283
71460rcu_preempt0-21swapper/008:48:080
71460rcu_preempt0-21swapper/008:48:080
71460rcu_preempt0-21swapper/008:48:080
71450rcu_preempt0-21swapper/012:18:140
71450rcu_preempt0-21swapper/012:18:140
99750440irq/38-i2c-mpc12316-21users10:33:320
99750440irq/38-i2c-mpc12316-21users10:33:320
99750440irq/38-i2c-mpc12316-21users10:33:320
71440rcu_preempt0-21swapper/010:26:400
71440rcu_preempt0-21swapper/010:26:400
46050440irq/122-QManpo3099-2110:48:550
46050440irq/122-QManpo3099-2110:48:550
46050440irq/122-QManpo3099-2110:48:550
71420rcu_preempt0-21swapper/008:48:260
71420rcu_preempt0-21swapper/008:48:260
71410rcu_preempt0-21swapper/109:23:231
71410rcu_preempt0-21swapper/109:23:231
71410rcu_preempt0-21swapper/109:23:231
71410rcu_preempt0-21swapper/009:13:350
71410rcu_preempt0-21swapper/009:13:350
46250410irq/120-QManpo31615-2110:48:551
46250410irq/120-QManpo31615-2110:48:551
46050410irq/122-QManpo0-210
46050410irq/122-QManpo0-210
100650410irq/38-i2c-mpc25726-21meminfo09:58:233
100650410irq/38-i2c-mpc25726-21meminfo09:58:233
71400rcu_preempt29865-21df11:08:191
71400rcu_preempt29865-21df11:08:191
71400rcu_preempt29865-21df11:08:191
71400rcu_preempt0-21swapper/111:06:591
71400rcu_preempt0-21swapper/111:06:591
71400rcu_preempt0-21swapper/111:06:591
71400rcu_preempt0-21swapper/110:18:141
71400rcu_preempt0-21swapper/110:18:141
71400rcu_preempt0-21swapper/110:18:141
71400rcu_preempt0-21swapper/012:28:040
71400rcu_preempt0-21swapper/012:28:040
46450400irq/118-QManpo32688-2110:48:552
46450400irq/118-QManpo32688-2110:48:552
46050400irq/122-QManpo24577-2110:48:550
46050400irq/122-QManpo24577-2110:48:550
46050400irq/122-QManpo24577-2110:48:550
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
46050400irq/122-QManpo0-210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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