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2025-12-30 - 22:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Tue Dec 30, 2025 12:43:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71630rcu_preempt0-21swapper/111:59:081
71630rcu_preempt0-21swapper/111:59:081
71630rcu_preempt0-21swapper/111:59:081
71520rcu_preempt0-21swapper/310:32:553
71520rcu_preempt0-21swapper/310:32:553
71520rcu_preempt0-21swapper/310:32:553
71520rcu_preempt0-21swapper/010:15:250
71520rcu_preempt0-21swapper/010:15:250
71450rcu_preempt0-21swapper/209:43:212
71450rcu_preempt0-21swapper/209:43:212
71440rcu_preempt3102-21taskset08:20:231
71440rcu_preempt3102-21taskset08:20:231
16078994418cyclictest0-21swapper/210:00:352
16078994418cyclictest0-21swapper/210:00:352
46050430irq/122-QManpo3102-210
46050430irq/122-QManpo3102-210
1607899434cyclictest0-21swapper/212:05:592
1607899434cyclictest0-21swapper/212:05:592
1607899434cyclictest0-21swapper/212:05:592
1607899432cyclictest1959-21runrttasks11:27:512
1607899432cyclictest1959-21runrttasks11:27:512
1607899432cyclictest14124-21ssh10:57:122
1607899432cyclictest14124-21ssh10:57:122
1607899432cyclictest14124-21ssh10:57:122
1607899431cyclictest0-21swapper/210:42:522
1607899431cyclictest0-21swapper/210:42:522
71420rcu_preempt2385-21irqstats09:40:450
71420rcu_preempt2385-21irqstats09:40:450
71420rcu_preempt0-21swapper/111:36:561
71420rcu_preempt0-21swapper/111:36:561
71420rcu_preempt0-21swapper/111:36:561
1607899423cyclictest0-21swapper/209:35:352
1607899423cyclictest0-21swapper/209:35:352
1607899423cyclictest0-21swapper/209:08:402
1607899423cyclictest0-21swapper/209:08:402
1607899423cyclictest0-21swapper/209:08:402
1607899423cyclictest0-21swapper/208:40:432
1607899423cyclictest0-21swapper/208:40:432
1607899423cyclictest0-21swapper/208:15:222
1607899423cyclictest0-21swapper/208:15:222
1607899422cyclictest31158-21memory10:30:442
1607899422cyclictest31158-21memory10:30:442
1607899422cyclictest31158-21memory10:30:442
16078994217cyclictest0-21swapper/209:25:542
16078994217cyclictest0-21swapper/209:25:542
71410rcu_preempt27134-21head12:15:511
71410rcu_preempt27134-21head12:15:511
71410rcu_preempt27134-21head12:15:511
1607899416cyclictest0-21swapper/211:38:082
1607899416cyclictest0-21swapper/211:38:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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