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2025-09-14 - 00:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack4slot4.osadl.org (updated Sat Sep 13, 2025 12:54:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71680rcu_preempt0-21swapper/309:54:003
71680rcu_preempt0-21swapper/309:54:003
71580rcu_preempt0-21swapper/010:57:570
71580rcu_preempt0-21swapper/010:57:570
71580rcu_preempt0-21swapper/010:57:570
71530rcu_preempt30983-21ssh11:21:423
71530rcu_preempt30983-21ssh11:21:423
71530rcu_preempt30983-21ssh11:21:423
71510rcu_preempt0-21swapper/110:02:181
71510rcu_preempt0-21swapper/110:02:181
71460rcu_preempt0-21swapper/011:51:220
71460rcu_preempt0-21swapper/011:51:220
46050450irq/122-QManpo24855-2109:24:360
46050450irq/122-QManpo24855-2109:24:360
9707994216cyclictest0-21swapper/012:31:300
9707994216cyclictest0-21swapper/012:31:300
71410rcu_preempt10406-21kworker/2:010:51:542
71410rcu_preempt10406-21kworker/2:010:51:542
71410rcu_preempt0-21swapper/012:12:130
71410rcu_preempt0-21swapper/012:12:130
71410rcu_preempt0-21swapper/012:12:130
71410rcu_preempt0-21swapper/011:08:080
71410rcu_preempt0-21swapper/011:08:080
71400rcu_preempt0-21swapper/310:11:523
71400rcu_preempt0-21swapper/310:11:523
71400rcu_preempt0-21swapper/310:11:523
71400rcu_preempt0-21swapper/211:16:312
71400rcu_preempt0-21swapper/211:16:312
71400rcu_preempt0-21swapper/210:08:462
71400rcu_preempt0-21swapper/210:08:462
71400rcu_preempt0-21swapper/111:21:221
71400rcu_preempt0-21swapper/111:21:221
71400rcu_preempt0-21swapper/011:17:350
71400rcu_preempt0-21swapper/011:17:350
71400rcu_preempt0-21swapper/010:32:290
71400rcu_preempt0-21swapper/010:32:290
46250390irq/120-QManpo0-2109:24:361
46250390irq/120-QManpo0-2109:24:361
71380rcu_preempt0-21swapper/012:24:050
71380rcu_preempt0-21swapper/012:24:050
71380rcu_preempt0-21swapper/012:17:260
71380rcu_preempt0-21swapper/012:17:260
71380rcu_preempt0-21swapper/010:56:210
71380rcu_preempt0-21swapper/010:56:210
71380rcu_preempt0-21swapper/010:40:210
71380rcu_preempt0-21swapper/010:40:210
71380rcu_preempt0-21swapper/010:40:210
71380rcu_preempt0-21swapper/010:07:450
71380rcu_preempt0-21swapper/010:07:450
71380rcu_preempt0-21swapper/008:11:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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