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2026-02-07 - 01:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot6.osadl.org (updated Fri Feb 06, 2026 12:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26775521130,109pltrace0-21swapper/507:07:195
29563521100,106pltrace0-21swapper/107:10:011
26775521020,88pltrace0-21swapper/607:05:146
2959428243,18sleep40-21swapper/407:09:024
2962126450,10sleep20-21swapper/207:09:242
2940926349,10sleep30-21swapper/307:06:443
2947826046,10sleep70-21swapper/707:07:447
2725125945,10sleep00-21swapper/007:05:050
2189352470,0pltrace0-21swapper/711:48:087
164002330,1sleep3441rcuc/310:35:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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