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2025-08-21 - 21:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot6.osadl.org (updated Thu Aug 21, 2025 12:44:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11749521100,106pltrace0-21swapper/207:05:172
11749521070,103pltrace0-21swapper/707:05:227
11749521030,94pltrace0-21swapper/307:05:283
31621521010,0pltrace0-21swapper/509:32:175
31132960,1sleep10-21swapper/111:35:151
1174952830,75pltrace0-21swapper/607:05:206
1439927042,10sleep40-21swapper/407:05:344
1458726450,10sleep10-21swapper/107:07:551
2771552620,0pltrace0-21swapper/008:27:170
1441826248,10sleep50-21swapper/507:05:525
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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