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2026-01-23 - 04:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot6.osadl.org (updated Fri Jan 23, 2026 00:44:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7774521450,136pltrace0-21swapper/519:06:095
7774521260,110pltrace0-21swapper/119:05:221
7774521240,115pltrace0-21swapper/319:05:033
7774521230,114pltrace0-21swapper/619:05:126
7774521210,67pltrace0-21swapper/719:05:117
7774521080,96pltrace0-21swapper/219:05:182
2479152970,1pltrace0-21swapper/421:29:074
116502940,0sleep50-21swapper/520:05:185
1044826642,20sleep00-21swapper/019:07:460
1028125945,10sleep40-21swapper/419:05:254
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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