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2025-06-29 - 01:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack4slot6.osadl.org (updated Sat Jun 28, 2025 12:44:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1713352980,95pltrace0-21swapper/307:10:013
1434552900,85pltrace0-21swapper/507:05:215
1713352890,56pltrace0-21swapper/707:08:397
1434552880,80pltrace0-21swapper/107:05:181
1708628549,10sleep20-21swapper/207:07:242
1705427850,10sleep60-21swapper/607:06:566
1700126147,10sleep00-21swapper/007:06:110
1714225743,10sleep40-21swapper/407:07:504
277652280,0sleep50-21swapper/509:20:195
563552270,5pltrace0-21swapper/710:40:157
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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