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2024-04-20 - 15:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sat Apr 20, 2024 12:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
508121280,4sleep33130199cyclictest11:53:303
1093321280,2sleep20-21swapper/211:54:122
1815721270,4sleep33130199cyclictest11:20:083
822621250,3sleep23129599cyclictest09:55:462
31093210035,49sleep10-21swapper/107:09:551
315212980,2sleep20-21swapper/209:31:112
36142970,3sleep23610-21sshd10:07:012
230632900,2sleep123065-21id11:00:501
13162890,2sleep21310-21sshd12:16:062
94052860,4sleep20-21swapper/209:36:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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