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2025-12-31 - 14:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Wed Dec 31, 2025 12:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2230621360,0sleep322307-21sshd09:29:133
3216210434,40sleep30-21swapper/307:09:283
324829925,61sleep10-21swapper/107:09:501
17502830,0sleep00-21swapper/011:59:480
292872820,0sleep00-21swapper/010:12:350
25972820,2sleep32439-21runrttasks10:46:383
238612820,2sleep30-21swapper/311:14:593
117342780,2sleep22439-21runrttasks11:10:422
204922720,2sleep30-21swapper/310:41:553
324982700,1sleep30-21swapper/311:28:023
304826433,12sleep20-21swapper/207:07:312
243172620,3sleep1351899cyclictest11:35:341
315825833,13sleep00-21swapper/007:08:410
154582340,2sleep30-21swapper/311:33:033
317812330,0sleep00-21swapper/009:21:500
55682312,27sleep1137550irq/27-eth012:00:311
230342280,4sleep1351899cyclictest11:45:231
4822270,2sleep12439-21runrttasks09:11:571
158882270,2sleep20-21swapper/209:57:302
158882270,2sleep20-21swapper/209:57:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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