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2026-05-09 - 17:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat May 09, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1513921370,0sleep215141-21id11:33:462
2187521150,2sleep30-21swapper/311:56:313
18213210330,69sleep30-21swapper/307:09:053
318462980,1sleep031844-21bash10:01:270
178752980,1sleep018525-21cyclictest10:28:490
319592940,2sleep10-21swapper/110:26:241
10022880,2sleep30-21swapper/311:39:243
38852870,2sleep22024-21nfsd10:16:032
90512860,2sleep10-21swapper/112:13:401
307332850,4sleep31854699cyclictest11:07:143
240162850,6sleep30-21swapper/309:18:223
1827728533,48sleep10-21swapper/107:09:511
309432840,3sleep01853399cyclictest12:30:380
303822840,4sleep31854699cyclictest12:00:523
13902830,2sleep10-21swapper/110:52:291
99612820,1sleep00-21swapper/012:13:470
139102820,2sleep20-21swapper/211:01:202
248132800,2sleep20-21swapper/209:56:442
157862800,1sleep315751-21sshd09:45:113
212562790,3sleep20-21swapper/210:03:502
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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