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2026-04-15 - 14:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Wed Apr 15, 2026 12:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
925721340,0sleep39258-21sshd10:54:203
925721340,0sleep39258-21sshd10:54:203
355321330,1sleep03-21ksoftirqd/011:25:190
150121200,3sleep22944999cyclictest09:36:372
2939821180,0sleep00-21swapper/011:03:190
2726221120,3sleep22944999cyclictest11:57:112
245562910,0sleep00-21swapper/011:09:440
36582880,2sleep23659-21sshd11:00:282
105862880,2sleep30-21swapper/312:06:293
2909528734,49sleep10-21swapper/107:08:491
66412830,2sleep30-21swapper/310:31:003
58822830,2sleep10-21swapper/110:53:581
58822830,2sleep10-21swapper/110:53:571
2894328332,47sleep30-21swapper/307:07:063
319532820,3sleep10-21swapper/109:32:231
327102800,2sleep30-21swapper/311:31:553
267842800,2sleep326785-21sshd11:20:203
99362790,1sleep09931-21sshd09:51:490
92182780,3sleep10-21swapper/111:58:461
266022780,1sleep20-21swapper/212:15:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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