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2025-12-12 - 14:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Fri Dec 12, 2025 00:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2630021640,3sleep01262799cyclictest23:34:120
168221550,3sleep11262899cyclictest22:34:491
3004821500,0sleep00-21swapper/021:18:490
2964921370,2sleep30-21swapper/323:50:143
3002421210,2sleep20-21swapper/223:56:262
2822021200,1sleep11262899cyclictest23:18:301
1641321180,1sleep10-21swapper/123:55:131
178921170,0sleep21785-21rm23:22:152
97521160,1sleep21262999cyclictest23:03:042
2882321050,2sleep11262899cyclictest22:43:471
123452960,2sleep312344-21sshd00:23:573
67642950,2sleep30-21swapper/300:13:233
39832940,0sleep00-21swapper/022:38:090
1232329433,48sleep30-21swapper/319:09:233
84602930,10sleep1135650irq/27-eth021:51:041
1232129233,47sleep10-21swapper/119:09:211
305892910,1sleep330587-21sshd23:09:143
128012910,3sleep312787-21sshd23:35:553
57392900,4sleep31263099cyclictest00:03:373
311812890,3sleep10-21swapper/100:15:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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