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2025-12-05 - 13:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Fri Dec 05, 2025 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2278221680,2sleep01300599cyclictest22:30:390
188221510,3sleep21301399cyclictest22:00:482
2846521500,1sleep30-21swapper/323:50:103
1694521320,2sleep20-21swapper/200:31:582
992921290,1sleep10-21swapper/100:17:111
1636121280,0sleep00-21swapper/023:52:050
1361721140,2sleep013605-21sshd00:14:200
478221100,0sleep00-21swapper/023:09:550
2763921020,2sleep20-21swapper/223:56:152
232072970,1sleep223203-21cp00:25:332
188652970,1sleep03-21ksoftirqd/022:55:200
62582890,3sleep10-21swapper/122:54:091
301022890,2sleep130098-21sshd23:43:591
21172890,2sleep12113-21bash21:33:571
175172890,2sleep20-21swapper/222:48:532
175172890,1sleep21301399cyclictest00:35:262
190752870,2sleep119072-21sshd22:36:341
1269428733,50sleep10-21swapper/119:09:141
1269128734,49sleep30-21swapper/319:09:113
112142870,2sleep30-21swapper/323:10:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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