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2026-07-19 - 02:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Jul 19, 2026 00:44:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3237121350,0sleep232372-21sshd00:18:282
567521340,1sleep15674-21sshd22:43:441
801329322,43sleep30-21swapper/319:07:223
189692910,1sleep20-21swapper/221:54:402
178942900,3sleep30-21swapper/321:25:483
805028934,51sleep10-21swapper/119:07:491
202652890,0sleep00-21swapper/021:47:250
15532860,2sleep11545-21bash22:11:021
115352860,2sleep111533-21sshd21:43:011
85812850,0sleep00-21swapper/023:17:300
96332830,0sleep00-21swapper/000:08:040
38892820,4sleep2848499cyclictest21:17:292
141392810,1sleep214085-21sshd22:33:512
116022810,2sleep10-21swapper/122:30:021
9452800,1sleep20-21swapper/200:26:162
113802800,0sleep00-21swapper/022:15:350
109042800,2sleep20-21swapper/223:42:452
77542790,3sleep3848599cyclictest23:53:073
102222790,2sleep30-21swapper/322:12:013
74962780,2sleep10-21swapper/100:30:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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