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2026-08-02 - 06:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Aug 02, 2026 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1429521220,0sleep00-21swapper/000:33:080
377121150,1sleep10-21swapper/100:14:411
2560521150,3sleep1753499cyclictest23:15:021
209842990,3sleep32023-21nfsd21:15:213
206622930,2sleep320652-21sshd23:20:173
190822930,2sleep10-21swapper/121:23:401
268112910,2sleep20-21swapper/223:24:042
122482900,4sleep3754499cyclictest21:20:133
87312890,3sleep20-21swapper/223:51:452
137972890,2sleep00-21swapper/023:31:320
725028828,48sleep30-21swapper/319:09:293
41222870,0sleep2754099cyclictest23:39:392
33052860,2sleep20-21swapper/200:08:492
705428532,44sleep10-21swapper/119:07:031
264142850,1sleep026404-21sshd21:15:460
117422850,2sleep211740-21sshd23:40:152
104632850,2sleep22024-21nfsd23:34:302
59842840,2sleep35978-21sshd21:34:203
33572840,1sleep33358-21sshd00:26:093
285922840,3sleep30-21swapper/321:56:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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