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2026-07-12 - 00:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat Jul 11, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2478821280,1sleep224791-21bash11:59:372
2000821150,2sleep30-21swapper/311:30:063
924529632,44sleep10-21swapper/107:07:581
195752940,3sleep20-21swapper/209:22:332
132552900,1sleep013252-21bash09:29:150
324252870,2sleep20-21swapper/211:53:202
106222860,1sleep10-21swapper/109:47:231
63652840,0sleep00-21swapper/010:19:210
239212840,5sleep10-21swapper/112:03:001
10102840,2sleep11008-21bash12:37:191
202702830,2sleep10-21swapper/112:28:421
914728133,44sleep30-21swapper/307:06:433
182782810,2sleep20-21swapper/212:28:262
290072790,4sleep3967299cyclictest09:27:103
249112790,1sleep30-21swapper/309:38:123
42382780,2sleep24235-21bash12:30:222
291682770,1sleep00-21swapper/009:56:160
129902770,2sleep312975-21sshd11:17:343
316382760,1sleep331639-21sshd10:54:143
235352760,2sleep123534-21bash10:13:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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