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2026-07-05 - 00:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat Jul 04, 2026 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251521340,3sleep0876799cyclictest11:20:440
1989421330,3sleep0876799cyclictest09:33:320
2682721200,0sleep00-21swapper/009:59:120
8288210832,47sleep30-21swapper/307:07:113
8291210132,40sleep10-21swapper/107:07:131
60572970,1sleep00-21swapper/011:39:020
289282920,2sleep10-21swapper/111:16:121
201472910,1sleep00-21swapper/011:29:580
140922900,1sleep10-21swapper/109:50:361
34852890,1sleep30-21swapper/309:38:403
325232880,0sleep30-21swapper/311:38:183
30282880,1sleep03031-21awk10:15:190
108152870,1sleep02512-21runrttasks12:16:250
312052840,1sleep031197-21sshd12:22:420
88762830,2sleep12024-21nfsd09:11:051
308562830,1sleep10-21swapper/109:49:041
263182810,1sleep20-21swapper/209:45:042
27372800,2sleep00-21swapper/010:48:180
19162790,2sleep30-21swapper/310:15:153
59362780,2sleep10-21swapper/111:10:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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