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2026-08-23 - 07:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Aug 23, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2939221380,1sleep00-21swapper/022:07:200
1916221310,1sleep00-21swapper/000:18:010
220321200,2sleep10-21swapper/100:10:411
1461021200,1sleep30-21swapper/321:54:493
2213621170,0sleep00-21swapper/021:12:090
1141821140,2sleep20-21swapper/221:22:372
137402980,1sleep10-21swapper/122:08:501
313522960,2sleep20-21swapper/222:25:092
287712940,1sleep00-21swapper/021:30:010
138232940,2sleep20-21swapper/200:11:462
297532920,1sleep229739-21sshd21:50:232
82222910,2sleep10-21swapper/122:25:521
210682910,4sleep30-21swapper/323:14:043
658429032,54sleep10-21swapper/119:08:471
169062880,3sleep116902-21sshd23:25:451
124922880,1sleep32024-21nfsd23:54:163
164422870,1sleep30-21swapper/321:49:193
120552870,2sleep30-21swapper/322:41:023
77722860,2sleep12024-21nfsd23:01:111
65182850,1sleep10-21swapper/100:19:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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