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2026-03-25 - 07:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Wed Mar 25, 2026 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2262121430,0sleep022620-21sshd00:10:450
1426721380,3sleep12547399cyclictest23:48:461
1247421210,1sleep22547499cyclictest21:27:212
1550421190,2sleep30-21swapper/300:13:403
1485121030,2sleep10-21swapper/123:38:111
25200210232,40sleep10-21swapper/119:09:501
131822990,1sleep02024-21nfsd21:13:370
78162980,0sleep00-21swapper/022:57:310
37432940,1sleep30-21swapper/322:46:243
157702920,1sleep30-21swapper/300:24:433
32242900,3sleep10-21swapper/123:16:031
247962880,3sleep20-21swapper/222:30:042
244132870,3sleep32547599cyclictest23:39:233
128342870,1sleep30-21swapper/319:50:213
291882860,2sleep129186-21sshd21:11:331
84342850,1sleep08-21rcu_preempt22:06:020
314272850,0sleep00-21swapper/021:19:140
281962840,2sleep228178-21sshd21:22:122
261122840,1sleep226116-21cpuspeed_turbos21:15:112
2496028332,47sleep30-21swapper/319:06:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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