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2026-09-13 - 10:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Sep 13, 2026 00:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184521280,0sleep00-21swapper/021:14:390
2940021260,2sleep329398-21sshd00:07:413
956721250,3sleep19560-21sshd21:29:511
1076021180,1sleep20-21swapper/221:50:372
1076021180,1sleep20-21swapper/221:50:362
23730210932,73sleep10-21swapper/119:08:201
23840210732,46sleep30-21swapper/319:09:433
75621010,1sleep00-21swapper/022:40:000
113482950,1sleep10-21swapper/123:07:221
40652910,3sleep14064-21sshd21:37:571
226102910,5sleep20-21swapper/200:07:032
145262900,1sleep00-21swapper/022:00:110
231582890,2sleep323157-21bash23:46:493
158512890,2sleep115853-21timerandwakeup20:00:201
147692890,2sleep014768-21sshd23:28:210
12272890,0sleep11223-21sshd22:54:401
119172880,3sleep20-21swapper/221:38:412
102892870,2sleep32024-21nfsd23:07:153
49162860,1sleep04911-21sshd23:48:060
170012860,1sleep016997-21sshd22:18:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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