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2025-12-27 - 15:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat Dec 27, 2025 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2041129534,57sleep30-21swapper/307:07:463
2022929333,56sleep10-21swapper/107:05:281
3422840,1sleep00-21swapper/011:29:130
200622840,2sleep20-21swapper/209:52:422
51522770,0sleep00-21swapper/011:30:220
2057027733,12sleep20-21swapper/207:09:462
205952740,2sleep20-21swapper/210:44:002
280552720,1sleep10-21swapper/110:15:211
252532710,5sleep12084999cyclictest12:29:411
112602700,1sleep10-21swapper/109:30:061
269802600,4sleep22085099cyclictest11:16:402
2037925633,11sleep00-21swapper/007:07:240
186452300,3sleep12439-21runrttasks11:14:201
147892270,25sleep2137550irq/27-eth012:25:492
144592250,3sleep22085099cyclictest12:15:192
151672240,1sleep32439-21runrttasks10:31:473
231412210,1sleep12439-21runrttasks07:15:131
2084899210,15cyclictest0-21swapper/011:16:270
99172200,18sleep2137550irq/27-eth011:32:012
20850992010,7cyclictest0-21swapper/209:40:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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