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2026-06-13 - 21:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat Jun 13, 2026 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73221240,3sleep22051999cyclictest11:40:492
2225021220,3sleep22051999cyclictest09:18:032
2016821190,2sleep120166-21sshd10:15:221
2926421120,1sleep20-21swapper/212:36:162
83482890,2sleep38342-21sshd09:59:443
64442880,3sleep20-21swapper/211:45:472
143142870,0sleep00-21swapper/012:16:060
114462840,3sleep311441-21sshd09:34:393
1990228234,44sleep10-21swapper/107:05:261
1997428133,44sleep30-21swapper/307:06:203
316872800,3sleep331689-21id09:54:593
281412780,0sleep028143-21grep10:35:230
36672750,0sleep00-21swapper/012:03:120
215972750,3sleep321594-21sshd11:00:153
176092750,2sleep30-21swapper/310:07:503
71862740,2sleep20-21swapper/210:32:572
230562730,4sleep12051399cyclictest10:41:501
100442710,1sleep210043-21sshd12:15:362
226842650,3sleep12051399cyclictest12:13:351
37552620,3sleep32052599cyclictest10:46:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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