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2026-09-06 - 10:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Sep 06, 2026 00:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
209221460,2sleep12512-21runrttasks23:36:591
2582021430,2sleep325819-21bash21:10:053
2505221430,0sleep025051-21sshd00:05:000
2505221430,0sleep025051-21sshd00:05:000
253321390,3sleep0269399cyclictest22:06:520
1338321370,0sleep213384-21bash21:56:122
463121360,4sleep0269399cyclictest21:40:440
1559021350,3sleep0269399cyclictest23:32:180
929221310,0sleep19294-21id00:26:411
2933821310,4sleep2270299cyclictest22:40:492
2145210232,42sleep30-21swapper/319:06:213
179021020,2sleep20-21swapper/221:13:362
68702980,3sleep3270599cyclictest22:53:333
210672960,2sleep120927-21sshd22:05:371
163952960,2sleep316397-21id00:33:083
326112930,1sleep10-21swapper/122:49:541
235129333,40sleep10-21swapper/119:08:391
231412930,1sleep30-21swapper/322:00:143
60072920,2sleep35970-21sshd21:58:393
310922920,5sleep00-21swapper/023:59:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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