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2026-08-09 - 06:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Aug 09, 2026 00:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
97021260,3sleep0494699cyclictest23:24:580
3268221240,2sleep3494999cyclictest22:25:493
1179221220,4sleep3494999cyclictest00:34:063
4515210432,44sleep30-21swapper/319:07:493
904321030,2sleep20-21swapper/223:55:102
187632990,1sleep018753-21sshd00:04:540
323652960,2sleep20-21swapper/222:23:042
126052930,1sleep00-21swapper/021:22:500
306752910,0sleep00-21swapper/022:25:380
4042900,2sleep22023-21nfsd21:16:032
97952880,1sleep09791-21sshd21:14:090
256952880,2sleep20-21swapper/222:25:172
43852860,2sleep10-21swapper/122:55:301
283792860,1sleep028373-21sshd21:44:500
464128432,48sleep10-21swapper/119:09:221
254242840,1sleep025420-21sshd22:05:060
208492830,1sleep30-21swapper/323:47:173
208492830,1sleep30-21swapper/323:47:173
194292830,2sleep30-21swapper/322:07:303
118422830,1sleep011840-21sshd00:36:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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