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2026-01-08 - 19:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Thu Jan 08, 2026 12:44:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
883821270,4sleep2812999cyclictest10:28:172
7705210433,40sleep30-21swapper/307:07:453
787029234,54sleep10-21swapper/107:09:481
245912920,0sleep00-21swapper/010:40:540
273692890,2sleep20-21swapper/212:25:152
224122870,0sleep00-21swapper/011:27:180
168402850,2sleep30-21swapper/310:19:253
131662830,2sleep30-21swapper/311:15:223
210302790,2sleep11883-21nfsd09:13:471
242632770,2sleep10-21swapper/111:22:261
304152760,2sleep30-21swapper/311:33:503
269772750,1sleep10-21swapper/111:54:031
324522740,1sleep332454-21bash12:36:253
28312720,1sleep02829-21bash10:22:100
202392690,5sleep3813499cyclictest12:13:463
760526836,11sleep20-21swapper/207:06:272
224632680,2sleep122462-21sshd10:10:051
256222670,0sleep00-21swapper/010:30:480
161882640,4sleep2812999cyclictest10:39:472
105182630,0sleep00-21swapper/010:02:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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