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2026-05-23 - 18:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat May 23, 2026 12:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3172621370,1sleep02320699cyclictest09:22:000
759421320,0sleep37405-21sshd09:40:193
2766121280,2sleep30-21swapper/309:28:373
1118221240,2sleep211177-21sshd09:13:092
2726721220,3sleep02320699cyclictest10:32:580
22860210432,43sleep30-21swapper/307:08:593
314602900,3sleep131458-21sshd12:00:241
2276428933,44sleep10-21swapper/107:07:451
319222880,2sleep20-21swapper/212:33:182
312522880,2sleep10-21swapper/112:22:431
226972870,2sleep30-21swapper/309:45:493
191412870,3sleep20-21swapper/212:39:322
208452850,0sleep00-21swapper/012:39:460
310532830,0sleep041ktimersoftd/011:49:160
169792830,2sleep30-21swapper/309:13:473
218972820,0sleep221895-21sshd10:14:332
191872810,2sleep30-21swapper/310:57:303
191872810,2sleep30-21swapper/310:57:293
117792810,4sleep22320899cyclictest12:16:312
5602800,0sleep041ktimersoftd/012:07:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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