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2026-09-20 - 19:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Sep 20, 2026 12:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2216521400,1sleep222164-21sshd09:50:382
2854721280,2sleep228546-21sshd11:35:552
866021260,4sleep22223899cyclictest10:58:402
2575621230,3sleep12223799cyclictest09:36:441
1856021220,2sleep118540-21sshd11:46:371
2157521200,3sleep12223799cyclictest10:51:021
21794210632,55sleep10-21swapper/107:07:511
224572990,1sleep20-21swapper/209:45:102
168362970,1sleep32223999cyclictest09:27:203
2185529333,48sleep30-21swapper/307:08:373
79382910,2sleep12512-21runrttasks11:22:201
117652900,1sleep00-21swapper/009:29:450
244452890,2sleep224447-21missed_timers12:10:222
302232880,1sleep030212-21sshd10:17:020
195012880,3sleep119498-21bash10:30:381
22062870,3sleep20-21swapper/209:37:362
33732850,1sleep00-21swapper/010:03:110
232642850,0sleep00-21swapper/010:10:450
232642850,0sleep00-21swapper/010:10:450
219142850,5sleep22223899cyclictest10:39:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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