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2024-04-19 - 12:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Fri Apr 19, 2024 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2813721200,3sleep21474899cyclictest23:10:542
3254221190,4sleep21474899cyclictest00:35:302
2600621130,2sleep20-21swapper/221:12:272
1417429835,59sleep30-21swapper/319:05:283
5412960,2sleep20-21swapper/221:55:282
222802960,1sleep10-21swapper/122:41:231
101612910,2sleep210150-21sshd22:14:462
1435629033,45sleep10-21swapper/119:07:351
269942890,1sleep30-21swapper/322:34:443
227212890,3sleep222722-21sshd21:50:182
197802880,2sleep31877-21nfsd22:15:453
197802880,2sleep31877-21nfsd22:15:443
253182870,1sleep025309-21sshd00:23:260
231662870,2sleep20-21swapper/222:16:082
231662870,2sleep20-21swapper/222:16:082
163262870,2sleep30-21swapper/321:15:093
132282860,2sleep113225-21sshd00:29:361
209532850,0sleep00-21swapper/022:08:430
35322840,2sleep10-21swapper/123:26:151
59892830,3sleep15987-21sshd21:25:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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