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2026-08-16 - 06:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Aug 16, 2026 00:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1563521440,3sleep2440799cyclictest00:10:572
392021380,1sleep00-21swapper/023:52:440
847221320,0sleep38454-21sshd21:14:253
1228521290,3sleep0440599cyclictest00:19:220
2076321240,4sleep1440699cyclictest22:38:511
3911210432,44sleep30-21swapper/319:07:013
50982990,2sleep20-21swapper/221:30:592
60342950,0sleep00-21swapper/023:06:510
217242920,1sleep30-21swapper/323:48:343
195562920,4sleep2440799cyclictest21:43:532
42522880,3sleep34251-21sshd23:29:423
381928824,52sleep10-21swapper/119:06:021
263432880,2sleep126342-21bash00:23:301
263432880,2sleep126342-21bash00:23:301
205752880,3sleep10-21swapper/123:16:381
31622870,2sleep23155-21bash22:10:392
302182870,2sleep30-21swapper/321:50:283
220572870,3sleep00-21swapper/022:33:050
38122850,2sleep23795-21sshd23:09:332
309332850,2sleep030923-21sshd22:51:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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