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2025-11-21 - 11:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Fri Nov 21, 2025 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1153221610,4sleep3725299cyclictest23:05:273
2313421450,0sleep123129-21cp22:41:161
1582021440,1sleep015817-21sshd22:56:190
2822121390,1sleep20-21swapper/223:26:062
166421350,1sleep01655-21sshd23:39:270
2022321310,4sleep2725199cyclictest22:25:072
1427821300,1sleep314279-21sshd23:50:003
3203921200,1sleep30-21swapper/322:00:383
2196721140,4sleep20-21swapper/200:16:252
2498821110,0sleep124989-21sshd21:47:141
6986210733,44sleep10-21swapper/119:09:551
114242930,1sleep10-21swapper/100:38:321
46582920,1sleep30-21swapper/321:42:023
58742900,2sleep30-21swapper/321:55:013
51052890,2sleep05104-21sshd21:26:080
51052890,2sleep05104-21sshd21:26:080
43272890,1sleep01848-21nfsd00:31:060
285822880,2sleep041ktimersoftd/021:19:030
21762870,2sleep30-21swapper/323:23:393
73062860,1sleep30-21swapper/321:26:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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