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2026-01-11 - 23:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Jan 11, 2026 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2259321300,1sleep20-21swapper/209:37:152
1909721120,1sleep1139099cyclictest10:32:171
237012960,3sleep10-21swapper/110:46:391
205832920,1sleep0419-21jbd2/dm-0-812:35:150
75429133,54sleep30-21swapper/307:05:333
116222890,1sleep30-21swapper/310:17:363
170032860,3sleep20-21swapper/209:26:172
95628533,48sleep10-21swapper/107:08:081
183662850,1sleep01993-21sshd11:14:080
43332820,1sleep04331-21sshd12:33:290
230952820,0sleep00-21swapper/012:00:110
281662810,2sleep228161-21sshd11:50:122
198612810,3sleep30-21swapper/312:20:593
198612810,3sleep30-21swapper/312:20:593
185712800,2sleep218574-21bash09:50:342
57322790,2sleep25731-21bash10:03:082
140372790,2sleep114031-21sshd09:46:401
63852780,1sleep30-21swapper/311:19:523
120222770,4sleep0138999cyclictest11:34:270
145052760,3sleep20-21swapper/210:24:572
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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