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2025-08-29 - 14:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Fri Aug 29, 2025 12:44:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1453921730,1sleep02916999cyclictest11:37:080
97421660,0sleep00-21swapper/011:32:260
1482121240,0sleep014803-21sshd12:39:430
2396921230,1sleep00-21swapper/009:30:170
2675421150,4sleep10-21swapper/109:10:391
1761921130,17sleep310950irq/23-ehci_hcd10:06:243
1504121000,3sleep20-21swapper/211:30:312
2865129732,43sleep30-21swapper/307:07:023
3542960,2sleep10-21swapper/112:38:251
2890629533,49sleep10-21swapper/107:09:551
200122950,2sleep30-21swapper/311:24:313
264672920,3sleep30-21swapper/311:25:113
113642920,3sleep30-21swapper/310:29:483
317702910,1sleep031765-21bash10:31:490
311732890,3sleep20-21swapper/210:59:012
316512880,1sleep30-21swapper/310:35:293
143292880,1sleep10-21swapper/111:59:081
122812870,1sleep00-21swapper/012:10:250
283582860,3sleep20-21swapper/209:14:162
323402850,3sleep02916999cyclictest10:21:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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