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2025-10-31 - 10:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Fri Oct 31, 2025 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
838521320,2sleep10-21swapper/100:23:151
72921290,0sleep00-21swapper/023:12:390
154021280,1sleep31524-21sshd21:50:333
1460821230,2sleep114590-21sshd22:40:171
3121121220,2sleep10-21swapper/123:50:431
3022221150,1sleep10-21swapper/123:38:451
1876921150,2sleep20-21swapper/223:55:372
2385521090,3sleep02948799cyclictest21:52:430
102652970,2sleep20-21swapper/221:21:142
176432940,2sleep217644-21bash21:25:032
52892930,3sleep22948999cyclictest00:30:012
42972910,2sleep11846-21nfsd23:07:031
160262900,2sleep20-21swapper/221:42:552
182472880,2sleep218248-21sshd00:08:042
141102880,2sleep10-21swapper/123:10:511
237042860,2sleep30-21swapper/300:15:063
69972850,2sleep16995-21bash23:21:541
2910328533,48sleep10-21swapper/119:08:271
193922830,2sleep219385-21sshd22:04:272
170472830,3sleep30-21swapper/322:59:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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