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2026-06-28 - 06:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sun Jun 28, 2026 00:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1728321380,1sleep10-21swapper/100:39:121
2981521310,1sleep10-21swapper/123:44:541
25756211633,46sleep30-21swapper/319:08:163
294572950,1sleep32615999cyclictest00:33:083
294572950,1sleep32615999cyclictest00:33:083
95602930,1sleep00-21swapper/021:59:330
72362930,2sleep10-21swapper/121:30:531
213782920,1sleep021376-21bash23:00:120
315202880,1sleep031469-21sshd21:55:000
239082863,42sleep10-21swapper/119:05:121
301722850,2sleep130171-21sshd22:53:271
131682850,2sleep30-21swapper/323:43:033
79302840,2sleep37923-21sshd23:39:033
41182840,1sleep00-21swapper/000:00:200
131622840,1sleep00-21swapper/023:57:510
217732830,1sleep00-21swapper/023:44:010
78652820,2sleep30-21swapper/321:23:253
24422820,1sleep08-21rcu_preempt21:15:210
201052820,3sleep02615699cyclictest21:13:530
293942810,2sleep30-21swapper/321:40:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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