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2025-12-15 - 22:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Mon Dec 15, 2025 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17549211438,47sleep10-21swapper/107:06:291
1768429536,47sleep30-21swapper/307:08:133
273682840,3sleep01808799cyclictest11:20:230
130312780,0sleep00-21swapper/008:10:110
191602750,3sleep10-21swapper/108:43:321
124902750,1sleep20-21swapper/209:52:302
13862650,1sleep30-21swapper/308:28:053
77802620,3sleep31809099cyclictest12:06:413
1768126037,11sleep00-21swapper/007:08:090
1754026037,10sleep20-21swapper/207:06:232
94172530,4sleep20-21swapper/210:22:272
183432350,0sleep03-21ksoftirqd/009:54:360
158912350,0sleep215892-21sshd10:35:092
189222300,3sleep01808799cyclictest10:25:210
1808799284,23cyclictest41ktimersoftd/010:40:000
113802260,3sleep30-21swapper/310:54:413
178362250,3sleep20-21swapper/211:49:172
118242250,2sleep20-21swapper/209:31:422
1808899240,23cyclictest137550irq/27-eth008:27:061
108272220,1sleep00-21swapper/011:05:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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