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2025-12-20 - 10:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat Dec 20, 2025 00:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1644821280,4sleep3581899cyclictest23:18:173
544529433,40sleep30-21swapper/319:08:333
542329131,39sleep10-21swapper/119:08:151
94002870,1sleep30-21swapper/323:57:363
139062850,3sleep0581599cyclictest22:56:370
161632840,2sleep20-21swapper/221:15:552
170692740,3sleep0581599cyclictest22:26:530
35792710,0sleep00-21swapper/022:12:310
326572700,2sleep30-21swapper/300:36:383
183962660,0sleep00-21swapper/000:21:210
51832630,1sleep22439-21runrttasks22:13:052
352225533,19sleep00-21swapper/019:05:050
536525034,12sleep20-21swapper/219:07:332
581599223,1cyclictest0-21swapper/000:18:070
323942210,1sleep10-21swapper/122:31:431
182052210,2sleep32439-21runrttasks21:26:333
3682190,17sleep128450irq/26-ahci[00022:21:381
224292190,0sleep00-21swapper/021:18:060
120652190,17sleep3137550irq/27-eth021:55:073
581899188,5cyclictest7284-21sshd22:13:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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