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2026-06-06 - 19:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot0.osadl.org (updated Sat Jun 06, 2026 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2433221260,0sleep124331-21bash23:37:121
1037321230,0sleep110367-21sshd23:25:011
15576210132,65sleep30-21swapper/319:08:393
200172980,1sleep00-21swapper/023:40:320
289152950,10sleep10-21swapper/122:29:591
236112930,0sleep00-21swapper/023:33:420
1568328434,38sleep10-21swapper/119:09:581
256112830,5sleep10-21swapper/123:55:271
93182820,1sleep39315-21cp21:17:083
63062820,3sleep10-21swapper/100:08:101
178782820,2sleep20-21swapper/223:51:112
326282810,2sleep132619-21sshd21:57:251
243192800,2sleep10-21swapper/122:18:211
6712780,3sleep20-21swapper/223:23:472
81532760,4sleep31594499cyclictest00:38:053
98942740,1sleep20-21swapper/200:27:142
318542740,1sleep031844-21sshd00:00:150
179722740,3sleep00-21swapper/023:47:290
8872730,2sleep01594199cyclictest21:12:520
6532730,1sleep31594499cyclictest23:34:463
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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