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2026-05-27 - 07:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Wed May 27, 2026 00:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2148721310,0sleep321488-21sshd21:27:533
3247321250,1sleep00-21swapper/021:46:410
779621010,2sleep30-21swapper/300:11:313
364521010,1sleep30-21swapper/322:43:303
275062980,4sleep32381399cyclictest21:18:153
2340529433,40sleep30-21swapper/319:08:103
74362900,2sleep30-21swapper/300:07:143
51242900,1sleep30-21swapper/300:18:253
23922900,2sleep30-21swapper/321:12:103
249862890,6sleep30-21swapper/322:31:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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