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2026-06-21 - 19:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sun Jun 21, 2026 12:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1975721330,3sleep03263299cyclictest10:19:370
484521000,4sleep13263399cyclictest10:25:151
3225729626,41sleep10-21swapper/107:08:431
166272910,2sleep20-21swapper/209:16:072
267552900,3sleep30-21swapper/310:02:503
11752890,0sleep00-21swapper/011:51:340
158442870,1sleep20-21swapper/209:40:122
253442860,3sleep00-21swapper/012:05:360
3224428533,48sleep30-21swapper/307:08:323
325582830,1sleep132557-21sshd10:20:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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