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2026-07-18 - 18:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sat Jul 18, 2026 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2067021200,3sleep22651099cyclictest12:30:172
25986211634,44sleep10-21swapper/107:06:521
325332850,3sleep02650899cyclictest09:15:110
274892850,3sleep20-21swapper/209:18:182
260302850,2sleep126029-21fschecks_time12:20:151
325672840,3sleep20-21swapper/212:16:552
200482840,3sleep22651099cyclictest09:49:402
301852830,2sleep30-21swapper/309:47:123
2592928333,45sleep30-21swapper/307:06:093
23052830,1sleep02298-21sshd11:00:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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