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2026-07-17 - 17:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Fri Jul 17, 2026 12:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89121290,3sleep0261099cyclictest12:00:140
1110921290,1sleep211100-21sshd11:41:402
3168621240,2sleep30-21swapper/310:00:503
2166721230,3sleep1261199cyclictest12:09:401
699121100,1sleep30-21swapper/309:23:083
699121100,1sleep30-21swapper/309:23:073
1988210431,43sleep10-21swapper/107:06:121
102082930,0sleep00-21swapper/012:27:430
165022900,2sleep116507-21cut07:40:121
110412900,2sleep10-21swapper/109:44:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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