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2026-07-15 - 16:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Wed Jul 15, 2026 12:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2922321520,3sleep21625999cyclictest10:58:472
3116321380,2sleep21625999cyclictest11:28:482
1016921210,1sleep110170-21sshd12:38:291
1819121190,3sleep21625999cyclictest10:45:442
1600121150,1sleep30-21swapper/311:04:363
651121110,2sleep30-21swapper/310:30:073
1470121090,2sleep20-21swapper/209:18:202
15726210332,41sleep30-21swapper/307:06:453
39662970,2sleep23967-21id12:11:442
186812950,3sleep20-21swapper/211:46:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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