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2026-06-09 - 10:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Tue Jun 09, 2026 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
239732990,1sleep00-21swapper/023:19:060
282122940,3sleep31346199cyclictest22:15:123
100142910,1sleep20-21swapper/221:31:122
316692900,2sleep20-21swapper/223:41:282
72722880,6sleep30-21swapper/300:29:253
298862870,1sleep30-21swapper/323:55:313
1288428734,49sleep30-21swapper/319:06:133
260212850,3sleep10-21swapper/121:43:171
1303628333,46sleep10-21swapper/119:07:561
59322820,4sleep31346199cyclictest23:06:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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