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2026-06-27 - 01:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Fri Jun 26, 2026 12:44:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
410421230,1sleep04099-21sshd10:21:520
34632960,2sleep13460-21sshd11:43:321
2156329331,41sleep10-21swapper/107:08:291
2149728931,46sleep30-21swapper/307:07:423
169612870,2sleep30-21swapper/309:17:223
81162860,3sleep20-21swapper/212:24:482
287482860,1sleep20-21swapper/209:15:132
255062860,3sleep20-21swapper/211:20:112
4152850,2sleep1418-21sshd09:12:111
160682850,1sleep016058-21sshd10:19:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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