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2026-05-20 - 23:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Wed May 20, 2026 12:44:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2469621220,3sleep20-21swapper/210:18:482
2391721170,1sleep223915-21sshd10:00:442
494721140,3sleep31645899cyclictest12:32:373
1681721140,4sleep11645699cyclictest11:03:391
1619929833,44sleep30-21swapper/307:09:583
266682970,2sleep10-21swapper/109:30:171
45912930,1sleep00-21swapper/010:30:200
134062930,2sleep20-21swapper/210:27:532
288592920,5sleep30-21swapper/309:50:243
192862910,1sleep02512-21runrttasks11:14:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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