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2026-05-13 - 17:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Wed May 13, 2026 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1275621480,0sleep212755-21sshd11:01:242
4707210233,40sleep10-21swapper/107:06:281
497729632,43sleep30-21swapper/307:09:423
313152940,2sleep231307-21sshd10:42:172
143512880,0sleep00-21swapper/009:54:060
111242860,3sleep10-21swapper/112:15:361
223592850,1sleep30-21swapper/309:19:423
87252820,4sleep20-21swapper/210:29:342
34982820,2sleep33494-21sshd09:38:413
301672820,2sleep10-21swapper/110:31:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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