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2026-06-11 - 12:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Thu Jun 11, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
697821500,0sleep06977-21sshd21:28:010
873621270,0sleep18737-21sshd22:54:111
214021250,4sleep1689599cyclictest22:32:231
1443021000,1sleep00-21swapper/000:35:040
130782950,2sleep00-21swapper/021:45:360
293012930,0sleep00-21swapper/022:28:250
241512920,0sleep00-21swapper/022:38:110
648829032,12sleep20-21swapper/219:08:102
253402890,3sleep20-21swapper/222:17:092
250602880,1sleep30-21swapper/321:36:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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