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2026-05-14 - 18:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Thu May 14, 2026 12:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1351321290,0sleep213515-21id09:38:252
223721250,4sleep11195899cyclictest09:20:131
2081321220,0sleep00-21swapper/012:20:410
1825821170,3sleep21195999cyclictest10:39:052
229921140,2sleep30-21swapper/310:40:413
1148529933,54sleep30-21swapper/307:07:253
295672910,3sleep10-21swapper/111:20:261
275752880,1sleep10-21swapper/110:25:441
66142850,3sleep30-21swapper/311:02:373
1149328533,48sleep10-21swapper/107:07:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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