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2026-08-04 - 07:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Tue Aug 04, 2026 00:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2966021360,0sleep229661-21sshd21:42:002
689421260,3sleep2485999cyclictest23:48:002
456721200,2sleep0485099cyclictest22:32:360
2014521200,1sleep2485999cyclictest21:17:552
4274210432,44sleep30-21swapper/319:05:593
236582990,2sleep123660-21sshd23:52:241
47992950,3sleep30-21swapper/322:42:013
223792950,1sleep00-21swapper/023:58:000
102152940,1sleep30-21swapper/322:27:183
94782900,2sleep19476-21sshd22:24:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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