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2026-04-23 - 20:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Thu Apr 23, 2026 12:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
845621190,0sleep38440-21sshd10:31:353
277292940,0sleep00-21swapper/009:18:420
265002920,1sleep20-21swapper/209:36:562
125792890,3sleep20-21swapper/211:22:442
302362870,2sleep10-21swapper/111:10:161
2035928634,48sleep10-21swapper/107:06:581
245662840,3sleep20-21swapper/210:36:432
199832840,1sleep10-21swapper/109:54:381
2031228333,41sleep30-21swapper/307:06:243
110112830,3sleep10-21swapper/111:32:561
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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