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2026-09-15 - 16:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Tue Sep 15, 2026 12:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2813921180,4sleep21254799cyclictest09:32:532
3256521140,1sleep00-21swapper/011:04:330
12050211034,47sleep30-21swapper/307:07:133
841421020,1sleep00-21swapper/012:35:390
12107210133,47sleep10-21swapper/107:07:551
12692990,1sleep00-21swapper/011:45:280
17342970,1sleep00-21swapper/011:13:230
307922960,3sleep20-21swapper/211:36:332
67382930,4sleep20-21swapper/211:49:002
39362930,1sleep03922-21sshd11:19:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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