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2026-06-12 - 12:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Fri Jun 12, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3144721320,1sleep30-21swapper/322:53:133
2574621240,2sleep325743-21sshd21:33:583
156821210,1sleep21553-21sshd21:48:392
1506521170,1sleep2634599cyclictest22:25:582
6059210532,43sleep10-21swapper/119:09:401
92842970,1sleep10-21swapper/100:20:591
232802890,2sleep10-21swapper/122:01:411
183982890,2sleep118388-21sshd21:57:281
35122880,2sleep32512-21runrttasks22:57:063
220102880,0sleep00-21swapper/021:40:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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