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2026-08-10 - 14:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Mon Aug 10, 2026 12:44:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1818121180,0sleep32023-21nfsd09:11:503
18422970,1sleep30-21swapper/308:10:143
34042950,0sleep00-21swapper/011:24:460
81722930,2sleep38166-21sshd12:21:403
187622930,3sleep30-21swapper/310:12:473
602629229,50sleep30-21swapper/307:06:593
607829032,54sleep10-21swapper/107:07:381
259652890,4sleep30-21swapper/312:38:033
244792880,2sleep10-21swapper/111:00:101
21712870,3sleep2653999cyclictest12:21:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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