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2026-07-28 - 01:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Mon Jul 27, 2026 12:44:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2449021360,5sleep01716499cyclictest10:54:390
1342321300,5sleep01716499cyclictest12:03:520
2019521210,3sleep21716699cyclictest10:28:002
1077521150,1sleep10-21swapper/109:46:441
1660829732,43sleep10-21swapper/107:06:301
43652940,1sleep00-21swapper/012:10:180
326872890,1sleep00-21swapper/010:25:460
326682870,1sleep30-21swapper/309:49:093
274722870,3sleep30-21swapper/312:09:203
286452860,2sleep128641-21sshd12:20:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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