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2025-12-21 - 03:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sun Dec 21, 2025 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3398210333,41sleep10-21swapper/119:08:451
3410210132,42sleep30-21swapper/319:08:543
40372900,2sleep10-21swapper/122:44:141
4442800,2sleep30-21swapper/322:53:183
323302770,1sleep10-21swapper/100:37:211
237322720,2sleep30-21swapper/300:34:513
30552710,1sleep20-21swapper/200:06:452
149032710,1sleep10-21swapper/121:26:091
349125732,22sleep00-21swapper/019:09:550
208362540,0sleep00-21swapper/021:28:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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