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2026-07-27 - 00:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sun Jul 26, 2026 12:44:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
237321310,1sleep32363-21rm11:16:293
2775121250,2sleep10-21swapper/109:48:301
2080221250,3sleep02575999cyclictest09:53:420
1178921220,2sleep30-21swapper/311:40:533
2187921210,3sleep22132-21sshd10:34:402
675821190,4sleep22576199cyclictest10:39:132
2386321190,2sleep223849-21sshd09:42:182
25402210232,41sleep10-21swapper/107:08:441
31002960,2sleep13101-21sshd12:29:341
31002960,2sleep13101-21sshd12:29:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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