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2026-05-29 - 22:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Fri May 29, 2026 12:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172021410,1sleep13055499cyclictest10:12:131
2842921330,3sleep30-21swapper/309:42:023
3002221320,2sleep13055499cyclictest10:19:041
1152221220,1sleep30-21swapper/310:02:303
2556821190,2sleep20-21swapper/209:41:372
30290210932,45sleep10-21swapper/107:09:571
30202210432,44sleep30-21swapper/307:08:583
90142950,1sleep00-21swapper/009:10:170
125662950,1sleep30-21swapper/311:42:573
33542920,2sleep23353-21sshd09:34:482
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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