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2026-06-14 - 14:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sun Jun 14, 2026 12:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1692121280,0sleep116922-21sshd11:56:261
353321180,4sleep11957799cyclictest11:47:251
2366821030,2sleep20-21swapper/212:15:422
80492980,3sleep20-21swapper/210:49:192
80492980,3sleep20-21swapper/210:49:192
30902940,2sleep20-21swapper/211:54:582
239352860,0sleep00-21swapper/012:34:320
1929128633,49sleep30-21swapper/307:09:393
135202860,3sleep20-21swapper/211:44:572
149022850,0sleep00-21swapper/009:28:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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