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2026-06-15 - 15:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Mon Jun 15, 2026 12:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2702321340,0sleep327024-21sshd10:56:423
527821240,1sleep30-21swapper/309:34:353
3101021210,2sleep12024-21nfsd10:17:371
701121090,2sleep17008-21sshd12:32:451
12955210035,47sleep10-21swapper/107:09:411
1273029427,39sleep30-21swapper/307:06:513
323932930,1sleep00-21swapper/010:21:080
121212910,1sleep02023-21nfsd12:22:070
263622880,0sleep00-21swapper/009:22:540
87272850,2sleep30-21swapper/309:17:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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