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2026-03-28 - 00:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Fri Mar 27, 2026 12:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1727521400,0sleep117272-21cp10:31:511
950821360,2sleep01081899cyclictest09:48:530
2171821300,3sleep01081899cyclictest11:10:530
782921190,1sleep10-21swapper/112:00:151
316412950,3sleep20-21swapper/211:59:252
208102900,1sleep020808-21sshd10:32:140
238112870,0sleep00-21swapper/010:25:360
1036728633,49sleep30-21swapper/307:07:473
26712850,2sleep10-21swapper/110:23:281
1041528533,48sleep10-21swapper/107:08:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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