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2026-06-18 - 18:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Thu Jun 18, 2026 12:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2529921330,1sleep225282-21sshd12:32:092
1483829432,50sleep10-21swapper/107:05:151
93412920,4sleep00-21swapper/009:17:070
128262920,1sleep00-21swapper/010:13:170
114182870,4sleep31639699cyclictest09:13:573
89462850,1sleep28942-21sshd10:05:172
38582850,0sleep00-21swapper/009:05:000
34112830,2sleep33400-21sshd11:36:513
324532820,0sleep00-21swapper/012:25:140
1587428233,44sleep30-21swapper/307:06:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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