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2026-05-19 - 22:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Tue May 19, 2026 12:44:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
589621380,3sleep0449299cyclictest12:03:550
1322721220,2sleep10-21swapper/112:04:441
1248721220,1sleep212486-21sshd12:15:192
127321170,0sleep00-21swapper/010:49:380
127321170,0sleep00-21swapper/010:49:370
277442990,3sleep20-21swapper/211:25:302
281232980,5sleep028118-21sshd10:34:500
220492970,1sleep08-21rcu_preempt10:19:560
411429532,59sleep10-21swapper/107:08:301
256032950,4sleep10-21swapper/111:18:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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