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2026-07-09 - 12:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Thu Jul 09, 2026 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
463721350,1sleep20-21swapper/221:10:212
2935021310,1sleep229348-21sshd23:07:392
1044421150,4sleep21041499cyclictest23:43:022
3263921140,2sleep31041599cyclictest22:01:293
10138210332,43sleep10-21swapper/119:09:461
993329332,48sleep30-21swapper/319:07:113
168292890,2sleep30-21swapper/321:49:143
257002880,3sleep20-21swapper/221:35:222
322702860,0sleep00-21swapper/021:54:280
185022850,2sleep01041299cyclictest23:43:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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