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2026-03-19 - 06:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Thu Mar 19, 2026 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
811421240,2sleep12132-21sshd00:04:351
2581521170,1sleep00-21swapper/000:14:000
1772529434,48sleep10-21swapper/119:07:531
224562920,3sleep31817099cyclictest00:20:453
70812900,2sleep16752-21sshd22:55:231
292592870,1sleep329257-21sshd21:51:293
51262860,2sleep25113-21sshd22:17:292
1784128633,49sleep30-21swapper/319:09:233
301112850,3sleep20-21swapper/223:23:422
287242850,2sleep10-21swapper/100:21:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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