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2026-03-21 - 04:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sat Mar 21, 2026 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1842921450,1sleep00-21swapper/022:53:570
3247121120,4sleep12186699cyclictest23:12:451
21339210133,40sleep30-21swapper/319:06:423
21339210133,40sleep30-21swapper/319:06:423
10222990,1sleep00-21swapper/021:30:100
15122950,0sleep00-21swapper/021:40:180
147822940,0sleep00-21swapper/021:28:090
170582920,1sleep20-21swapper/200:31:012
270672900,3sleep20-21swapper/223:26:562
265422900,1sleep00-21swapper/022:47:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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