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2026-05-16 - 19:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sat May 16, 2026 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62321250,1sleep0624-21sshd11:40:380
2595721250,1sleep00-21swapper/010:07:570
1505121170,5sleep31216599cyclictest12:39:553
11662211534,43sleep30-21swapper/307:07:023
11803210033,55sleep10-21swapper/107:08:481
147012980,3sleep20-21swapper/211:21:002
130062980,2sleep10-21swapper/112:36:031
19522940,1sleep11943-21sshd10:05:201
163722940,0sleep00-21swapper/011:56:200
253952890,2sleep10-21swapper/110:43:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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