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2026-08-11 - 15:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Tue Aug 11, 2026 12:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2273121400,1sleep00-21swapper/010:28:300
1143721080,2sleep32140999cyclictest09:58:563
20930210732,45sleep30-21swapper/307:07:323
54372950,3sleep10-21swapper/112:16:131
54292940,5sleep20-21swapper/211:17:262
285292920,2sleep20-21swapper/212:32:572
233862910,1sleep20-21swapper/210:05:402
194662910,3sleep20-21swapper/210:40:192
120312880,2sleep212019-21sshd10:16:022
276912870,1sleep00-21swapper/010:08:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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