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2026-07-11 - 11:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sat Jul 11, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238021290,4sleep2310999cyclictest23:22:022
2756121200,0sleep227563-21sshd21:50:122
59022930,2sleep10-21swapper/121:26:271
183132900,4sleep20-21swapper/200:16:402
48512890,1sleep20-21swapper/223:29:472
255592880,0sleep00-21swapper/021:28:390
166022880,1sleep30-21swapper/322:57:553
243102860,2sleep30-21swapper/300:17:223
264128533,48sleep10-21swapper/119:07:261
120232850,2sleep10-21swapper/100:07:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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