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2026-07-25 - 21:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Sat Jul 25, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1562821530,2sleep30-21swapper/310:33:463
1850221310,3sleep21905499cyclictest11:33:282
1444121240,4sleep31905599cyclictest09:38:553
3175421200,4sleep31905599cyclictest11:07:523
91721130,1sleep30-21swapper/310:56:263
37392990,2sleep13740-21sshd12:14:071
128252980,2sleep312764-21sshd11:57:053
295492960,0sleep00-21swapper/011:01:560
186182950,0sleep00-21swapper/010:04:490
254442940,1sleep025353-21sshd12:24:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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