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2026-05-06 - 13:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot0.osadl.org (updated Wed May 06, 2026 00:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1998021500,1sleep30-21swapper/323:05:253
1635121440,0sleep016316-21sshd22:43:010
1635121440,0sleep016316-21sshd22:43:010
1643729832,44sleep10-21swapper/119:09:021
157722920,0sleep00-21swapper/022:35:430
304672890,0sleep00-21swapper/023:14:020
99692880,2sleep11675999cyclictest00:35:231
32442880,2sleep32512-21runrttasks23:22:233
276402880,0sleep00-21swapper/021:50:110
245312880,1sleep10-21swapper/121:32:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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