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2026-05-28 - 10:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot1.osadl.org (updated Thu May 28, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2920539910,0EcMasterDemoSyn2921529tAtEmLog_019:39:445
1436639850,0EcMasterDemoSyn1437629tAtEmLog_020:15:155
2857539840,0EcMasterDemoSyn2858529tAtEmLog_021:56:395
3259539830,0EcMasterDemoSyn3260629tAtEmLog_022:52:265
2684739830,1EcMasterDemoSyn26855-21runintdemo5min19:34:400
3096539820,0EcMasterDemoSyn3097529tAtEmLog_000:03:265
2684739820,0EcMasterDemoSyn2685729tAtEmLog_019:34:415
2683639820,0EcMasterDemoSyn2684629tAtEmLog_023:43:095
2245939820,0EcMasterDemoSyn2246929tAtEmLog_023:22:515
1509439820,0EcMasterDemoSyn1510429tAtEmLog_021:31:185
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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