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2025-11-28 - 07:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot1.osadl.org (updated Fri Nov 28, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29494391100,0EcMasterDemoSyn29499-21runintdemo5min22:02:350
2696039970,1EcMasterDemoSyn301rcuc/123:49:031
54322920,0sleep00-21swapper/021:46:470
2397639830,0EcMasterDemoSyn2398629tAtEmLog_023:03:255
2330439830,0EcMasterDemoSyn2331429tAtEmLog_019:15:145
190562830,0sleep00-21swapper/021:35:090
1686439830,0EcMasterDemoSyn1687429tAtEmLog_021:11:515
651239820,0EcMasterDemoSyn652229tAtEmLog_019:45:395
651239820,0EcMasterDemoSyn652229tAtEmLog_019:45:395
2342439820,0EcMasterDemoSyn2343429tAtEmLog_020:21:095
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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