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2026-01-12 - 11:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack5slot1.osadl.org (updated Mon Jan 12, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2259039930,0EcMasterDemoSyn2260029tAtEmLog_019:44:085
2944139910,0EcMasterDemoSyn2945129tAtEmLog_021:25:335
1240239910,0EcMasterDemoSyn1241229tAtEmLog_020:29:475
2983639860,0EcMasterDemoSyn2984629tAtEmLog_022:36:335
1053639860,0EcMasterDemoSyn1054629tAtEmLog_021:15:255
1073739840,0EcMasterDemoSyn1074729tAtEmLog_021:50:555
1313739830,0EcMasterDemoSyn1314729tAtEmLog_019:23:525
602739820,0EcMasterDemoSyn603729tAtEmLog_019:08:395
264239820,0EcMasterDemoSyn265229tAtEmLog_020:09:295
1991139820,0EcMasterDemoSyn1992129tAtEmLog_023:06:585
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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