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2026-02-26 - 18:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Feb 26, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2578139920,0EcMasterDemoSyn2579129tAtEmLog_011:52:385
131542870,0sleep50-21swapper/508:50:235
427939830,0EcMasterDemoSyn428929tAtEmLog_010:46:425
2724739830,0EcMasterDemoSyn2725729tAtEmLog_010:41:385
2332139830,0EcMasterDemoSyn2333129tAtEmLog_009:45:515
1781139830,0EcMasterDemoSyn1782129tAtEmLog_010:36:345
1781139830,0EcMasterDemoSyn1782129tAtEmLog_010:36:335
1757539830,0EcMasterDemoSyn1758529tAtEmLog_011:12:045
440039820,0EcMasterDemoSyn441029tAtEmLog_008:34:525
341739820,0EcMasterDemoSyn342729tAtEmLog_011:22:125
1079739820,0EcMasterDemoSyn1080729tAtEmLog_007:39:055
2494639810,0EcMasterDemoSyn2495629tAtEmLog_012:28:075
2734339770,0EcMasterDemoSyn0-21swapper/208:14:352
1346939540,1EcMasterDemoSyn13474-21runintdemo5min10:51:470
2724739390,1EcMasterDemoSyn27255-21grep10:41:382
159439300,1EcMasterDemoSyn1601-21grep12:33:122
2068139280,1EcMasterDemoSyn20689-21runintdemo5min12:07:504
1788839240,1EcMasterDemoSyn17897-21runintdemo5min07:54:183
919139220,1EcMasterDemoSyn9197-21ps08:45:000
919139220,1EcMasterDemoSyn9197-21ps08:44:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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