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2026-04-05 - 08:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Apr 05, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12243391050,1EcMasterDemoSyn12249-21runintdemo5min23:16:480
12243391050,1EcMasterDemoSyn12249-21runintdemo5min23:16:480
1824239950,0EcMasterDemoSyn1825229tAtEmLog_021:50:365
2458439900,8EcMasterDemoSyn2459429tAtEmLog_019:28:365
1476739870,0EcMasterDemoSyn1477329tAtEmLog_019:08:195
425239830,0EcMasterDemoSyn426229tAtEmLog_022:00:455
3171539830,0EcMasterDemoSyn3172529tAtEmLog_022:15:575
2930839830,0EcMasterDemoSyn2931829tAtEmLog_019:38:445
1339839830,0EcMasterDemoSyn1340829tAtEmLog_022:05:495
1167939830,0EcMasterDemoSyn1168929tAtEmLog_023:52:185
2747539820,0EcMasterDemoSyn2748529tAtEmLog_021:55:405
258439820,0EcMasterDemoSyn259429tAtEmLog_023:47:155
2531639820,0EcMasterDemoSyn2532629tAtEmLog_020:39:365
2139639820,0EcMasterDemoSyn2140629tAtEmLog_023:21:535
1949639820,0EcMasterDemoSyn1950629tAtEmLog_019:18:285
760339810,0EcMasterDemoSyn761329tAtEmLog_023:32:015
2296039810,0EcMasterDemoSyn2297029tAtEmLog_020:34:325
399539800,0EcMasterDemoSyn400529tAtEmLog_019:53:585
1300939800,0EcMasterDemoSyn1301929tAtEmLog_021:30:185
3102839210,1EcMasterDemoSyn31034-21ps22:51:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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