You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-16 - 14:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Feb 16, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2636639960,0EcMasterDemoSyn2637629tAtEmLog_011:05:155
284239840,0EcMasterDemoSyn0-21swapper/310:34:503
371239830,0EcMasterDemoSyn372229tAtEmLog_011:10:185
257339830,0EcMasterDemoSyn258329tAtEmLog_012:21:195
1263039830,0EcMasterDemoSyn1264029tAtEmLog_008:07:475
297439820,0EcMasterDemoSyn298429tAtEmLog_009:59:205
363639810,0EcMasterDemoSyn364629tAtEmLog_011:45:495
363639810,0EcMasterDemoSyn364629tAtEmLog_011:45:495
3189439810,0EcMasterDemoSyn3190429tAtEmLog_011:25:325
3064639810,0EcMasterDemoSyn3065629tAtEmLog_009:39:035
3001739810,0EcMasterDemoSyn3002729tAtEmLog_007:37:205
1637839560,0EcMasterDemoSyn1638729tAtEmLog_009:18:455
1615799230,15cyclictest4904-21sh09:25:020
1615799220,9cyclictest9099-21diskmemload10:36:510
1615799215,7cyclictest11148-21ssh09:45:210
1615799210,9cyclictest8425-21sh12:06:380
1615799210,9cyclictest5379-21diskmemload12:23:180
1615799210,9cyclictest31735-21diskmemload12:37:550
1615799210,10cyclictest1187-21cut11:45:110
1615799210,10cyclictest1187-21cut11:45:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional