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2026-02-09 - 07:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Feb 09, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3043539910,0EcMasterDemoSyn3044529tAtEmLog_000:04:595
924039830,0EcMasterDemoSyn925029tAtEmLog_021:12:355
468439820,0EcMasterDemoSyn469429tAtEmLog_020:01:345
353339820,0EcMasterDemoSyn354329tAtEmLog_023:14:175
3102939820,0EcMasterDemoSyn3103929tAtEmLog_020:57:215
294739820,0EcMasterDemoSyn295729tAtEmLog_023:49:465
294739820,0EcMasterDemoSyn295729tAtEmLog_023:49:465
1922239820,0EcMasterDemoSyn1923229tAtEmLog_020:32:015
1829739820,0EcMasterDemoSyn1830729tAtEmLog_022:28:385
1768539820,0EcMasterDemoSyn1769529tAtEmLog_023:04:085
796039810,0EcMasterDemoSyn797029tAtEmLog_023:34:345
440139810,0EcMasterDemoSyn441129tAtEmLog_022:03:175
3235539810,0EcMasterDemoSyn3236529tAtEmLog_019:51:265
275539810,0EcMasterDemoSyn276629tAtEmLog_000:25:165
2526339810,0EcMasterDemoSyn2527329tAtEmLog_019:36:145
2218039810,0EcMasterDemoSyn2219029tAtEmLog_023:24:255
248022600,0sleep224801-21ssh23:43:402
248022600,0sleep224801-21ssh23:43:402
219772330,0sleep00-21swapper/022:30:180
2867439240,1EcMasterDemoSyn28682-21runintdemo5min20:52:184
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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