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2026-02-24 - 13:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Feb 24, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9121391270,0EcMasterDemoSyn9126-21runintdemo5min20:59:550
1715721140,0sleep00-21swapper/000:26:260
718939920,0EcMasterDemoSyn719929tAtEmLog_022:51:295
161452880,0sleep50-21swapper/521:45:255
573439840,0EcMasterDemoSyn574429tAtEmLog_019:43:525
573439840,0EcMasterDemoSyn574429tAtEmLog_019:43:515
839139830,0EcMasterDemoSyn840129tAtEmLog_019:48:565
2971639830,0EcMasterDemoSyn2972629tAtEmLog_020:34:345
2868239830,0EcMasterDemoSyn2869229tAtEmLog_019:23:355
2555539830,0EcMasterDemoSyn2556529tAtEmLog_023:01:385
3207739820,0EcMasterDemoSyn3208729tAtEmLog_020:39:385
3104539820,0EcMasterDemoSyn3105529tAtEmLog_019:28:385
2735839820,0EcMasterDemoSyn2736829tAtEmLog_020:29:305
2630539820,0EcMasterDemoSyn2631529tAtEmLog_019:18:315
2025239820,0EcMasterDemoSyn2026229tAtEmLog_020:14:165
1973739820,0EcMasterDemoSyn1974729tAtEmLog_023:52:205
1310439820,0EcMasterDemoSyn1311429tAtEmLog_019:59:045
1201139820,0EcMasterDemoSyn1202129tAtEmLog_022:36:155
1150339820,0EcMasterDemoSyn1151329tAtEmLog_021:04:595
1057139820,0EcMasterDemoSyn1058329tAtEmLog_023:47:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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