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2026-03-02 - 00:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Mar 01, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
728739920,0EcMasterDemoSyn729729tAtEmLog_010:52:115
1709939860,0EcMasterDemoSyn0-21swapper/210:21:462
967239830,0EcMasterDemoSyn968229tAtEmLog_008:55:335
1779739830,0EcMasterDemoSyn1780729tAtEmLog_009:46:165
1291439830,0EcMasterDemoSyn1292429tAtEmLog_010:01:295
793539820,0EcMasterDemoSyn794529tAtEmLog_010:16:415
3178439820,0EcMasterDemoSyn3179429tAtEmLog_007:29:215
3146839820,0EcMasterDemoSyn3147829tAtEmLog_009:36:075
1408039820,1EcMasterDemoSyn1409029tAtEmLog_007:59:475
564839810,0EcMasterDemoSyn565829tAtEmLog_012:03:115
368339810,0EcMasterDemoSyn369329tAtEmLog_009:56:245
2468639810,0EcMasterDemoSyn2469629tAtEmLog_007:14:095
2117139810,0EcMasterDemoSyn2118129tAtEmLog_008:14:595
1986139810,0EcMasterDemoSyn1987129tAtEmLog_011:53:025
731539800,0EcMasterDemoSyn732529tAtEmLog_008:50:295
2228339800,0EcMasterDemoSyn2229329tAtEmLog_009:31:035
47139610,0EcMasterDemoSyn481-21runintdemo5min12:18:231
300272560,0sleep030025-21ssh11:58:510
148642260,4sleep241-21ksoftirqd/212:25:462
3146839230,1EcMasterDemoSyn31473-21runintdemo5min09:36:074
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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