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2026-03-13 - 23:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Mar 13, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21198391130,0EcMasterDemoSyn0-21swapper/311:54:203
320239920,0EcMasterDemoSyn321229tAtEmLog_009:22:125
320239920,0EcMasterDemoSyn321229tAtEmLog_009:22:115
2286739910,0EcMasterDemoSyn2287729tAtEmLog_008:21:205
1144839870,0EcMasterDemoSyn1145429tAtEmLog_012:24:455
56982830,1sleep10-21swapper/110:34:471
258539830,0EcMasterDemoSyn259529tAtEmLog_011:44:115
2531739830,0EcMasterDemoSyn2532729tAtEmLog_012:14:375
2048639830,0EcMasterDemoSyn2049629tAtEmLog_008:16:175
1688639830,0EcMasterDemoSyn1689529tAtEmLog_009:12:045
3032139820,0EcMasterDemoSyn3033129tAtEmLog_011:59:245
2994439820,0EcMasterDemoSyn2995429tAtEmLog_008:36:335
2124039820,0EcMasterDemoSyn2125029tAtEmLog_007:10:215
778639810,0EcMasterDemoSyn779629tAtEmLog_010:53:295
72722810,1sleep2391rcuc/211:10:242
358939810,0EcMasterDemoSyn359929tAtEmLog_007:40:475
2872339810,0EcMasterDemoSyn2873329tAtEmLog_007:25:345
2060139810,0EcMasterDemoSyn2061129tAtEmLog_012:29:505
1872939810,0EcMasterDemoSyn1873929tAtEmLog_007:05:185
1806739810,0EcMasterDemoSyn1807729tAtEmLog_008:11:125
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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