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2026-02-23 - 09:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Feb 23, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156072960,1sleep00-21swapper/000:35:170
139842890,1sleep30-21swapper/319:30:003
66439830,0EcMasterDemoSyn67429tAtEmLog_020:09:065
385539830,0EcMasterDemoSyn386529tAtEmLog_022:05:435
306039830,0EcMasterDemoSyn307029tAtEmLog_020:14:115
2051239830,0EcMasterDemoSyn2052229tAtEmLog_000:37:525
542839820,0EcMasterDemoSyn543829tAtEmLog_020:19:145
1620939820,0EcMasterDemoSyn1621929tAtEmLog_019:33:375
1620939820,0EcMasterDemoSyn1621929tAtEmLog_019:33:375
881039810,0EcMasterDemoSyn882029tAtEmLog_019:18:235
407639810,0EcMasterDemoSyn408629tAtEmLog_019:08:165
2233439810,0EcMasterDemoSyn2234429tAtEmLog_020:54:455
1762039810,0EcMasterDemoSyn1763029tAtEmLog_020:44:355
1285439810,0EcMasterDemoSyn1286429tAtEmLog_021:35:185
1783639770,1EcMasterDemoSyn17843-21grep22:31:051
1252639380,0EcMasterDemoSyn0-21swapper/020:34:280
3151039260,3EcMasterDemoSyn0-21swapper/223:31:562
66439250,1EcMasterDemoSyn670-21ps20:09:063
4322992420,3cyclictest2974-21kworker/4:0+events19:23:274
1138239230,1EcMasterDemoSyn11388-21ps00:32:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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