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2026-06-22 - 01:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Jun 21, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20789391490,1EcMasterDemoSyn20797-21runintdemo5min08:34:060
19635391470,0EcMasterDemoSyn0-21swapper/410:10:264
9057391140,0EcMasterDemoSyn9066-21runintdemo5min11:16:223
32095391130,0EcMasterDemoSyn0-21swapper/411:11:174
32095391130,0EcMasterDemoSyn0-21swapper/411:11:174
21527391050,0EcMasterDemoSyn0-21swapper/212:17:132
969539980,0EcMasterDemoSyn9704-21runintdemo5min10:40:534
2152739830,0EcMasterDemoSyn2153729tAtEmLog_012:17:125
1463439830,0EcMasterDemoSyn1464429tAtEmLog_010:25:395
64139820,0EcMasterDemoSyn66029tAtEmLog_010:00:195
45139820,0EcMasterDemoSyn46129tAtEmLog_010:35:485
416739820,0EcMasterDemoSyn417729tAtEmLog_007:58:375
2745939820,0EcMasterDemoSyn2746929tAtEmLog_009:40:015
2314739820,0EcMasterDemoSyn2315729tAtEmLog_008:39:115
2078939820,0EcMasterDemoSyn2079929tAtEmLog_008:34:065
1957639820,0EcMasterDemoSyn1958629tAtEmLog_007:23:075
1314539820,0EcMasterDemoSyn1315529tAtEmLog_011:36:385
492139810,0EcMasterDemoSyn493129tAtEmLog_009:09:365
469339810,0EcMasterDemoSyn470429tAtEmLog_010:56:065
403239810,0EcMasterDemoSyn404229tAtEmLog_011:31:355
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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