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2026-02-21 - 07:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat Feb 21, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22537391210,0EcMasterDemoSyn0-21swapper/100:32:331
505339830,0EcMasterDemoSyn506329tAtEmLog_021:24:545
2541739830,0EcMasterDemoSyn2542729tAtEmLog_022:10:345
1979539830,0EcMasterDemoSyn1980529tAtEmLog_019:13:055
765439820,0EcMasterDemoSyn766429tAtEmLog_021:04:385
50539820,0EcMasterDemoSyn51629tAtEmLog_020:49:255
3031239820,0EcMasterDemoSyn3032229tAtEmLog_020:44:205
2689439820,0EcMasterDemoSyn2690429tAtEmLog_019:28:185
2321239820,0EcMasterDemoSyn2322229tAtEmLog_020:29:085
111639820,0EcMasterDemoSyn112629tAtEmLog_023:26:385
1103739820,0EcMasterDemoSyn1104729tAtEmLog_020:03:465
1027839820,0EcMasterDemoSyn1028929tAtEmLog_021:45:135
2912339810,0EcMasterDemoSyn2913329tAtEmLog_023:06:215
2442839810,0EcMasterDemoSyn2443829tAtEmLog_023:21:345
2253739810,0EcMasterDemoSyn2254729tAtEmLog_000:32:335
2215639810,0EcMasterDemoSyn2216629tAtEmLog_019:18:095
1742239800,0EcMasterDemoSyn1743329tAtEmLog_019:08:005
2974239590,0EcMasterDemoSyn29748-21ps22:30:504
158422340,0sleep10-21swapper/100:10:241
232672330,1sleep014-21ksoftirqd/022:27:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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