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2025-12-14 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Dec 14, 2025 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24028391740,0EcMasterDemoSyn24034-21ssh10:02:570
32082860,1sleep20-21swapper/211:02:122
634439830,0EcMasterDemoSyn635429tAtEmLog_011:39:185
548339830,0EcMasterDemoSyn549329tAtEmLog_012:14:485
1190239830,0EcMasterDemoSyn1191229tAtEmLog_010:48:365
1185139830,0EcMasterDemoSyn1186129tAtEmLog_007:35:545
640239820,0EcMasterDemoSyn641229tAtEmLog_008:36:465
478039820,0EcMasterDemoSyn479029tAtEmLog_007:20:425
3173239820,0EcMasterDemoSyn3174229tAtEmLog_008:21:335
2670939820,0EcMasterDemoSyn2671929tAtEmLog_009:12:165
2545639820,0EcMasterDemoSyn2546629tAtEmLog_011:13:575
2275539820,0EcMasterDemoSyn2276629tAtEmLog_009:27:275
2223039820,0EcMasterDemoSyn2224029tAtEmLog_008:01:165
1913439820,0EcMasterDemoSyn1914429tAtEmLog_007:51:085
1658339820,0EcMasterDemoSyn1659329tAtEmLog_010:33:235
1065339820,0EcMasterDemoSyn1066429tAtEmLog_011:59:355
97839810,0EcMasterDemoSyn98829tAtEmLog_010:08:015
713539810,0EcMasterDemoSyn714529tAtEmLog_007:25:475
381139810,0EcMasterDemoSyn382129tAtEmLog_009:17:195
2694339810,0EcMasterDemoSyn2695329tAtEmLog_008:11:245
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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