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2026-03-30 - 07:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Mar 30, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1914539910,0EcMasterDemoSyn1915529tAtEmLog_023:35:515
254952840,1sleep40-21swapper/423:21:304
94139830,0EcMasterDemoSyn95129tAtEmLog_023:25:435
2647139830,0EcMasterDemoSyn2648129tAtEmLog_019:27:235
1816239830,0EcMasterDemoSyn1817229tAtEmLog_021:49:225
3200339820,0EcMasterDemoSyn3201329tAtEmLog_022:14:435
2988339820,0EcMasterDemoSyn2989329tAtEmLog_020:43:275
2750439820,0EcMasterDemoSyn2751429tAtEmLog_020:38:225
2712339820,0EcMasterDemoSyn2713329tAtEmLog_022:29:565
3224039810,0EcMasterDemoSyn3225029tAtEmLog_020:48:315
2514239810,0EcMasterDemoSyn2515229tAtEmLog_020:33:185
2173339810,0EcMasterDemoSyn2174329tAtEmLog_019:17:135
1332239400,1EcMasterDemoSyn13328-21ps20:07:574
179622380,0sleep40-21swapper/419:10:144
2251039190,0EcMasterDemoSyn0-21swapper/522:45:085
2713499180,15tDemoTimingTask27795-21chrt22:30:115
1732899181,11cyclictest16-1pr/legacy22:24:503
1731499185,10cyclictest22202-21sh23:55:270
1731499180,14cyclictest9422-21sh23:13:060
1731499180,10cyclictest21082-21sh00:13:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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