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2026-02-25 - 07:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Wed Feb 25, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1809139930,0EcMasterDemoSyn1810129tAtEmLog_023:11:535
162072930,0sleep00-21swapper/021:24:300
1396539830,0EcMasterDemoSyn1397529tAtEmLog_022:51:365
1367639830,0EcMasterDemoSyn1368629tAtEmLog_019:43:595
2946339820,0EcMasterDemoSyn2947329tAtEmLog_019:08:285
2629439820,0EcMasterDemoSyn2630429tAtEmLog_023:52:275
260639820,0EcMasterDemoSyn261629tAtEmLog_000:33:015
184139820,0EcMasterDemoSyn185129tAtEmLog_019:18:365
1838939820,0EcMasterDemoSyn1839929tAtEmLog_019:54:075
1440339820,0EcMasterDemoSyn1441329tAtEmLog_020:54:585
3074739810,0EcMasterDemoSyn3075729tAtEmLog_000:12:445
3021039810,0EcMasterDemoSyn3022029tAtEmLog_020:19:275
258739810,0EcMasterDemoSyn259729tAtEmLog_020:29:375
258739810,0EcMasterDemoSyn259729tAtEmLog_020:29:365
2312339810,0EcMasterDemoSyn2313329tAtEmLog_020:04:155
1466439810,0EcMasterDemoSyn1467429tAtEmLog_021:40:365
1204439810,0EcMasterDemoSyn1205429tAtEmLog_020:49:535
2074639680,0EcMasterDemoSyn0-21swapper/219:59:112
405739640,0EcMasterDemoSyn0-21swapper/223:22:012
174062620,0sleep20-21swapper/200:05:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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