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2026-02-25 - 15:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Wed Feb 25, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1196739840,0EcMasterDemoSyn1197729tAtEmLog_007:49:065
1600239830,0EcMasterDemoSyn1601229tAtEmLog_011:32:145
349339820,0EcMasterDemoSyn350329tAtEmLog_008:39:495
2356039820,0EcMasterDemoSyn2357029tAtEmLog_010:06:025
2356039820,0EcMasterDemoSyn2357029tAtEmLog_010:06:015
2225739820,0EcMasterDemoSyn2226729tAtEmLog_010:41:305
1877139820,0EcMasterDemoSyn1878129tAtEmLog_012:28:015
2485839810,0EcMasterDemoSyn2486829tAtEmLog_007:08:335
1315739810,0EcMasterDemoSyn1316729tAtEmLog_010:36:275
2141439580,0EcMasterDemoSyn2142429tAtEmLog_008:14:265
55739560,0EcMasterDemoSyn0-21swapper/512:17:525
166542470,45sleep46047-21kworker/u24:1+flush-9:009:44:434
25083992624,2cyclictest26292-21kworker/4:1+events10:41:304
25083992420,3cyclictest16326-21turbostat11:15:004
1210939220,2EcMasterDemoSyn12106-21ssh11:11:573
2631529180,7tAtEmLog_02109-21chrt11:06:155
2506699181,13cyclictest780-21runrttasks07:55:590
2506699180,9cyclictest28024-21sh10:26:470
2506699180,9cyclictest16436-21sh09:44:320
2506699180,10cyclictest6528-21sh11:09:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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