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2026-08-23 - 10:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Aug 23, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
144639838470,0EcMasterDemoSyn0-21swapper/519:52:085
1505239198880,0EcMasterDemoSyn0-21swapper/523:25:145
303539142250,0EcMasterDemoSyn0-21swapper/521:37:065
2937339101880,0EcMasterDemoSyn0-21swapper/520:22:465
13913983330,0EcMasterDemoSyn0-21swapper/519:16:025
64453983270,0EcMasterDemoSyn0-21swapper/500:20:135
135573983240,0EcMasterDemoSyn0-21swapper/500:08:335
58683983200,0EcMasterDemoSyn0-21swapper/522:07:415
303003983200,0EcMasterDemoSyn0-21swapper/519:13:075
182033983200,0EcMasterDemoSyn0-21swapper/523:55:265
235023983180,0EcMasterDemoSyn0-21swapper/521:46:125
93573983160,0EcMasterDemoSyn0-21swapper/522:38:385
226773983130,0EcMasterDemoSyn0-21swapper/523:13:565
106033983120,0EcMasterDemoSyn0-21swapper/523:37:365
32263983100,0EcMasterDemoSyn0-21swapper/523:49:155
246843983050,0EcMasterDemoSyn0-21swapper/500:13:395
304803983040,0EcMasterDemoSyn0-21swapper/523:31:475
19933983030,0EcMasterDemoSyn0-21swapper/520:28:355
50333983020,0EcMasterDemoSyn0-21swapper/500:04:545
49923983000,0EcMasterDemoSyn671rcuc/522:50:395
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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