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2025-11-23 - 14:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Nov 23, 2025 12:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28951391420,1EcMasterDemoSyn28957-21ps11:38:273
1184521030,0sleep50-21swapper/511:00:195
571639900,0EcMasterDemoSyn0-21swapper/008:15:370
1369939830,0EcMasterDemoSyn13707-21runintdemo5min09:21:321
860839820,0EcMasterDemoSyn861829tAtEmLog_011:23:145
522039820,0EcMasterDemoSyn522929tAtEmLog_010:07:115
3104139820,0EcMasterDemoSyn3105129tAtEmLog_008:00:235
2895139820,0EcMasterDemoSyn2896129tAtEmLog_011:38:275
2556739820,0EcMasterDemoSyn2557729tAtEmLog_010:22:235
198039820,0EcMasterDemoSyn199029tAtEmLog_011:18:105
1704939820,0EcMasterDemoSyn1705929tAtEmLog_012:39:185
1369939820,0EcMasterDemoSyn1370929tAtEmLog_009:21:315
1187439820,0EcMasterDemoSyn1188429tAtEmLog_010:12:155
934739810,0EcMasterDemoSyn935729tAtEmLog_007:19:515
2213039810,0EcMasterDemoSyn2214029tAtEmLog_011:33:235
1785339810,0EcMasterDemoSyn1786329tAtEmLog_008:40:585
1750639810,0EcMasterDemoSyn1751629tAtEmLog_009:51:585
61539800,0EcMasterDemoSyn62629tAtEmLog_009:11:245
2895139620,0EcMasterDemoSyn2896129tAtEmLog_011:43:305
2125439280,1EcMasterDemoSyn21252-21ssh11:08:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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