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2026-07-16 - 15:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Jul 16, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2751139910,0EcMasterDemoSyn2752129tAtEmLog_007:21:205
1714639910,0EcMasterDemoSyn1715629tAtEmLog_008:06:585
236252880,0sleep20-21swapper/211:56:292
336939820,0EcMasterDemoSyn337929tAtEmLog_010:34:025
2986839820,0EcMasterDemoSyn2987829tAtEmLog_007:26:245
2975039820,0EcMasterDemoSyn2976029tAtEmLog_011:24:455
2666039820,0EcMasterDemoSyn2667029tAtEmLog_008:27:155
2192439820,0EcMasterDemoSyn2193429tAtEmLog_008:17:075
1969739820,0EcMasterDemoSyn1970729tAtEmLog_009:12:545
1955739820,0EcMasterDemoSyn1956729tAtEmLog_008:12:025
1654739820,0EcMasterDemoSyn1655729tAtEmLog_010:59:245
2901939810,0EcMasterDemoSyn2902929tAtEmLog_008:32:195
2430339810,0EcMasterDemoSyn2431329tAtEmLog_008:22:115
1767039810,0EcMasterDemoSyn1768029tAtEmLog_010:23:535
1479039780,0EcMasterDemoSyn14796-21ps08:01:543
1858539730,0EcMasterDemoSyn0-21swapper/209:48:232
1376639430,1EcMasterDemoSyn13772-21ps10:03:364
2048399226,7cyclictest27933-21ssh09:17:200
2048399220,9cyclictest32281-21sh11:07:350
2048399220,9cyclictest1398-21sh10:32:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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