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2026-01-21 - 23:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Wed Jan 21, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1209739970,0EcMasterDemoSyn1210829tAtEmLog_010:22:245
2138039920,0EcMasterDemoSyn2139029tAtEmLog_010:27:295
1490439920,0EcMasterDemoSyn1491429tAtEmLog_008:05:305
687939910,0EcMasterDemoSyn688929tAtEmLog_012:08:545
312722910,1sleep20-21swapper/207:35:142
1962739830,0EcMasterDemoSyn1963729tAtEmLog_008:15:395
1791639830,0EcMasterDemoSyn1792629tAtEmLog_011:38:295
1627039830,0EcMasterDemoSyn1628029tAtEmLog_010:42:425
3100539820,0EcMasterDemoSyn3101529tAtEmLog_007:35:055
3070939820,0EcMasterDemoSyn3071929tAtEmLog_010:32:335
1726039820,0EcMasterDemoSyn1727029tAtEmLog_008:10:345
1919339810,0EcMasterDemoSyn1920329tAtEmLog_009:31:435
2481739800,0EcMasterDemoSyn2482729tAtEmLog_012:19:035
245742750,0sleep30-21swapper/309:35:123
3194639380,5EcMasterDemoSyn31953-21grep09:57:044
281012330,0sleep50-21swapper/511:44:225
1209739230,1EcMasterDemoSyn0-21swapper/410:22:254
18641992117,3cyclictest23329-21turbostat07:20:010
1864199180,9cyclictest18739-21sh11:56:510
1864199180,10cyclictest9518-21sh11:51:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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