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2026-08-15 - 21:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat Aug 15, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
50439824870,1EcMasterDemoSyn0-21swapper/507:14:555
123239195200,0EcMasterDemoSyn0-21swapper/510:48:215
1108139149260,0EcMasterDemoSyn0-21swapper/510:52:425
1155639147440,0EcMasterDemoSyn0-21swapper/512:06:195
3262139110350,0EcMasterDemoSyn0-21swapper/507:49:555
126563990710,0EcMasterDemoSyn0-21swapper/507:26:565
287783983310,0EcMasterDemoSyn0-21swapper/510:31:145
287783983310,0EcMasterDemoSyn0-21swapper/510:31:145
275843983250,1EcMasterDemoSyn0-21swapper/507:44:045
300683983230,0EcMasterDemoSyn0-21swapper/508:20:315
294683983210,0EcMasterDemoSyn0-21swapper/509:33:455
188663983210,0EcMasterDemoSyn0-21swapper/509:43:345
57153983200,0EcMasterDemoSyn0-21swapper/509:22:495
136203983200,0EcMasterDemoSyn0-21swapper/512:36:545
38073983170,0EcMasterDemoSyn0-21swapper/511:04:245
257963983160,0EcMasterDemoSyn0-21swapper/508:51:315
56753983150,0EcMasterDemoSyn0-21swapper/512:04:085
232133983150,0EcMasterDemoSyn0-21swapper/507:39:415
196083983150,0EcMasterDemoSyn0-21swapper/510:56:245
285873983100,1EcMasterDemoSyn0-21swapper/510:02:065
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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