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2026-05-15 - 21:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri May 15, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14278391160,0EcMasterDemoSyn0-21swapper/410:22:104
14278391160,0EcMasterDemoSyn0-21swapper/410:22:104
3196039920,0EcMasterDemoSyn3197029tAtEmLog_011:43:185
502839850,0EcMasterDemoSyn503829tAtEmLog_010:17:065
1936839840,0EcMasterDemoSyn1937829tAtEmLog_008:15:245
3181039830,0EcMasterDemoSyn3182029tAtEmLog_008:40:455
1841039830,0EcMasterDemoSyn1842029tAtEmLog_011:17:575
885039820,0EcMasterDemoSyn886029tAtEmLog_009:01:025
2337639820,0EcMasterDemoSyn2338629tAtEmLog_011:02:445
1966439820,0EcMasterDemoSyn1967529tAtEmLog_009:31:275
1427839820,0EcMasterDemoSyn1428829tAtEmLog_010:22:105
1427839820,0EcMasterDemoSyn1428829tAtEmLog_010:22:105
2882939810,0EcMasterDemoSyn2883929tAtEmLog_009:36:325
2803739810,0EcMasterDemoSyn2804729tAtEmLog_007:29:465
1912639810,0EcMasterDemoSyn1913729tAtEmLog_010:06:585
1735339810,0EcMasterDemoSyn1736329tAtEmLog_012:28:585
1735339810,0EcMasterDemoSyn1736329tAtEmLog_012:28:575
852539660,0EcMasterDemoSyn0-21swapper/207:55:072
303332340,0sleep10-21swapper/110:13:281
1966439330,0EcMasterDemoSyn0-21swapper/109:31:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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