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2026-02-16 - 08:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Feb 16, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3068739950,0EcMasterDemoSyn3069829tAtEmLog_021:49:085
2613339920,4EcMasterDemoSyn26139-21ps21:28:512
178092900,0sleep10-21swapper/100:04:561
1218439860,0EcMasterDemoSyn1219429tAtEmLog_021:39:005
700139840,0EcMasterDemoSyn701129tAtEmLog_023:05:125
700139840,0EcMasterDemoSyn701129tAtEmLog_023:05:125
372339840,0EcMasterDemoSyn373329tAtEmLog_023:20:255
2090239830,0EcMasterDemoSyn2091429tAtEmLog_022:19:345
1386639830,0EcMasterDemoSyn1387629tAtEmLog_020:48:175
617139820,0EcMasterDemoSyn618229tAtEmLog_020:33:045
2439739820,0EcMasterDemoSyn2440729tAtEmLog_020:02:395
2196739820,0EcMasterDemoSyn2197729tAtEmLog_019:57:345
818739810,0EcMasterDemoSyn819729tAtEmLog_023:40:425
513839810,0EcMasterDemoSyn514829tAtEmLog_019:22:055
240139600,1EcMasterDemoSyn2408-21grep22:44:553
617139450,0EcMasterDemoSyn0-21swapper/020:33:040
2675439390,1EcMasterDemoSyn26760-21ps20:07:430
30758992219,2cyclictest2626-21kworker/3:1+events19:17:003
728029200,0tAtEmLog_00-21swapper/522:34:455
3075799200,10cyclictest6552-21ssh00:15:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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