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2026-07-30 - 09:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Jul 30, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1194039910,0EcMasterDemoSyn1195029tAtEmLog_019:57:365
560939830,0EcMasterDemoSyn561929tAtEmLog_023:30:345
2147139830,0EcMasterDemoSyn2148129tAtEmLog_000:16:135
1780039830,0EcMasterDemoSyn1781029tAtEmLog_023:55:555
559839820,0EcMasterDemoSyn560829tAtEmLog_020:53:235
2378439820,0EcMasterDemoSyn2379429tAtEmLog_020:22:575
1987639820,0EcMasterDemoSyn1988629tAtEmLog_021:13:395
1975239820,0EcMasterDemoSyn1976229tAtEmLog_019:06:545
87739810,0EcMasterDemoSyn88729tAtEmLog_020:43:145
745439810,0EcMasterDemoSyn746429tAtEmLog_022:19:355
692639810,0EcMasterDemoSyn693629tAtEmLog_019:47:275
554239810,0EcMasterDemoSyn555229tAtEmLog_021:23:485
3237239810,0EcMasterDemoSyn3238229tAtEmLog_023:45:475
3091139810,0EcMasterDemoSyn3092129tAtEmLog_020:38:105
2911039810,0EcMasterDemoSyn2912029tAtEmLog_023:25:315
2894339810,0EcMasterDemoSyn2895329tAtEmLog_021:18:445
2387239810,0EcMasterDemoSyn2388229tAtEmLog_023:05:135
218739810,0EcMasterDemoSyn219729tAtEmLog_019:37:195
1451939810,0EcMasterDemoSyn1452929tAtEmLog_023:35:395
1432139810,0EcMasterDemoSyn1433129tAtEmLog_020:02:405
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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