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2026-02-05 - 04:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Feb 05, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2862321000,1sleep4581rcuc/423:05:454
2305539920,0EcMasterDemoSyn2306529tAtEmLog_021:17:195
2076739920,0EcMasterDemoSyn2077729tAtEmLog_019:15:375
2387239910,0EcMasterDemoSyn2388229tAtEmLog_020:31:405
2387239910,0EcMasterDemoSyn2388229tAtEmLog_020:31:405
954039840,0EcMasterDemoSyn955029tAtEmLog_021:27:265
595239830,0EcMasterDemoSyn596229tAtEmLog_021:02:055
2860839830,0EcMasterDemoSyn2861829tAtEmLog_020:41:495
3022139820,0EcMasterDemoSyn3023129tAtEmLog_019:35:545
2795039820,0EcMasterDemoSyn2796029tAtEmLog_021:37:355
2359139820,0EcMasterDemoSyn2360129tAtEmLog_021:52:485
1840639820,0EcMasterDemoSyn1841629tAtEmLog_019:10:335
1677139820,0EcMasterDemoSyn1678129tAtEmLog_020:16:285
1440539820,0EcMasterDemoSyn1441529tAtEmLog_020:11:235
478139810,0EcMasterDemoSyn479129tAtEmLog_021:42:405
1882739810,0EcMasterDemoSyn1883729tAtEmLog_021:32:315
1402539810,0EcMasterDemoSyn1403529tAtEmLog_023:34:135
1646199220,9cyclictest28649-21sh22:48:570
1329129190,0tAtEmLog_00-21swapper/519:05:265
969599180,8tDemoTimingTask17787-21chrt22:42:425
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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