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2026-05-02 - 08:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat May 02, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3044321420,0sleep50-21swapper/523:52:585
248332920,0sleep20-21swapper/222:02:392
2074639920,0EcMasterDemoSyn2075629tAtEmLog_022:35:325
1545739910,0EcMasterDemoSyn1546729tAtEmLog_022:15:145
3151539900,0EcMasterDemoSyn3152529tAtEmLog_020:13:325
71039890,0EcMasterDemoSyn72629tAtEmLog_021:49:535
606439840,0EcMasterDemoSyn607429tAtEmLog_023:21:095
2341539840,0EcMasterDemoSyn2342529tAtEmLog_000:06:485
2020439840,0EcMasterDemoSyn2021429tAtEmLog_023:11:005
1030239840,0EcMasterDemoSyn1031129tAtEmLog_021:19:275
996139830,0EcMasterDemoSyn997129tAtEmLog_021:54:565
37439820,0EcMasterDemoSyn38429tAtEmLog_019:07:365
2171339820,0EcMasterDemoSyn2172329tAtEmLog_019:53:155
108139810,0EcMasterDemoSyn109129tAtEmLog_023:36:225
9102760,0sleep0151ktimers/023:00:240
266792240,0sleep20-21swapper/221:28:072
1517439210,0EcMasterDemoSyn15180-21ps23:26:140
65099181,13cyclictest16-1pr/legacy23:16:041
64799185,9cyclictest2327-21sh21:15:020
64799180,14cyclictest3519-21sh00:14:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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