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2026-08-02 - 11:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Aug 02, 2026 00:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16333395670,0EcMasterDemoSyn0-21swapper/519:32:575
16333391000,0EcMasterDemoSyn0-21swapper/419:27:534
554339920,0EcMasterDemoSyn555329tAtEmLog_021:49:525
3267939830,0EcMasterDemoSyn3268929tAtEmLog_022:05:055
2105239830,0EcMasterDemoSyn2106229tAtEmLog_019:38:025
1443739830,0EcMasterDemoSyn1444729tAtEmLog_022:30:275
1396439830,0EcMasterDemoSyn1397529tAtEmLog_000:01:435
890239820,0EcMasterDemoSyn891229tAtEmLog_022:45:395
2555739820,0EcMasterDemoSyn2556729tAtEmLog_021:24:315
2555739820,0EcMasterDemoSyn2556729tAtEmLog_021:24:315
2245739820,0EcMasterDemoSyn2246729tAtEmLog_020:49:015
1218039820,0EcMasterDemoSyn1219029tAtEmLog_023:05:575
923039810,0EcMasterDemoSyn924029tAtEmLog_019:12:415
923039810,0EcMasterDemoSyn924029tAtEmLog_019:12:405
2601039810,0EcMasterDemoSyn2602029tAtEmLog_000:27:055
1633339810,0EcMasterDemoSyn1634329tAtEmLog_019:27:545
1397139810,0EcMasterDemoSyn1398129tAtEmLog_019:22:495
1397139810,0EcMasterDemoSyn1398129tAtEmLog_019:22:495
311462790,1sleep383-21kcompactd000:11:283
17322660,0sleep2391rcuc/222:24:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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