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2026-08-09 - 01:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat Aug 08, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1255139108810,0EcMasterDemoSyn0-21swapper/512:09:355
84683983270,0EcMasterDemoSyn0-21swapper/512:36:295
230973983260,0EcMasterDemoSyn0-21swapper/512:14:175
134553983070,0EcMasterDemoSyn0-21swapper/511:10:585
115923983000,0EcMasterDemoSyn0-21swapper/511:39:445
179563982990,0EcMasterDemoSyn0-21swapper/511:56:495
280533982980,0EcMasterDemoSyn0-21swapper/511:46:385
28819391160,0EcMasterDemoSyn0-21swapper/311:03:383
2990039920,0EcMasterDemoSyn2991029tAtEmLog_011:33:075
57039910,0EcMasterDemoSyn58029tAtEmLog_012:33:105
2803339910,0EcMasterDemoSyn2804329tAtEmLog_011:17:505
1886339890,0EcMasterDemoSyn1887329tAtEmLog_010:59:165
134542850,0sleep50-21swapper/511:25:255
2956439840,0EcMasterDemoSyn2957429tAtEmLog_007:19:035
1882239840,0EcMasterDemoSyn1883229tAtEmLog_011:42:365
372339830,0EcMasterDemoSyn373329tAtEmLog_008:40:105
363539830,0EcMasterDemoSyn364529tAtEmLog_011:06:335
3096139830,0EcMasterDemoSyn3097129tAtEmLog_012:17:305
1953839830,0EcMasterDemoSyn1954829tAtEmLog_012:26:585
1102239830,0EcMasterDemoSyn1103229tAtEmLog_012:23:205
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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