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2026-09-04 - 01:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Sep 03, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1595139247930,0EcMasterDemoSyn0-21swapper/512:02:255
1736339225070,0EcMasterDemoSyn0-21swapper/510:05:335
3142139165400,0EcMasterDemoSyn0-21swapper/512:24:385
2081139135420,0EcMasterDemoSyn0-21swapper/507:55:525
311833999320,0EcMasterDemoSyn0-21swapper/507:32:345
163803996930,0EcMasterDemoSyn0-21swapper/508:26:305
298883983310,0EcMasterDemoSyn0-21swapper/508:05:455
143203983240,0EcMasterDemoSyn0-21swapper/511:17:375
46353983220,0EcMasterDemoSyn0-21swapper/511:27:505
72143983210,0EcMasterDemoSyn0-21swapper/507:40:565
78113983190,0EcMasterDemoSyn0-21swapper/508:18:065
184783983180,0EcMasterDemoSyn0-21swapper/509:51:425
6623983170,0EcMasterDemoSyn0-21swapper/509:44:045
245943983160,0EcMasterDemoSyn0-21swapper/510:52:525
124813983160,0EcMasterDemoSyn0-21swapper/510:32:515
177793983120,0EcMasterDemoSyn0-21swapper/507:18:435
189163983100,0EcMasterDemoSyn0-21swapper/512:18:485
153423983100,0EcMasterDemoSyn0-21swapper/510:48:525
260603983080,0EcMasterDemoSyn0-21swapper/511:52:135
60503983070,0EcMasterDemoSyn0-21swapper/510:00:275
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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