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2026-02-20 - 11:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Feb 20, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22906391600,0EcMasterDemoSyn0-21swapper/123:46:401
17770391100,3EcMasterDemoSyn17776-21runintdemo5min21:39:534
392939910,0EcMasterDemoSyn393929tAtEmLog_020:18:455
3203439830,0EcMasterDemoSyn3204529tAtEmLog_023:51:445
3155939820,0EcMasterDemoSyn3156929tAtEmLog_020:08:365
287739820,0EcMasterDemoSyn288729tAtEmLog_019:07:465
2297739820,0EcMasterDemoSyn2298729tAtEmLog_022:00:105
1945039820,0EcMasterDemoSyn1946029tAtEmLog_019:43:155
1511939820,0EcMasterDemoSyn1512929tAtEmLog_022:30:365
1379839820,0EcMasterDemoSyn1380829tAtEmLog_023:41:365
2877739810,0EcMasterDemoSyn2878729tAtEmLog_022:55:575
2792239810,0EcMasterDemoSyn2793229tAtEmLog_023:31:275
2552039810,0EcMasterDemoSyn2553029tAtEmLog_021:04:225
1707039810,0EcMasterDemoSyn1708029tAtEmLog_019:38:115
3177239660,0EcMasterDemoSyn3178229tAtEmLog_021:34:485
251712590,0sleep40-21swapper/421:00:234
861039490,0EcMasterDemoSyn8616-21runintdemo5min21:34:493
1234839350,1EcMasterDemoSyn12355-21runintdemo5min19:28:023
313899200,8cyclictest32231-21ssh23:51:503
313899190,8cyclictest27785-21wget21:45:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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