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2026-06-25 - 07:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Jun 25, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1754739920,0EcMasterDemoSyn1755729tAtEmLog_020:54:415
608539840,0EcMasterDemoSyn609729tAtEmLog_023:21:445
2038139830,0EcMasterDemoSyn2039129tAtEmLog_021:25:065
1227239830,0EcMasterDemoSyn1228229tAtEmLog_021:55:325
1022639830,0EcMasterDemoSyn1023729tAtEmLog_023:42:015
2877539820,0EcMasterDemoSyn2878529tAtEmLog_023:52:095
1862739820,0EcMasterDemoSyn1863729tAtEmLog_019:48:445
1682739820,0EcMasterDemoSyn1683729tAtEmLog_022:15:495
1456739820,0EcMasterDemoSyn1457729tAtEmLog_000:02:185
1456739820,0EcMasterDemoSyn1457729tAtEmLog_000:02:185
3204739810,0EcMasterDemoSyn3205729tAtEmLog_019:08:105
2807339810,0EcMasterDemoSyn2808329tAtEmLog_020:09:025
2603339810,0EcMasterDemoSyn2604329tAtEmLog_022:20:535
2591839810,0EcMasterDemoSyn2592829tAtEmLog_021:45:235
2334039810,0EcMasterDemoSyn2335029tAtEmLog_019:58:545
1995839810,0EcMasterDemoSyn1996829tAtEmLog_020:59:455
1621539810,0EcMasterDemoSyn1622529tAtEmLog_019:43:415
1383839810,0EcMasterDemoSyn1384829tAtEmLog_019:38:365
50862300,0sleep00-21swapper/020:25:200
3273239200,4EcMasterDemoSyn0-21swapper/500:12:265
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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