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2025-11-30 - 15:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Nov 30, 2025 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17299391510,1EcMasterDemoSyn17308-21runintdemo5min08:01:053
948391150,1EcMasterDemoSyn957-21wc09:22:131
3250439930,0EcMasterDemoSyn3251429tAtEmLog_011:54:215
2045239930,0EcMasterDemoSyn2046229tAtEmLog_009:37:265
2260339910,0EcMasterDemoSyn2261329tAtEmLog_007:05:185
2286839840,0EcMasterDemoSyn2287829tAtEmLog_012:09:345
266139830,0EcMasterDemoSyn267129tAtEmLog_010:12:575
1421239830,0EcMasterDemoSyn1422229tAtEmLog_009:01:575
785039820,1EcMasterDemoSyn786029tAtEmLog_011:59:265
440739820,0EcMasterDemoSyn441729tAtEmLog_008:41:395
273939820,0EcMasterDemoSyn274929tAtEmLog_012:40:005
273939820,0EcMasterDemoSyn274929tAtEmLog_012:39:595
2157539820,0EcMasterDemoSyn2158529tAtEmLog_010:02:475
1657139820,0EcMasterDemoSyn1658129tAtEmLog_009:07:015
1491739820,0EcMasterDemoSyn1492729tAtEmLog_007:56:025
1256139820,0EcMasterDemoSyn1257129tAtEmLog_007:50:575
1150739820,0EcMasterDemoSyn1151729tAtEmLog_011:13:485
1056739820,0EcMasterDemoSyn1057729tAtEmLog_011:39:095
1015139820,0EcMasterDemoSyn1016129tAtEmLog_007:45:535
3057439810,0EcMasterDemoSyn3058429tAtEmLog_007:20:315
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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