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2026-07-31 - 22:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Jul 31, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32440391070,2EcMasterDemoSyn0-21swapper/110:14:541
865639930,0EcMasterDemoSyn866629tAtEmLog_008:58:505
2296739900,0EcMasterDemoSyn2297729tAtEmLog_010:45:185
103842900,0sleep50-21swapper/510:20:155
929139830,0EcMasterDemoSyn930129tAtEmLog_010:19:585
496139830,0EcMasterDemoSyn497129tAtEmLog_007:42:465
3160539830,0EcMasterDemoSyn3161529tAtEmLog_008:38:335
3008839830,0EcMasterDemoSyn3009829tAtEmLog_007:27:335
2872939830,0EcMasterDemoSyn2873929tAtEmLog_009:54:375
404839820,0EcMasterDemoSyn405829tAtEmLog_010:35:115
257539820,0EcMasterDemoSyn258529tAtEmLog_007:37:415
2131439820,0EcMasterDemoSyn2132429tAtEmLog_009:14:035
2056939820,0EcMasterDemoSyn2057929tAtEmLog_007:07:175
1943239820,0EcMasterDemoSyn1944229tAtEmLog_011:56:185
1798739820,0EcMasterDemoSyn1799729tAtEmLog_011:00:325
1133439820,0EcMasterDemoSyn1134429tAtEmLog_009:03:545
1055839820,0EcMasterDemoSyn1056829tAtEmLog_011:51:145
629639810,0EcMasterDemoSyn630629tAtEmLog_008:53:455
3244039810,0EcMasterDemoSyn3245029tAtEmLog_010:14:545
2869739810,0EcMasterDemoSyn2870729tAtEmLog_012:01:225
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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