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2026-03-05 - 07:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Mar 05, 2026 00:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28306391590,0EcMasterDemoSyn0-21swapper/300:28:593
12331391160,1EcMasterDemoSyn12336-21runintdemo5min20:45:520
1721721100,0sleep00-21swapper/023:46:240
88621030,1sleep50-21swapper/523:55:185
129572940,0sleep00-21swapper/023:26:030
2486039900,0EcMasterDemoSyn2487029tAtEmLog_020:05:185
1417139900,0EcMasterDemoSyn1418129tAtEmLog_000:39:085
1097839840,0EcMasterDemoSyn1098829tAtEmLog_023:43:225
1638439830,0EcMasterDemoSyn1639429tAtEmLog_022:17:095
432639820,0EcMasterDemoSyn433629tAtEmLog_019:24:445
2505139820,0EcMasterDemoSyn2506129tAtEmLog_023:33:135
2183339820,0EcMasterDemoSyn2184329tAtEmLog_021:06:105
1469039820,0EcMasterDemoSyn1470029tAtEmLog_020:50:575
997439810,0EcMasterDemoSyn998429tAtEmLog_020:40:475
3193939810,0EcMasterDemoSyn3194929tAtEmLog_019:14:355
2956739810,0EcMasterDemoSyn2957729tAtEmLog_019:09:305
1140339810,0EcMasterDemoSyn1141329tAtEmLog_019:39:565
2998639560,0EcMasterDemoSyn0-21swapper/123:18:001
1922839510,1EcMasterDemoSyn19237-21runintdemo5min00:23:563
29710992320,2cyclictest32352-21kworker/1:0+events23:53:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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