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2026-05-23 - 20:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat May 23, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2999339890,0EcMasterDemoSyn3000329tAtEmLog_007:20:335
178462890,0sleep50-21swapper/510:20:215
949439830,0EcMasterDemoSyn950429tAtEmLog_008:51:495
472439830,0EcMasterDemoSyn473429tAtEmLog_008:41:415
1282739830,0EcMasterDemoSyn1283729tAtEmLog_009:42:325
2232739820,0EcMasterDemoSyn2233729tAtEmLog_008:11:155
1433739820,0EcMasterDemoSyn1434729tAtEmLog_007:56:035
1422839820,0EcMasterDemoSyn1423829tAtEmLog_009:01:585
1198039820,0EcMasterDemoSyn1199029tAtEmLog_007:50:585
114539820,0EcMasterDemoSyn115629tAtEmLog_012:34:565
726839810,0EcMasterDemoSyn727829tAtEmLog_007:40:505
3161839810,0EcMasterDemoSyn3162829tAtEmLog_009:17:105
2664739810,0EcMasterDemoSyn2665729tAtEmLog_010:43:245
2523939810,0EcMasterDemoSyn2524929tAtEmLog_007:10:245
2199639810,0EcMasterDemoSyn2200629tAtEmLog_009:47:365
204339810,0EcMasterDemoSyn205329tAtEmLog_008:36:365
1253739810,0EcMasterDemoSyn1254729tAtEmLog_010:53:315
2330699190,10cyclictest780-21runrttasks11:03:210
635529180,7tAtEmLog_09902-21chrt12:20:495
2572429180,7tAtEmLog_031759-21chrt11:21:325
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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