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2026-06-30 - 19:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Jun 30, 2026 12:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23628391000,2EcMasterDemoSyn41-21ksoftirqd/210:31:512
1354039920,0EcMasterDemoSyn1355029tAtEmLog_008:25:045
2506039840,0EcMasterDemoSyn2507029tAtEmLog_012:38:375
232739840,0EcMasterDemoSyn233729tAtEmLog_009:05:385
3084439830,0EcMasterDemoSyn3085429tAtEmLog_007:54:385
1778139830,0EcMasterDemoSyn1779129tAtEmLog_011:22:335
108939830,0EcMasterDemoSyn109929tAtEmLog_007:59:435
973339820,0EcMasterDemoSyn974329tAtEmLog_010:06:305
849539820,0EcMasterDemoSyn850629tAtEmLog_008:14:555
562739820,0EcMasterDemoSyn563729tAtEmLog_009:10:425
2728239820,0EcMasterDemoSyn2729229tAtEmLog_008:50:255
2362839820,0EcMasterDemoSyn2363829tAtEmLog_010:31:505
874039810,0EcMasterDemoSyn875029tAtEmLog_007:09:005
3237939810,0EcMasterDemoSyn3238929tAtEmLog_009:00:355
2635539810,0EcMasterDemoSyn2636729tAtEmLog_012:03:075
1886839810,0EcMasterDemoSyn1887829tAtEmLog_010:11:335
1620039810,0EcMasterDemoSyn1621029tAtEmLog_008:30:085
347039800,0EcMasterDemoSyn348029tAtEmLog_008:04:475
2848639380,1EcMasterDemoSyn28495-21wc07:49:343
2848639380,1EcMasterDemoSyn28495-21wc07:49:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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