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2026-02-14 - 17:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat Feb 14, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1821139920,0EcMasterDemoSyn1822129tAtEmLog_009:03:235
2987539840,0EcMasterDemoSyn2988529tAtEmLog_007:11:495
459339830,0EcMasterDemoSyn460329tAtEmLog_009:18:355
1803139830,0EcMasterDemoSyn1804129tAtEmLog_012:05:565
879139820,0EcMasterDemoSyn880129tAtEmLog_010:14:225
3235839820,0EcMasterDemoSyn3236829tAtEmLog_011:20:175
2370039820,0EcMasterDemoSyn2371029tAtEmLog_008:07:365
135539820,0EcMasterDemoSyn136529tAtEmLog_008:27:525
1347639820,0EcMasterDemoSyn1348629tAtEmLog_008:53:145
396439810,0EcMasterDemoSyn397429tAtEmLog_011:05:055
383539810,0EcMasterDemoSyn384529tAtEmLog_012:16:055
3223539810,0EcMasterDemoSyn3224529tAtEmLog_009:33:485
2750339810,0EcMasterDemoSyn2751329tAtEmLog_007:06:455
23532810,0sleep20-21swapper/210:28:142
3223239800,0EcMasterDemoSyn3224329tAtEmLog_007:16:535
3223239800,0EcMasterDemoSyn3224329tAtEmLog_007:16:525
2717139720,1EcMasterDemoSyn27177-21ps12:11:013
2872539410,1EcMasterDemoSyn28733-21grep08:17:443
436139250,2EcMasterDemoSyn0-21swapper/109:54:051
27857992212,9cyclictest13267-21cron12:40:004
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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