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2026-01-13 - 02:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Jan 13, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2790739840,0EcMasterDemoSyn2791729tAtEmLog_023:57:455
3159239830,0EcMasterDemoSyn3160229tAtEmLog_020:34:565
1641539830,0EcMasterDemoSyn1642529tAtEmLog_021:45:555
1566139830,0EcMasterDemoSyn1567129tAtEmLog_022:56:545
1467439830,0EcMasterDemoSyn1468429tAtEmLog_019:59:265
996239820,0EcMasterDemoSyn997229tAtEmLog_019:49:175
567539820,0EcMasterDemoSyn568529tAtEmLog_023:27:205
2899539820,0EcMasterDemoSyn2900529tAtEmLog_023:22:165
2284839820,0EcMasterDemoSyn2285829tAtEmLog_019:08:435
2212339820,0EcMasterDemoSyn2213329tAtEmLog_020:14:385
522939810,0EcMasterDemoSyn523929tAtEmLog_019:39:095
3026339810,0EcMasterDemoSyn3027329tAtEmLog_019:23:565
2586539810,0EcMasterDemoSyn2587529tAtEmLog_021:15:295
2285739810,0EcMasterDemoSyn2286729tAtEmLog_000:12:585
377439800,0EcMasterDemoSyn378429tAtEmLog_000:38:195
1195039570,0EcMasterDemoSyn1196029tAtEmLog_021:30:415
42842220,0sleep40-21swapper/419:35:174
2305399200,9cyclictest27799-21ssh21:16:484
2305399200,10cyclictest5970-21ssh22:51:274
2305399200,10cyclictest10939-21ssh23:48:294
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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