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2026-02-26 - 11:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Feb 26, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2255321530,0sleep50-21swapper/523:50:425
8762391280,0EcMasterDemoSyn0-21swapper/121:55:561
8762391280,0EcMasterDemoSyn0-21swapper/121:55:561
13006391190,3EcMasterDemoSyn13012-21ps20:55:042
248042960,0sleep40-21swapper/422:40:284
3053839920,0EcMasterDemoSyn3054829tAtEmLog_020:24:395
284839830,0EcMasterDemoSyn285929tAtEmLog_020:34:475
2741339820,1EcMasterDemoSyn2742329tAtEmLog_019:08:345
1162839820,0EcMasterDemoSyn1163829tAtEmLog_019:44:055
2816039810,0EcMasterDemoSyn2817029tAtEmLog_020:19:355
2583339810,0EcMasterDemoSyn2584329tAtEmLog_023:17:045
2579239810,0EcMasterDemoSyn2580229tAtEmLog_020:14:295
2432739810,0EcMasterDemoSyn2433729tAtEmLog_000:28:045
1633939810,0EcMasterDemoSyn1634929tAtEmLog_019:54:125
63662310,1sleep10-21swapper/123:42:011
168872240,6sleep132-21ksoftirqd/121:00:241
27628992010,8cyclictest32761-21cron22:10:012
2762899200,7cyclictest2566-21chrt20:31:072
403329190,0tAtEmLog_00-21swapper/521:40:415
2762899193,6cyclictest17211-21fschecks_time19:55:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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