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2026-02-21 - 00:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Feb 20, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
648839920,0EcMasterDemoSyn649829tAtEmLog_007:38:215
809039830,0EcMasterDemoSyn810029tAtEmLog_011:26:345
2926239820,0EcMasterDemoSyn2927229tAtEmLog_007:18:055
1635239820,0EcMasterDemoSyn1636229tAtEmLog_007:58:395
1399339820,0EcMasterDemoSyn1400329tAtEmLog_007:53:345
1176839820,0EcMasterDemoSyn1177829tAtEmLog_012:22:215
3240539810,0EcMasterDemoSyn3241529tAtEmLog_010:10:305
3240539810,0EcMasterDemoSyn3241529tAtEmLog_010:10:295
3180339810,0EcMasterDemoSyn3181329tAtEmLog_010:46:005
235639810,0EcMasterDemoSyn236629tAtEmLog_012:17:165
159039810,0EcMasterDemoSyn160029tAtEmLog_007:28:145
1474539810,0EcMasterDemoSyn1475529tAtEmLog_009:04:345
887339440,1EcMasterDemoSyn8882-21wc07:43:262
316032320,1sleep50-21swapper/509:35:135
218782240,3sleep014-21ksoftirqd/010:05:140
1704739230,0EcMasterDemoSyn0-21swapper/309:45:073
2447099213,9cyclictest29589-21latency_hist07:19:591
24476992018,2cyclictest31951-21kworker/4:2+events12:37:344
2447099206,7cyclictest15846-21ssh10:37:301
2447099200,10cyclictest20387-21ssh10:57:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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