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2026-07-24 - 09:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Jul 24, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10426391030,0EcMasterDemoSyn0-21swapper/219:54:032
1628839920,0EcMasterDemoSyn1629829tAtEmLog_022:41:225
1848539830,0EcMasterDemoSyn1849529tAtEmLog_000:32:565
867139820,0EcMasterDemoSyn868129tAtEmLog_023:32:055
731239820,0EcMasterDemoSyn732229tAtEmLog_022:36:185
62139820,0EcMasterDemoSyn63129tAtEmLog_019:33:455
407839820,0EcMasterDemoSyn408829tAtEmLog_020:49:485
3214339820,0EcMasterDemoSyn3215329tAtEmLog_021:55:445
643839810,0EcMasterDemoSyn644829tAtEmLog_020:54:535
503739810,0EcMasterDemoSyn504729tAtEmLog_021:40:325
3224539810,0EcMasterDemoSyn3225529tAtEmLog_021:20:155
2830539810,0EcMasterDemoSyn2831529tAtEmLog_019:23:365
1802039810,0EcMasterDemoSyn1803029tAtEmLog_022:05:525
2841239800,0EcMasterDemoSyn2842229tAtEmLog_021:35:275
2323339800,0EcMasterDemoSyn2324329tAtEmLog_021:15:105
172339800,0EcMasterDemoSyn173329tAtEmLog_020:44:455
21417992316,6cyclictest16980-21cron21:30:002
2141299230,9cyclictest780-21runrttasks23:24:220
2141299230,10cyclictest27748-21sh21:17:140
2141299230,10cyclictest24394-21sh23:59:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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