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2026-01-13 - 20:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Jan 13, 2026 12:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2261739830,0EcMasterDemoSyn2262729tAtEmLog_012:38:245
431539820,0EcMasterDemoSyn432529tAtEmLog_012:28:155
2892739820,0EcMasterDemoSyn2893729tAtEmLog_011:47:415
1586539820,0EcMasterDemoSyn1587529tAtEmLog_007:18:555
1578539820,0EcMasterDemoSyn1579529tAtEmLog_011:22:205
2766539810,0EcMasterDemoSyn2767529tAtEmLog_012:23:115
1326739810,0EcMasterDemoSyn1327729tAtEmLog_012:33:195
343039580,0EcMasterDemoSyn344029tAtEmLog_009:51:025
343039580,0EcMasterDemoSyn344029tAtEmLog_009:51:025
1339439560,0EcMasterDemoSyn1340429tAtEmLog_008:29:535
161492490,0sleep20-21swapper/209:53:312
161492490,0sleep20-21swapper/209:53:312
3792290,1sleep20-21swapper/210:02:272
162112250,0sleep20-21swapper/211:22:362
877439240,1EcMasterDemoSyn11120-21chrt07:08:465
2207639240,0EcMasterDemoSyn22082-21runintdemo5min09:20:370
557539220,1EcMasterDemoSyn5580-21runintdemo5min08:04:330
11322992011,3cyclictest731-21gdbus08:00:001
11322992011,3cyclictest731-21gdbus07:59:591
11317992017,2cyclictest18374-21turbostat07:25:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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