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2026-07-31 - 10:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Jul 31, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3137391320,0EcMasterDemoSyn0-21swapper/020:48:310
15608391200,1EcMasterDemoSyn15616-21runintdemo5min00:31:393
754139930,0EcMasterDemoSyn755129tAtEmLog_022:19:485
2337839930,0EcMasterDemoSyn2338829tAtEmLog_020:23:105
139152890,0sleep00-21swapper/022:40:500
2547839840,1EcMasterDemoSyn2548729tAtEmLog_022:29:555
579539830,0EcMasterDemoSyn580529tAtEmLog_020:53:355
446239830,0EcMasterDemoSyn447229tAtEmLog_019:42:375
355639830,0EcMasterDemoSyn356829tAtEmLog_000:06:175
1288939830,0EcMasterDemoSyn1289929tAtEmLog_021:08:485
815239820,0EcMasterDemoSyn816229tAtEmLog_020:58:395
77139820,0EcMasterDemoSyn78229tAtEmLog_020:43:265
2514539820,0EcMasterDemoSyn2515529tAtEmLog_023:05:265
2384539820,0EcMasterDemoSyn2385529tAtEmLog_023:40:565
2135839820,0EcMasterDemoSyn2136829tAtEmLog_000:16:265
1245939820,0EcMasterDemoSyn1247029tAtEmLog_000:11:225
2503739810,0EcMasterDemoSyn2504729tAtEmLog_019:17:155
2018239810,0EcMasterDemoSyn2019229tAtEmLog_023:20:395
1627239810,0EcMasterDemoSyn1628229tAtEmLog_020:07:585
323822550,0sleep40-21swapper/420:40:174
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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