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2026-03-05 - 19:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Mar 05, 2026 12:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2184392810,0EcMasterDemoSyn0-21swapper/509:56:555
28060391140,0EcMasterDemoSyn0-21swapper/211:58:382
882139960,0EcMasterDemoSyn0-21swapper/112:23:591
882139960,0EcMasterDemoSyn0-21swapper/112:23:591
2100139940,1EcMasterDemoSyn21009-21grep09:31:350
2037239930,0EcMasterDemoSyn2038229tAtEmLog_010:42:345
276239900,0EcMasterDemoSyn277229tAtEmLog_008:45:565
128939820,0EcMasterDemoSyn129929tAtEmLog_011:07:555
34639810,0EcMasterDemoSyn35929tAtEmLog_008:40:525
2903939810,0EcMasterDemoSyn2904929tAtEmLog_007:29:525
1895539810,0EcMasterDemoSyn1896529tAtEmLog_011:53:345
1226639560,0EcMasterDemoSyn1227629tAtEmLog_009:11:175
214192490,0sleep30-21swapper/311:36:293
179482280,0sleep40-21swapper/411:52:514
27122220,0sleep40-21swapper/409:57:154
1969499197,4cyclictest27015-21ssh09:17:181
1969399190,16cyclictest21010-21sh11:36:110
163362190,0sleep40-21swapper/409:46:504
1969599181,13cyclictest16-1pr/legacy10:27:202
1969499183,7cyclictest18304-21ssh12:29:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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