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2025-08-29 - 14:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Aug 29, 2025 12:45:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226633913970,0EcMasterDemoSyn22671-21runintdemo5min10:58:506
23630291170,116tAtEmLog_02362039EcMasterDemoSyn08:26:423
3125339920,0EcMasterDemoSyn3126329tAtEmLog_008:36:523
3125339920,0EcMasterDemoSyn3126329tAtEmLog_008:36:523
600839870,0EcMasterDemoSyn601829tAtEmLog_009:27:343
548539870,0EcMasterDemoSyn549529tAtEmLog_007:46:103
2203339870,0EcMasterDemoSyn2204329tAtEmLog_007:15:443
1854939870,0EcMasterDemoSyn1855929tAtEmLog_010:03:033
1697339870,0EcMasterDemoSyn1698329tAtEmLog_010:28:243
366239860,0EcMasterDemoSyn367229tAtEmLog_011:34:193
3253439860,0EcMasterDemoSyn3254429tAtEmLog_007:36:013
2105639860,0EcMasterDemoSyn2106629tAtEmLog_008:16:353
1814239860,0EcMasterDemoSyn1815229tAtEmLog_011:44:283
1814239860,0EcMasterDemoSyn1815229tAtEmLog_011:44:283
1693239860,0EcMasterDemoSyn1694229tAtEmLog_007:05:353
1665639860,0EcMasterDemoSyn1666629tAtEmLog_011:19:083
1086639860,0EcMasterDemoSyn1087629tAtEmLog_007:56:183
953239850,0EcMasterDemoSyn954229tAtEmLog_010:48:413
845539850,0EcMasterDemoSyn846529tAtEmLog_011:59:403
396139850,0EcMasterDemoSyn397129tAtEmLog_008:47:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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