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2026-05-09 - 08:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat May 09, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7197391450,0EcMasterDemoSyn0-21swapper/121:05:221
8081391330,0EcMasterDemoSyn0-21swapper/123:32:251
871121010,0sleep10-21swapper/123:50:231
2357639940,0EcMasterDemoSyn2358629tAtEmLog_020:34:555
13852940,0sleep10-21swapper/123:46:301
1942339930,0EcMasterDemoSyn1943329tAtEmLog_021:51:005
1456039910,0EcMasterDemoSyn1457029tAtEmLog_022:06:135
3069239900,0EcMasterDemoSyn3070229tAtEmLog_000:02:505
220182890,0sleep50-21swapper/500:15:335
2793339870,0EcMasterDemoSyn2794329tAtEmLog_022:31:345
1714639840,0EcMasterDemoSyn1715629tAtEmLog_019:13:485
2906439830,0EcMasterDemoSyn2907429tAtEmLog_021:20:345
1051539830,0EcMasterDemoSyn1052529tAtEmLog_021:10:265
2962239820,0EcMasterDemoSyn2963229tAtEmLog_019:39:085
1885839820,0EcMasterDemoSyn1886829tAtEmLog_020:24:485
3200039810,0EcMasterDemoSyn3201029tAtEmLog_019:44:145
2891439810,0EcMasterDemoSyn2892429tAtEmLog_020:45:055
1503039810,0EcMasterDemoSyn1504029tAtEmLog_021:30:425
1414739810,0EcMasterDemoSyn1415729tAtEmLog_022:41:425
192332590,0sleep40-21swapper/423:38:554
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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