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2025-12-11 - 03:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Dec 11, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
481839830,0EcMasterDemoSyn482829tAtEmLog_022:04:075
2272339830,0EcMasterDemoSyn2273329tAtEmLog_022:59:555
403939820,0EcMasterDemoSyn404929tAtEmLog_019:26:555
3105839820,0EcMasterDemoSyn3106829tAtEmLog_000:36:145
2956339820,0EcMasterDemoSyn2957329tAtEmLog_021:59:045
2024339820,0EcMasterDemoSyn2025329tAtEmLog_023:20:115
1482339820,0EcMasterDemoSyn1483329tAtEmLog_020:58:125
3125239810,0EcMasterDemoSyn3126229tAtEmLog_021:38:465
281139810,0EcMasterDemoSyn282129tAtEmLog_022:24:255
2357639810,0EcMasterDemoSyn2358629tAtEmLog_021:33:425
2197539810,0EcMasterDemoSyn2198529tAtEmLog_021:53:595
1974839810,0EcMasterDemoSyn1975829tAtEmLog_023:40:285
1528239810,0EcMasterDemoSyn1529229tAtEmLog_022:54:505
3035139410,0EcMasterDemoSyn481rcuc/320:22:433
271639230,0EcMasterDemoSyn0-21swapper/520:32:505
2197539210,1EcMasterDemoSyn21984-21wc21:53:592
27281992018,2cyclictest26221-21kworker/4:0+events21:08:194
2726099206,10cyclictest1438-21sh00:39:160
2726099190,14cyclictest8129-21cat20:45:010
2727799181,7cyclictest1737850latency_hist21:05:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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