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2026-07-28 - 03:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Jul 28, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
670039920,0EcMasterDemoSyn671029tAtEmLog_020:13:155
164939830,0EcMasterDemoSyn165929tAtEmLog_023:15:485
797039820,0EcMasterDemoSyn798029tAtEmLog_019:07:205
2567639820,0EcMasterDemoSyn2568629tAtEmLog_020:53:495
2221739820,0EcMasterDemoSyn2222729tAtEmLog_000:21:445
2096039820,0EcMasterDemoSyn2097029tAtEmLog_020:43:405
1145339820,0EcMasterDemoSyn1146329tAtEmLog_020:23:235
2761839810,0EcMasterDemoSyn2762829tAtEmLog_000:06:315
1683339810,0EcMasterDemoSyn1684329tAtEmLog_000:36:565
1313739810,0EcMasterDemoSyn1314729tAtEmLog_000:16:395
138822690,1sleep350-21ksoftirqd/300:17:103
49242410,0sleep10-21swapper/121:11:491
3041139230,0EcMasterDemoSyn0-21swapper/521:03:575
306572220,0sleep20-21swapper/221:25:422
826799196,9cyclictest32648-21sh23:51:110
826799196,9cyclictest17866-21sh21:19:350
828099181,13cyclictest16-1pr/legacy19:47:513
826799180,14cyclictest28177-21sh21:25:060
826799180,10cyclictest30387-21sh22:01:490
826799180,10cyclictest30387-21sh22:01:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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