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2026-05-03 - 16:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun May 03, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15002391290,3EcMasterDemoSyn651irq_work/512:22:275
30685391210,0EcMasterDemoSyn0-21swapper/309:14:493
29284391070,0EcMasterDemoSyn0-21swapper/312:12:173
905339940,0EcMasterDemoSyn906129tAtEmLog_010:30:535
8942930,0sleep10-21swapper/109:33:451
255342900,0sleep50-21swapper/509:29:425
50632840,0sleep40-21swapper/412:35:124
1231339840,0EcMasterDemoSyn1232229tAtEmLog_009:40:115
400839820,0EcMasterDemoSyn401829tAtEmLog_007:23:155
400839820,0EcMasterDemoSyn401829tAtEmLog_007:23:155
2631539820,0EcMasterDemoSyn2632529tAtEmLog_009:30:015
255239820,0EcMasterDemoSyn256229tAtEmLog_008:29:105
1857639820,0EcMasterDemoSyn1858629tAtEmLog_010:00:275
1600039820,0EcMasterDemoSyn1601029tAtEmLog_007:48:365
1466939820,0EcMasterDemoSyn1467929tAtEmLog_008:54:315
1364039820,0EcMasterDemoSyn1365029tAtEmLog_007:43:335
1012339820,0EcMasterDemoSyn1013329tAtEmLog_012:37:405
451839810,0EcMasterDemoSyn452829tAtEmLog_010:10:355
2779139810,0EcMasterDemoSyn2780129tAtEmLog_010:05:325
1940439810,0EcMasterDemoSyn1941429tAtEmLog_009:04:415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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