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2026-02-19 - 11:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Feb 19, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
369639840,0EcMasterDemoSyn370629tAtEmLog_022:30:245
369639840,0EcMasterDemoSyn370629tAtEmLog_022:30:235
148939830,0EcMasterDemoSyn150129tAtEmLog_021:19:235
2977439820,0EcMasterDemoSyn2978429tAtEmLog_020:28:425
2267139820,0EcMasterDemoSyn2267729tAtEmLog_020:13:285
1299239820,0EcMasterDemoSyn1300229tAtEmLog_022:35:285
1086439820,0EcMasterDemoSyn1087429tAtEmLog_019:48:085
809739810,0EcMasterDemoSyn810729tAtEmLog_022:50:415
750939810,0EcMasterDemoSyn751929tAtEmLog_023:26:115
341339810,0EcMasterDemoSyn342329tAtEmLog_019:32:545
2872439810,0EcMasterDemoSyn2873429tAtEmLog_019:17:415
2458739810,0EcMasterDemoSyn2459729tAtEmLog_021:14:205
1322139810,0EcMasterDemoSyn1323129tAtEmLog_019:53:125
3079239430,0EcMasterDemoSyn0-21swapper/123:21:061
133752250,3sleep50-21swapper/523:11:325
264202240,0sleep30-21swapper/300:12:313
24279992018,2cyclictest19888-21kworker/1:1+events20:03:211
2428099191,13cyclictest16-1pr/legacy19:22:462
2991739180,0EcMasterDemoSyn0-21swapper/522:10:075
2428199180,10cyclictest4036-21sh23:42:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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