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2026-02-17 - 21:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Feb 17, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2719439910,0EcMasterDemoSyn2720429tAtEmLog_008:43:335
1299739910,0EcMasterDemoSyn1300729tAtEmLog_008:13:075
727239830,0EcMasterDemoSyn728229tAtEmLog_010:55:225
660039830,0EcMasterDemoSyn661029tAtEmLog_009:08:545
2631239830,0EcMasterDemoSyn2632229tAtEmLog_011:05:325
221739830,0EcMasterDemoSyn222729tAtEmLog_011:46:065
2051539830,0EcMasterDemoSyn2052529tAtEmLog_011:56:145
588939820,0EcMasterDemoSyn589929tAtEmLog_010:19:525
314339820,0EcMasterDemoSyn315329tAtEmLog_007:52:505
3083539820,0EcMasterDemoSyn3084529tAtEmLog_007:42:415
3045339820,0EcMasterDemoSyn3046329tAtEmLog_010:50:195
2439139820,0EcMasterDemoSyn2440129tAtEmLog_009:54:325
2009939820,0EcMasterDemoSyn2010929tAtEmLog_008:28:205
1943839820,0EcMasterDemoSyn1944829tAtEmLog_012:31:445
1014639820,0EcMasterDemoSyn1015729tAtEmLog_009:29:115
2481739810,0EcMasterDemoSyn2482729tAtEmLog_008:38:275
1996239810,0EcMasterDemoSyn1997229tAtEmLog_010:09:455
1851939810,0EcMasterDemoSyn1852929tAtEmLog_007:17:195
1616139810,0EcMasterDemoSyn1617129tAtEmLog_007:12:165
1212739810,0EcMasterDemoSyn1213729tAtEmLog_011:15:415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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