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2026-08-08 - 00:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Aug 07, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1729439162400,0EcMasterDemoSyn0-21swapper/510:13:165
1423839145930,0EcMasterDemoSyn0-21swapper/512:24:595
2885139138600,0EcMasterDemoSyn0-21swapper/509:49:375
189613983220,0EcMasterDemoSyn0-21swapper/509:59:495
282103983210,0EcMasterDemoSyn0-21swapper/510:18:015
77463983200,0EcMasterDemoSyn0-21swapper/510:09:165
77463983200,0EcMasterDemoSyn0-21swapper/510:09:165
10473983120,0EcMasterDemoSyn0-21swapper/510:50:255
311383983080,0EcMasterDemoSyn0-21swapper/511:04:365
166253983070,0EcMasterDemoSyn0-21swapper/510:43:065
234553983030,0EcMasterDemoSyn0-21swapper/512:28:595
199593983000,0EcMasterDemoSyn0-21swapper/510:59:305
48003982980,0EcMasterDemoSyn0-21swapper/512:35:105
239443982810,0EcMasterDemoSyn0-21swapper/510:46:015
1677391590,0EcMasterDemoSyn0-21swapper/309:51:243
24607391280,1EcMasterDemoSyn24616-21runintdemo5min10:46:202
22853391270,0EcMasterDemoSyn0-21swapper/311:59:283
4109391190,1EcMasterDemoSyn4115-21ps10:37:142
32296391170,4EcMasterDemoSyn32302-21ps12:32:342
19333391170,1EcMasterDemoSyn16954-21diskmemload10:44:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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