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2026-01-14 - 22:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Wed Jan 14, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20362990,1sleep0221rcuc/009:10:130
1531039970,4EcMasterDemoSyn15316-21ps10:11:284
234522960,1sleep30-21swapper/308:45:233
1417839920,0EcMasterDemoSyn1418829tAtEmLog_011:22:275
273112840,0sleep30-21swapper/311:30:113
3205839830,0EcMasterDemoSyn3206829tAtEmLog_007:59:375
1923839830,0EcMasterDemoSyn1924829tAtEmLog_008:40:105
1154239830,0EcMasterDemoSyn1155229tAtEmLog_008:24:585
911039820,0EcMasterDemoSyn912029tAtEmLog_008:19:535
53039820,0EcMasterDemoSyn54029tAtEmLog_009:05:325
2006139820,0EcMasterDemoSyn2007129tAtEmLog_007:34:165
1168139820,0EcMasterDemoSyn1169129tAtEmLog_012:33:275
86639810,0EcMasterDemoSyn87629tAtEmLog_010:57:065
2734239810,0EcMasterDemoSyn2735229tAtEmLog_007:49:285
1581039810,0EcMasterDemoSyn1582029tAtEmLog_009:35:575
1306739810,0EcMasterDemoSyn1307729tAtEmLog_011:57:575
1025239810,0EcMasterDemoSyn1026229tAtEmLog_007:13:585
614229210,3tAtEmLog_00-21swapper/510:11:275
326062210,0sleep00-21swapper/010:03:470
3142939210,0EcMasterDemoSyn31435-21ps09:25:504
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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