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2026-03-22 - 20:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Mar 22, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23678391360,5EcMasterDemoSyn23687-21wc10:29:152
23678391020,2EcMasterDemoSyn23676-21ssh10:29:140
1882639930,0EcMasterDemoSyn1883629tAtEmLog_007:16:325
344639830,0EcMasterDemoSyn345629tAtEmLog_007:52:025
2065539820,0EcMasterDemoSyn2066529tAtEmLog_008:27:325
3114139810,0EcMasterDemoSyn3115129tAtEmLog_007:41:545
2775639810,0EcMasterDemoSyn2776629tAtEmLog_008:42:465
2367839810,0EcMasterDemoSyn2368829tAtEmLog_010:29:155
1734539810,0EcMasterDemoSyn1735529tAtEmLog_012:30:565
1374139810,0EcMasterDemoSyn1375129tAtEmLog_007:06:245
108839810,0EcMasterDemoSyn109829tAtEmLog_007:46:585
171642780,0sleep30-21swapper/309:50:043
2400939480,0EcMasterDemoSyn0-21swapper/509:53:445
1882639240,1EcMasterDemoSyn18832-21runintdemo5min07:16:323
34722200,1sleep2391rcuc/210:17:432
108839190,0EcMasterDemoSyn1097-21wc07:46:581
2224529180,10tAtEmLog_022270-21chrt12:15:445
1414999185,10cyclictest8087-21sh10:38:210
1414999185,10cyclictest19704-21sh10:09:160
1414999180,8cyclictest16-1pr/legacy10:54:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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