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2026-03-04 - 13:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Wed Mar 04, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1920439840,0EcMasterDemoSyn1921429tAtEmLog_022:22:065
1920439840,0EcMasterDemoSyn1921429tAtEmLog_022:22:065
2930539830,0EcMasterDemoSyn2931529tAtEmLog_020:25:295
2332439830,0EcMasterDemoSyn2333429tAtEmLog_022:42:235
2122739830,0EcMasterDemoSyn2123729tAtEmLog_020:10:165
2083439830,0EcMasterDemoSyn2084429tAtEmLog_000:28:535
1021839830,0EcMasterDemoSyn1022829tAtEmLog_019:49:595
1977539820,0EcMasterDemoSyn1978529tAtEmLog_021:46:365
1837139820,0EcMasterDemoSyn1838129tAtEmLog_022:57:365
1698839820,0EcMasterDemoSyn1699829tAtEmLog_000:08:365
167239820,0EcMasterDemoSyn168229tAtEmLog_020:35:375
1586139820,0EcMasterDemoSyn1587129tAtEmLog_021:06:025
3081039810,0EcMasterDemoSyn3082029tAtEmLog_019:24:385
2693639810,0EcMasterDemoSyn2694629tAtEmLog_023:38:105
2364139800,0EcMasterDemoSyn2365129tAtEmLog_019:09:255
2083439610,0EcMasterDemoSyn0-21swapper/300:28:533
924739330,4EcMasterDemoSyn9254-21grep22:52:322
1971939220,1EcMasterDemoSyn19727-21grep21:11:071
3103339180,1EcMasterDemoSyn31042-21runintdemo5min23:58:264
23799991815,2cyclictest11086-21kworker/3:1+events23:38:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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