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2026-04-18 - 13:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat Apr 18, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19833391160,0EcMasterDemoSyn0-21swapper/123:48:551
2004439930,0EcMasterDemoSyn2005429tAtEmLog_021:01:355
2004439930,0EcMasterDemoSyn2005429tAtEmLog_021:01:355
3133939910,0EcMasterDemoSyn3134929tAtEmLog_022:07:305
1336839870,0EcMasterDemoSyn1337429tAtEmLog_019:40:275
222842850,0sleep20-21swapper/223:14:172
1876439850,0EcMasterDemoSyn1877429tAtEmLog_000:24:255
317539830,0EcMasterDemoSyn318529tAtEmLog_022:27:475
2895339830,0EcMasterDemoSyn2896529tAtEmLog_023:54:005
227639830,0EcMasterDemoSyn228629tAtEmLog_019:20:105
2245539830,0EcMasterDemoSyn2246529tAtEmLog_021:06:395
866139820,0EcMasterDemoSyn867129tAtEmLog_021:37:055
743739820,0EcMasterDemoSyn744729tAtEmLog_022:48:045
1059939820,0EcMasterDemoSyn1060929tAtEmLog_019:35:235
2783839810,0EcMasterDemoSyn2784829tAtEmLog_000:29:305
2553039810,0EcMasterDemoSyn2554029tAtEmLog_020:05:485
169039810,0EcMasterDemoSyn170129tAtEmLog_023:38:475
1572439810,0EcMasterDemoSyn1573429tAtEmLog_019:45:315
1189439810,0EcMasterDemoSyn1190429tAtEmLog_023:08:225
1189439810,0EcMasterDemoSyn1190429tAtEmLog_023:08:215
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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