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2026-03-01 - 11:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Mar 01, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18296391060,0EcMasterDemoSyn18304-21runintdemo5min23:47:513
1922739930,0EcMasterDemoSyn1923729tAtEmLog_020:55:285
2832139920,0EcMasterDemoSyn2833129tAtEmLog_023:17:275
263152890,0sleep40-21swapper/423:16:024
3009839820,0EcMasterDemoSyn3010929tAtEmLog_021:30:585
2951439820,0EcMasterDemoSyn2952429tAtEmLog_022:06:275
1968639820,0EcMasterDemoSyn1969629tAtEmLog_022:36:525
1540139820,0EcMasterDemoSyn1541129tAtEmLog_022:16:365
132939820,0EcMasterDemoSyn133929tAtEmLog_022:26:445
1111939820,0EcMasterDemoSyn1112929tAtEmLog_021:56:185
2419639810,0EcMasterDemoSyn2420629tAtEmLog_022:57:105
2419639810,0EcMasterDemoSyn2420629tAtEmLog_022:57:095
713939800,0EcMasterDemoSyn714929tAtEmLog_020:09:505
404239800,0EcMasterDemoSyn405229tAtEmLog_019:59:405
3119539800,0EcMasterDemoSyn3120529tAtEmLog_019:34:195
2811739800,0EcMasterDemoSyn2812729tAtEmLog_019:24:125
2397839800,0EcMasterDemoSyn2398829tAtEmLog_019:08:585
84232380,0sleep38422-21ssh00:18:253
76762350,1sleep50-21swapper/523:41:445
1003839220,1EcMasterDemoSyn10031-21ssh23:07:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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