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2026-06-23 - 16:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Jun 23, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1827439234150,0EcMasterDemoSyn0-21swapper/508:44:365
280339133950,0EcMasterDemoSyn0-21swapper/507:15:305
53533983510,0EcMasterDemoSyn0-21swapper/507:54:555
99543983390,0EcMasterDemoSyn0-21swapper/508:00:015
83043983120,0EcMasterDemoSyn0-21swapper/508:32:545
318423983060,0EcMasterDemoSyn0-21swapper/508:23:255
20463983060,0EcMasterDemoSyn0-21swapper/509:00:395
187853983030,0EcMasterDemoSyn0-21swapper/508:09:335
194993982930,0EcMasterDemoSyn0-21swapper/507:35:115
97623952720,0EcMasterDemoSyn0-21swapper/507:59:415
8756391730,1EcMasterDemoSyn8762-21ps07:23:051
16527391370,0EcMasterDemoSyn0-21swapper/310:05:313
19011391120,0EcMasterDemoSyn19016-21runintdemo5min07:34:474
27085391050,1EcMasterDemoSyn27094-21runintdemo5min08:54:002
2556439970,0EcMasterDemoSyn2557429tAtEmLog_008:51:065
2633839910,0EcMasterDemoSyn2634829tAtEmLog_007:05:585
3044439840,0EcMasterDemoSyn3045429tAtEmLog_007:45:245
2721939840,0EcMasterDemoSyn2722929tAtEmLog_008:18:155
255272840,0sleep50-21swapper/511:22:145
2078139840,0EcMasterDemoSyn2079129tAtEmLog_008:45:375
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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