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2026-08-07 - 11:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Aug 07, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2835139920,0EcMasterDemoSyn2836129tAtEmLog_021:21:585
230339910,0EcMasterDemoSyn231329tAtEmLog_022:38:015
1165839900,0EcMasterDemoSyn1166829tAtEmLog_020:10:575
395839830,0EcMasterDemoSyn396829tAtEmLog_022:02:315
2547339830,0EcMasterDemoSyn2548329tAtEmLog_000:04:135
2424539830,0EcMasterDemoSyn2425529tAtEmLog_000:39:435
2929439820,0EcMasterDemoSyn2930429tAtEmLog_022:53:145
2302839820,0EcMasterDemoSyn2303829tAtEmLog_021:37:105
2112339820,0EcMasterDemoSyn2113329tAtEmLog_020:31:155
1839639820,0EcMasterDemoSyn1840629tAtEmLog_023:23:395
1130339820,0EcMasterDemoSyn1131329tAtEmLog_022:43:055
593339810,0EcMasterDemoSyn594329tAtEmLog_022:58:175
46739810,0EcMasterDemoSyn47729tAtEmLog_020:56:365
325639810,0EcMasterDemoSyn326629tAtEmLog_021:01:405
2732339810,0EcMasterDemoSyn2733329tAtEmLog_023:28:435
1402639810,0EcMasterDemoSyn1403629tAtEmLog_020:16:025
1288339810,0EcMasterDemoSyn1289329tAtEmLog_023:38:525
561439800,0EcMasterDemoSyn562429tAtEmLog_021:06:455
1876439790,0EcMasterDemoSyn1877429tAtEmLog_020:26:115
949639210,1EcMasterDemoSyn9502-21ps23:18:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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