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2026-02-25 - 00:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Feb 24, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10203391130,1EcMasterDemoSyn10211-21grep07:33:454
29653391120,1EcMasterDemoSyn0-21swapper/410:41:234
765521010,0sleep50-21swapper/511:23:105
2101439900,0EcMasterDemoSyn2102429tAtEmLog_010:00:495
2352639840,0EcMasterDemoSyn2353629tAtEmLog_012:07:365
273739830,0EcMasterDemoSyn274729tAtEmLog_009:50:415
1988639830,0EcMasterDemoSyn1989629tAtEmLog_007:54:035
1261339830,0EcMasterDemoSyn1262329tAtEmLog_007:38:515
910939820,0EcMasterDemoSyn911929tAtEmLog_008:39:425
910939820,0EcMasterDemoSyn911929tAtEmLog_008:39:415
2375339820,0EcMasterDemoSyn2376329tAtEmLog_009:10:075
2086939820,0EcMasterDemoSyn2088229tAtEmLog_009:25:195
1517039820,0EcMasterDemoSyn1518029tAtEmLog_007:43:555
1506039820,0EcMasterDemoSyn1507029tAtEmLog_011:27:025
746339810,0EcMasterDemoSyn747329tAtEmLog_009:35:285
702439810,0EcMasterDemoSyn703429tAtEmLog_010:10:585
3263939810,0EcMasterDemoSyn3264929tAtEmLog_012:12:405
3072839810,0EcMasterDemoSyn3073829tAtEmLog_007:08:245
1020339810,0EcMasterDemoSyn1021329tAtEmLog_007:33:455
2534439240,1EcMasterDemoSyn25349-21runintdemo5min10:21:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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