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2025-12-15 - 16:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Dec 16, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8284391050,3EcMasterDemoSyn8293-21sh00:04:452
244939850,0EcMasterDemoSyn245929tAtEmLog_020:52:045
1869339840,0EcMasterDemoSyn1870329tAtEmLog_023:34:205
995939830,0EcMasterDemoSyn996929tAtEmLog_022:18:165
265902830,0sleep50-21swapper/500:33:085
2572639830,0EcMasterDemoSyn2573629tAtEmLog_019:20:475
1323339830,0EcMasterDemoSyn1324329tAtEmLog_020:06:265
1323339830,0EcMasterDemoSyn1324329tAtEmLog_020:06:255
957239820,0EcMasterDemoSyn958229tAtEmLog_023:29:165
322839820,0EcMasterDemoSyn323829tAtEmLog_021:57:595
2329239820,0EcMasterDemoSyn2330229tAtEmLog_019:15:435
2254239820,0EcMasterDemoSyn2255429tAtEmLog_022:08:075
1855839820,0EcMasterDemoSyn1856829tAtEmLog_019:05:355
1256839820,0EcMasterDemoSyn1257829tAtEmLog_000:25:025
1121439820,0EcMasterDemoSyn1122729tAtEmLog_021:27:325
1013739820,0EcMasterDemoSyn1014729tAtEmLog_019:56:175
3013339810,0EcMasterDemoSyn3014329tAtEmLog_021:37:425
2786239810,0EcMasterDemoSyn2787229tAtEmLog_023:39:245
2412039810,0EcMasterDemoSyn2413029tAtEmLog_022:43:375
2269239810,0EcMasterDemoSyn2270229tAtEmLog_020:26:435
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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