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2026-03-06 - 10:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Mar 06, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13092391070,2EcMasterDemoSyn41-21ksoftirqd/222:42:372
71492970,0sleep00-21swapper/022:57:110
2224939900,0EcMasterDemoSyn2225929tAtEmLog_019:29:565
1339839890,0EcMasterDemoSyn0-21swapper/220:15:342
867839830,0EcMasterDemoSyn868829tAtEmLog_020:05:275
2322139830,0EcMasterDemoSyn2323129tAtEmLog_021:36:425
920939820,0EcMasterDemoSyn921929tAtEmLog_021:46:515
386039820,0EcMasterDemoSyn386929tAtEmLog_022:37:335
3241739820,0EcMasterDemoSyn3242729tAtEmLog_021:41:485
2711239820,0EcMasterDemoSyn2712229tAtEmLog_022:32:305
257239820,0EcMasterDemoSyn258229tAtEmLog_023:48:345
587539700,1EcMasterDemoSyn5882-21runintdemo5min20:00:231
2145739670,0EcMasterDemoSyn0-21swapper/123:23:111
1797639420,1EcMasterDemoSyn1798429tAtEmLog_022:27:255
3025539370,1EcMasterDemoSyn30262-21grep20:51:051
2080039220,1EcMasterDemoSyn20807-21grep20:30:474
455139180,0EcMasterDemoSyn0-21swapper/522:02:045
2223999180,8tDemoTimingTask30922-21chrt22:52:285
12908991812,4cyclictest14921-21cat22:25:252
1290299180,14cyclictest780-21runrttasks23:33:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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