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2025-11-02 - 13:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Nov 02, 2025 00:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21510997340,731tDemoTimingTask21594-21sleep20:20:005
11096997170,715tDemoTimingTask111092sleep521:50:525
7449996500,648tDemoTimingTask7560-21sleep19:50:005
23348391030,0EcMasterDemoSyn2335829tAtEmLog_000:38:105
19249391020,0EcMasterDemoSyn1925929tAtEmLog_023:01:515
3012239990,0EcMasterDemoSyn3013229tAtEmLog_021:20:265
3240839930,0EcMasterDemoSyn3241829tAtEmLog_023:32:165
2987639930,0EcMasterDemoSyn2988629tAtEmLog_022:46:385
604439920,0EcMasterDemoSyn605429tAtEmLog_020:55:055
510839920,0EcMasterDemoSyn511829tAtEmLog_019:44:055
449939920,0EcMasterDemoSyn450929tAtEmLog_023:57:375
2455039920,0EcMasterDemoSyn2456029tAtEmLog_022:21:175
2247039920,0EcMasterDemoSyn2248029tAtEmLog_022:41:345
1683739920,0EcMasterDemoSyn1684729tAtEmLog_022:16:125
31239910,0EcMasterDemoSyn32329tAtEmLog_019:33:575
3114539910,0EcMasterDemoSyn3115529tAtEmLog_020:39:525
2215139910,0EcMasterDemoSyn2216129tAtEmLog_023:47:295
2073339910,0EcMasterDemoSyn2074329tAtEmLog_019:08:365
1286139910,0EcMasterDemoSyn1287129tAtEmLog_021:30:345
2647939900,0EcMasterDemoSyn2648929tAtEmLog_020:29:435
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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