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2025-09-18 - 06:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Sep 18, 2025 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24603292130,212tAtEmLog_02459339EcMasterDemoSyn20:54:267
31402291960,195tAtEmLog_03139239EcMasterDemoSyn20:03:457
20911291930,192tAtEmLog_02090139EcMasterDemoSyn19:43:287
20911291930,192tAtEmLog_02090139EcMasterDemoSyn19:43:277
2715291900,189tAtEmLog_0270539EcMasterDemoSyn19:07:597
12977291890,188tAtEmLog_01296739EcMasterDemoSyn19:28:157
5257291850,184tAtEmLog_0524739EcMasterDemoSyn19:13:027
2014121150,3sleep5549199cyclictest23:05:265
18366291040,103tAtEmLog_01835639EcMasterDemoSyn19:33:217
807639990,0EcMasterDemoSyn808629tAtEmLog_021:35:027
807639990,0EcMasterDemoSyn808629tAtEmLog_021:35:027
1040339990,0EcMasterDemoSyn1041329tAtEmLog_019:18:087
2186439920,0EcMasterDemoSyn2187629tAtEmLog_022:46:017
519639910,0EcMasterDemoSyn520629tAtEmLog_022:56:107
409239910,0EcMasterDemoSyn410229tAtEmLog_020:08:507
924139900,0EcMasterDemoSyn925129tAtEmLog_020:18:597
3254139900,0EcMasterDemoSyn3255129tAtEmLog_021:04:377
2743939900,0EcMasterDemoSyn2744929tAtEmLog_023:31:397
2743939900,0EcMasterDemoSyn2744929tAtEmLog_023:31:397
2679039900,0EcMasterDemoSyn2680029tAtEmLog_000:17:177
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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