You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-21 - 19:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat Feb 21, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73439920,0EcMasterDemoSyn74729tAtEmLog_010:46:075
135972910,1sleep50-21swapper/510:53:455
277322870,0sleep50-21swapper/512:13:075
2419239840,0EcMasterDemoSyn2420229tAtEmLog_008:13:595
511439830,0EcMasterDemoSyn512429tAtEmLog_007:33:255
2889539830,0EcMasterDemoSyn2890529tAtEmLog_010:25:505
837739820,0EcMasterDemoSyn838729tAtEmLog_012:02:115
765039820,0EcMasterDemoSyn766029tAtEmLog_007:38:295
1238439820,0EcMasterDemoSyn1239429tAtEmLog_007:48:385
1002839820,0EcMasterDemoSyn1003829tAtEmLog_007:43:345
1947939810,0EcMasterDemoSyn1948929tAtEmLog_008:03:505
1905339800,0EcMasterDemoSyn1906329tAtEmLog_010:56:155
249442640,0sleep30-21swapper/312:11:103
2766639580,0EcMasterDemoSyn2767629tAtEmLog_011:41:535
31942450,1sleep20-21swapper/210:30:152
2261639310,1EcMasterDemoSyn581rcuc/411:52:024
2261639310,1EcMasterDemoSyn581rcuc/411:52:024
13752220,0sleep30-21swapper/311:22:193
2558299201,10cyclictest25376-21ssh12:11:284
2558299200,10cyclictest23121-21sh09:47:244
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional