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2026-05-10 - 10:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun May 10, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
561339920,0EcMasterDemoSyn562329tAtEmLog_020:24:535
1425639920,0EcMasterDemoSyn1426629tAtEmLog_023:07:095
86039830,0EcMasterDemoSyn87029tAtEmLog_020:14:465
2112039830,0EcMasterDemoSyn2113129tAtEmLog_020:55:205
2010539830,0EcMasterDemoSyn2011529tAtEmLog_022:16:285
2010539830,0EcMasterDemoSyn2011529tAtEmLog_022:16:285
1838139830,1EcMasterDemoSyn1839129tAtEmLog_023:27:275
2856339820,0EcMasterDemoSyn2857329tAtEmLog_020:04:375
2471639820,0EcMasterDemoSyn2472629tAtEmLog_022:01:155
2370839820,0EcMasterDemoSyn2371829tAtEmLog_021:00:235
2141439820,0EcMasterDemoSyn2142429tAtEmLog_019:49:255
1875539820,0EcMasterDemoSyn1876529tAtEmLog_019:44:195
1637739820,0EcMasterDemoSyn1638729tAtEmLog_019:39:165
153139820,0EcMasterDemoSyn154329tAtEmLog_022:06:195
1829639810,0EcMasterDemoSyn1830629tAtEmLog_020:50:145
1568439810,0EcMasterDemoSyn1569429tAtEmLog_021:20:415
1301139810,0EcMasterDemoSyn1302129tAtEmLog_020:40:075
1249239800,0EcMasterDemoSyn1250229tAtEmLog_000:18:105
323439690,0EcMasterDemoSyn0-21swapper/420:19:504
323439690,0EcMasterDemoSyn0-21swapper/420:19:494
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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