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2026-01-12 - 15:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Jan 12, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3116639930,0EcMasterDemoSyn3117629tAtEmLog_007:08:415
502939920,0EcMasterDemoSyn503929tAtEmLog_008:29:485
305792880,1sleep330566-21apt-get12:30:103
2718939860,1EcMasterDemoSyn27194-21runintdemo5min09:45:534
740139840,0EcMasterDemoSyn741129tAtEmLog_011:22:135
740139840,0EcMasterDemoSyn741129tAtEmLog_011:22:135
820739830,0EcMasterDemoSyn821729tAtEmLog_010:46:445
2967439830,0EcMasterDemoSyn2968429tAtEmLog_011:52:395
2730039830,0EcMasterDemoSyn2731029tAtEmLog_010:21:225
2230439830,0EcMasterDemoSyn2231429tAtEmLog_010:36:345
1805539830,0EcMasterDemoSyn1806529tAtEmLog_012:23:045
143039830,0EcMasterDemoSyn144029tAtEmLog_007:13:445
1342939830,0EcMasterDemoSyn1343929tAtEmLog_007:39:065
350239820,0EcMasterDemoSyn351229tAtEmLog_009:15:275
3239539820,0EcMasterDemoSyn3240529tAtEmLog_008:19:405
2452139820,0EcMasterDemoSyn2453129tAtEmLog_012:07:515
1237839820,0EcMasterDemoSyn1238829tAtEmLog_011:07:015
1089439820,0EcMasterDemoSyn1090429tAtEmLog_007:34:025
403839810,0EcMasterDemoSyn404829tAtEmLog_010:26:275
379639810,0EcMasterDemoSyn380629tAtEmLog_007:18:505
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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