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2026-06-22 - 15:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Jun 22, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11203391180,3EcMasterDemoSyn11212-21grep09:55:211
1371391110,0EcMasterDemoSyn0-21swapper/409:50:154
29962860,1sleep42988-21python311:20:204
1573639840,0EcMasterDemoSyn1574629tAtEmLog_010:15:385
1120339830,0EcMasterDemoSyn1121529tAtEmLog_009:55:205
637339820,0EcMasterDemoSyn638329tAtEmLog_007:23:125
2851239820,0EcMasterDemoSyn2852229tAtEmLog_009:29:585
2816839820,0EcMasterDemoSyn2817829tAtEmLog_008:08:515
196839820,0EcMasterDemoSyn197829tAtEmLog_010:25:455
1739239820,0EcMasterDemoSyn1740229tAtEmLog_008:54:285
1350239820,0EcMasterDemoSyn1351229tAtEmLog_007:38:245
1021339820,0EcMasterDemoSyn1022329tAtEmLog_011:06:195
791139810,0EcMasterDemoSyn792129tAtEmLog_012:17:195
3242339810,0EcMasterDemoSyn3243329tAtEmLog_011:36:455
2218339810,0EcMasterDemoSyn2219329tAtEmLog_009:04:385
2218339810,0EcMasterDemoSyn2219329tAtEmLog_009:04:375
1704339810,0EcMasterDemoSyn1705329tAtEmLog_012:22:245
1012139810,0EcMasterDemoSyn1013129tAtEmLog_009:19:495
2216439800,0EcMasterDemoSyn2217429tAtEmLog_012:07:105
2020639800,0EcMasterDemoSyn2021629tAtEmLog_010:35:545
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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