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2026-06-29 - 17:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Jun 29, 2026 12:44:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1329239920,0EcMasterDemoSyn1330229tAtEmLog_011:32:335
1641839840,0EcMasterDemoSyn1642829tAtEmLog_008:09:415
86639820,0EcMasterDemoSyn87629tAtEmLog_010:31:425
433139820,0EcMasterDemoSyn434129tAtEmLog_008:50:175
3174639820,0EcMasterDemoSyn3175629tAtEmLog_007:34:135
2384839820,0EcMasterDemoSyn2385829tAtEmLog_010:26:395
2241339820,0EcMasterDemoSyn2242329tAtEmLog_011:37:375
92839810,0EcMasterDemoSyn93829tAtEmLog_009:56:135
3097339810,0EcMasterDemoSyn3098329tAtEmLog_008:40:095
101539660,0EcMasterDemoSyn0-21swapper/108:45:131
2471039270,1EcMasterDemoSyn24720-21wc09:15:381
430539250,1EcMasterDemoSyn4312-21runintdemo5min07:44:211
215442220,4sleep421632-21cat09:15:004
275152210,0sleep10-21swapper/109:53:281
3250599190,9tDemoTimingTask4446-21chrt11:10:015
2010199190,11cyclictest9244-21sh10:19:180
2010199181,13cyclictest780-21runrttasks07:27:000
2010199180,14cyclictest20234-21sh09:49:430
3151929170,10tAtEmLog_02698-21chrt11:45:025
2353129170,10tAtEmLog_023545-21chrt08:24:555
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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