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2026-05-15 - 08:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri May 15, 2026 00:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1988239890,0EcMasterDemoSyn19890-21ps21:41:344
3061839840,0EcMasterDemoSyn3062829tAtEmLog_020:10:175
800639830,0EcMasterDemoSyn801629tAtEmLog_023:58:295
479239830,0EcMasterDemoSyn480229tAtEmLog_023:02:425
1708339830,0EcMasterDemoSyn1709329tAtEmLog_000:03:335
1505039830,0EcMasterDemoSyn1506029tAtEmLog_021:56:455
892539820,0EcMasterDemoSyn893529tAtEmLog_023:22:595
586239820,0EcMasterDemoSyn587429tAtEmLog_021:51:425
2521439820,0EcMasterDemoSyn2522429tAtEmLog_021:06:045
2301939820,0EcMasterDemoSyn2302929tAtEmLog_023:12:505
2285739820,0EcMasterDemoSyn2286729tAtEmLog_021:01:005
2285739820,0EcMasterDemoSyn2286729tAtEmLog_021:01:005
2107739820,0EcMasterDemoSyn2108729tAtEmLog_000:23:505
1544239820,0EcMasterDemoSyn1545229tAtEmLog_021:21:165
1066239820,0EcMasterDemoSyn1067229tAtEmLog_021:36:295
53539800,0EcMasterDemoSyn54529tAtEmLog_019:09:255
223652340,0sleep30-21swapper/323:30:183
418439270,1EcMasterDemoSyn4190-21ps23:38:120
70599195,6cyclictest31700-21cron00:30:001
70599190,9cyclictest304-21hddtemp_smartct23:00:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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