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2026-07-20 - 23:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Jul 20, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
155633983200,0EcMasterDemoSyn0-21swapper/508:37:525
194213971670,0EcMasterDemoSyn0-21swapper/508:41:325
298013935040,0EcMasterDemoSyn0-21swapper/508:53:575
218722920,1sleep10-21swapper/110:10:211
528139910,0EcMasterDemoSyn529129tAtEmLog_009:01:335
315439910,0EcMasterDemoSyn316429tAtEmLog_007:12:155
3268639850,0EcMasterDemoSyn3269629tAtEmLog_008:55:435
3268639850,0EcMasterDemoSyn3269629tAtEmLog_008:55:435
1200739840,0EcMasterDemoSyn1201929tAtEmLog_009:29:285
580139830,0EcMasterDemoSyn581129tAtEmLog_008:17:315
2382639830,0EcMasterDemoSyn2383629tAtEmLog_008:46:145
601039820,0EcMasterDemoSyn602029tAtEmLog_010:20:105
551439820,0EcMasterDemoSyn552429tAtEmLog_007:17:185
344039820,0EcMasterDemoSyn345029tAtEmLog_008:12:275
2104439820,0EcMasterDemoSyn2105429tAtEmLog_009:34:325
1906539820,0EcMasterDemoSyn1907529tAtEmLog_007:36:575
1397439820,0EcMasterDemoSyn1398429tAtEmLog_007:26:055
1089739820,0EcMasterDemoSyn1090729tAtEmLog_007:23:535
77039810,0EcMasterDemoSyn78229tAtEmLog_007:07:115
661639810,0EcMasterDemoSyn662629tAtEmLog_010:55:415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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