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2026-02-27 - 15:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri Feb 27, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9871396940,1EcMasterDemoSyn171rcu_preempt07:08:461
78382940,0sleep50-21swapper/511:35:135
279839930,0EcMasterDemoSyn280829tAtEmLog_012:07:575
112582930,0sleep50-21swapper/512:30:175
2601939910,0EcMasterDemoSyn2602929tAtEmLog_008:50:105
2888039840,0EcMasterDemoSyn2889029tAtEmLog_008:55:165
3170139820,0EcMasterDemoSyn3171129tAtEmLog_007:54:245
2904339820,0EcMasterDemoSyn2905329tAtEmLog_007:49:205
2362739820,0EcMasterDemoSyn2363729tAtEmLog_009:56:065
165039820,0EcMasterDemoSyn166029tAtEmLog_007:59:295
980539810,0EcMasterDemoSyn981529tAtEmLog_010:06:155
874639810,0EcMasterDemoSyn875629tAtEmLog_008:14:425
874639810,0EcMasterDemoSyn875629tAtEmLog_008:14:415
1442139810,0EcMasterDemoSyn1443129tAtEmLog_009:51:025
132662490,0sleep10-21swapper/109:50:221
1224439420,1EcMasterDemoSyn12252-21grep07:13:514
34152340,1sleep10-21swapper/112:08:221
909439240,0EcMasterDemoSyn0-21swapper/510:41:455
2808639240,1EcMasterDemoSyn28092-21ps10:16:243
131132220,0sleep00-21swapper/011:55:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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