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2026-03-05 - 01:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Wed Mar 04, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34172930,0sleep50-21swapper/511:10:585
1584439840,1EcMasterDemoSyn1585429tAtEmLog_010:42:255
256932830,0sleep40-21swapper/409:19:354
1521439830,0EcMasterDemoSyn1522429tAtEmLog_011:17:565
2827139820,0EcMasterDemoSyn2828129tAtEmLog_008:40:435
237739820,0EcMasterDemoSyn238729tAtEmLog_007:50:025
237739820,0EcMasterDemoSyn238729tAtEmLog_007:50:015
185339820,0EcMasterDemoSyn186329tAtEmLog_010:17:055
113139820,0EcMasterDemoSyn114129tAtEmLog_011:28:045
113139820,0EcMasterDemoSyn114129tAtEmLog_011:28:045
1104239820,0EcMasterDemoSyn1105229tAtEmLog_010:22:095
1770539810,0EcMasterDemoSyn1771529tAtEmLog_007:14:315
1533439800,0EcMasterDemoSyn1534429tAtEmLog_007:09:285
2737539790,0EcMasterDemoSyn0-21swapper/212:18:472
322732430,0sleep20-21swapper/210:15:442
712039350,1EcMasterDemoSyn7125-21runintdemo5min08:00:102
1829439240,1EcMasterDemoSyn18303-21runintdemo5min12:13:412
15488992018,2cyclictest7367-21kworker/4:1+events10:42:254
15483992016,3cyclictest32186-21turbostat11:10:003
1547299206,10cyclictest10491-21ssh12:27:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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