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2026-07-30 - 22:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Jul 30, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3028839890,0EcMasterDemoSyn30295-21grep11:40:544
539539830,0EcMasterDemoSyn540529tAtEmLog_007:32:275
3163839830,0EcMasterDemoSyn3164829tAtEmLog_008:28:135
314839830,0EcMasterDemoSyn315829tAtEmLog_011:25:425
303539830,0EcMasterDemoSyn304529tAtEmLog_007:27:225
2274339830,0EcMasterDemoSyn2275529tAtEmLog_012:31:375
2452939820,0EcMasterDemoSyn2453929tAtEmLog_008:13:015
1608139820,0EcMasterDemoSyn1609129tAtEmLog_009:03:435
1362139820,0EcMasterDemoSyn1363129tAtEmLog_010:19:465
117239820,0EcMasterDemoSyn118429tAtEmLog_009:54:255
1031639820,0EcMasterDemoSyn1032629tAtEmLog_007:42:355
775439810,0EcMasterDemoSyn776429tAtEmLog_007:37:305
680439810,0EcMasterDemoSyn681429tAtEmLog_011:45:595
633739810,0EcMasterDemoSyn634729tAtEmLog_009:39:125
493639810,0EcMasterDemoSyn494629tAtEmLog_012:21:285
3171839810,0EcMasterDemoSyn3172829tAtEmLog_012:36:405
2809839810,0EcMasterDemoSyn2810829tAtEmLog_010:09:375
2656939810,0EcMasterDemoSyn2657929tAtEmLog_010:45:085
2656939810,0EcMasterDemoSyn2657929tAtEmLog_010:45:085
2434139810,0EcMasterDemoSyn2435129tAtEmLog_009:49:205
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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