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2025-12-22 - 08:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Dec 22, 2025 00:44:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11214391650,0EcMasterDemoSyn0-21swapper/423:43:004
29884391310,0EcMasterDemoSyn0-21swapper/422:42:104
846821050,1sleep08469-21ls20:45:000
703439920,0EcMasterDemoSyn704429tAtEmLog_023:22:435
2891139920,0EcMasterDemoSyn2892129tAtEmLog_020:20:105
204239910,0EcMasterDemoSyn205229tAtEmLog_023:37:575
2333439830,0EcMasterDemoSyn2334429tAtEmLog_021:10:545
110339830,0EcMasterDemoSyn111329tAtEmLog_000:13:275
2538739820,0EcMasterDemoSyn2539729tAtEmLog_022:57:235
2534139820,0EcMasterDemoSyn2535129tAtEmLog_023:32:525
2469139820,0EcMasterDemoSyn2470229tAtEmLog_021:46:225
216139820,0EcMasterDemoSyn217129tAtEmLog_023:02:265
2055039820,0EcMasterDemoSyn2056029tAtEmLog_023:12:365
1976139820,0EcMasterDemoSyn1977129tAtEmLog_021:05:485
1621739820,0EcMasterDemoSyn1622629tAtEmLog_023:27:475
584739810,0EcMasterDemoSyn585729tAtEmLog_021:36:145
584739810,0EcMasterDemoSyn585729tAtEmLog_021:36:145
2957239810,0EcMasterDemoSyn2958229tAtEmLog_022:06:395
2446239810,0EcMasterDemoSyn2447229tAtEmLog_000:08:215
2416439810,0EcMasterDemoSyn2417429tAtEmLog_020:10:025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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