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2026-02-18 - 22:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Wed Feb 18, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
183842990,1sleep50-21swapper/509:21:475
161002930,0sleep20-21swapper/210:14:052
964339910,0EcMasterDemoSyn965329tAtEmLog_007:22:385
2071039830,0EcMasterDemoSyn2072029tAtEmLog_008:53:535
1355339830,0EcMasterDemoSyn1356329tAtEmLog_012:16:445
2168239820,0EcMasterDemoSyn2169229tAtEmLog_007:47:585
1461839820,0EcMasterDemoSyn1462829tAtEmLog_011:05:455
138539820,0EcMasterDemoSyn139529tAtEmLog_008:13:195
818239810,0EcMasterDemoSyn819229tAtEmLog_010:09:585
613539810,0EcMasterDemoSyn614529tAtEmLog_008:23:295
3113439810,0EcMasterDemoSyn3114429tAtEmLog_008:08:165
2859139810,0EcMasterDemoSyn2860129tAtEmLog_011:31:065
2770139810,0EcMasterDemoSyn2771129tAtEmLog_012:06:365
1805239810,0EcMasterDemoSyn1806229tAtEmLog_008:48:505
1569439800,0EcMasterDemoSyn1570429tAtEmLog_008:43:465
2770139780,3EcMasterDemoSyn27708-21runintdemo5min12:06:363
375939740,0EcMasterDemoSyn0-21swapper/009:49:410
2355539380,1EcMasterDemoSyn23563-21grep11:46:192
73762340,0sleep17375-21ssh11:02:011
2828992826,2cyclictest16891-21kworker/2:2+events08:33:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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