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2026-02-22 - 21:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Feb 22, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2446739830,0EcMasterDemoSyn2447729tAtEmLog_012:07:225
514139820,0EcMasterDemoSyn515129tAtEmLog_012:32:445
297339820,0EcMasterDemoSyn298429tAtEmLog_007:18:205
1619639820,0EcMasterDemoSyn1620629tAtEmLog_010:51:195
1188539820,0EcMasterDemoSyn1189529tAtEmLog_010:31:025
2241039810,0EcMasterDemoSyn2242029tAtEmLog_007:58:545
2005539810,0EcMasterDemoSyn2006529tAtEmLog_007:53:505
1498839810,0EcMasterDemoSyn1499829tAtEmLog_007:43:415
3029939800,0EcMasterDemoSyn3030929tAtEmLog_010:41:105
1939039520,1EcMasterDemoSyn19397-21grep12:22:352
174762310,0sleep00-21swapper/011:27:450
112732260,0sleep10-21swapper/111:06:311
297339230,1EcMasterDemoSyn2982-21runintdemo5min07:18:192
3217439220,0EcMasterDemoSyn32183-21runintdemo5min08:19:113
30879992018,2cyclictest32662-21kworker/1:0+events12:37:481
3087899190,15cyclictest31431-21sh09:49:060
2447729190,0tAtEmLog_00-21swapper/512:12:265
3088199185,9cyclictest716-21snmpd07:52:113
30879991810,6cyclictest4614-21cut10:45:151
3087999180,10cyclictest23501-21rm09:44:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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