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2026-07-26 - 14:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Jul 26, 2026 12:44:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1157121600,0sleep20-21swapper/210:06:382
13872960,0sleep30-21swapper/309:42:513
2535139840,0EcMasterDemoSyn2536129tAtEmLog_011:45:495
2446639830,0EcMasterDemoSyn2447629tAtEmLog_010:14:325
76939820,0EcMasterDemoSyn78129tAtEmLog_007:47:295
436839820,0EcMasterDemoSyn437929tAtEmLog_010:39:535
3199539820,0EcMasterDemoSyn3200529tAtEmLog_009:23:495
312139820,0EcMasterDemoSyn313129tAtEmLog_009:44:075
3099039820,0EcMasterDemoSyn3100029tAtEmLog_011:30:365
3099039820,0EcMasterDemoSyn3100029tAtEmLog_011:30:365
1734539820,0EcMasterDemoSyn1735529tAtEmLog_008:22:585
2845539810,0EcMasterDemoSyn2846529tAtEmLog_007:37:205
2845539810,0EcMasterDemoSyn2846529tAtEmLog_007:37:205
2786639810,0EcMasterDemoSyn2787629tAtEmLog_010:34:505
1970039810,0EcMasterDemoSyn1971029tAtEmLog_008:28:035
1641039810,0EcMasterDemoSyn1642029tAtEmLog_007:11:595
1207739810,0EcMasterDemoSyn1208629tAtEmLog_009:49:115
1024039810,0EcMasterDemoSyn1025029tAtEmLog_008:07:465
1876839800,0EcMasterDemoSyn1877829tAtEmLog_007:17:035
1547539490,0EcMasterDemoSyn0-21swapper/310:09:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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