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2026-03-03 - 04:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Mar 03, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31573391460,0EcMasterDemoSyn0-21swapper/319:34:373
8631391240,0EcMasterDemoSyn0-21swapper/000:23:410
13710391000,4EcMasterDemoSyn13716-21ps00:08:284
2487139900,0EcMasterDemoSyn2488129tAtEmLog_021:16:035
213662900,0sleep30-21swapper/322:07:373
625539830,0EcMasterDemoSyn626529tAtEmLog_021:41:245
37039820,0EcMasterDemoSyn38029tAtEmLog_023:07:365
2982139820,0EcMasterDemoSyn2983129tAtEmLog_020:35:295
2951539820,0EcMasterDemoSyn2952529tAtEmLog_021:36:205
1541539820,0EcMasterDemoSyn1542529tAtEmLog_021:46:285
1395339820,0EcMasterDemoSyn1396329tAtEmLog_020:05:035
1039639820,0EcMasterDemoSyn1040529tAtEmLog_022:37:115
3157339810,0EcMasterDemoSyn3158329tAtEmLog_019:34:375
1835939810,0EcMasterDemoSyn1836929tAtEmLog_023:53:155
152139810,0EcMasterDemoSyn153129tAtEmLog_019:39:425
1371039810,0EcMasterDemoSyn1372029tAtEmLog_000:08:285
152139500,1EcMasterDemoSyn1528-21grep19:39:424
146082350,0sleep00-21swapper/022:04:160
77782310,1sleep30-21swapper/321:00:013
77782310,1sleep30-21swapper/321:00:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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