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2026-03-03 - 17:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Tue Mar 03, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4692391340,1EcMasterDemoSyn4701-21runintdemo5min12:08:314
9400391130,0EcMasterDemoSyn0-21swapper/411:53:194
23574391020,1EcMasterDemoSyn23583-21runintdemo5min11:43:101
1666939900,0EcMasterDemoSyn1667929tAtEmLog_007:19:285
748039840,0EcMasterDemoSyn749029tAtEmLog_009:11:035
748039840,0EcMasterDemoSyn749029tAtEmLog_009:11:025
1953839840,0EcMasterDemoSyn1954829tAtEmLog_008:30:295
372639830,0EcMasterDemoSyn373629tAtEmLog_009:05:585
2576139830,0EcMasterDemoSyn2576929tAtEmLog_009:56:415
879839820,0EcMasterDemoSyn880829tAtEmLog_008:10:115
469239820,0EcMasterDemoSyn470229tAtEmLog_012:08:315
1850339820,0EcMasterDemoSyn1851329tAtEmLog_011:58:235
1434039820,0EcMasterDemoSyn1435029tAtEmLog_008:20:195
536839810,0EcMasterDemoSyn537829tAtEmLog_011:33:015
2710839810,0EcMasterDemoSyn2711929tAtEmLog_012:38:575
3139939740,3EcMasterDemoSyn31407-21runintdemo5min08:55:490
1953839430,0EcMasterDemoSyn0-21swapper/208:30:282
297452260,1sleep229746-21ssh09:23:352
1178799196,9cyclictest13294-21ssh12:13:160
1178799191,14cyclictest780-21runrttasks11:27:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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