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2026-02-08 - 05:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Feb 08, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3040391230,0EcMasterDemoSyn0-21swapper/421:12:274
151262990,0sleep20-21swapper/200:16:092
2132139920,0EcMasterDemoSyn2133129tAtEmLog_000:20:045
2400339840,0EcMasterDemoSyn2401329tAtEmLog_019:46:145
2268139840,0EcMasterDemoSyn2269129tAtEmLog_020:52:105
3076739830,0EcMasterDemoSyn3077729tAtEmLog_021:27:405
1712339830,0EcMasterDemoSyn1713329tAtEmLog_021:37:495
1558639830,0EcMasterDemoSyn1559629tAtEmLog_020:36:575
477239820,0EcMasterDemoSyn478229tAtEmLog_019:05:405
266539820,0EcMasterDemoSyn267529tAtEmLog_023:34:265
2158239820,0EcMasterDemoSyn2159229tAtEmLog_021:58:065
134639820,0EcMasterDemoSyn135629tAtEmLog_020:06:325
1189339820,0EcMasterDemoSyn1190329tAtEmLog_019:20:535
313839810,0EcMasterDemoSyn314829tAtEmLog_021:53:005
2593739810,0EcMasterDemoSyn2594729tAtEmLog_023:29:225
2032139810,0EcMasterDemoSyn2033129tAtEmLog_020:47:065
1723939810,0EcMasterDemoSyn1724929tAtEmLog_022:48:485
1660739810,0EcMasterDemoSyn1661729tAtEmLog_019:31:035
315632490,1sleep50-21swapper/521:10:175
1896339200,1EcMasterDemoSyn18969-21ps19:36:074
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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