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2026-08-22 - 20:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sat Aug 22, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1234439165930,0EcMasterDemoSyn0-21swapper/512:38:325
161539165800,0EcMasterDemoSyn0-21swapper/510:50:245
2674139138340,1EcMasterDemoSyn0-21swapper/508:24:475
2565939131900,1EcMasterDemoSyn0-21swapper/508:57:355
2533739121110,0EcMasterDemoSyn0-21swapper/507:47:145
24413994680,0EcMasterDemoSyn0-21swapper/509:07:045
58573983390,0EcMasterDemoSyn0-21swapper/511:21:445
65203983260,0EcMasterDemoSyn0-21swapper/509:54:445
285823983250,0EcMasterDemoSyn0-21swapper/512:15:595
68363983180,0EcMasterDemoSyn0-21swapper/510:38:245
118703983160,0EcMasterDemoSyn0-21swapper/508:42:165
176793983140,0EcMasterDemoSyn0-21swapper/511:56:205
324663983130,0EcMasterDemoSyn0-21swapper/511:04:585
324663983130,0EcMasterDemoSyn0-21swapper/511:04:585
316023983120,0EcMasterDemoSyn0-21swapper/507:19:545
190073983120,0EcMasterDemoSyn0-21swapper/509:16:115
225363983110,0EcMasterDemoSyn0-21swapper/510:15:505
259453983100,0EcMasterDemoSyn0-21swapper/512:00:205
147293983100,0EcMasterDemoSyn0-21swapper/510:41:415
136073983100,0EcMasterDemoSyn0-21swapper/508:10:125
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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