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2026-01-29 - 03:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Thu Jan 29, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29311391330,1EcMasterDemoSyn29320-21runintdemo5min23:13:203
1249539920,0EcMasterDemoSyn1250529tAtEmLog_019:25:105
808439910,0EcMasterDemoSyn809429tAtEmLog_020:20:555
564639830,0EcMasterDemoSyn565629tAtEmLog_020:15:515
561339820,0EcMasterDemoSyn562329tAtEmLog_023:53:545
2982539820,0EcMasterDemoSyn2983529tAtEmLog_022:37:505
2501539820,0EcMasterDemoSyn2502529tAtEmLog_022:53:035
2398039820,0EcMasterDemoSyn2399029tAtEmLog_000:04:025
2255739820,0EcMasterDemoSyn2256729tAtEmLog_020:51:215
2018539820,0EcMasterDemoSyn2019529tAtEmLog_023:08:155
196939820,0EcMasterDemoSyn197929tAtEmLog_021:47:075
1904439820,0EcMasterDemoSyn1905429tAtEmLog_000:19:165
181639820,0EcMasterDemoSyn182629tAtEmLog_021:11:385
1119939820,0EcMasterDemoSyn1121029tAtEmLog_022:27:415
1037239820,0EcMasterDemoSyn1038229tAtEmLog_023:38:415
673639810,0EcMasterDemoSyn674629tAtEmLog_022:07:245
3067439810,0EcMasterDemoSyn3068429tAtEmLog_020:00:395
2593839810,0EcMasterDemoSyn2594829tAtEmLog_019:50:305
2513939810,0EcMasterDemoSyn2514929tAtEmLog_021:42:035
2050239810,0EcMasterDemoSyn2051229tAtEmLog_021:21:465
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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