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2026-03-09 - 13:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Mon Mar 09, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12488391110,0EcMasterDemoSyn0-21swapper/521:16:455
4642391060,2EcMasterDemoSyn4649-21grep20:10:483
11745391050,0EcMasterDemoSyn11751-21ps20:26:020
2284391000,2EcMasterDemoSyn2292-21grep20:05:453
102372940,4sleep40-21swapper/422:09:334
1173139920,0EcMasterDemoSyn1174129tAtEmLog_019:20:065
548739910,0EcMasterDemoSyn549729tAtEmLog_023:53:565
228439910,0EcMasterDemoSyn229429tAtEmLog_020:05:445
1884939830,0EcMasterDemoSyn1885929tAtEmLog_020:41:145
935039820,0EcMasterDemoSyn936029tAtEmLog_019:15:035
668239820,0EcMasterDemoSyn669229tAtEmLog_019:09:575
38539820,0EcMasterDemoSyn39529tAtEmLog_000:09:095
2356139820,0EcMasterDemoSyn2357129tAtEmLog_020:51:235
2280939820,0EcMasterDemoSyn2281929tAtEmLog_000:39:355
2056239820,0EcMasterDemoSyn2057229tAtEmLog_022:32:475
1646639820,0EcMasterDemoSyn1647629tAtEmLog_020:36:115
1337439820,0EcMasterDemoSyn1338429tAtEmLog_000:34:305
229639810,0EcMasterDemoSyn230629tAtEmLog_022:22:405
1884939720,1EcMasterDemoSyn18857-21grep20:41:143
59082560,1sleep05907-21ssh23:35:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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