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2026-02-15 - 18:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Sun Feb 15, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20889391020,2EcMasterDemoSyn0-21swapper/212:21:132
2971839850,0EcMasterDemoSyn29726-21runintdemo5min10:04:174
2039639840,0EcMasterDemoSyn2040629tAtEmLog_009:59:135
190039840,0EcMasterDemoSyn191129tAtEmLog_009:13:355
36239830,0EcMasterDemoSyn37229tAtEmLog_008:12:445
988339820,0EcMasterDemoSyn989329tAtEmLog_008:33:015
653839820,0EcMasterDemoSyn654829tAtEmLog_009:33:525
3042239820,0EcMasterDemoSyn3043229tAtEmLog_011:50:475
278639820,0EcMasterDemoSyn279629tAtEmLog_008:17:485
2570939820,0EcMasterDemoSyn2572029tAtEmLog_012:06:005
2442839820,0EcMasterDemoSyn2443829tAtEmLog_009:03:255
711239810,0EcMasterDemoSyn712229tAtEmLog_011:55:525
2625239810,0EcMasterDemoSyn2626229tAtEmLog_011:30:305
2088939810,0EcMasterDemoSyn2089929tAtEmLog_012:21:135
1728339810,0EcMasterDemoSyn1729329tAtEmLog_008:48:135
1224539810,0EcMasterDemoSyn1225529tAtEmLog_008:38:055
1211739810,0EcMasterDemoSyn1212729tAtEmLog_011:40:395
1575339230,1EcMasterDemoSyn15762-21runintdemo5min10:14:250
67382200,0sleep30-21swapper/312:13:563
267939200,6EcMasterDemoSyn0-21swapper/512:11:045
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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