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2026-05-01 - 18:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack5slot1.osadl.org (updated Fri May 01, 2026 12:44:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25402391070,4EcMasterDemoSyn25408-21ps10:45:353
1451739910,0EcMasterDemoSyn1452729tAtEmLog_008:08:245
1012439850,0EcMasterDemoSyn1013629tAtEmLog_012:06:435
1918839840,0EcMasterDemoSyn1919829tAtEmLog_009:49:495
3019839830,0EcMasterDemoSyn3020829tAtEmLog_007:32:555
3255539820,0EcMasterDemoSyn3256529tAtEmLog_007:37:595
312882820,0sleep30-21swapper/311:25:143
2458039820,0EcMasterDemoSyn2459029tAtEmLog_011:21:065
1924239820,0EcMasterDemoSyn1925229tAtEmLog_008:18:335
1687439820,0EcMasterDemoSyn1688429tAtEmLog_008:13:295
1216239820,0EcMasterDemoSyn1217229tAtEmLog_008:03:205
506439810,0EcMasterDemoSyn507429tAtEmLog_007:48:075
2540239810,0EcMasterDemoSyn2541229tAtEmLog_010:45:355
2316639810,0EcMasterDemoSyn2317629tAtEmLog_012:32:045
102439810,0EcMasterDemoSyn103429tAtEmLog_012:01:405
191492800,0sleep20-21swapper/210:42:352
191492800,0sleep20-21swapper/210:42:342
373639660,1EcMasterDemoSyn3745-21wc08:54:023
83802350,0sleep20-21swapper/211:30:122
2842439250,1EcMasterDemoSyn28433-21wc09:19:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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