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2026-02-18 - 02:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Wed Feb 18, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18257391390,1EcMasterDemoSyn18265-21runintdemo5min22:35:120
1502839940,0EcMasterDemoSyn1503929tAtEmLog_022:50:255
499939920,0EcMasterDemoSyn500929tAtEmLog_023:56:205
499939920,0EcMasterDemoSyn500929tAtEmLog_023:56:205
2760639890,0EcMasterDemoSyn0-21swapper/200:26:462
612239840,0EcMasterDemoSyn613229tAtEmLog_019:22:315
547839830,0EcMasterDemoSyn548729tAtEmLog_022:45:205
2761439830,0EcMasterDemoSyn2762429tAtEmLog_022:04:465
2760639830,0EcMasterDemoSyn2761629tAtEmLog_000:26:465
2435039830,0EcMasterDemoSyn2436029tAtEmLog_021:09:005
2094739830,0EcMasterDemoSyn2095729tAtEmLog_019:52:555
1825739830,0EcMasterDemoSyn1826729tAtEmLog_022:35:125
774839820,0EcMasterDemoSyn775829tAtEmLog_020:33:295
60439820,0EcMasterDemoSyn61429tAtEmLog_020:18:165
2819339820,0EcMasterDemoSyn2820329tAtEmLog_022:40:165
1563539820,0EcMasterDemoSyn1564529tAtEmLog_019:42:485
1008439820,0EcMasterDemoSyn1009429tAtEmLog_023:41:075
3111539810,0EcMasterDemoSyn3112529tAtEmLog_019:07:185
2359839810,0EcMasterDemoSyn2360829tAtEmLog_019:58:005
1725939810,0EcMasterDemoSyn1726929tAtEmLog_020:53:475
108039780,1EcMasterDemoSyn0-21swapper/419:12:214
246782700,1sleep10-21swapper/121:09:591
1847839640,1EcMasterDemoSyn18487-21wc21:24:122
2334839320,0EcMasterDemoSyn0-21swapper/400:06:294
58492250,1sleep10-21swapper/122:45:231
2597939250,0EcMasterDemoSyn25987-21grep20:03:050
217852240,0sleep50-21swapper/500:05:255
127842240,1sleep0221rcuc/000:00:250
31426992321,2cyclictest14804-21kworker/3:1+events21:49:333
31426992321,2cyclictest14804-21kworker/3:1+events21:49:333
305092230,0sleep40-21swapper/422:41:154
31426992017,2cyclictest14804-21kworker/3:1+events20:33:303
1848999200,10tDemoTimingTask19950-21taskset21:25:015
164202190,0sleep30-21swapper/323:26:523
3141599180,9cyclictest780-21runrttasks22:26:420
3141599180,15cyclictest780-21runrttasks23:47:030
3141599180,10cyclictest32064-21sh00:11:040
3141599180,10cyclictest17474-21sh00:39:470
3141599180,10cyclictest16965-21sh22:34:300
1855629180,7tAtEmLog_021917-21chrt00:24:045
1725939180,1EcMasterDemoSyn17267-21grep20:53:472
883739170,7EcMasterDemoSyn12265-21chrt21:55:385
32749991716,0tDemoTimingTask0-21swapper/500:16:365
3142699170,10cyclictest493-21rm23:35:483
3142699170,10cyclictest493-21rm23:35:483
3142499170,10cyclictest12639-21ssh23:42:542
3141599175,9cyclictest728-21lldpd22:00:110
3141599175,9cyclictest31882-21ssh22:06:220
3141599170,9cyclictest7252-21sh21:17:480
3141599170,9cyclictest27224-21grep23:15:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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