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2026-01-25 - 17:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Sun Jan 25, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9302391572670,0EcMasterDemoSyn0-21swapper/509:30:245
1056539222060,1EcMasterDemoSyn0-21swapper/511:19:175
239853983340,0EcMasterDemoSyn0-21swapper/512:09:315
190213983290,0EcMasterDemoSyn0-21swapper/510:16:155
244373983270,0EcMasterDemoSyn0-21swapper/511:34:135
121353983200,0EcMasterDemoSyn0-21swapper/508:23:015
121353983200,0EcMasterDemoSyn0-21swapper/508:23:005
177253983190,0EcMasterDemoSyn0-21swapper/507:53:525
162133983190,0EcMasterDemoSyn0-21swapper/509:38:245
122253983170,0EcMasterDemoSyn0-21swapper/508:59:265
220353983160,0EcMasterDemoSyn0-21swapper/507:22:305
180013983150,0EcMasterDemoSyn0-21swapper/512:37:545
71813983130,0EcMasterDemoSyn0-21swapper/509:28:335
193683983120,0EcMasterDemoSyn0-21swapper/511:28:455
319403983100,0EcMasterDemoSyn0-21swapper/507:34:115
291993983100,0EcMasterDemoSyn0-21swapper/511:39:405
48423983090,0EcMasterDemoSyn0-21swapper/511:47:405
15063983090,0EcMasterDemoSyn0-21swapper/508:46:195
8093983070,0EcMasterDemoSyn0-21swapper/509:56:145
207493983070,0EcMasterDemoSyn0-21swapper/510:55:135
53233983000,0EcMasterDemoSyn0-21swapper/510:37:235
38363982940,1EcMasterDemoSyn0-21swapper/508:14:375
270883943680,0EcMasterDemoSyn0-21swapper/508:04:255
148063941880,0EcMasterDemoSyn0-21swapper/511:59:195
4873915860,1EcMasterDemoSyn0-21swapper/512:19:215
7530399240,0EcMasterDemoSyn0-21swapper/207:06:262
15885395400,0EcMasterDemoSyn0-21swapper/509:02:435
14601391260,0EcMasterDemoSyn0-21swapper/211:23:122
616939930,0EcMasterDemoSyn617929tAtEmLog_010:02:425
39539920,0EcMasterDemoSyn40529tAtEmLog_011:42:515
2530939920,0EcMasterDemoSyn2531929tAtEmLog_008:37:095
1932439920,0EcMasterDemoSyn1933829tAtEmLog_007:55:145
1266839920,0EcMasterDemoSyn1267829tAtEmLog_012:31:175
1266839920,0EcMasterDemoSyn1267829tAtEmLog_012:31:165
908539910,0EcMasterDemoSyn909529tAtEmLog_007:09:195
902039910,0EcMasterDemoSyn903029tAtEmLog_012:28:005
382739910,0EcMasterDemoSyn383729tAtEmLog_012:21:485
2465739910,0EcMasterDemoSyn2466729tAtEmLog_012:10:095
1988839910,0EcMasterDemoSyn1989829tAtEmLog_010:54:025
186939910,0EcMasterDemoSyn187929tAtEmLog_010:34:235
1856139910,0EcMasterDemoSyn1857129tAtEmLog_007:19:315
903639900,0EcMasterDemoSyn904629tAtEmLog_010:40:345
524539900,0EcMasterDemoSyn525529tAtEmLog_011:13:215
427839900,0EcMasterDemoSyn0-21swapper/311:46:303
3053639900,0EcMasterDemoSyn3054629tAtEmLog_008:07:155
2614439900,0EcMasterDemoSyn2615429tAtEmLog_009:49:585
2035439900,0EcMasterDemoSyn2036429tAtEmLog_008:31:185
1352339890,0EcMasterDemoSyn1353329tAtEmLog_007:49:245
2362339850,0EcMasterDemoSyn2363329tAtEmLog_010:21:155
2362339850,0EcMasterDemoSyn2363329tAtEmLog_010:21:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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