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2026-02-17 - 18:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Tue Feb 17, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2719439910,0EcMasterDemoSyn2720429tAtEmLog_008:43:335
1299739910,0EcMasterDemoSyn1300729tAtEmLog_008:13:075
727239830,0EcMasterDemoSyn728229tAtEmLog_010:55:225
660039830,0EcMasterDemoSyn661029tAtEmLog_009:08:545
2631239830,0EcMasterDemoSyn2632229tAtEmLog_011:05:325
221739830,0EcMasterDemoSyn222729tAtEmLog_011:46:065
2051539830,0EcMasterDemoSyn2052529tAtEmLog_011:56:145
588939820,0EcMasterDemoSyn589929tAtEmLog_010:19:525
314339820,0EcMasterDemoSyn315329tAtEmLog_007:52:505
3083539820,0EcMasterDemoSyn3084529tAtEmLog_007:42:415
3045339820,0EcMasterDemoSyn3046329tAtEmLog_010:50:195
2439139820,0EcMasterDemoSyn2440129tAtEmLog_009:54:325
2009939820,0EcMasterDemoSyn2010929tAtEmLog_008:28:205
1943839820,0EcMasterDemoSyn1944829tAtEmLog_012:31:445
1014639820,0EcMasterDemoSyn1015729tAtEmLog_009:29:115
2481739810,0EcMasterDemoSyn2482729tAtEmLog_008:38:275
1996239810,0EcMasterDemoSyn1997229tAtEmLog_010:09:455
1851939810,0EcMasterDemoSyn1852929tAtEmLog_007:17:195
1616139810,0EcMasterDemoSyn1617129tAtEmLog_007:12:165
1212739810,0EcMasterDemoSyn1213729tAtEmLog_011:15:415
1079139320,0EcMasterDemoSyn10800-21runintdemo5min10:04:394
2367739260,0EcMasterDemoSyn23686-21runintdemo5min09:19:010
2246039220,1EcMasterDemoSyn22466-21ps08:33:240
1409199190,15cyclictest19262-21ssh09:33:570
1409199180,9cyclictest30132-21sh12:01:370
1409199180,10cyclictest29796-21sh11:44:010
1409199180,10cyclictest2325-21sh12:22:200
2918499170,10tDemoTimingTask30539-21chrt09:40:015
187499171,14tDemoTimingTask4065-21chrt09:01:315
1409599171,12cyclictest16-1pr/legacy08:53:404
1409599171,12cyclictest16-1pr/legacy08:53:404
14092991713,3cyclictest10380-21runintdemo5min12:26:401
1409299170,9cyclictest17742-21ssh09:32:531
1409199170,9cyclictest27668-21sh10:49:240
1409199170,9cyclictest20916-21sh11:39:030
1409199170,9cyclictest2034-21sh11:10:200
1409199170,9cyclictest15076-21sh11:00:070
1409199170,9cyclictest1313-21sh09:59:270
1409199170,14cyclictest10914-21sh10:57:370
1062329170,9tAtEmLog_019779-21chrt10:45:015
2956799160,9tDemoTimingTask29598-21chrt08:48:415
1553499160,9tDemoTimingTask20845-21taskset12:15:015
1520729160,14tAtEmLog_015800-21taskset10:25:105
1409499163,9cyclictest26081-21unixbench_singl11:05:243
1409499160,9cyclictest27478-21diskmemload12:18:343
1409399168,6cyclictest32050-21grep11:45:142
1409299160,9cyclictest19965-21ssh09:16:261
1409199168,6cyclictest11353-21tail10:40:150
1409199165,6cyclictest12472-21cpuspeed_turbos12:10:130
1409199161,8cyclictest9489-21sh12:08:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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