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2026-02-23 - 19:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Mon Feb 23, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24054391490,1EcMasterDemoSyn24060-21ps09:04:561
1625339920,0EcMasterDemoSyn1626329tAtEmLog_012:37:555
947039910,0EcMasterDemoSyn948029tAtEmLog_010:10:525
947039910,0EcMasterDemoSyn948029tAtEmLog_010:10:525
917339900,0EcMasterDemoSyn918329tAtEmLog_010:46:215
592439840,0EcMasterDemoSyn593429tAtEmLog_007:18:275
496439840,0EcMasterDemoSyn497429tAtEmLog_010:26:045
2167439840,0EcMasterDemoSyn2168429tAtEmLog_008:59:525
382339830,0EcMasterDemoSyn383329tAtEmLog_011:37:045
2618239830,0EcMasterDemoSyn2619229tAtEmLog_012:07:295
1710239830,0EcMasterDemoSyn1711229tAtEmLog_012:02:255
1710239830,0EcMasterDemoSyn1711229tAtEmLog_012:02:255
3050139820,0EcMasterDemoSyn3051129tAtEmLog_012:27:465
2672839820,0EcMasterDemoSyn2673829tAtEmLog_009:10:015
2270139820,0EcMasterDemoSyn2271129tAtEmLog_007:53:575
1903639820,0EcMasterDemoSyn1904629tAtEmLog_009:40:255
935739810,0EcMasterDemoSyn936729tAtEmLog_009:35:225
881639810,0EcMasterDemoSyn882629tAtEmLog_011:21:515
830439810,0EcMasterDemoSyn831429tAtEmLog_007:23:315
793939810,0EcMasterDemoSyn794929tAtEmLog_011:57:215
1798839810,0EcMasterDemoSyn1799829tAtEmLog_007:43:495
1421539810,0EcMasterDemoSyn1422529tAtEmLog_009:55:385
1555339800,0EcMasterDemoSyn1556329tAtEmLog_007:38:435
1869839670,0EcMasterDemoSyn18703-21runintdemo5min10:15:563
3177439450,0EcMasterDemoSyn31781-21runintdemo5min11:16:460
1301839280,0EcMasterDemoSyn13024-21ps07:33:400
1421539250,0EcMasterDemoSyn0-21swapper/309:55:393
479639190,0EcMasterDemoSyn0-21swapper/508:24:215
1417991912,6cyclictest15696-21turbostat.cron07:40:004
141799181,13cyclictest16-1pr/legacy09:45:294
141099180,10cyclictest8851-21ssh10:10:250
141099180,10cyclictest8851-21ssh10:10:240
1067099180,10tDemoTimingTask11098-21chrt07:30:015
2712299170,7tDemoTimingTask29605-21chrt11:33:455
2168429170,7tAtEmLog_023834-21taskset09:02:055
141799170,10cyclictest17448-21ssh11:09:244
141499171,12cyclictest16-1pr/legacy08:29:263
141199175,8cyclictest15320-21tune2fs08:45:141
141199170,9cyclictest11963-21/usr/sbin/munin09:55:201
141099170,9cyclictest8033-21ssh10:45:330
141099170,9cyclictest19391-21sh09:40:390
141099170,9cyclictest18248-21cut11:45:150
141099170,9cyclictest15353-21diskmemload11:07:580
141099170,13cyclictest780-21runrttasks08:32:260
3178599160,9tDemoTimingTask27326-21sleep11:19:555
3010729160,10tAtEmLog_030139-21chrt08:09:145
141499164,8cyclictest21628-21latency_hist09:25:003
141299165,6cyclictest7676-21seq10:27:572
141299163,9cyclictest755-21postgres08:25:052
141299161,9cyclictest7949-21sh11:39:582
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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