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2025-08-28 - 22:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Thu Aug 28, 2025 12:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
686291850,184tAtEmLog_067639EcMasterDemoSyn10:38:353
6887291840,183tAtEmLog_0687739EcMasterDemoSyn09:27:363
28741291830,182tAtEmLog_02873139EcMasterDemoSyn11:24:133
473439930,0EcMasterDemoSyn474429tAtEmLog_008:33:573
2761439920,0EcMasterDemoSyn2762429tAtEmLog_007:12:493
1238039920,0EcMasterDemoSyn1239029tAtEmLog_008:49:103
727839860,0EcMasterDemoSyn728829tAtEmLog_008:39:023
644239860,0EcMasterDemoSyn645229tAtEmLog_009:47:543
287139860,0EcMasterDemoSyn288129tAtEmLog_007:28:033
2698139860,0EcMasterDemoSyn2699129tAtEmLog_010:53:493
2610739860,0EcMasterDemoSyn2611729tAtEmLog_010:03:073
2610739860,0EcMasterDemoSyn2611729tAtEmLog_010:03:073
248739860,0EcMasterDemoSyn249729tAtEmLog_011:44:313
2408939860,0EcMasterDemoSyn2409929tAtEmLog_012:35:133
2061939860,0EcMasterDemoSyn2062929tAtEmLog_010:23:243
1898239860,0EcMasterDemoSyn1899229tAtEmLog_007:58:283
1544939860,0EcMasterDemoSyn1545929tAtEmLog_012:30:093
959739850,0EcMasterDemoSyn960729tAtEmLog_011:29:173
850739850,0EcMasterDemoSyn851729tAtEmLog_011:03:573
687739850,0EcMasterDemoSyn688729tAtEmLog_009:22:323
450739850,0EcMasterDemoSyn451729tAtEmLog_012:04:483
2859239850,0EcMasterDemoSyn2860229tAtEmLog_009:14:313
2834639850,0EcMasterDemoSyn2835629tAtEmLog_011:59:443
2582139850,0EcMasterDemoSyn2583129tAtEmLog_009:37:453
239639850,0EcMasterDemoSyn240629tAtEmLog_009:19:343
1973639850,0EcMasterDemoSyn1974629tAtEmLog_011:54:403
188839850,0EcMasterDemoSyn189829tAtEmLog_008:28:523
1491639850,0EcMasterDemoSyn1492629tAtEmLog_008:54:143
1100439850,0EcMasterDemoSyn1101429tAtEmLog_007:43:153
571539840,0EcMasterDemoSyn572529tAtEmLog_007:33:063
239962720,0sleep6581ksoftirqd/609:10:146
115772670,0sleep50-21swapper/509:26:075
321612650,2sleep1211ksoftirqd/110:07:211
46652640,0sleep00-21swapper/011:25:150
60232600,0sleep40-21swapper/411:01:074
115712570,0sleep20-21swapper/209:51:192
63972550,0sleep40-21swapper/410:12:214
690029530,52tAtEmLog_0688839EcMasterDemoSyn12:25:053
89602500,0sleep40-21swapper/408:40:254
2532099502,16cyclictest0-21swapper/010:48:440
2532099452,23cyclictest415-21systemd-journal11:59:440
2532099450,42cyclictest415-21systemd-journal12:04:480
2532099426,16cyclictest415-21systemd-journal08:18:440
2532099383,16cyclictest0-21swapper/007:30:000
2532099372,18cyclictest0-21swapper/010:00:130
2532099372,18cyclictest0-21swapper/010:00:120
2532699357,16cyclictest20228-21ps10:48:451
2532699347,16cyclictest415-21systemd-journal10:58:531
25326993410,16cyclictest0-21swapper/110:53:491
25320993412,8cyclictest0-21swapper/007:48:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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