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2026-02-08 - 12:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Sun Feb 08, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3040391230,0EcMasterDemoSyn0-21swapper/421:12:274
151262990,0sleep20-21swapper/200:16:092
2132139920,0EcMasterDemoSyn2133129tAtEmLog_000:20:045
2400339840,0EcMasterDemoSyn2401329tAtEmLog_019:46:145
2268139840,0EcMasterDemoSyn2269129tAtEmLog_020:52:105
3076739830,0EcMasterDemoSyn3077729tAtEmLog_021:27:405
1712339830,0EcMasterDemoSyn1713329tAtEmLog_021:37:495
1558639830,0EcMasterDemoSyn1559629tAtEmLog_020:36:575
477239820,0EcMasterDemoSyn478229tAtEmLog_019:05:405
266539820,0EcMasterDemoSyn267529tAtEmLog_023:34:265
2158239820,0EcMasterDemoSyn2159229tAtEmLog_021:58:065
134639820,0EcMasterDemoSyn135629tAtEmLog_020:06:325
1189339820,0EcMasterDemoSyn1190329tAtEmLog_019:20:535
313839810,0EcMasterDemoSyn314829tAtEmLog_021:53:005
2593739810,0EcMasterDemoSyn2594729tAtEmLog_023:29:225
2032139810,0EcMasterDemoSyn2033129tAtEmLog_020:47:065
1723939810,0EcMasterDemoSyn1724929tAtEmLog_022:48:485
1660739810,0EcMasterDemoSyn1661729tAtEmLog_019:31:035
315632490,1sleep50-21swapper/521:10:175
1896339200,1EcMasterDemoSyn18969-21ps19:36:074
716099180,15tDemoTimingTask7199-21chrt19:10:555
518999181,7cyclictest12762-21cat23:40:000
518999180,10cyclictest6167-21idleruntime-cro21:49:590
3044499180,10tDemoTimingTask31565-21chrt23:50:015
1897499180,10tDemoTimingTask19900-21chrt19:40:015
520399170,9cyclictest12653-21sh22:28:423
519499170,9cyclictest22804-21ssh22:34:161
518999174,9cyclictest780-21runrttasks22:10:210
518999174,9cyclictest780-21runrttasks22:10:210
518999174,9cyclictest32013-21wc00:25:230
518999171,9cyclictest31793-21latency_hist23:15:000
518999170,9cyclictest1904-21sh22:22:360
518999170,9cyclictest18489-21sh23:06:590
518999170,9cyclictest15330-21sh00:16:180
518999170,14cyclictest26128-21ssh22:18:150
1232829170,7tAtEmLog_013567-21chrt23:04:515
716099160,14tDemoTimingTask7806-21chrt19:15:085
5207991613,2cyclictest699-21polkitd21:00:014
5203991612,3cyclictest30899-21cpuspeed_turbos21:10:113
520399160,9cyclictest780-21runrttasks00:28:213
519499169,5cyclictest16465-21tail21:55:141
519499160,9cyclictest30104-21sh22:38:031
519499160,10cyclictest5713-21ssh22:42:161
518999164,8cyclictest1852-21taskset22:58:020
518999163,9cyclictest780-21runrttasks19:31:110
5189991611,4cyclictest32619-21cpuspeed_turbos23:15:130
518999160,13cyclictest27714-21sh22:36:240
518999160,11cyclictest6065-21aten2_r5power_p22:25:120
3140999160,10tDemoTimingTask31413-21chrt20:01:285
1713239160,7EcMasterDemoSyn19141-21taskset22:14:415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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