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2026-05-31 - 23:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Sun May 31, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17664391200,3EcMasterDemoSyn17670-21runintdemo5min11:51:243
2870639910,8EcMasterDemoSyn2871629tAtEmLog_007:22:385
39272880,0sleep10-21swapper/110:50:181
628339840,0EcMasterDemoSyn629329tAtEmLog_007:42:565
955439830,0EcMasterDemoSyn956429tAtEmLog_010:35:215
3267339830,0EcMasterDemoSyn3268329tAtEmLog_009:19:165
2845539820,0EcMasterDemoSyn2846529tAtEmLog_008:28:335
2779039820,0EcMasterDemoSyn2780029tAtEmLog_011:20:595
2676439820,0EcMasterDemoSyn2677429tAtEmLog_011:56:295
2676439820,0EcMasterDemoSyn2677429tAtEmLog_011:56:295
1366339820,0EcMasterDemoSyn1367329tAtEmLog_011:31:075
954939810,0EcMasterDemoSyn955929tAtEmLog_011:10:505
2771139810,0EcMasterDemoSyn2772129tAtEmLog_009:34:295
2579939810,0EcMasterDemoSyn2580929tAtEmLog_008:23:305
1573839810,0EcMasterDemoSyn1574829tAtEmLog_008:03:125
136739810,0EcMasterDemoSyn137729tAtEmLog_007:32:475
2277339800,0EcMasterDemoSyn2278329tAtEmLog_011:36:125
240832640,0sleep10-21swapper/112:30:431
21891993124,6cyclictest1600-21kworker/2:2+events12:31:442
21895993028,2cyclictest17886-21kworker/3:1+events09:28:433
21891992826,2cyclictest17788-21kworker/2:0+events09:01:192
21898992523,2cyclictest15379-21kworker/4:0+events10:16:194
21895992421,2cyclictest17886-21kworker/3:1+events08:46:023
21891992421,2cyclictest17788-21kworker/2:0+events10:36:142
21891992317,5cyclictest1600-21kworker/2:2+events11:21:242
21885992320,2cyclictest18510-21kworker/1:0+events10:41:281
1796339230,3EcMasterDemoSyn17971-21runintdemo5min10:04:550
21895992219,2cyclictest17886-21kworker/3:1+events08:35:583
21891992216,5cyclictest17788-21kworker/2:0+events09:05:232
21885992220,2cyclictest18510-21kworker/1:0+events12:37:181
21885992219,2cyclictest18510-21kworker/1:0+events08:54:021
21885992219,2cyclictest18510-21kworker/1:0+events07:49:141
21895992119,2cyclictest17886-21kworker/3:1+events08:44:173
21898992018,2cyclictest15379-21kworker/4:0+events11:02:094
21895992017,2cyclictest17886-21kworker/3:1+events11:42:133
21895992017,2cyclictest17886-21kworker/3:1+events08:55:423
21895992016,3cyclictest648-21dbus-daemon07:34:593
1679329200,0tAtEmLog_00-21swapper/512:31:575
21895991916,2cyclictest17886-21kworker/3:1+events12:07:473
2189199196,7cyclictest24237-21ssh09:32:022
2189199195,6cyclictest11737-21cpuspeed_turbos07:55:122
21891991916,2cyclictest17788-21kworker/2:0+events10:20:502
21891991916,2cyclictest1600-21kworker/2:2+events11:33:052
21891991914,4cyclictest17788-21kworker/2:0+events10:28:042
2189199190,9cyclictest9514-21ssh09:24:232
2189199190,9cyclictest8912-21sh09:41:172
2189199190,9cyclictest6446-21latency_hist11:10:002
2189199190,9cyclictest2414-21sh12:00:472
2189199190,9cyclictest13598-21sh10:01:492
2189199190,8cyclictest26955-21sh10:09:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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