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2025-11-03 - 13:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Mon Nov 03, 2025 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15494997280,725tDemoTimingTask17826-21sleep20:39:595
303391010,0EcMasterDemoSyn31329tAtEmLog_021:30:445
1626639990,0EcMasterDemoSyn1627629tAtEmLog_023:52:435
117132930,0sleep00-21swapper/022:00:140
985439920,0EcMasterDemoSyn986429tAtEmLog_019:13:505
926439920,0EcMasterDemoSyn927429tAtEmLog_023:47:395
2705239920,0EcMasterDemoSyn2706229tAtEmLog_022:31:355
2418239920,0EcMasterDemoSyn2419229tAtEmLog_019:44:155
1719139920,0EcMasterDemoSyn1720129tAtEmLog_021:20:365
993239910,0EcMasterDemoSyn994229tAtEmLog_022:41:445
577339910,0EcMasterDemoSyn578329tAtEmLog_020:14:415
2955639910,0EcMasterDemoSyn2956629tAtEmLog_023:17:145
228139910,0EcMasterDemoSyn229129tAtEmLog_022:36:405
2183039910,0EcMasterDemoSyn2184029tAtEmLog_019:39:115
204439910,0EcMasterDemoSyn205529tAtEmLog_023:42:355
204439910,0EcMasterDemoSyn205529tAtEmLog_023:42:355
1444839910,0EcMasterDemoSyn1445829tAtEmLog_023:07:055
1398039910,0EcMasterDemoSyn1399029tAtEmLog_022:01:105
1218839910,0EcMasterDemoSyn1219829tAtEmLog_019:18:545
1210839910,0EcMasterDemoSyn1211929tAtEmLog_022:21:275
110739910,0EcMasterDemoSyn111729tAtEmLog_020:04:325
436139900,0EcMasterDemoSyn437129tAtEmLog_022:16:235
3123439900,0EcMasterDemoSyn3124429tAtEmLog_021:05:225
2971339900,0EcMasterDemoSyn2972329tAtEmLog_000:02:525
2916539900,0EcMasterDemoSyn2917529tAtEmLog_000:28:135
2651039900,0EcMasterDemoSyn2652029tAtEmLog_019:49:205
2318639900,0EcMasterDemoSyn2319629tAtEmLog_023:57:485
2318639900,0EcMasterDemoSyn2319629tAtEmLog_023:57:485
208539900,0EcMasterDemoSyn209529tAtEmLog_021:10:275
1970939900,0EcMasterDemoSyn1971929tAtEmLog_022:26:315
1920139900,0EcMasterDemoSyn1921129tAtEmLog_019:34:075
1686939900,0EcMasterDemoSyn1687929tAtEmLog_019:29:035
2873939890,0EcMasterDemoSyn2874929tAtEmLog_021:00:195
1717039890,0EcMasterDemoSyn1718029tAtEmLog_022:46:485
1670139890,0EcMasterDemoSyn1670729tAtEmLog_000:18:055
2262739880,0EcMasterDemoSyn2263729tAtEmLog_000:23:095
1548339560,0EcMasterDemoSyn1549329tAtEmLog_020:40:015
3088629410,39tAtEmLog_027843-21turbostat21:54:555
7719992422,1cyclictest10566-21kworker/4:2+events19:34:064
7719992421,2cyclictest10566-21kworker/4:2+events20:09:374
58502240,0sleep10-21swapper/119:05:131
2727139180,0EcMasterDemoSyn0-21swapper/523:37:315
348639170,1EcMasterDemoSyn3493-21grep00:07:560
7701991511,3cyclictest31267-21turbostat20:00:010
7701991511,3cyclictest31267-21turbostat20:00:000
3206839150,3EcMasterDemoSyn651irq_work/522:56:575
770199143,4cyclictest816-21runrttasks21:42:160
770199140,6cyclictest816-21runrttasks00:20:420
771499130,11cyclictest7302-21latency_hist21:15:003
771099131,10cyclictest30947-21memory21:05:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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