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2026-01-26 - 06:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Mon Jan 26, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2742939155500,0EcMasterDemoSyn0-21swapper/523:36:375
1578939150490,1EcMasterDemoSyn0-21swapper/522:13:325
184183998920,0EcMasterDemoSyn0-21swapper/522:51:055
56493997370,0EcMasterDemoSyn0-21swapper/520:50:255
133653983310,0EcMasterDemoSyn0-21swapper/500:33:055
244803983260,0EcMasterDemoSyn0-21swapper/521:46:335
59203983210,0EcMasterDemoSyn0-21swapper/522:38:175
151883983190,0EcMasterDemoSyn0-21swapper/521:36:435
114343983150,0EcMasterDemoSyn0-21swapper/520:57:005
113653983140,0EcMasterDemoSyn0-21swapper/521:33:045
124163983120,0EcMasterDemoSyn0-21swapper/520:22:455
266553983110,0EcMasterDemoSyn0-21swapper/521:50:125
145333983080,0EcMasterDemoSyn0-21swapper/523:59:135
49063983070,0EcMasterDemoSyn0-21swapper/523:12:345
115903983070,0EcMasterDemoSyn0-21swapper/522:09:095
140243983050,0EcMasterDemoSyn0-21swapper/520:25:185
299543983010,0EcMasterDemoSyn0-21swapper/523:05:175
150203954900,1EcMasterDemoSyn0-21swapper/519:50:205
20498391340,0EcMasterDemoSyn20502-21sed19:55:222
2954739970,0EcMasterDemoSyn2955729tAtEmLog_022:28:455
2853239950,0EcMasterDemoSyn2854229tAtEmLog_023:03:015
2472039940,0EcMasterDemoSyn2473629tAtEmLog_020:35:245
1376239930,0EcMasterDemoSyn1377229tAtEmLog_019:13:275
938639920,0EcMasterDemoSyn939629tAtEmLog_023:52:565
624139920,0EcMasterDemoSyn625129tAtEmLog_020:15:235
3266039920,0EcMasterDemoSyn3267029tAtEmLog_019:34:555
860339910,0EcMasterDemoSyn861329tAtEmLog_019:42:585
3240239910,0EcMasterDemoSyn3241229tAtEmLog_023:42:235
3213639910,9EcMasterDemoSyn3214629tAtEmLog_020:09:335
296839910,0EcMasterDemoSyn297829tAtEmLog_020:48:105
2676639910,0EcMasterDemoSyn2677629tAtEmLog_019:27:175
2210439910,0EcMasterDemoSyn2211429tAtEmLog_000:06:035
2143439910,0EcMasterDemoSyn2144429tAtEmLog_019:20:445
1489039910,0EcMasterDemoSyn1490029tAtEmLog_023:24:095
1344739910,0EcMasterDemoSyn1345729tAtEmLog_021:00:115
101739910,0EcMasterDemoSyn102729tAtEmLog_021:20:365
363239900,0EcMasterDemoSyn364229tAtEmLog_023:45:395
2819139900,0EcMasterDemoSyn2820129tAtEmLog_000:14:045
263172900,0sleep40-21swapper/420:02:034
2487439900,0EcMasterDemoSyn2488429tAtEmLog_022:59:445
1796439900,0EcMasterDemoSyn1797429tAtEmLog_023:26:205
1702039900,0EcMasterDemoSyn1703029tAtEmLog_019:15:585
1211539900,0EcMasterDemoSyn1212529tAtEmLog_019:45:525
915639890,0EcMasterDemoSyn916629tAtEmLog_023:16:525
445239890,0EcMasterDemoSyn446229tAtEmLog_019:39:175
187339860,0EcMasterDemoSyn189329tAtEmLog_000:20:155
1008439860,1EcMasterDemoSyn10091-21ps19:45:091
3107439850,0EcMasterDemoSyn3108429tAtEmLog_000:15:535
2407539840,0EcMasterDemoSyn2409229tAtEmLog_021:10:235
944339830,0EcMasterDemoSyn945329tAtEmLog_022:41:075
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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