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2025-11-02 - 21:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Sun Nov 02, 2025 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63829910950,1093tDemoTimingTask64572sleep509:30:435
21904391050,1EcMasterDemoSyn21912-21grep07:13:454
25250391010,0EcMasterDemoSyn2526029tAtEmLog_010:11:135
1167391010,0EcMasterDemoSyn117729tAtEmLog_007:39:055
2306391000,0EcMasterDemoSyn231629tAtEmLog_008:50:065
2118139990,0EcMasterDemoSyn2119129tAtEmLog_011:01:565
116739930,1EcMasterDemoSyn1173-21runintdemo5min07:39:062
67872920,0sleep20-21swapper/211:16:302
3252039920,0EcMasterDemoSyn3253029tAtEmLog_009:25:355
2740839920,0EcMasterDemoSyn2741829tAtEmLog_008:34:535
2190439920,0EcMasterDemoSyn2191429tAtEmLog_007:13:455
1962339920,0EcMasterDemoSyn1963329tAtEmLog_009:15:275
1320839920,0EcMasterDemoSyn1321829tAtEmLog_009:10:225
840939910,0EcMasterDemoSyn841929tAtEmLog_007:54:195
698039910,0EcMasterDemoSyn699229tAtEmLog_011:42:305
3130639910,0EcMasterDemoSyn3131629tAtEmLog_012:23:045
3124639910,0EcMasterDemoSyn3125629tAtEmLog_007:34:025
260039910,0EcMasterDemoSyn261029tAtEmLog_010:46:435
2584039910,0EcMasterDemoSyn2585029tAtEmLog_009:45:525
2244639910,0EcMasterDemoSyn2245629tAtEmLog_008:24:445
1956239910,0EcMasterDemoSyn1957229tAtEmLog_007:08:405
1704439910,0EcMasterDemoSyn1705429tAtEmLog_010:31:295
1542439910,0EcMasterDemoSyn1543429tAtEmLog_008:09:315
1309439910,0EcMasterDemoSyn1310529tAtEmLog_008:04:285
740639900,0EcMasterDemoSyn741629tAtEmLog_011:17:095
3271239900,0EcMasterDemoSyn3272229tAtEmLog_011:37:265
3247239900,0EcMasterDemoSyn3248229tAtEmLog_012:02:475
1934139900,0EcMasterDemoSyn1935129tAtEmLog_010:06:085
640139890,0EcMasterDemoSyn641129tAtEmLog_012:07:515
485439890,0EcMasterDemoSyn486429tAtEmLog_010:21:215
3203739890,0EcMasterDemoSyn3204729tAtEmLog_009:50:565
3151639890,0EcMasterDemoSyn3152629tAtEmLog_010:16:185
3151639890,0EcMasterDemoSyn3152629tAtEmLog_010:16:175
2898539890,0EcMasterDemoSyn2899529tAtEmLog_010:41:395
2891539890,0EcMasterDemoSyn2892529tAtEmLog_007:28:575
2636839890,0EcMasterDemoSyn2637829tAtEmLog_011:32:215
2507439890,0EcMasterDemoSyn2508429tAtEmLog_008:29:485
2300539890,0EcMasterDemoSyn2301529tAtEmLog_010:36:355
1922939890,0EcMasterDemoSyn1923929tAtEmLog_009:40:485
2622139880,0EcMasterDemoSyn2623129tAtEmLog_009:20:315
128139880,0EcMasterDemoSyn129129tAtEmLog_011:12:045
1074439880,0EcMasterDemoSyn1075429tAtEmLog_007:59:225
3238239260,0EcMasterDemoSyn0-21swapper/508:45:015
3238239260,0EcMasterDemoSyn0-21swapper/508:45:015
19772992623,2cyclictest10632-21kworker/3:0+events11:17:093
2423739250,0EcMasterDemoSyn0-21swapper/107:18:491
19759992320,2cyclictest11043-21kworker/1:0+events09:35:421
281362220,1sleep10-21swapper/111:34:151
19759992017,2cyclictest23160-21turbostat09:49:551
19772991815,2cyclictest10632-21kworker/3:0+events07:59:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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