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2026-01-13 - 06:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Tue Jan 13, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2790739840,0EcMasterDemoSyn2791729tAtEmLog_023:57:455
3159239830,0EcMasterDemoSyn3160229tAtEmLog_020:34:565
1641539830,0EcMasterDemoSyn1642529tAtEmLog_021:45:555
1566139830,0EcMasterDemoSyn1567129tAtEmLog_022:56:545
1467439830,0EcMasterDemoSyn1468429tAtEmLog_019:59:265
996239820,0EcMasterDemoSyn997229tAtEmLog_019:49:175
567539820,0EcMasterDemoSyn568529tAtEmLog_023:27:205
2899539820,0EcMasterDemoSyn2900529tAtEmLog_023:22:165
2284839820,0EcMasterDemoSyn2285829tAtEmLog_019:08:435
2212339820,0EcMasterDemoSyn2213329tAtEmLog_020:14:385
522939810,0EcMasterDemoSyn523929tAtEmLog_019:39:095
3026339810,0EcMasterDemoSyn3027329tAtEmLog_019:23:565
2586539810,0EcMasterDemoSyn2587529tAtEmLog_021:15:295
2285739810,0EcMasterDemoSyn2286729tAtEmLog_000:12:585
377439800,0EcMasterDemoSyn378429tAtEmLog_000:38:195
1195039570,0EcMasterDemoSyn1196029tAtEmLog_021:30:415
42842220,0sleep40-21swapper/419:35:174
2305399200,9cyclictest27799-21ssh21:16:484
2305399200,10cyclictest5970-21ssh22:51:274
2305399200,10cyclictest10939-21ssh23:48:294
2305399190,10cyclictest8637-21rm00:22:534
2305399190,10cyclictest13710-21ssh22:55:324
245629180,0tAtEmLog_00-21swapper/522:01:075
2305399180,9cyclictest831-21runrttasks22:03:314
2305399180,9cyclictest3847-21ssh00:38:214
2305399180,9cyclictest29281-21sh22:10:324
2305399180,9cyclictest28105-21cat19:20:004
2305399180,9cyclictest26380-21ssh23:20:254
2305399180,9cyclictest26185-21ssh22:26:574
2305399180,9cyclictest24694-21chrt22:44:334
2305399180,9cyclictest24354-21sh22:08:364
2305399180,7cyclictest22100-21cron23:55:004
2305399180,10cyclictest831-21runrttasks23:06:294
2305399180,10cyclictest831-21runrttasks21:44:014
2304399181,9cyclictest20800-21chrt22:24:320
23043991810,6cyclictest15467-21tr21:10:160
2304399180,9cyclictest831-21runrttasks21:28:380
2304399180,14cyclictest6601-21sh00:21:240
2304399180,10cyclictest26933-21sh23:03:250
897439170,7EcMasterDemoSyn15978-21taskset00:26:435
897439170,7EcMasterDemoSyn15978-21taskset00:26:435
2305399171,12cyclictest16-1pr/legacy21:35:454
2305399170,9cyclictest744-21snmpd22:16:454
2305399170,9cyclictest5416-21ssh21:58:074
2305399170,9cyclictest31866-21sh22:48:114
2305399170,9cyclictest26204-21sh23:56:324
2305399170,9cyclictest23312-21/usr/sbin/munin19:10:194
2305399170,9cyclictest22496-21/usr/sbin/munin20:15:234
2305399170,9cyclictest21780-21ssh00:12:134
2305299173,9cyclictest2676-21aten2_r5power_e20:45:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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