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2026-02-16 - 02:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Mon Feb 16, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3068739950,0EcMasterDemoSyn3069829tAtEmLog_021:49:085
2613339920,4EcMasterDemoSyn26139-21ps21:28:512
178092900,0sleep10-21swapper/100:04:561
1218439860,0EcMasterDemoSyn1219429tAtEmLog_021:39:005
700139840,0EcMasterDemoSyn701129tAtEmLog_023:05:125
700139840,0EcMasterDemoSyn701129tAtEmLog_023:05:125
372339840,0EcMasterDemoSyn373329tAtEmLog_023:20:255
2090239830,0EcMasterDemoSyn2091429tAtEmLog_022:19:345
1386639830,0EcMasterDemoSyn1387629tAtEmLog_020:48:175
617139820,0EcMasterDemoSyn618229tAtEmLog_020:33:045
2439739820,0EcMasterDemoSyn2440729tAtEmLog_020:02:395
2196739820,0EcMasterDemoSyn2197729tAtEmLog_019:57:345
818739810,0EcMasterDemoSyn819729tAtEmLog_023:40:425
513839810,0EcMasterDemoSyn514829tAtEmLog_019:22:055
240139600,1EcMasterDemoSyn2408-21grep22:44:553
617139450,0EcMasterDemoSyn0-21swapper/020:33:040
2675439390,1EcMasterDemoSyn26760-21ps20:07:430
30758992219,2cyclictest2626-21kworker/3:1+events19:17:003
728029200,0tAtEmLog_00-21swapper/522:34:455
3075799200,10cyclictest6552-21ssh00:15:472
3075799190,7cyclictest20281-21sh23:47:522
30756991917,2cyclictest2415-21kworker/1:0+events20:38:091
30758991816,2cyclictest2626-21kworker/3:1+events22:55:023
3075799186,3cyclictest2196739EcMasterDemoSyn19:57:352
3075799180,7cyclictest28889-21ssh00:28:472
3075799180,7cyclictest20397-21ssh23:12:062
3075799180,7cyclictest10375-21ssh23:42:142
3075799180,10cyclictest20894-21latency_hist22:55:002
3075599186,9cyclictest18959-21sh21:42:210
3075599180,14cyclictest31549-21sh00:11:520
3075599180,10cyclictest32425-21sh23:36:180
3047529180,10tAtEmLog_031361-21chrt22:25:015
2198599180,10tDemoTimingTask28654-21chrt23:35:015
1682199181,7tDemoTimingTask21147-21chrt21:25:245
30758991713,3cyclictest9457-21systemctl21:20:013
3075899170,10cyclictest4610-21ssh22:45:213
3075799179,6cyclictest29063-21tail21:30:152
3075799175,8cyclictest26961-21cron20:09:592
3075799174,6cyclictest9473-21cpuspeed_turbos21:55:142
3075799174,6cyclictest13137-21df19:40:122
3075799173,7cyclictest9409-21xargs19:30:222
3075799173,6cyclictest19312-21date23:30:002
3075799171,8cyclictest28325-21latency_hist23:35:012
3075799171,10cyclictest1677-21sh22:08:482
3075799170,9cyclictest18355-21sh21:24:502
3075799170,9cyclictest10138-21ssh23:24:562
3075799170,8cyclictest16100-21ssh00:21:052
3075799170,7cyclictest96131cpuspeed_turbos20:40:132
3075799170,7cyclictest4779-21grep22:45:232
3075799170,7cyclictest30171-21sh22:24:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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