You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-01 - 09:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Sun Feb 01, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
770639910,0EcMasterDemoSyn771629tAtEmLog_020:31:185
2224639910,0EcMasterDemoSyn2225629tAtEmLog_021:01:455
882239830,0EcMasterDemoSyn883229tAtEmLog_000:34:445
2882939830,0EcMasterDemoSyn2883929tAtEmLog_019:05:075
2882939830,0EcMasterDemoSyn2883929tAtEmLog_019:05:075
2517639830,0EcMasterDemoSyn2518729tAtEmLog_021:27:065
1274439830,0EcMasterDemoSyn1275429tAtEmLog_020:41:285
1118939830,0EcMasterDemoSyn1119929tAtEmLog_022:48:145
1066139830,0EcMasterDemoSyn1067129tAtEmLog_023:59:135
769539820,0EcMasterDemoSyn770529tAtEmLog_019:25:235
2460339820,0EcMasterDemoSyn2461329tAtEmLog_021:06:495
2460339820,0EcMasterDemoSyn2461329tAtEmLog_021:06:485
2265139820,0EcMasterDemoSyn2266129tAtEmLog_019:55:505
1734139820,0EcMasterDemoSyn1735129tAtEmLog_019:45:415
1574339820,0EcMasterDemoSyn1575329tAtEmLog_021:57:315
1492739820,0EcMasterDemoSyn1493729tAtEmLog_019:40:375
660639810,0EcMasterDemoSyn661629tAtEmLog_023:38:565
1582239810,0EcMasterDemoSyn1583229tAtEmLog_021:22:025
186872770,0sleep40-21swapper/422:52:054
1989539640,0EcMasterDemoSyn0-21swapper/100:04:181
1989539370,1EcMasterDemoSyn19892-21ssh00:04:184
1492739360,0EcMasterDemoSyn0-21swapper/119:40:371
30940993027,2cyclictest1217-21kworker/3:2+events00:24:343
307902300,1sleep130792-21rm23:51:591
43382270,0sleep30-21swapper/322:09:213
3094299214,6cyclictest7801runrttasks21:30:274
3094299194,10cyclictest5216-21/usr/sbin/munin22:45:174
30942991916,2cyclictest8228-21turbostat19:34:564
3094299186,8cyclictest10071-21ssh23:58:494
3094299185,9cyclictest6675-21ssh21:35:114
3094299185,8cyclictest32613-21ssh21:14:004
3094299185,7cyclictest13118-21ssh22:31:164
3094299183,11cyclictest374-21ssh00:11:524
3093599184,9cyclictest21147-21latency_hist00:05:012
3092699185,10cyclictest29111-21/usr/sbin/munin00:10:090
3092699181,9cyclictest24051-21runrttasks23:48:360
3092699181,9cyclictest17478-21diskmemload22:15:460
3092699180,10cyclictest780-21runrttasks20:22:060
299529180,8tAtEmLog_05318-21taskset20:26:035
2045999180,11tDemoTimingTask23961-21chrt22:20:015
661799170,7tDemoTimingTask12141-21chrt23:41:305
3094299176,9cyclictest25158-21ps21:27:054
3094299175,8cyclictest9065-21sh21:54:114
3094299175,8cyclictest31459-21ssh00:29:254
3094299175,8cyclictest29359-21ssh22:22:404
3094299175,8cyclictest16312-21ssh00:38:384
3094299175,8cyclictest12797-21chrt20:41:404
3094299175,8cyclictest11618-21ssh22:13:034
3094299175,7cyclictest18652-21ssh21:23:544
3094299174,8cyclictest26147-21diskmemload23:14:104
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional