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2026-01-24 - 14:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Sat Jan 24, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8053393891060,0EcMasterDemoSyn0-21swapper/507:15:245
25703391655500,0EcMasterDemoSyn0-21swapper/508:45:195
29344391242240,0EcMasterDemoSyn0-21swapper/510:00:235
2323339248830,0EcMasterDemoSyn0-21swapper/508:42:255
2117839212190,0EcMasterDemoSyn0-21swapper/511:38:205
1484839184230,0EcMasterDemoSyn0-21swapper/509:09:215
655439120050,0EcMasterDemoSyn0-21swapper/509:00:155
37853983290,1EcMasterDemoSyn0-21swapper/511:19:455
26973983280,0EcMasterDemoSyn0-21swapper/511:53:185
229773983270,0EcMasterDemoSyn0-21swapper/507:31:015
252103983250,0EcMasterDemoSyn0-21swapper/511:42:215
162993983250,0EcMasterDemoSyn0-21swapper/510:56:275
88353983240,0EcMasterDemoSyn0-21swapper/510:49:325
18553983240,0EcMasterDemoSyn0-21swapper/507:44:525
110833983220,0EcMasterDemoSyn0-21swapper/511:26:195
300893983210,0EcMasterDemoSyn0-21swapper/511:47:285
76683983200,0EcMasterDemoSyn0-21swapper/510:11:395
218333983180,0EcMasterDemoSyn0-21swapper/511:03:225
206503983150,0EcMasterDemoSyn0-21swapper/512:12:575
117803983150,0EcMasterDemoSyn0-21swapper/512:39:315
306103983140,0EcMasterDemoSyn0-21swapper/511:12:505
94403983130,0EcMasterDemoSyn0-21swapper/508:28:125
136563983120,0EcMasterDemoSyn0-21swapper/509:43:145
73913983110,0EcMasterDemoSyn0-21swapper/512:34:485
292433983100,0EcMasterDemoSyn0-21swapper/507:39:245
120543983090,0EcMasterDemoSyn0-21swapper/510:16:235
252843983070,0EcMasterDemoSyn0-21swapper/511:06:175
18799391070,1EcMasterDemoSyn18810-21proc_pri12:10:192
37239920,0EcMasterDemoSyn38229tAtEmLog_007:06:105
3012539920,0EcMasterDemoSyn3013529tAtEmLog_010:35:355
2172139920,0EcMasterDemoSyn2173129tAtEmLog_010:26:515
1334039920,0EcMasterDemoSyn1335029tAtEmLog_007:55:425
119339920,0EcMasterDemoSyn120329tAtEmLog_008:19:455
690039910,0EcMasterDemoSyn691029tAtEmLog_007:14:555
436139910,0EcMasterDemoSyn437129tAtEmLog_008:56:325
3211139910,0EcMasterDemoSyn3212129tAtEmLog_009:27:295
2766739910,0EcMasterDemoSyn2767729tAtEmLog_009:22:455
2400739910,0EcMasterDemoSyn2401729tAtEmLog_009:19:285
1691839910,0EcMasterDemoSyn1692829tAtEmLog_009:45:425
1637439910,0EcMasterDemoSyn1638429tAtEmLog_007:25:075
1513639910,0EcMasterDemoSyn1514629tAtEmLog_012:05:575
1420339910,0EcMasterDemoSyn1421329tAtEmLog_007:21:295
1243739910,0EcMasterDemoSyn1244729tAtEmLog_012:04:295
2504239900,0EcMasterDemoSyn2505229tAtEmLog_012:17:365
1812839900,0EcMasterDemoSyn1813829tAtEmLog_008:01:095
1622839900,0EcMasterDemoSyn1623829tAtEmLog_011:32:265
708939890,0EcMasterDemoSyn709929tAtEmLog_011:57:565
429339840,0EcMasterDemoSyn430329tAtEmLog_009:32:345
194342840,1sleep319439-21runintdemo5min12:10:303
1700239840,0EcMasterDemoSyn1701229tAtEmLog_008:35:245
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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