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2026-02-06 - 10:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Fri Feb 06, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7373391260,1EcMasterDemoSyn7379-21ps20:31:450
116422980,1sleep00-21swapper/022:13:110
2524839830,0EcMasterDemoSyn2525829tAtEmLog_020:01:195
2524839830,0EcMasterDemoSyn2525829tAtEmLog_020:01:195
1157139830,0EcMasterDemoSyn1158129tAtEmLog_022:13:105
869439820,0EcMasterDemoSyn870429tAtEmLog_019:25:505
3163639820,0EcMasterDemoSyn3164629tAtEmLog_019:05:335
265739820,0EcMasterDemoSyn266729tAtEmLog_020:21:365
2313239820,0EcMasterDemoSyn2314029tAtEmLog_023:14:015
1713139820,0EcMasterDemoSyn1714129tAtEmLog_020:52:025
906539810,0EcMasterDemoSyn907529tAtEmLog_023:24:095
633439810,0EcMasterDemoSyn634429tAtEmLog_019:20:445
3268139810,0EcMasterDemoSyn3269129tAtEmLog_020:16:325
2551839810,0EcMasterDemoSyn2552829tAtEmLog_022:03:015
2550539810,0EcMasterDemoSyn2551529tAtEmLog_021:27:315
2177639810,0EcMasterDemoSyn2178629tAtEmLog_000:25:005
1325139810,0EcMasterDemoSyn1326129tAtEmLog_023:44:265
3031739800,0EcMasterDemoSyn3032729tAtEmLog_020:11:285
974339560,0EcMasterDemoSyn0-21swapper/222:48:392
264702540,1sleep30-21swapper/322:39:133
1399439300,1EcMasterDemoSyn14002-21rm23:08:564
3205599240,10cyclictest11535-21sh21:20:130
3205599230,9cyclictest780-21runrttasks20:28:240
310492230,0sleep30-21swapper/322:23:463
3205599220,7cyclictest1253-21cat21:50:000
1157339220,1EcMasterDemoSyn11581-21grep21:37:401
3205599210,9cyclictest827-21fschecks_count23:55:150
3205599210,9cyclictest20327-21fschecks_count22:00:150
3205599210,8cyclictest780-21runrttasks20:55:380
3205599210,7cyclictest27848-21sh21:10:480
3205599210,10cyclictest17789-21sh21:40:250
3205599206,6cyclictest24830-21cat23:15:000
3205599201,9cyclictest1698-21diskmemload23:01:380
3205599200,9cyclictest887-21ssh22:42:390
3205599200,9cyclictest811-21runintdemo5min22:53:440
3205599200,9cyclictest780-21runrttasks21:07:330
3205599200,9cyclictest780-21runrttasks19:10:190
3205599200,9cyclictest6605-21diskmemload00:34:290
3205599200,9cyclictest5340-21ssh22:45:330
3205599200,9cyclictest4277-21ssh23:39:280
3205599200,9cyclictest3893-21diskmemload00:15:060
3205599200,9cyclictest3244-21sh00:14:520
3205599200,9cyclictest26494-21sh00:26:590
3205599200,9cyclictest26462-21ssh23:51:020
3205599200,9cyclictest22973-21timerandwakeup22:55:240
3205599200,9cyclictest22350-21sh23:49:300
3205599200,9cyclictest21493-21sh00:24:490
3205599200,9cyclictest21150-21ssh23:30:190
3205599200,9cyclictest10603-21sh23:06:330
3205599200,9cyclictest10537-21ssh21:36:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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