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2026-02-08 - 21:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Sun Feb 08, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10475391190,1EcMasterDemoSyn10483-21runintdemo5min09:02:230
732339910,0EcMasterDemoSyn7328-21runintdemo5min12:04:562
337839910,0EcMasterDemoSyn338829tAtEmLog_008:47:105
337839910,0EcMasterDemoSyn338829tAtEmLog_008:47:095
405539830,0EcMasterDemoSyn406529tAtEmLog_011:09:095
3251039830,0EcMasterDemoSyn3252029tAtEmLog_009:37:535
2238139830,0EcMasterDemoSyn2239129tAtEmLog_011:19:185
922639820,0EcMasterDemoSyn923729tAtEmLog_009:42:575
3104939820,0EcMasterDemoSyn3105929tAtEmLog_008:37:015
286139820,0EcMasterDemoSyn287129tAtEmLog_012:20:095
2763439820,0EcMasterDemoSyn2764429tAtEmLog_010:28:355
1177739820,0EcMasterDemoSyn1178729tAtEmLog_007:56:275
468939810,0EcMasterDemoSyn469929tAtEmLog_010:33:385
3060439810,0EcMasterDemoSyn3061429tAtEmLog_011:59:525
2181539810,0EcMasterDemoSyn2182529tAtEmLog_012:30:175
324839760,1EcMasterDemoSyn3254-21ps11:44:390
2790739660,0EcMasterDemoSyn0-21swapper/109:17:351
2869039320,1EcMasterDemoSyn28697-21grep08:31:572
2586139320,1EcMasterDemoSyn25867-21ps12:15:040
71132300,0sleep00-21swapper/010:52:380
20792992310,6cyclictest28039-21grep11:40:134
2077599220,10cyclictest21265-21sh12:12:010
1743039220,1EcMasterDemoSyn17439-21runintdemo5min11:34:300
2077599210,7cyclictest30525-21ssh10:30:100
2077599210,7cyclictest26357-21sh09:16:320
2079299200,9cyclictest780-21runrttasks12:02:404
2079299200,9cyclictest1693-21ssh09:56:124
2079299200,10cyclictest3445-21rm11:08:444
2079299200,10cyclictest21569-21ssh10:42:454
2079299200,10cyclictest21569-21ssh10:42:454
2079299200,10cyclictest20004-21ssh09:30:314
2079299200,10cyclictest18425-21chrt10:23:314
2079299200,10cyclictest14983-21sh12:26:124
2077599205,6cyclictest16947-21aten2_r5power_p10:05:120
2077599201,7cyclictest14336-21latency_hist11:15:010
2077599201,11cyclictest30020-21cat10:30:000
2077599201,11cyclictest17875-21/usr/sbin/munin09:30:090
2077599200,9cyclictest3743-21idleruntime12:20:160
2077599200,9cyclictest3676-21sh12:02:200
2077599200,9cyclictest15469-21ssh09:45:560
2077599200,8cyclictest16660-21sh12:27:240
2077599200,7cyclictest27364-21sh11:04:060
2077599200,7cyclictest24348-21sh09:50:440
2077599200,7cyclictest16176-21sh10:57:380
2077599200,7cyclictest12800-21latency_hist11:50:000
2077599200,6cyclictest7221-21ssh10:35:120
2077599200,12cyclictest27625-21sh12:33:470
2077599200,12cyclictest21030-21ssh11:18:210
2077599200,12cyclictest11983-21ssh09:44:510
2079299193,8cyclictest9766-21proc_pri09:00:204
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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