You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-10 - 14:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Tue Feb 10, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212892930,1sleep20-21swapper/212:02:492
3144539920,0EcMasterDemoSyn3145529tAtEmLog_008:01:525
1441639920,0EcMasterDemoSyn1442629tAtEmLog_007:26:235
2981739900,0EcMasterDemoSyn2982729tAtEmLog_009:07:485
2981739900,0EcMasterDemoSyn2982729tAtEmLog_009:07:485
139139900,0EcMasterDemoSyn140129tAtEmLog_008:06:575
2746239840,0EcMasterDemoSyn2747229tAtEmLog_009:02:435
294339830,0EcMasterDemoSyn295329tAtEmLog_010:59:215
2670939830,0EcMasterDemoSyn2671929tAtEmLog_007:51:435
2435239830,0EcMasterDemoSyn2436229tAtEmLog_007:46:405
1704839830,0EcMasterDemoSyn1705829tAtEmLog_010:49:135
1563039830,0EcMasterDemoSyn1564029tAtEmLog_008:37:225
2671239820,0EcMasterDemoSyn2672229tAtEmLog_010:18:475
2129439820,0EcMasterDemoSyn2130429tAtEmLog_011:09:305
1801139820,0EcMasterDemoSyn1802129tAtEmLog_008:42:265
1205939820,0EcMasterDemoSyn1206929tAtEmLog_007:21:185
832539810,0EcMasterDemoSyn833529tAtEmLog_009:33:095
1677739810,0EcMasterDemoSyn1678729tAtEmLog_007:31:275
2162639700,0EcMasterDemoSyn0-21swapper/012:20:290
528399190,15cyclictest4976-21ssh12:11:271
528599181,15cyclictest5545-21/usr/sbin/munin07:10:172
527899180,14cyclictest10519-21sh09:51:370
527899180,10cyclictest669-21sh10:04:400
3153129180,0tAtEmLog_00-21swapper/510:08:365
298739180,0EcMasterDemoSyn0-21swapper/512:10:215
727729170,9tAtEmLog_07309-21chrt07:11:135
528699174,9cyclictest716-21snmpd12:24:133
528599179,6cyclictest28633-21cut09:05:152
528599179,6cyclictest28633-21cut09:05:142
527899175,9cyclictest25908-21sh09:42:310
527899170,9cyclictest780-21runrttasks11:36:280
527899170,9cyclictest780-21runrttasks09:13:470
527899170,9cyclictest780-21runrttasks09:13:460
527899170,9cyclictest3165-21sh12:29:010
527899170,9cyclictest20866-21sh10:33:160
527899170,9cyclictest19100-21sh12:01:150
527899170,9cyclictest15875-21latency_hist08:39:590
527899170,7cyclictest780-21runrttasks07:26:460
527899170,14cyclictest12656-21runrttasks09:17:400
3012799170,10tDemoTimingTask30204-21chrt11:50:075
2672399170,7tDemoTimingTask30193-21chrt10:20:185
210929170,7tAtEmLog_08368-21taskset11:37:525
1217299170,10tDemoTimingTask12192-21chrt11:04:265
683899160,9tDemoTimingTask15287-21chrt11:59:565
528799168,6cyclictest7395-21tune2fs11:55:144
528799164,8cyclictest25967-21cpuspeed09:25:114
528699163,11cyclictest15440-21unixbench_singl08:35:253
528699160,9cyclictest20134-21sh11:26:043
528699160,10cyclictest13758-21ssh09:18:243
5285991612,3cyclictest645-21avahi-daemon07:30:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional