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2026-02-21 - 00:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Fri Feb 20, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
648839920,0EcMasterDemoSyn649829tAtEmLog_007:38:215
809039830,0EcMasterDemoSyn810029tAtEmLog_011:26:345
2926239820,0EcMasterDemoSyn2927229tAtEmLog_007:18:055
1635239820,0EcMasterDemoSyn1636229tAtEmLog_007:58:395
1399339820,0EcMasterDemoSyn1400329tAtEmLog_007:53:345
1176839820,0EcMasterDemoSyn1177829tAtEmLog_012:22:215
3240539810,0EcMasterDemoSyn3241529tAtEmLog_010:10:305
3240539810,0EcMasterDemoSyn3241529tAtEmLog_010:10:295
3180339810,0EcMasterDemoSyn3181329tAtEmLog_010:46:005
235639810,0EcMasterDemoSyn236629tAtEmLog_012:17:165
159039810,0EcMasterDemoSyn160029tAtEmLog_007:28:145
1474539810,0EcMasterDemoSyn1475529tAtEmLog_009:04:345
887339440,1EcMasterDemoSyn8882-21wc07:43:262
316032320,1sleep50-21swapper/509:35:135
218782240,3sleep014-21ksoftirqd/010:05:140
1704739230,0EcMasterDemoSyn0-21swapper/309:45:073
2447099213,9cyclictest29589-21latency_hist07:19:591
24476992018,2cyclictest31951-21kworker/4:2+events12:37:344
2447099206,7cyclictest15846-21ssh10:37:301
2447099200,10cyclictest20387-21ssh10:57:581
2447099190,10cyclictest21657-21ssh12:27:571
2447099190,10cyclictest15535-21sh12:24:591
3045739180,1EcMasterDemoSyn30463-21ps09:34:592
2642799180,10tDemoTimingTask27138-21chrt09:50:165
24474991814,3cyclictest22230-21cpuspeed_turbos09:30:133
2447499180,9cyclictest12749-21sh12:23:013
2447099180,9cyclictest22126-21ssh09:12:061
2447099180,10cyclictest32535-21rm10:10:351
2447099180,10cyclictest32535-21rm10:10:341
2447099180,10cyclictest29528-21runrttasks11:03:001
2447099180,10cyclictest21831-21perl12:10:131
2447099180,10cyclictest12042-21/usr/sbin/munin07:50:201
2446999185,9cyclictest28466-21sh11:02:160
2446999185,9cyclictest24257-21sh12:29:480
2446999185,9cyclictest20084-21sh09:46:050
2446999181,9cyclictest780-21runrttasks11:28:400
24469991815,2cyclictest25952-21turbostat08:24:550
2446999180,9cyclictest23244-21sh12:10:280
2446999180,14cyclictest19813-21sh11:50:510
2446999180,10cyclictest5877-21sh12:19:450
1711299180,8tDemoTimingTask17561-21chrt09:10:045
1664999180,10tDemoTimingTask20756-21chrt12:10:005
1361799180,11tDemoTimingTask20992-21chrt10:05:015
663699170,7tDemoTimingTask7268-21chrt12:38:005
368399170,7tDemoTimingTask4586-21taskset11:06:545
2820229170,10tAtEmLog_028207-21chrt08:24:015
24476991713,3cyclictest648-21dbus-daemon10:40:004
2447099178,3cyclictest0-21swapper/111:15:001
2447099170,9cyclictest780-21runrttasks09:23:061
2447099170,9cyclictest6978-21/usr/sbin/munin07:40:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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