You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-05 - 08:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Thu Feb 05, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2862321000,1sleep4581rcuc/423:05:454
2305539920,0EcMasterDemoSyn2306529tAtEmLog_021:17:195
2076739920,0EcMasterDemoSyn2077729tAtEmLog_019:15:375
2387239910,0EcMasterDemoSyn2388229tAtEmLog_020:31:405
2387239910,0EcMasterDemoSyn2388229tAtEmLog_020:31:405
954039840,0EcMasterDemoSyn955029tAtEmLog_021:27:265
595239830,0EcMasterDemoSyn596229tAtEmLog_021:02:055
2860839830,0EcMasterDemoSyn2861829tAtEmLog_020:41:495
3022139820,0EcMasterDemoSyn3023129tAtEmLog_019:35:545
2795039820,0EcMasterDemoSyn2796029tAtEmLog_021:37:355
2359139820,0EcMasterDemoSyn2360129tAtEmLog_021:52:485
1840639820,0EcMasterDemoSyn1841629tAtEmLog_019:10:335
1677139820,0EcMasterDemoSyn1678129tAtEmLog_020:16:285
1440539820,0EcMasterDemoSyn1441529tAtEmLog_020:11:235
478139810,0EcMasterDemoSyn479129tAtEmLog_021:42:405
1882739810,0EcMasterDemoSyn1883729tAtEmLog_021:32:315
1402539810,0EcMasterDemoSyn1403529tAtEmLog_023:34:135
1646199220,9cyclictest28649-21sh22:48:570
1329129190,0tAtEmLog_00-21swapper/519:05:265
969599180,8tDemoTimingTask17787-21chrt22:42:425
725839180,0EcMasterDemoSyn0-21swapper/519:56:115
1647899181,12cyclictest16-1pr/legacy19:51:054
16473991810,6cyclictest9790-21grep21:10:143
1646999185,9cyclictest711-21gdbus20:55:192
16469991810,6cyclictest30633-21grep20:45:252
1646199185,9cyclictest16905-21sh23:53:220
1646199185,9cyclictest1020-21sh00:37:580
1646199181,12cyclictest16-1pr/legacy23:29:080
1646199181,11cyclictest17257-21cat22:25:010
1646199180,10cyclictest8888-21sh23:49:070
1646999170,10cyclictest12160-21ssh00:25:532
1646999170,10cyclictest12160-21ssh00:25:532
16465991713,3cyclictest12001-21cron22:40:001
1646199170,9cyclictest3856-21sh22:52:460
1646199170,9cyclictest32175-21sh00:19:530
1646199170,9cyclictest32175-21sh00:19:520
1646199170,9cyclictest30408-21sh00:00:210
1646199170,9cyclictest27760-21sort22:30:190
1646199170,9cyclictest2224-21sh21:23:540
357239160,9EcMasterDemoSyn3615-21taskset20:57:065
1647899168,6cyclictest32247-21tune2fs22:15:144
16478991612,3cyclictest693-21in:imuxsock00:00:004
16478991612,3cyclictest23307-21turbostat00:15:004
1646999169,5cyclictest24535-21sh23:40:002
1646999168,6cyclictest4772-21grep21:00:182
16465991612,3cyclictest699-21polkitd00:05:031
1646599160,9cyclictest19628-21ssh22:25:271
1646599160,9cyclictest19628-21ssh22:25:271
1646199164,9cyclictest2040-21sh22:15:590
1646199163,9cyclictest25297-21sh21:18:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional