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2026-01-21 - 10:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Wed Jan 21, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2635421050,0sleep483-21kcompactd022:26:174
656239830,0EcMasterDemoSyn657229tAtEmLog_023:28:165
94239820,0EcMasterDemoSyn95229tAtEmLog_020:30:475
3070339820,0EcMasterDemoSyn3071329tAtEmLog_021:16:245
2162339820,0EcMasterDemoSyn2163529tAtEmLog_021:11:215
1749639820,0EcMasterDemoSyn1750629tAtEmLog_021:06:175
1741039820,0EcMasterDemoSyn1742029tAtEmLog_022:57:495
1275639820,0EcMasterDemoSyn1276629tAtEmLog_020:56:085
1008739820,0EcMasterDemoSyn1009729tAtEmLog_019:45:085
457439810,0EcMasterDemoSyn458429tAtEmLog_000:03:455
3099839810,0EcMasterDemoSyn3100829tAtEmLog_020:25:425
1513539810,0EcMasterDemoSyn1514529tAtEmLog_021:01:115
1040039810,0EcMasterDemoSyn1041029tAtEmLog_020:51:035
3274639770,1EcMasterDemoSyn32752-21ps19:24:514
126412340,0sleep40-21swapper/422:36:554
989139200,1EcMasterDemoSyn9899-21runintdemo5min22:17:164
25726992012,6cyclictest20130-21strings00:30:153
2570799190,10cyclictest831-21runrttasks23:18:090
454429180,11tAtEmLog_07969-21chrt22:34:565
454429180,11tAtEmLog_07969-21chrt22:34:555
2570799185,10cyclictest2340-21ssh23:07:290
221099180,8tDemoTimingTask6816-21sleep21:40:005
94239170,1EcMasterDemoSyn949-21grep20:30:473
743699170,10tDemoTimingTask7459-21chrt21:21:305
2573099171,12cyclictest16-1pr/legacy22:47:404
2572299170,13cyclictest19356-21latency_hist20:05:012
2571599174,10cyclictest18474-21sh21:45:351
2570799170,9cyclictest31927-21sh23:24:330
2570799170,9cyclictest17287-21open_files00:10:200
2570799170,9cyclictest11190-21sh22:54:420
2275929170,10tAtEmLog_024212-21chrt00:14:555
1843829170,7tAtEmLog_018968-21chrt20:01:505
774199160,14tDemoTimingTask9517-21chrt19:41:355
2573099160,12cyclictest24415-21sh21:30:514
2572299166,5cyclictest5689-21tail20:45:582
2572299164,9cyclictest10464-21cstates19:45:132
2572299161,11cyclictest16-1pr/legacy23:02:532
2572299161,10cyclictest327-21systemd-journal19:50:122
2572299160,12cyclictest2900-21sh00:20:232
2571599165,6cyclictest543-21cat20:30:221
2571599160,13cyclictest831-21runrttasks20:26:541
2571599160,10cyclictest13264-21sh00:26:141
2571599160,10cyclictest13264-21sh00:26:141
2570799164,9cyclictest8503-21latency_hist20:50:010
2570799164,9cyclictest24815-21cut20:15:130
2570799162,10cyclictest13526-21sh00:26:250
2570799162,10cyclictest13526-21sh00:26:240
25707991612,3cyclictest16773-21needreboot21:05:180
2570799160,9cyclictest5057-21sh22:32:500
2570799160,9cyclictest5057-21sh22:32:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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