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2026-02-05 - 15:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack5slot1.osadl.org (updated Thu Feb 05, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20412392220,0EcMasterDemoSyn0-21swapper/510:28:195
1896739920,0EcMasterDemoSyn1897729tAtEmLog_011:39:195
2482739830,0EcMasterDemoSyn2483729tAtEmLog_010:48:375
1076539830,0EcMasterDemoSyn1077529tAtEmLog_010:58:455
2969639820,0EcMasterDemoSyn2970629tAtEmLog_010:33:245
2002739820,0EcMasterDemoSyn2003729tAtEmLog_009:52:505
2002739820,0EcMasterDemoSyn2003729tAtEmLog_009:52:495
1924039820,0EcMasterDemoSyn1925029tAtEmLog_007:20:425
131439820,0EcMasterDemoSyn132529tAtEmLog_009:42:425
2303339810,0EcMasterDemoSyn2304329tAtEmLog_011:59:365
97632350,0sleep50-21swapper/510:22:175
1379639320,0EcMasterDemoSyn13802-21ps12:30:020
1492439240,0EcMasterDemoSyn0-21swapper/311:19:023
579929230,2tAtEmLog_00-21swapper/511:19:015
1076539230,1EcMasterDemoSyn10774-21wc10:58:452
17772220,0sleep50-21swapper/511:47:175
17772220,0sleep50-21swapper/511:47:175
2407439210,4EcMasterDemoSyn24082-21runintdemo5min11:24:070
187062200,0sleep00-21swapper/009:51:550
187062200,0sleep00-21swapper/009:51:550
132529200,0tAtEmLog_00-21swapper/509:47:455
132529200,0tAtEmLog_00-21swapper/509:47:455
1255699201,9cyclictest30684-21latency_hist11:10:000
1255699190,11cyclictest780-21runrttasks11:13:270
3254829180,10tAtEmLog_0458-21chrt12:04:565
2741229180,0tAtEmLog_00-21swapper/512:24:565
1255899181,13cyclictest16-1pr/legacy09:17:192
1255899181,12cyclictest16-1pr/legacy11:54:312
1255699180,10cyclictest9380-21sh12:09:500
1255699180,10cyclictest2530-21sh10:18:480
598199170,7tDemoTimingTask8281-21chrt08:05:535
463839170,10EcMasterDemoSyn4680-21chrt09:07:165
2003899170,9tDemoTimingTask23469-21chrt09:55:015
12560991713,3cyclictest18638-21idleruntime-cro12:15:004
1255999171,12cyclictest16-1pr/legacy07:46:033
1255999171,12cyclictest16-1pr/legacy07:46:023
1255899171,12cyclictest16-1pr/legacy10:43:322
1255799171,12cyclictest16-1pr/legacy07:51:061
1255799170,13cyclictest4143-21latency_hist08:00:011
1255699170,9cyclictest27999-21sh12:01:310
1255699170,9cyclictest1783-21sh11:29:500
1255699170,9cyclictest16237-21sh12:13:200
1255699170,13cyclictest780-21runrttasks08:39:540
598199160,6tDemoTimingTask6130-21chrt08:02:595
3253839160,6EcMasterDemoSyn9059-21taskset12:09:395
2483999160,9tDemoTimingTask27127-21taskset10:50:005
1256099160,7cyclictest623-21ssh11:46:294
1256099160,7cyclictest623-21ssh11:46:294
1256099160,12cyclictest16-1pr/legacy10:38:274
1256099160,10cyclictest7627-21taskset10:56:344
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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