You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-15 - 02:45
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Fri May 15, 2026 01:00:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
264559991265,845cyclictest64450irq/122-eth022:25:014
264559975272,550cyclictest0-21swapper/422:35:144
264559971031,676cyclictest0-21swapper/400:36:074
264579970770,82cyclictest0-21swapper/622:44:496
264559970064,633cyclictest0-21swapper/423:22:444
264559969313,677cyclictest0-21swapper/423:53:394
264559968911,675cyclictest0-21swapper/423:05:544
26457996780,42cyclictest121rcu_preempt23:45:136
264559966268,591cyclictest0-21swapper/421:53:374
2645199661239,169cyclictest24748-21ssh23:13:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional