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2026-05-12 - 00:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Mon May 11, 2026 12:57:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3199970424,677cyclictest0-21swapper/309:46:333
32299660576,3cyclictest631rcuc/610:57:396
3199965214,635cyclictest0-21swapper/309:52:083
3219965117,2cyclictest0-21swapper/511:01:525
322996363,3cyclictest0-21swapper/610:51:496
317996351,2cyclictest0-21swapper/111:01:521
3219963341,338cyclictest0-21swapper/511:18:575
3219963341,338cyclictest0-21swapper/511:18:575
3189962532,387cyclictest0-21swapper/210:31:292
3199961217,592cyclictest0-21swapper/311:14:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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