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2026-05-19 - 20:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Tue May 19, 2026 12:56:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
146449979127,761cyclictest0-21swapper/411:08:104
146449974667,676cyclictest0-21swapper/410:29:214
146409970571,84cyclictest0-21swapper/012:36:020
146449969114,2cyclictest31704-21uptime10:05:284
146449967740,41cyclictest0-21swapper/411:01:574
146469967582,126cyclictest0-21swapper/609:52:456
146439967235,465cyclictest0-21swapper/311:53:283
146439966770,423cyclictest0-21swapper/309:24:553
146449966573,210cyclictest121rcu_preempt11:51:504
1464699662109,296cyclictest0-21swapper/610:03:586
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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