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2026-09-19 - 23:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sat Sep 19, 2026 12:56:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
103029970066,296cyclictest57-21ksoftirqd/511:05:335
102999962530,592cyclictest17886-21diskmemload10:48:272
1030399624112,296cyclictest0-21swapper/610:54:136
102999962271,82cyclictest0-21swapper/210:26:082
102999961670,462cyclictest0-21swapper/210:21:372
1030299615107,126cyclictest0-21swapper/511:58:445
103049961199,381cyclictest0-21swapper/710:26:567
1029799607562,42cyclictest111rcuc/009:42:310
10301995921,42cyclictest0-21swapper/409:40:184
1030199592123,211cyclictest121rcu_preempt10:55:534
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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