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2026-04-20 - 02:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Mon Apr 20, 2026 00:58:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19340997220,211cyclictest0-21swapper/721:23:127
193369970524,84cyclictest0-21swapper/322:49:283
193359966673,126cyclictest26416-21timerwakeupswit21:25:332
193369966473,380cyclictest0-21swapper/300:08:043
193349962933,381cyclictest0-21swapper/121:25:161
193369962471,84cyclictest0-21swapper/323:31:213
193369962227,514cyclictest0-21swapper/322:33:063
193349962029,381cyclictest0-21swapper/100:20:231
193369961720,423cyclictest0-21swapper/321:24:193
1933899616106,296cyclictest2166-21taskset21:54:565
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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