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2026-05-01 - 07:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Thu Apr 30, 2026 12:57:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18249976383,677cyclictest0-21swapper/110:38:361
18249974725,126cyclictest0-21swapper/110:49:271
182499744115,417cyclictest0-21swapper/111:28:461
182499739699,37cyclictest231rcuc/110:53:231
18249969154,634cyclictest0-21swapper/111:02:311
1824996780,84cyclictest0-21swapper/112:28:291
18259967333,381cyclictest0-21swapper/210:20:532
18309966471,126cyclictest0-21swapper/710:21:447
182499663109,296cyclictest0-21swapper/110:55:041
183099655100,296cyclictest0-21swapper/711:49:267
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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