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2026-04-17 - 01:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Thu Apr 16, 2026 12:57:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57189974060,84cyclictest0-21swapper/709:19:417
5718997329,720cyclictest0-21swapper/711:54:557
57189965924,166cyclictest0-21swapper/710:45:037
57129964852,297cyclictest0-21swapper/109:14:591
57189963034,593cyclictest0-21swapper/712:08:317
57189962981,84cyclictest0-21swapper/710:20:107
571199617106,126cyclictest0-21swapper/010:26:190
57159961261,126cyclictest121rcu_preempt10:38:444
57189960513,508cyclictest0-21swapper/711:08:257
57169959686,507cyclictest0-21swapper/512:06:485
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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