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2026-07-04 - 07:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sat Jul 04, 2026 00:55:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36129978159,719cyclictest0-21swapper/223:01:202
36129976282,84cyclictest0-21swapper/221:54:422
36179967679,381cyclictest0-21swapper/723:44:507
36129967579,593cyclictest0-21swapper/200:31:302
36129965824,550cyclictest0-21swapper/200:18:142
361499653142,423cyclictest3608-21cyclictest00:33:424
36129963135,592cyclictest15760-21pmu-power00:10:242
36109962934,380cyclictest698-21ptp4l23:47:180
36149962534,126cyclictest0-21swapper/422:25:234
361599624117,126cyclictest0-21swapper/500:32:065
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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