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2026-06-13 - 06:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sat Jun 13, 2026 00:57:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
319779975276,84cyclictest0-21swapper/423:58:194
319779975272,550cyclictest121rcu_preempt22:11:214
319779974725,719cyclictest0-21swapper/419:51:454
319779973354,83cyclictest64450irq/122-eth023:48:104
31977996801,676cyclictest0-21swapper/421:42:514
319759967477,338cyclictest0-21swapper/222:05:152
3197499671165,41cyclictest1022-21kworker/u16:322:53:381
319779966873,84cyclictest0-21swapper/422:21:444
319779966526,551cyclictest0-21swapper/420:50:024
3197699664119,542cyclictest0-21swapper/322:22:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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