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2026-04-11 - 23:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sat Apr 11, 2026 12:55:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285449984134,804cyclictest0-21swapper/611:30:526
2854499740102,635cyclictest0-21swapper/609:35:286
285389969417,126cyclictest121rcu_preempt11:15:350
285449967334,550cyclictest0-21swapper/611:41:426
285449966325,635cyclictest0-21swapper/611:15:176
285449965114,634cyclictest0-21swapper/611:58:556
2854299637173,296cyclictest64450irq/122-eth011:15:164
285449963034,126cyclictest0-21swapper/611:39:136
2854199629120,84cyclictest121rcu_preempt12:24:173
285449962837,425cyclictest0-21swapper/611:45:236
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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