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2026-08-15 - 15:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sat Aug 15, 2026 12:55:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1059699722168,338cyclictest0-21swapper/311:13:353
1059499698276,126cyclictest0-21swapper/108:00:491
1059499696185,339cyclictest121rcu_preempt11:01:121
10594996781,86cyclictest0-21swapper/108:15:511
1059499658317,126cyclictest0-21swapper/111:13:551
105979964411,296cyclictest0-21swapper/411:03:494
1060099623584,3cyclictest721ktimersoftd/710:38:047
105989962125,593cyclictest0-21swapper/510:10:065
105989961567,468cyclictest8292-21ssh12:18:155
105939960211,2cyclictest0-21swapper/008:29:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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