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2026-09-05 - 18:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sat Sep 05, 2026 12:53:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34829979876,719cyclictest0-21swapper/310:17:483
34759971880,464cyclictest0-21swapper/009:15:100
34829969313,677cyclictest0-21swapper/311:35:363
34829967074,593cyclictest0-21swapper/309:54:173
34759966931,84cyclictest0-21swapper/009:47:340
34829966729,635cyclictest0-21swapper/309:20:143
348199645176,338cyclictest30864-1kworker/u17:010:22:562
3482996361,384cyclictest0-21swapper/309:17:373
34829963380,84cyclictest0-21swapper/311:48:233
34869962774,338cyclictest0-21swapper/609:52:366
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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