You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-29 - 17:18
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sat Aug 29, 2026 12:55:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21620998030,84cyclictest121rcu_preempt09:52:530
21620996790,84cyclictest0-21swapper/009:48:570
216209965664,126cyclictest0-21swapper/010:11:030
216249964449,421cyclictest0-21swapper/409:13:444
21624996427,3cyclictest0-21swapper/411:21:294
21620996330,84cyclictest0-21swapper/011:04:490
216209962733,591cyclictest0-21swapper/011:23:350
21623996261,2cyclictest0-21swapper/311:21:303
216249962430,591cyclictest64450irq/122-eth012:34:154
216229960714,3cyclictest0-21swapper/211:21:302
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional