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2026-05-14 - 02:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Thu May 14, 2026 00:58:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137629979472,719cyclictest0-21swapper/100:39:581
1376499764124,381cyclictest0-21swapper/323:31:383
1376499715117,381cyclictest0-21swapper/300:12:263
137639965320,7cyclictest9367-21ssh23:23:482
137639965320,7cyclictest9367-21ssh23:23:472
137639965320,7cyclictest9367-21ssh23:23:472
137619965059,48cyclictest121rcu_preempt00:04:540
137619965059,48cyclictest121rcu_preempt00:04:540
137659963483,85cyclictest121rcu_preempt23:31:384
137639962835,423cyclictest0-21swapper/223:10:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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