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2026-07-11 - 07:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sat Jul 11, 2026 00:58:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
308809975128,720cyclictest0-21swapper/223:06:542
308809972040,677cyclictest0-21swapper/200:33:242
308859966829,381cyclictest0-21swapper/719:48:407
308809966426,550cyclictest0-21swapper/223:43:122
3088299656403,92cyclictest0-21swapper/400:14:174
308849965572,118cyclictest0-21swapper/623:17:526
308819965214,84cyclictest0-21swapper/321:48:383
308859965096,126cyclictest0-21swapper/722:30:207
30882996405,126cyclictest0-21swapper/419:48:394
308819963985,126cyclictest0-21swapper/321:18:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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