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2026-06-28 - 10:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sun Jun 28, 2026 01:00:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117619970630,430cyclictest12802-21kworker/u16:221:30:324
117619966425,557cyclictest0-21swapper/400:36:094
117619966128,630cyclictest0-21swapper/400:26:534
117619966125,549cyclictest0-21swapper/400:01:534
117649965418,126cyclictest0-21swapper/721:29:557
11758996435,422cyclictest19746-21diskmemload22:37:101
117619963137,591cyclictest470-21ssh00:05:084
11761996300,82cyclictest0-21swapper/421:18:294
11761996300,82cyclictest0-21swapper/421:18:294
117619962530,592cyclictest0-21swapper/423:34:014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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