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2026-05-22 - 21:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Fri May 22, 2026 12:55:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30461998070,804cyclictest0-21swapper/712:12:097
3045699780736,42cyclictest311rcuc/211:37:282
304559975334,127cyclictest0-21swapper/111:38:141
304619970062,635cyclictest0-21swapper/711:49:517
304609966531,339cyclictest25976-21ssh10:27:136
304619965964,592cyclictest0-21swapper/711:36:517
3046199659106,549cyclictest0-21swapper/711:57:027
3045899627117,338cyclictest121rcu_preempt10:27:374
304549961823,464cyclictest0-21swapper/012:01:340
304579960699,338cyclictest0-21swapper/311:57:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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