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2026-05-15 - 15:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Fri May 15, 2026 12:55:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
166249978117,762cyclictest0-21swapper/211:45:042
1662299743189,424cyclictest0-21swapper/011:47:390
166249971173,84cyclictest0-21swapper/212:28:422
1662599705113,466cyclictest0-21swapper/312:24:423
1662699695102,126cyclictest0-21swapper/411:15:574
166249967378,592cyclictest0-21swapper/212:24:362
1662599672121,126cyclictest121rcu_preempt12:36:283
166249967276,381cyclictest0-21swapper/212:38:072
166249966671,84cyclictest0-21swapper/210:45:272
166289966366,380cyclictest0-21swapper/611:14:356
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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