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2026-03-22 - 19:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sun Mar 22, 2026 12:54:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
196079975028,719cyclictest0-21swapper/011:21:000
19607997220,42cyclictest0-21swapper/010:08:060
1960799720465,253cyclictest0-21swapper/010:24:090
196099971377,84cyclictest0-21swapper/212:36:212
1961499707113,126cyclictest0-21swapper/709:26:027
1961399706155,84cyclictest121rcu_preempt09:32:376
1961199676123,380cyclictest0-21swapper/409:32:384
1961099673209,124cyclictest121rcu_preempt10:27:353
196109965764,126cyclictest0-21swapper/312:18:333
196099965055,380cyclictest0-21swapper/211:37:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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