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2026-04-13 - 00:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot3.osadl.org (updated Sun Apr 12, 2026 12:59:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278439983469,762cyclictest0-21swapper/312:14:333
2784399777734,41cyclictest391rcuc/311:25:033
2784399777734,41cyclictest391rcuc/311:25:033
2784499726682,42cyclictest481ktimersoftd/411:25:034
2784499726682,42cyclictest481ktimersoftd/411:25:034
27843997210,84cyclictest0-21swapper/310:27:573
2784799697143,253cyclictest0-21swapper/707:22:367
278409968648,465cyclictest27838-21cyclictest11:40:040
27840996832,42cyclictest0-21swapper/011:25:040
27840996832,42cyclictest0-21swapper/011:25:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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