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2026-11-01 - 02:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sat Oct 31, 2026 12:54:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178619976383,507cyclictest0-21swapper/510:51:485
178619976383,507cyclictest0-21swapper/510:51:475
178589969619,295cyclictest0-21swapper/209:39:562
17857996888,126cyclictest0-21swapper/109:47:051
178589968083,381cyclictest0-21swapper/210:20:042
1785899671585,84cyclictest311rcuc/210:56:202
178619965099,293cyclictest0-21swapper/509:35:255
1785999649350,126cyclictest0-21swapper/309:50:323
178629963379,422cyclictest0-21swapper/611:32:176
1786399632120,381cyclictest0-21swapper/710:29:577
1785699626117,506cyclictest0-21swapper/010:17:140
178629962331,513cyclictest0-21swapper/610:51:206
178629962331,513cyclictest0-21swapper/610:51:206
1785899623111,339cyclictest0-21swapper/211:18:562
1785999619533,84cyclictest391rcuc/310:54:133
1785999619533,84cyclictest391rcuc/310:54:133
178629961864,423cyclictest0-21swapper/610:42:296
1785699614192,3cyclictest30403-21rm09:28:300
178599961359,340cyclictest0-21swapper/309:35:423
1786299612101,380cyclictest0-21swapper/609:29:586
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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