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2025-11-30 - 11:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sun Nov 30, 2025 00:50:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1547529865,29sleep50-21swapper/519:08:425
1472929187,2sleep00-21swapper/019:05:250
1542528551,30sleep30-21swapper/319:08:013
1530528346,29sleep60-21swapper/619:06:596
1555228249,29sleep70-21swapper/719:09:507
1547428047,29sleep40-21swapper/419:08:424
1508828046,29sleep20-21swapper/219:05:262
1541427844,29sleep10-21swapper/119:07:501
15998995654,1cyclictest0-21swapper/223:35:212
126992540,0sleep00-21swapper/020:50:140
16003995353,0cyclictest0-21swapper/722:20:237
15997995252,0cyclictest0-21swapper/100:15:351
97422510,0sleep40-21swapper/421:33:494
16000995048,1cyclictest0-21swapper/400:17:454
16000994847,1cyclictest0-21swapper/423:41:334
44452470,0sleep60-21swapper/623:35:216
15998994710,0cyclictest0-21swapper/223:53:292
15997994747,0cyclictest0-21swapper/123:10:151
208372460,0sleep40-21swapper/400:00:014
15999994644,1cyclictest0-21swapper/322:10:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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