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2025-07-16 - 00:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Tue Jul 15, 2025 12:50:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3186728873,10sleep50-21swapper/507:09:475
3184428349,30sleep20-21swapper/207:09:292
3162928249,29sleep30-21swapper/307:06:243
3176328166,10sleep60-21swapper/607:08:216
3174327844,29sleep40-21swapper/407:08:024
3171027743,29sleep70-21swapper/707:07:347
2928027642,30sleep10-21swapper/107:05:021
2927927439,30sleep00-21swapper/007:05:010
102692590,0sleep10-21swapper/111:30:191
303242500,0sleep70-21swapper/711:55:497
24262470,0sleep30-21swapper/311:26:373
274212450,0sleep40-21swapper/411:55:134
249642420,0sleep10-21swapper/111:06:091
32520992323,0cyclictest69450irq/124-eth012:25:214
32523992218,4cyclictest630-21avahi-daemon10:29:357
243982210,0sleep40-21swapper/410:35:144
32519992010,7cyclictest0-21swapper/311:49:293
32518992015,3cyclictest734-21gmain11:43:532
32523991916,3cyclictest19802-21nscd11:02:477
2416821910,0sleep10-21swapper/111:37:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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