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2025-06-28 - 23:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sat Jun 28, 2025 12:50:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2162628551,29sleep60-21swapper/607:09:486
2152328450,30sleep70-21swapper/707:08:217
2156728340,39sleep30-21swapper/307:08:573
2149828046,29sleep00-21swapper/007:07:570
2146228046,30sleep20-21swapper/207:07:282
2141027945,29sleep40-21swapper/407:06:414
2151227743,29sleep50-21swapper/507:08:105
1903827542,29sleep10-21swapper/107:05:021
32662540,0sleep00-21swapper/010:15:000
52142520,0sleep50-21swapper/512:20:205
136952510,0sleep00-21swapper/012:25:110
173992480,0sleep40-21swapper/411:08:054
125712480,0sleep20-21swapper/212:24:402
21312470,0sleep10-21swapper/107:30:001
294762440,0sleep40-21swapper/410:26:414
22074994342,0cyclictest0-21swapper/407:10:174
22076993735,1cyclictest0-21swapper/607:10:166
22075993535,0cyclictest0-21swapper/512:06:035
22075993535,0cyclictest0-21swapper/512:06:035
22074992929,0cyclictest0-21swapper/412:31:394
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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