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2026-03-15 - 05:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot3.osadl.org (updated Sat Mar 14, 2026 00:56:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1959199673119,296cyclictest0-21swapper/300:26:273
1959199665240,127cyclictest628-21nscd23:09:253
195899965622,3cyclictest0-21swapper/123:15:411
195889964896,380cyclictest26431-21sh22:44:430
195949964593,127cyclictest0-21swapper/623:10:376
19590996391,127cyclictest0-21swapper/200:24:042
1959599637125,381cyclictest0-21swapper/700:03:417
1959199623157,84cyclictest121rcu_preempt23:19:583
1959399620534,84cyclictest551rcuc/522:48:085
1959099618107,508cyclictest0-21swapper/200:09:472
195899961562,380cyclictest0-21swapper/122:12:311
195919961216,126cyclictest0-21swapper/323:57:123
195909961261,126cyclictest0-21swapper/223:56:592
195949961119,84cyclictest0-21swapper/600:44:536
1959299608100,126cyclictest0-21swapper/400:29:594
195949960652,380cyclictest0-21swapper/622:43:156
19590996018,127cyclictest0-21swapper/222:59:522
19591995940,84cyclictest0-21swapper/322:58:473
19590995940,84cyclictest1602-21runrttasks21:02:032
19590995940,84cyclictest0-21swapper/222:50:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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